1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include "amdgpu.h" 26 #include "amdgpu_vcn.h" 27 #include "amdgpu_pm.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "vcn_v2_0.h" 31 #include "mmsch_v3_0.h" 32 33 #include "vcn/vcn_3_0_0_offset.h" 34 #include "vcn/vcn_3_0_0_sh_mask.h" 35 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 36 37 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x27 38 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x0f 39 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x10 40 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x11 41 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x29 42 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x66 43 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 44 45 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x431 46 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x3b4 47 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x3b5 48 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x25c 49 50 #define VCN_INSTANCES_SIENNA_CICHLID 2 51 52 static int amdgpu_ih_clientid_vcns[] = { 53 SOC15_IH_CLIENTID_VCN, 54 SOC15_IH_CLIENTID_VCN1 55 }; 56 57 static int amdgpu_ucode_id_vcns[] = { 58 AMDGPU_UCODE_ID_VCN, 59 AMDGPU_UCODE_ID_VCN1 60 }; 61 62 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); 63 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); 64 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); 65 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); 66 static int vcn_v3_0_set_powergating_state(void *handle, 67 enum amd_powergating_state state); 68 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 69 int inst_idx, struct dpg_pause_state *new_state); 70 71 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); 72 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); 73 74 /** 75 * vcn_v3_0_early_init - set function pointers 76 * 77 * @handle: amdgpu_device pointer 78 * 79 * Set ring and irq function pointers 80 */ 81 static int vcn_v3_0_early_init(void *handle) 82 { 83 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 84 85 if (amdgpu_sriov_vf(adev)) { 86 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 87 adev->vcn.harvest_config = 0; 88 adev->vcn.num_enc_rings = 1; 89 90 } else { 91 if (adev->asic_type == CHIP_SIENNA_CICHLID) { 92 u32 harvest; 93 int i; 94 95 adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; 96 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 97 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); 98 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK) 99 adev->vcn.harvest_config |= 1 << i; 100 } 101 102 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0 | 103 AMDGPU_VCN_HARVEST_VCN1)) 104 /* both instances are harvested, disable the block */ 105 return -ENOENT; 106 } else 107 adev->vcn.num_vcn_inst = 1; 108 109 adev->vcn.num_enc_rings = 2; 110 } 111 112 vcn_v3_0_set_dec_ring_funcs(adev); 113 vcn_v3_0_set_enc_ring_funcs(adev); 114 vcn_v3_0_set_irq_funcs(adev); 115 116 return 0; 117 } 118 119 /** 120 * vcn_v3_0_sw_init - sw init for VCN block 121 * 122 * @handle: amdgpu_device pointer 123 * 124 * Load firmware and sw initialization 125 */ 126 static int vcn_v3_0_sw_init(void *handle) 127 { 128 struct amdgpu_ring *ring; 129 int i, j, r; 130 int vcn_doorbell_index = 0; 131 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 132 133 r = amdgpu_vcn_sw_init(adev); 134 if (r) 135 return r; 136 137 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 138 const struct common_firmware_header *hdr; 139 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 140 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 141 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 142 adev->firmware.fw_size += 143 roundup2(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 144 145 if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID) { 146 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; 147 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; 148 adev->firmware.fw_size += 149 roundup2(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 150 } 151 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 152 } 153 154 r = amdgpu_vcn_resume(adev); 155 if (r) 156 return r; 157 158 if (amdgpu_sriov_vf(adev)) { 159 vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; 160 /* get DWORD offset */ 161 vcn_doorbell_index = vcn_doorbell_index << 1; 162 } 163 164 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 165 if (adev->vcn.harvest_config & (1 << i)) 166 continue; 167 168 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 169 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 170 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 171 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 172 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 173 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 174 175 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 176 adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9); 177 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 178 adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0); 179 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 180 adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1); 181 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 182 adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD); 183 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 184 adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP); 185 186 /* VCN DEC TRAP */ 187 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 188 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst[i].irq); 189 if (r) 190 return r; 191 192 ring = &adev->vcn.inst[i].ring_dec; 193 ring->use_doorbell = true; 194 if (amdgpu_sriov_vf(adev)) { 195 ring->doorbell_index = vcn_doorbell_index; 196 /* NOTE: increment so next VCN engine use next DOORBELL DWORD */ 197 vcn_doorbell_index++; 198 } else { 199 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; 200 } 201 if (adev->asic_type == CHIP_SIENNA_CICHLID && i != 0) 202 ring->no_scheduler = true; 203 snprintf(ring->name, sizeof(ring->name), "vcn_dec_%d", i); 204 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 205 AMDGPU_RING_PRIO_DEFAULT); 206 if (r) 207 return r; 208 209 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 210 /* VCN ENC TRAP */ 211 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], 212 j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, &adev->vcn.inst[i].irq); 213 if (r) 214 return r; 215 216 ring = &adev->vcn.inst[i].ring_enc[j]; 217 ring->use_doorbell = true; 218 if (amdgpu_sriov_vf(adev)) { 219 ring->doorbell_index = vcn_doorbell_index; 220 /* NOTE: increment so next VCN engine use next DOORBELL DWORD */ 221 vcn_doorbell_index++; 222 } else { 223 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; 224 } 225 if (adev->asic_type == CHIP_SIENNA_CICHLID && i != 1) 226 ring->no_scheduler = true; 227 snprintf(ring->name, sizeof(ring->name), "vcn_enc_%d.%d", i, j); 228 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, 229 AMDGPU_RING_PRIO_DEFAULT); 230 if (r) 231 return r; 232 } 233 } 234 235 if (amdgpu_sriov_vf(adev)) { 236 r = amdgpu_virt_alloc_mm_table(adev); 237 if (r) 238 return r; 239 } 240 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 241 adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; 242 243 return 0; 244 } 245 246 /** 247 * vcn_v3_0_sw_fini - sw fini for VCN block 248 * 249 * @handle: amdgpu_device pointer 250 * 251 * VCN suspend and free up sw allocation 252 */ 253 static int vcn_v3_0_sw_fini(void *handle) 254 { 255 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 256 int r; 257 258 if (amdgpu_sriov_vf(adev)) 259 amdgpu_virt_free_mm_table(adev); 260 261 r = amdgpu_vcn_suspend(adev); 262 if (r) 263 return r; 264 265 r = amdgpu_vcn_sw_fini(adev); 266 267 return r; 268 } 269 270 /** 271 * vcn_v3_0_hw_init - start and test VCN block 272 * 273 * @handle: amdgpu_device pointer 274 * 275 * Initialize the hardware, boot up the VCPU and do some testing 276 */ 277 static int vcn_v3_0_hw_init(void *handle) 278 { 279 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 280 struct amdgpu_ring *ring; 281 int i, j, r; 282 283 if (amdgpu_sriov_vf(adev)) { 284 r = vcn_v3_0_start_sriov(adev); 285 if (r) 286 goto done; 287 288 /* initialize VCN dec and enc ring buffers */ 289 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 290 if (adev->vcn.harvest_config & (1 << i)) 291 continue; 292 293 ring = &adev->vcn.inst[i].ring_dec; 294 ring->wptr = 0; 295 ring->wptr_old = 0; 296 vcn_v3_0_dec_ring_set_wptr(ring); 297 ring->sched.ready = true; 298 299 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 300 ring = &adev->vcn.inst[i].ring_enc[j]; 301 ring->wptr = 0; 302 ring->wptr_old = 0; 303 vcn_v3_0_enc_ring_set_wptr(ring); 304 ring->sched.ready = true; 305 } 306 } 307 } else { 308 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 309 if (adev->vcn.harvest_config & (1 << i)) 310 continue; 311 312 ring = &adev->vcn.inst[i].ring_dec; 313 314 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 315 ring->doorbell_index, i); 316 317 r = amdgpu_ring_test_helper(ring); 318 if (r) 319 goto done; 320 321 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 322 ring = &adev->vcn.inst[i].ring_enc[j]; 323 r = amdgpu_ring_test_helper(ring); 324 if (r) 325 goto done; 326 } 327 } 328 } 329 330 done: 331 if (!r) 332 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 333 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 334 335 return r; 336 } 337 338 /** 339 * vcn_v3_0_hw_fini - stop the hardware block 340 * 341 * @handle: amdgpu_device pointer 342 * 343 * Stop the VCN block, mark ring as not ready any more 344 */ 345 static int vcn_v3_0_hw_fini(void *handle) 346 { 347 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 348 int i; 349 350 cancel_delayed_work_sync(&adev->vcn.idle_work); 351 352 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 353 if (adev->vcn.harvest_config & (1 << i)) 354 continue; 355 356 if (!amdgpu_sriov_vf(adev)) { 357 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 358 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 359 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { 360 vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 361 } 362 } 363 } 364 365 return 0; 366 } 367 368 /** 369 * vcn_v3_0_suspend - suspend VCN block 370 * 371 * @handle: amdgpu_device pointer 372 * 373 * HW fini and suspend VCN block 374 */ 375 static int vcn_v3_0_suspend(void *handle) 376 { 377 int r; 378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 379 380 r = vcn_v3_0_hw_fini(adev); 381 if (r) 382 return r; 383 384 r = amdgpu_vcn_suspend(adev); 385 386 return r; 387 } 388 389 /** 390 * vcn_v3_0_resume - resume VCN block 391 * 392 * @handle: amdgpu_device pointer 393 * 394 * Resume firmware and hw init VCN block 395 */ 396 static int vcn_v3_0_resume(void *handle) 397 { 398 int r; 399 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 400 401 r = amdgpu_vcn_resume(adev); 402 if (r) 403 return r; 404 405 r = vcn_v3_0_hw_init(adev); 406 407 return r; 408 } 409 410 /** 411 * vcn_v3_0_mc_resume - memory controller programming 412 * 413 * @adev: amdgpu_device pointer 414 * @inst: instance number 415 * 416 * Let the VCN memory controller know it's offsets 417 */ 418 static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) 419 { 420 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 421 uint32_t offset; 422 423 /* cache window 0: fw */ 424 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 425 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 426 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)); 427 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 428 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)); 429 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); 430 offset = 0; 431 } else { 432 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 433 lower_32_bits(adev->vcn.inst[inst].gpu_addr)); 434 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 435 upper_32_bits(adev->vcn.inst[inst].gpu_addr)); 436 offset = size; 437 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 438 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 439 } 440 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); 441 442 /* cache window 1: stack */ 443 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 444 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 445 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 446 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset)); 447 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); 448 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 449 450 /* cache window 2: context */ 451 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 452 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 453 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 454 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 455 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0); 456 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 457 } 458 459 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 460 { 461 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 462 uint32_t offset; 463 464 /* cache window 0: fw */ 465 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 466 if (!indirect) { 467 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 468 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 469 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); 470 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 471 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 472 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); 473 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 474 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 475 } else { 476 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 477 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 478 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 479 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 480 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 481 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 482 } 483 offset = 0; 484 } else { 485 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 486 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 487 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 488 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 489 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 490 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 491 offset = size; 492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 493 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 494 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 495 } 496 497 if (!indirect) 498 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 499 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 500 else 501 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 502 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 503 504 /* cache window 1: stack */ 505 if (!indirect) { 506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 507 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 508 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 509 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 510 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 511 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 512 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 513 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 514 } else { 515 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 516 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 518 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 519 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 520 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 521 } 522 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 523 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 524 525 /* cache window 2: context */ 526 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 527 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 528 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 529 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 530 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 531 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 533 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 534 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 535 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 536 537 /* non-cache window */ 538 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 539 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect); 540 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 541 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect); 542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 543 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 544 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 545 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect); 546 } 547 548 static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) 549 { 550 uint32_t data = 0; 551 552 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 553 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 554 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 555 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 556 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 557 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 558 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 559 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 560 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 561 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 562 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 563 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 564 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 565 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 566 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 567 568 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 569 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 570 UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF); 571 } else { 572 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 573 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 574 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 575 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 576 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 577 | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 578 | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 579 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 580 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 581 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 582 | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 583 | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 584 | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 585 | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 586 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 587 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); 588 } 589 590 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 591 data &= ~0x103; 592 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 593 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 594 UVD_POWER_STATUS__UVD_PG_EN_MASK; 595 596 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 597 } 598 599 static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) 600 { 601 uint32_t data; 602 603 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 604 /* Before power off, this indicator has to be turned on */ 605 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); 606 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 607 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 608 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); 609 610 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 611 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 612 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 613 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 614 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 615 | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT 616 | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT 617 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 618 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 619 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 620 | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT 621 | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT 622 | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT 623 | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT); 624 WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data); 625 626 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 627 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 628 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 629 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 630 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 631 | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT 632 | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT 633 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 634 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 635 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 636 | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT 637 | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT 638 | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT 639 | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT); 640 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF); 641 } 642 } 643 644 /** 645 * vcn_v3_0_disable_clock_gating - disable VCN clock gating 646 * 647 * @adev: amdgpu_device pointer 648 * @inst: instance number 649 * 650 * Disable clock gating for VCN block 651 */ 652 static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) 653 { 654 uint32_t data; 655 656 /* VCN disable CGC */ 657 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 658 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 659 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 660 else 661 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 662 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 663 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 664 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 665 666 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); 667 data &= ~(UVD_CGC_GATE__SYS_MASK 668 | UVD_CGC_GATE__UDEC_MASK 669 | UVD_CGC_GATE__MPEG2_MASK 670 | UVD_CGC_GATE__REGS_MASK 671 | UVD_CGC_GATE__RBC_MASK 672 | UVD_CGC_GATE__LMI_MC_MASK 673 | UVD_CGC_GATE__LMI_UMC_MASK 674 | UVD_CGC_GATE__IDCT_MASK 675 | UVD_CGC_GATE__MPRD_MASK 676 | UVD_CGC_GATE__MPC_MASK 677 | UVD_CGC_GATE__LBSI_MASK 678 | UVD_CGC_GATE__LRBBM_MASK 679 | UVD_CGC_GATE__UDEC_RE_MASK 680 | UVD_CGC_GATE__UDEC_CM_MASK 681 | UVD_CGC_GATE__UDEC_IT_MASK 682 | UVD_CGC_GATE__UDEC_DB_MASK 683 | UVD_CGC_GATE__UDEC_MP_MASK 684 | UVD_CGC_GATE__WCB_MASK 685 | UVD_CGC_GATE__VCPU_MASK 686 | UVD_CGC_GATE__MMSCH_MASK); 687 688 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); 689 690 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); 691 692 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 693 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 694 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 695 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 696 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 697 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 698 | UVD_CGC_CTRL__SYS_MODE_MASK 699 | UVD_CGC_CTRL__UDEC_MODE_MASK 700 | UVD_CGC_CTRL__MPEG2_MODE_MASK 701 | UVD_CGC_CTRL__REGS_MODE_MASK 702 | UVD_CGC_CTRL__RBC_MODE_MASK 703 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 704 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 705 | UVD_CGC_CTRL__IDCT_MODE_MASK 706 | UVD_CGC_CTRL__MPRD_MODE_MASK 707 | UVD_CGC_CTRL__MPC_MODE_MASK 708 | UVD_CGC_CTRL__LBSI_MODE_MASK 709 | UVD_CGC_CTRL__LRBBM_MODE_MASK 710 | UVD_CGC_CTRL__WCB_MODE_MASK 711 | UVD_CGC_CTRL__VCPU_MODE_MASK 712 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 713 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 714 715 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE); 716 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 717 | UVD_SUVD_CGC_GATE__SIT_MASK 718 | UVD_SUVD_CGC_GATE__SMP_MASK 719 | UVD_SUVD_CGC_GATE__SCM_MASK 720 | UVD_SUVD_CGC_GATE__SDB_MASK 721 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 722 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 723 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 724 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 725 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 726 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 727 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 728 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 729 | UVD_SUVD_CGC_GATE__SCLR_MASK 730 | UVD_SUVD_CGC_GATE__ENT_MASK 731 | UVD_SUVD_CGC_GATE__IME_MASK 732 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 733 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 734 | UVD_SUVD_CGC_GATE__SITE_MASK 735 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 736 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 737 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 738 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 739 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK 740 | UVD_SUVD_CGC_GATE__EFC_MASK 741 | UVD_SUVD_CGC_GATE__SAOE_MASK 742 | UVD_SUVD_CGC_GATE__SRE_AV1_MASK 743 | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK 744 | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK 745 | UVD_SUVD_CGC_GATE__SCM_AV1_MASK 746 | UVD_SUVD_CGC_GATE__SMPA_MASK); 747 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data); 748 749 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2); 750 data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK 751 | UVD_SUVD_CGC_GATE2__MPBE1_MASK 752 | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK 753 | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK 754 | UVD_SUVD_CGC_GATE2__MPC1_MASK); 755 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data); 756 757 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 758 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 759 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 760 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 761 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 762 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 763 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 764 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 765 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 766 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 767 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 768 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 769 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 770 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 771 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 772 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 773 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 774 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 775 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 776 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 777 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 778 } 779 780 static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 781 uint8_t sram_sel, int inst_idx, uint8_t indirect) 782 { 783 uint32_t reg_data = 0; 784 785 /* enable sw clock gating control */ 786 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 787 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 788 else 789 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 790 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 791 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 792 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 793 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 794 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 795 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 796 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 797 UVD_CGC_CTRL__SYS_MODE_MASK | 798 UVD_CGC_CTRL__UDEC_MODE_MASK | 799 UVD_CGC_CTRL__MPEG2_MODE_MASK | 800 UVD_CGC_CTRL__REGS_MODE_MASK | 801 UVD_CGC_CTRL__RBC_MODE_MASK | 802 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 803 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 804 UVD_CGC_CTRL__IDCT_MODE_MASK | 805 UVD_CGC_CTRL__MPRD_MODE_MASK | 806 UVD_CGC_CTRL__MPC_MODE_MASK | 807 UVD_CGC_CTRL__LBSI_MODE_MASK | 808 UVD_CGC_CTRL__LRBBM_MODE_MASK | 809 UVD_CGC_CTRL__WCB_MODE_MASK | 810 UVD_CGC_CTRL__VCPU_MODE_MASK | 811 UVD_CGC_CTRL__MMSCH_MODE_MASK); 812 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 813 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 814 815 /* turn off clock gating */ 816 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 817 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); 818 819 /* turn on SUVD clock gating */ 820 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 821 VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 822 823 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 824 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 825 VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 826 } 827 828 /** 829 * vcn_v3_0_enable_clock_gating - enable VCN clock gating 830 * 831 * @adev: amdgpu_device pointer 832 * @inst: instance number 833 * 834 * Enable clock gating for VCN block 835 */ 836 static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) 837 { 838 uint32_t data; 839 840 /* enable VCN CGC */ 841 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 842 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 843 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 844 else 845 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 846 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 847 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 848 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 849 850 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); 851 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 852 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 853 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 854 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 855 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 856 | UVD_CGC_CTRL__SYS_MODE_MASK 857 | UVD_CGC_CTRL__UDEC_MODE_MASK 858 | UVD_CGC_CTRL__MPEG2_MODE_MASK 859 | UVD_CGC_CTRL__REGS_MODE_MASK 860 | UVD_CGC_CTRL__RBC_MODE_MASK 861 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 862 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 863 | UVD_CGC_CTRL__IDCT_MODE_MASK 864 | UVD_CGC_CTRL__MPRD_MODE_MASK 865 | UVD_CGC_CTRL__MPC_MODE_MASK 866 | UVD_CGC_CTRL__LBSI_MODE_MASK 867 | UVD_CGC_CTRL__LRBBM_MODE_MASK 868 | UVD_CGC_CTRL__WCB_MODE_MASK 869 | UVD_CGC_CTRL__VCPU_MODE_MASK 870 | UVD_CGC_CTRL__MMSCH_MODE_MASK); 871 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); 872 873 data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL); 874 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 875 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 876 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 877 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 878 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 879 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 880 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 881 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 882 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 883 | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 884 | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK 885 | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK 886 | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK 887 | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK 888 | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK 889 | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK 890 | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK 891 | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK 892 | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK); 893 WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data); 894 } 895 896 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) 897 { 898 struct amdgpu_ring *ring; 899 uint32_t rb_bufsz, tmp; 900 901 /* disable register anti-hang mechanism */ 902 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, 903 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 904 /* enable dynamic power gating mode */ 905 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); 906 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 907 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 908 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); 909 910 if (indirect) 911 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; 912 913 /* enable clock gating */ 914 vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); 915 916 /* enable VCPU clock */ 917 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 918 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 919 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; 920 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 921 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 922 923 /* disable master interupt */ 924 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 925 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); 926 927 /* setup mmUVD_LMI_CTRL */ 928 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 929 UVD_LMI_CTRL__REQ_MODE_MASK | 930 UVD_LMI_CTRL__CRC_RESET_MASK | 931 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 932 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 933 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 934 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 935 0x00100000L); 936 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 937 VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect); 938 939 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 940 VCN, inst_idx, mmUVD_MPC_CNTL), 941 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 942 943 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 944 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), 945 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 946 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 947 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 948 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 949 950 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 951 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), 952 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 953 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 954 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 955 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 956 957 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 958 VCN, inst_idx, mmUVD_MPC_SET_MUX), 959 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 960 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 961 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 962 963 vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); 964 965 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 966 VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 967 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 968 VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 969 970 /* enable LMI MC and UMC channels */ 971 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 972 VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect); 973 974 /* unblock VCPU register access */ 975 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 976 VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect); 977 978 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 979 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 980 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 981 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 982 983 /* enable master interrupt */ 984 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 985 VCN, inst_idx, mmUVD_MASTINT_EN), 986 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 987 988 /* add nop to workaround PSP size check */ 989 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( 990 VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect); 991 992 if (indirect) 993 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, 994 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - 995 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); 996 997 ring = &adev->vcn.inst[inst_idx].ring_dec; 998 /* force RBC into idle state */ 999 rb_bufsz = order_base_2(ring->ring_size); 1000 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1001 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1002 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1003 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1004 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1005 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); 1006 1007 /* Stall DPG before WPTR/RPTR reset */ 1008 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1009 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1010 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1011 1012 /* set the write pointer delay */ 1013 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); 1014 1015 /* set the wb address */ 1016 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, 1017 (upper_32_bits(ring->gpu_addr) >> 2)); 1018 1019 /* programm the RB_BASE for ring buffer */ 1020 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1021 lower_32_bits(ring->gpu_addr)); 1022 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1023 upper_32_bits(ring->gpu_addr)); 1024 1025 /* Initialize the ring buffer's read and write pointers */ 1026 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); 1027 1028 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); 1029 1030 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); 1031 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, 1032 lower_32_bits(ring->wptr)); 1033 1034 /* Unstall DPG */ 1035 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1036 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1037 1038 return 0; 1039 } 1040 1041 static int vcn_v3_0_start(struct amdgpu_device *adev) 1042 { 1043 struct amdgpu_ring *ring; 1044 uint32_t rb_bufsz, tmp; 1045 int i, j, k, r; 1046 1047 if (adev->pm.dpm_enabled) 1048 amdgpu_dpm_enable_uvd(adev, true); 1049 1050 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1051 if (adev->vcn.harvest_config & (1 << i)) 1052 continue; 1053 1054 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG){ 1055 r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); 1056 continue; 1057 } 1058 1059 /* disable VCN power gating */ 1060 vcn_v3_0_disable_static_power_gating(adev, i); 1061 1062 /* set VCN status busy */ 1063 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 1064 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); 1065 1066 /*SW clock gating */ 1067 vcn_v3_0_disable_clock_gating(adev, i); 1068 1069 /* enable VCPU clock */ 1070 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1071 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 1072 1073 /* disable master interrupt */ 1074 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, 1075 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1076 1077 /* enable LMI MC and UMC channels */ 1078 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, 1079 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1080 1081 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1082 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1083 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1084 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1085 1086 /* setup mmUVD_LMI_CTRL */ 1087 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); 1088 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 1089 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1090 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1091 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1092 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 1093 1094 /* setup mmUVD_MPC_CNTL */ 1095 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); 1096 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 1097 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 1098 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); 1099 1100 /* setup UVD_MPC_SET_MUXA0 */ 1101 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, 1102 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1103 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1104 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1105 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1106 1107 /* setup UVD_MPC_SET_MUXB0 */ 1108 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, 1109 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1110 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1111 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1112 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 1113 1114 /* setup mmUVD_MPC_SET_MUX */ 1115 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, 1116 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1117 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1118 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 1119 1120 vcn_v3_0_mc_resume(adev, i); 1121 1122 /* VCN global tiling registers */ 1123 WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG, 1124 adev->gfx.config.gb_addr_config); 1125 1126 /* unblock VCPU register access */ 1127 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, 1128 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1129 1130 /* release VCPU reset to boot */ 1131 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1132 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1133 1134 for (j = 0; j < 10; ++j) { 1135 uint32_t status; 1136 1137 for (k = 0; k < 100; ++k) { 1138 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); 1139 if (status & 2) 1140 break; 1141 mdelay(10); 1142 } 1143 r = 0; 1144 if (status & 2) 1145 break; 1146 1147 DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i); 1148 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1149 UVD_VCPU_CNTL__BLK_RST_MASK, 1150 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1151 mdelay(10); 1152 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1153 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1154 1155 mdelay(10); 1156 r = -1; 1157 } 1158 1159 if (r) { 1160 DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i); 1161 return r; 1162 } 1163 1164 /* enable master interrupt */ 1165 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 1166 UVD_MASTINT_EN__VCPU_EN_MASK, 1167 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1168 1169 /* clear the busy bit of VCN_STATUS */ 1170 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, 1171 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1172 1173 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); 1174 1175 ring = &adev->vcn.inst[i].ring_dec; 1176 /* force RBC into idle state */ 1177 rb_bufsz = order_base_2(ring->ring_size); 1178 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1179 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1180 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1181 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1182 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1183 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); 1184 1185 /* programm the RB_BASE for ring buffer */ 1186 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1187 lower_32_bits(ring->gpu_addr)); 1188 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1189 upper_32_bits(ring->gpu_addr)); 1190 1191 /* Initialize the ring buffer's read and write pointers */ 1192 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); 1193 1194 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); 1195 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, 1196 lower_32_bits(ring->wptr)); 1197 ring = &adev->vcn.inst[i].ring_enc[0]; 1198 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1199 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1200 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); 1201 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1202 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); 1203 1204 ring = &adev->vcn.inst[i].ring_enc[1]; 1205 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1206 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1207 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1208 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1209 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); 1210 } 1211 1212 return 0; 1213 } 1214 1215 static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) 1216 { 1217 int i, j; 1218 struct amdgpu_ring *ring; 1219 uint64_t cache_addr; 1220 uint64_t rb_addr; 1221 uint64_t ctx_addr; 1222 uint32_t param, resp, expected; 1223 uint32_t offset, cache_size; 1224 uint32_t tmp, timeout; 1225 uint32_t id; 1226 1227 struct amdgpu_mm_table *table = &adev->virt.mm_table; 1228 uint32_t *table_loc; 1229 uint32_t table_size; 1230 uint32_t size, size_dw; 1231 1232 struct mmsch_v3_0_cmd_direct_write 1233 direct_wt = { {0} }; 1234 struct mmsch_v3_0_cmd_direct_read_modify_write 1235 direct_rd_mod_wt = { {0} }; 1236 struct mmsch_v3_0_cmd_direct_polling 1237 direct_poll = { {0} }; 1238 struct mmsch_v3_0_cmd_end end = { {0} }; 1239 struct mmsch_v3_0_init_header header; 1240 1241 direct_wt.cmd_header.command_type = 1242 MMSCH_COMMAND__DIRECT_REG_WRITE; 1243 direct_rd_mod_wt.cmd_header.command_type = 1244 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1245 direct_poll.cmd_header.command_type = 1246 MMSCH_COMMAND__DIRECT_REG_POLLING; 1247 end.cmd_header.command_type = 1248 MMSCH_COMMAND__END; 1249 1250 header.version = MMSCH_VERSION; 1251 header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; 1252 for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES; i++) { 1253 header.inst[i].init_status = 0; 1254 header.inst[i].table_offset = 0; 1255 header.inst[i].table_size = 0; 1256 } 1257 1258 table_loc = (uint32_t *)table->cpu_addr; 1259 table_loc += header.total_size; 1260 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 1261 if (adev->vcn.harvest_config & (1 << i)) 1262 continue; 1263 1264 table_size = 0; 1265 1266 MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i, 1267 mmUVD_STATUS), 1268 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY); 1269 1270 cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1271 1272 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1273 id = amdgpu_ucode_id_vcns[i]; 1274 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1275 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1276 adev->firmware.ucode[id].tmr_mc_addr_lo); 1277 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1278 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1279 adev->firmware.ucode[id].tmr_mc_addr_hi); 1280 offset = 0; 1281 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1282 mmUVD_VCPU_CACHE_OFFSET0), 1283 0); 1284 } else { 1285 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1286 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1287 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 1288 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1289 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1290 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 1291 offset = cache_size; 1292 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1293 mmUVD_VCPU_CACHE_OFFSET0), 1294 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 1295 } 1296 1297 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1298 mmUVD_VCPU_CACHE_SIZE0), 1299 cache_size); 1300 1301 cache_addr = adev->vcn.inst[i].gpu_addr + offset; 1302 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1303 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1304 lower_32_bits(cache_addr)); 1305 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1306 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1307 upper_32_bits(cache_addr)); 1308 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1309 mmUVD_VCPU_CACHE_OFFSET1), 1310 0); 1311 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1312 mmUVD_VCPU_CACHE_SIZE1), 1313 AMDGPU_VCN_STACK_SIZE); 1314 1315 cache_addr = adev->vcn.inst[i].gpu_addr + offset + 1316 AMDGPU_VCN_STACK_SIZE; 1317 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1318 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1319 lower_32_bits(cache_addr)); 1320 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1321 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1322 upper_32_bits(cache_addr)); 1323 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1324 mmUVD_VCPU_CACHE_OFFSET2), 1325 0); 1326 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1327 mmUVD_VCPU_CACHE_SIZE2), 1328 AMDGPU_VCN_CONTEXT_SIZE); 1329 1330 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1331 ring = &adev->vcn.inst[i].ring_enc[j]; 1332 ring->wptr = 0; 1333 rb_addr = ring->gpu_addr; 1334 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1335 mmUVD_RB_BASE_LO), 1336 lower_32_bits(rb_addr)); 1337 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1338 mmUVD_RB_BASE_HI), 1339 upper_32_bits(rb_addr)); 1340 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1341 mmUVD_RB_SIZE), 1342 ring->ring_size / 4); 1343 } 1344 1345 ring = &adev->vcn.inst[i].ring_dec; 1346 ring->wptr = 0; 1347 rb_addr = ring->gpu_addr; 1348 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1349 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1350 lower_32_bits(rb_addr)); 1351 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1352 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1353 upper_32_bits(rb_addr)); 1354 /* force RBC into idle state */ 1355 tmp = order_base_2(ring->ring_size); 1356 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1357 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1358 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1359 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1360 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1361 MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i, 1362 mmUVD_RBC_RB_CNTL), 1363 tmp); 1364 1365 /* add end packet */ 1366 MMSCH_V3_0_INSERT_END(); 1367 1368 /* refine header */ 1369 header.inst[i].init_status = 1; 1370 header.inst[i].table_offset = header.total_size; 1371 header.inst[i].table_size = table_size; 1372 header.total_size += table_size; 1373 } 1374 1375 /* Update init table header in memory */ 1376 size = sizeof(struct mmsch_v3_0_init_header); 1377 table_loc = (uint32_t *)table->cpu_addr; 1378 memcpy((void *)table_loc, &header, size); 1379 1380 /* message MMSCH (in VCN[0]) to initialize this client 1381 * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1382 * of memory descriptor location 1383 */ 1384 ctx_addr = table->gpu_addr; 1385 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); 1386 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); 1387 1388 /* 2, update vmid of descriptor */ 1389 tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); 1390 tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1391 /* use domain0 for MM scheduler */ 1392 tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1393 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp); 1394 1395 /* 3, notify mmsch about the size of this descriptor */ 1396 size = header.total_size; 1397 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); 1398 1399 /* 4, set resp to zero */ 1400 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1401 1402 /* 5, kick off the initialization and wait until 1403 * MMSCH_VF_MAILBOX_RESP becomes non-zero 1404 */ 1405 param = 0x10000001; 1406 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param); 1407 tmp = 0; 1408 timeout = 1000; 1409 resp = 0; 1410 expected = param + 1; 1411 while (resp != expected) { 1412 resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); 1413 if (resp == expected) 1414 break; 1415 1416 udelay(10); 1417 tmp = tmp + 10; 1418 if (tmp >= timeout) { 1419 DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\ 1420 " waiting for mmMMSCH_VF_MAILBOX_RESP "\ 1421 "(expected=0x%08x, readback=0x%08x)\n", 1422 tmp, expected, resp); 1423 return -EBUSY; 1424 } 1425 } 1426 1427 return 0; 1428 } 1429 1430 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) 1431 { 1432 uint32_t tmp; 1433 1434 /* Wait for power status to be 1 */ 1435 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1436 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1437 1438 /* wait for read ptr to be equal to write ptr */ 1439 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); 1440 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1441 1442 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); 1443 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1444 1445 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1446 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1447 1448 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, 1449 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1450 1451 /* disable dynamic power gating mode */ 1452 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, 1453 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1454 1455 return 0; 1456 } 1457 1458 static int vcn_v3_0_stop(struct amdgpu_device *adev) 1459 { 1460 uint32_t tmp; 1461 int i, r = 0; 1462 1463 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1464 if (adev->vcn.harvest_config & (1 << i)) 1465 continue; 1466 1467 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1468 r = vcn_v3_0_stop_dpg_mode(adev, i); 1469 continue; 1470 } 1471 1472 /* wait for vcn idle */ 1473 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1474 if (r) 1475 return r; 1476 1477 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1478 UVD_LMI_STATUS__READ_CLEAN_MASK | 1479 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1480 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1481 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1482 if (r) 1483 return r; 1484 1485 /* disable LMI UMC channel */ 1486 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); 1487 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1488 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); 1489 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1490 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1491 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); 1492 if (r) 1493 return r; 1494 1495 /* block VCPU register access */ 1496 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 1497 UVD_RB_ARB_CTRL__VCPU_DIS_MASK, 1498 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK); 1499 1500 /* reset VCPU */ 1501 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 1502 UVD_VCPU_CNTL__BLK_RST_MASK, 1503 ~UVD_VCPU_CNTL__BLK_RST_MASK); 1504 1505 /* disable VCPU clock */ 1506 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, 1507 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1508 1509 /* apply soft reset */ 1510 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1511 tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1512 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1513 tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET); 1514 tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1515 WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp); 1516 1517 /* clear status */ 1518 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); 1519 1520 /* apply HW clock gating */ 1521 vcn_v3_0_enable_clock_gating(adev, i); 1522 1523 /* enable VCN power gating */ 1524 vcn_v3_0_enable_static_power_gating(adev, i); 1525 } 1526 1527 if (adev->pm.dpm_enabled) 1528 amdgpu_dpm_enable_uvd(adev, false); 1529 1530 return 0; 1531 } 1532 1533 static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, 1534 int inst_idx, struct dpg_pause_state *new_state) 1535 { 1536 struct amdgpu_ring *ring; 1537 uint32_t reg_data = 0; 1538 int ret_code; 1539 1540 /* pause/unpause if state is changed */ 1541 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1542 DRM_DEBUG("dpg pause state changed %d -> %d", 1543 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1544 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & 1545 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1546 1547 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1548 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, 1549 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1550 1551 if (!ret_code) { 1552 /* pause DPG */ 1553 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1554 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1555 1556 /* wait for ACK */ 1557 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, 1558 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1559 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1560 1561 /* Stall DPG before WPTR/RPTR reset */ 1562 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1563 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1564 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1565 1566 /* Restore */ 1567 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 1568 ring->wptr = 0; 1569 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); 1570 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1571 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); 1572 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1573 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1574 1575 ring = &adev->vcn.inst[inst_idx].ring_enc[1]; 1576 ring->wptr = 0; 1577 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1578 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1579 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); 1580 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1581 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1582 1583 /* Unstall DPG */ 1584 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1585 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1586 1587 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1588 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1589 } 1590 } else { 1591 /* unpause dpg, no need to wait */ 1592 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1593 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); 1594 } 1595 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1596 } 1597 1598 return 0; 1599 } 1600 1601 /** 1602 * vcn_v3_0_dec_ring_get_rptr - get read pointer 1603 * 1604 * @ring: amdgpu_ring pointer 1605 * 1606 * Returns the current hardware read pointer 1607 */ 1608 static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1609 { 1610 struct amdgpu_device *adev = ring->adev; 1611 1612 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); 1613 } 1614 1615 /** 1616 * vcn_v3_0_dec_ring_get_wptr - get write pointer 1617 * 1618 * @ring: amdgpu_ring pointer 1619 * 1620 * Returns the current hardware write pointer 1621 */ 1622 static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1623 { 1624 struct amdgpu_device *adev = ring->adev; 1625 1626 if (ring->use_doorbell) 1627 return adev->wb.wb[ring->wptr_offs]; 1628 else 1629 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); 1630 } 1631 1632 /** 1633 * vcn_v3_0_dec_ring_set_wptr - set write pointer 1634 * 1635 * @ring: amdgpu_ring pointer 1636 * 1637 * Commits the write pointer to the hardware 1638 */ 1639 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1640 { 1641 struct amdgpu_device *adev = ring->adev; 1642 1643 if (ring->use_doorbell) { 1644 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1645 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1646 } else { 1647 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1648 } 1649 } 1650 1651 static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { 1652 .type = AMDGPU_RING_TYPE_VCN_DEC, 1653 .align_mask = 0xf, 1654 .vmhub = AMDGPU_MMHUB_0, 1655 .get_rptr = vcn_v3_0_dec_ring_get_rptr, 1656 .get_wptr = vcn_v3_0_dec_ring_get_wptr, 1657 .set_wptr = vcn_v3_0_dec_ring_set_wptr, 1658 .emit_frame_size = 1659 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1660 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1661 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 1662 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 1663 6, 1664 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 1665 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 1666 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 1667 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 1668 .test_ring = vcn_v2_0_dec_ring_test_ring, 1669 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1670 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 1671 .insert_start = vcn_v2_0_dec_ring_insert_start, 1672 .insert_end = vcn_v2_0_dec_ring_insert_end, 1673 .pad_ib = amdgpu_ring_generic_pad_ib, 1674 .begin_use = amdgpu_vcn_ring_begin_use, 1675 .end_use = amdgpu_vcn_ring_end_use, 1676 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 1677 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 1678 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1679 }; 1680 1681 /** 1682 * vcn_v3_0_enc_ring_get_rptr - get enc read pointer 1683 * 1684 * @ring: amdgpu_ring pointer 1685 * 1686 * Returns the current hardware enc read pointer 1687 */ 1688 static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1689 { 1690 struct amdgpu_device *adev = ring->adev; 1691 1692 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) 1693 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); 1694 else 1695 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); 1696 } 1697 1698 /** 1699 * vcn_v3_0_enc_ring_get_wptr - get enc write pointer 1700 * 1701 * @ring: amdgpu_ring pointer 1702 * 1703 * Returns the current hardware enc write pointer 1704 */ 1705 static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1706 { 1707 struct amdgpu_device *adev = ring->adev; 1708 1709 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1710 if (ring->use_doorbell) 1711 return adev->wb.wb[ring->wptr_offs]; 1712 else 1713 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); 1714 } else { 1715 if (ring->use_doorbell) 1716 return adev->wb.wb[ring->wptr_offs]; 1717 else 1718 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); 1719 } 1720 } 1721 1722 /** 1723 * vcn_v3_0_enc_ring_set_wptr - set enc write pointer 1724 * 1725 * @ring: amdgpu_ring pointer 1726 * 1727 * Commits the enc write pointer to the hardware 1728 */ 1729 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1730 { 1731 struct amdgpu_device *adev = ring->adev; 1732 1733 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { 1734 if (ring->use_doorbell) { 1735 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1736 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1737 } else { 1738 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1739 } 1740 } else { 1741 if (ring->use_doorbell) { 1742 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1743 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1744 } else { 1745 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1746 } 1747 } 1748 } 1749 1750 static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { 1751 .type = AMDGPU_RING_TYPE_VCN_ENC, 1752 .align_mask = 0x3f, 1753 .nop = VCN_ENC_CMD_NO_OP, 1754 .vmhub = AMDGPU_MMHUB_0, 1755 .get_rptr = vcn_v3_0_enc_ring_get_rptr, 1756 .get_wptr = vcn_v3_0_enc_ring_get_wptr, 1757 .set_wptr = vcn_v3_0_enc_ring_set_wptr, 1758 .emit_frame_size = 1759 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1760 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1761 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 1762 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 1763 1, /* vcn_v2_0_enc_ring_insert_end */ 1764 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 1765 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 1766 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 1767 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 1768 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1769 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1770 .insert_nop = amdgpu_ring_insert_nop, 1771 .insert_end = vcn_v2_0_enc_ring_insert_end, 1772 .pad_ib = amdgpu_ring_generic_pad_ib, 1773 .begin_use = amdgpu_vcn_ring_begin_use, 1774 .end_use = amdgpu_vcn_ring_end_use, 1775 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 1776 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 1777 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1778 }; 1779 1780 static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1781 { 1782 int i; 1783 1784 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1785 if (adev->vcn.harvest_config & (1 << i)) 1786 continue; 1787 1788 adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; 1789 adev->vcn.inst[i].ring_dec.me = i; 1790 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i); 1791 } 1792 } 1793 1794 static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1795 { 1796 int i, j; 1797 1798 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1799 if (adev->vcn.harvest_config & (1 << i)) 1800 continue; 1801 1802 for (j = 0; j < adev->vcn.num_enc_rings; ++j) { 1803 adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; 1804 adev->vcn.inst[i].ring_enc[j].me = i; 1805 } 1806 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i); 1807 } 1808 } 1809 1810 static bool vcn_v3_0_is_idle(void *handle) 1811 { 1812 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1813 int i, ret = 1; 1814 1815 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1816 if (adev->vcn.harvest_config & (1 << i)) 1817 continue; 1818 1819 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); 1820 } 1821 1822 return ret; 1823 } 1824 1825 static int vcn_v3_0_wait_for_idle(void *handle) 1826 { 1827 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1828 int i, ret = 0; 1829 1830 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1831 if (adev->vcn.harvest_config & (1 << i)) 1832 continue; 1833 1834 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 1835 UVD_STATUS__IDLE); 1836 if (ret) 1837 return ret; 1838 } 1839 1840 return ret; 1841 } 1842 1843 static int vcn_v3_0_set_clockgating_state(void *handle, 1844 enum amd_clockgating_state state) 1845 { 1846 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1847 bool enable = (state == AMD_CG_STATE_GATE) ? true : false; 1848 int i; 1849 1850 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1851 if (adev->vcn.harvest_config & (1 << i)) 1852 continue; 1853 1854 if (enable) { 1855 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) 1856 return -EBUSY; 1857 vcn_v3_0_enable_clock_gating(adev, i); 1858 } else { 1859 vcn_v3_0_disable_clock_gating(adev, i); 1860 } 1861 } 1862 1863 return 0; 1864 } 1865 1866 static int vcn_v3_0_set_powergating_state(void *handle, 1867 enum amd_powergating_state state) 1868 { 1869 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1870 int ret; 1871 1872 /* for SRIOV, guest should not control VCN Power-gating 1873 * MMSCH FW should control Power-gating and clock-gating 1874 * guest should avoid touching CGC and PG 1875 */ 1876 if (amdgpu_sriov_vf(adev)) { 1877 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1878 return 0; 1879 } 1880 1881 if(state == adev->vcn.cur_state) 1882 return 0; 1883 1884 if (state == AMD_PG_STATE_GATE) 1885 ret = vcn_v3_0_stop(adev); 1886 else 1887 ret = vcn_v3_0_start(adev); 1888 1889 if(!ret) 1890 adev->vcn.cur_state = state; 1891 1892 return ret; 1893 } 1894 1895 static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, 1896 struct amdgpu_irq_src *source, 1897 unsigned type, 1898 enum amdgpu_interrupt_state state) 1899 { 1900 return 0; 1901 } 1902 1903 static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, 1904 struct amdgpu_irq_src *source, 1905 struct amdgpu_iv_entry *entry) 1906 { 1907 uint32_t ip_instance; 1908 1909 switch (entry->client_id) { 1910 case SOC15_IH_CLIENTID_VCN: 1911 ip_instance = 0; 1912 break; 1913 case SOC15_IH_CLIENTID_VCN1: 1914 ip_instance = 1; 1915 break; 1916 default: 1917 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1918 return 0; 1919 } 1920 1921 DRM_DEBUG("IH: VCN TRAP\n"); 1922 1923 switch (entry->src_id) { 1924 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1925 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); 1926 break; 1927 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1928 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); 1929 break; 1930 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1931 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); 1932 break; 1933 default: 1934 DRM_ERROR("Unhandled interrupt: %d %d\n", 1935 entry->src_id, entry->src_data[0]); 1936 break; 1937 } 1938 1939 return 0; 1940 } 1941 1942 static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { 1943 .set = vcn_v3_0_set_interrupt_state, 1944 .process = vcn_v3_0_process_interrupt, 1945 }; 1946 1947 static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) 1948 { 1949 int i; 1950 1951 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 1952 if (adev->vcn.harvest_config & (1 << i)) 1953 continue; 1954 1955 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; 1956 adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; 1957 } 1958 } 1959 1960 static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { 1961 .name = "vcn_v3_0", 1962 .early_init = vcn_v3_0_early_init, 1963 .late_init = NULL, 1964 .sw_init = vcn_v3_0_sw_init, 1965 .sw_fini = vcn_v3_0_sw_fini, 1966 .hw_init = vcn_v3_0_hw_init, 1967 .hw_fini = vcn_v3_0_hw_fini, 1968 .suspend = vcn_v3_0_suspend, 1969 .resume = vcn_v3_0_resume, 1970 .is_idle = vcn_v3_0_is_idle, 1971 .wait_for_idle = vcn_v3_0_wait_for_idle, 1972 .check_soft_reset = NULL, 1973 .pre_soft_reset = NULL, 1974 .soft_reset = NULL, 1975 .post_soft_reset = NULL, 1976 .set_clockgating_state = vcn_v3_0_set_clockgating_state, 1977 .set_powergating_state = vcn_v3_0_set_powergating_state, 1978 }; 1979 1980 const struct amdgpu_ip_block_version vcn_v3_0_ip_block = 1981 { 1982 .type = AMD_IP_BLOCK_TYPE_VCN, 1983 .major = 3, 1984 .minor = 0, 1985 .rev = 0, 1986 .funcs = &vcn_v3_0_ip_funcs, 1987 }; 1988