1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "amdgpu_pm.h" 31 #include "amdgpu_psp.h" 32 #include "mmsch_v2_0.h" 33 #include "vcn_v2_0.h" 34 35 #include "vcn/vcn_2_0_0_offset.h" 36 #include "vcn/vcn_2_0_0_sh_mask.h" 37 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" 38 39 #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET 0x1fd 40 #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET 0x503 41 #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET 0x504 42 #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET 0x505 43 #define mmUVD_NO_OP_INTERNAL_OFFSET 0x53f 44 #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET 0x54a 45 #define mmUVD_SCRATCH9_INTERNAL_OFFSET 0xc01d 46 47 #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET 0x1e1 48 #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET 0x5a6 49 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7 50 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2 51 52 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); 53 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev); 54 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev); 55 static int vcn_v2_0_set_powergating_state(void *handle, 56 enum amd_powergating_state state); 57 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 58 int inst_idx, struct dpg_pause_state *new_state); 59 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev); 60 /** 61 * vcn_v2_0_early_init - set function pointers 62 * 63 * @handle: amdgpu_device pointer 64 * 65 * Set ring and irq function pointers 66 */ 67 static int vcn_v2_0_early_init(void *handle) 68 { 69 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 70 71 adev->vcn.num_vcn_inst = 1; 72 if (amdgpu_sriov_vf(adev)) 73 adev->vcn.num_enc_rings = 1; 74 else 75 adev->vcn.num_enc_rings = 2; 76 77 vcn_v2_0_set_dec_ring_funcs(adev); 78 vcn_v2_0_set_enc_ring_funcs(adev); 79 vcn_v2_0_set_irq_funcs(adev); 80 81 return 0; 82 } 83 84 /** 85 * vcn_v2_0_sw_init - sw init for VCN block 86 * 87 * @handle: amdgpu_device pointer 88 * 89 * Load firmware and sw initialization 90 */ 91 static int vcn_v2_0_sw_init(void *handle) 92 { 93 struct amdgpu_ring *ring; 94 int i, r; 95 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 96 volatile struct amdgpu_fw_shared *fw_shared; 97 98 /* VCN DEC TRAP */ 99 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 100 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, 101 &adev->vcn.inst->irq); 102 if (r) 103 return r; 104 105 /* VCN ENC TRAP */ 106 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 107 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 108 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 109 &adev->vcn.inst->irq); 110 if (r) 111 return r; 112 } 113 114 r = amdgpu_vcn_sw_init(adev); 115 if (r) 116 return r; 117 118 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 119 const struct common_firmware_header *hdr; 120 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 121 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 122 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 123 adev->firmware.fw_size += 124 roundup2(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 125 DRM_INFO("PSP loading VCN firmware\n"); 126 } 127 128 r = amdgpu_vcn_resume(adev); 129 if (r) 130 return r; 131 132 ring = &adev->vcn.inst->ring_dec; 133 134 ring->use_doorbell = true; 135 ring->doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1 << 1; 136 137 snprintf(ring->name, sizeof(ring->name), "vcn_dec"); 138 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 139 AMDGPU_RING_PRIO_DEFAULT); 140 if (r) 141 return r; 142 143 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; 144 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; 145 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; 146 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; 147 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; 148 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; 149 150 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; 151 adev->vcn.inst->external.scratch9 = SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 152 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; 153 adev->vcn.inst->external.data0 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 154 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; 155 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 156 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; 157 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 158 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET; 159 adev->vcn.inst->external.nop = SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 160 161 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 162 ring = &adev->vcn.inst->ring_enc[i]; 163 ring->use_doorbell = true; 164 if (!amdgpu_sriov_vf(adev)) 165 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + i; 166 else 167 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + i; 168 snprintf(ring->name, sizeof(ring->name), "vcn_enc%d", i); 169 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 170 AMDGPU_RING_PRIO_DEFAULT); 171 if (r) 172 return r; 173 } 174 175 adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode; 176 177 r = amdgpu_virt_alloc_mm_table(adev); 178 if (r) 179 return r; 180 181 fw_shared = adev->vcn.inst->fw_shared_cpu_addr; 182 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG); 183 return 0; 184 } 185 186 /** 187 * vcn_v2_0_sw_fini - sw fini for VCN block 188 * 189 * @handle: amdgpu_device pointer 190 * 191 * VCN suspend and free up sw allocation 192 */ 193 static int vcn_v2_0_sw_fini(void *handle) 194 { 195 int r; 196 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 197 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr; 198 199 fw_shared->present_flag_0 = 0; 200 201 amdgpu_virt_free_mm_table(adev); 202 203 r = amdgpu_vcn_suspend(adev); 204 if (r) 205 return r; 206 207 r = amdgpu_vcn_sw_fini(adev); 208 209 return r; 210 } 211 212 /** 213 * vcn_v2_0_hw_init - start and test VCN block 214 * 215 * @handle: amdgpu_device pointer 216 * 217 * Initialize the hardware, boot up the VCPU and do some testing 218 */ 219 static int vcn_v2_0_hw_init(void *handle) 220 { 221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 222 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 223 int i, r; 224 225 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, 226 ring->doorbell_index, 0); 227 228 if (amdgpu_sriov_vf(adev)) 229 vcn_v2_0_start_sriov(adev); 230 231 r = amdgpu_ring_test_helper(ring); 232 if (r) 233 goto done; 234 235 //Disable vcn decode for sriov 236 if (amdgpu_sriov_vf(adev)) 237 ring->sched.ready = false; 238 239 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 240 ring = &adev->vcn.inst->ring_enc[i]; 241 r = amdgpu_ring_test_helper(ring); 242 if (r) 243 goto done; 244 } 245 246 done: 247 if (!r) 248 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 249 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 250 251 return r; 252 } 253 254 /** 255 * vcn_v2_0_hw_fini - stop the hardware block 256 * 257 * @handle: amdgpu_device pointer 258 * 259 * Stop the VCN block, mark ring as not ready any more 260 */ 261 static int vcn_v2_0_hw_fini(void *handle) 262 { 263 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 264 265 cancel_delayed_work_sync(&adev->vcn.idle_work); 266 267 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 268 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 269 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) 270 vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 271 272 return 0; 273 } 274 275 /** 276 * vcn_v2_0_suspend - suspend VCN block 277 * 278 * @handle: amdgpu_device pointer 279 * 280 * HW fini and suspend VCN block 281 */ 282 static int vcn_v2_0_suspend(void *handle) 283 { 284 int r; 285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 286 287 r = vcn_v2_0_hw_fini(adev); 288 if (r) 289 return r; 290 291 r = amdgpu_vcn_suspend(adev); 292 293 return r; 294 } 295 296 /** 297 * vcn_v2_0_resume - resume VCN block 298 * 299 * @handle: amdgpu_device pointer 300 * 301 * Resume firmware and hw init VCN block 302 */ 303 static int vcn_v2_0_resume(void *handle) 304 { 305 int r; 306 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 307 308 r = amdgpu_vcn_resume(adev); 309 if (r) 310 return r; 311 312 r = vcn_v2_0_hw_init(adev); 313 314 return r; 315 } 316 317 /** 318 * vcn_v2_0_mc_resume - memory controller programming 319 * 320 * @adev: amdgpu_device pointer 321 * 322 * Let the VCN memory controller know it's offsets 323 */ 324 static void vcn_v2_0_mc_resume(struct amdgpu_device *adev) 325 { 326 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 327 uint32_t offset; 328 329 if (amdgpu_sriov_vf(adev)) 330 return; 331 332 /* cache window 0: fw */ 333 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 334 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 335 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 336 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 337 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 338 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 339 offset = 0; 340 } else { 341 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 342 lower_32_bits(adev->vcn.inst->gpu_addr)); 343 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 344 upper_32_bits(adev->vcn.inst->gpu_addr)); 345 offset = size; 346 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 347 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 348 } 349 350 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 351 352 /* cache window 1: stack */ 353 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 354 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 355 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 356 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 357 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 358 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 359 360 /* cache window 2: context */ 361 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 362 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 363 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 364 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 365 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 366 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 367 368 /* non-cache window */ 369 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, 370 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr)); 371 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, 372 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr)); 373 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0); 374 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0, 375 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared))); 376 377 WREG32_SOC15(UVD, 0, mmUVD_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 378 } 379 380 static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirect) 381 { 382 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 383 uint32_t offset; 384 385 /* cache window 0: fw */ 386 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 387 if (!indirect) { 388 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 389 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 390 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); 391 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 392 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 393 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); 394 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 395 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 396 } else { 397 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 398 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); 399 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 400 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); 401 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 402 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); 403 } 404 offset = 0; 405 } else { 406 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 407 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 408 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 409 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 410 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 411 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 412 offset = size; 413 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 414 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 415 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); 416 } 417 418 if (!indirect) 419 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 420 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); 421 else 422 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 423 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); 424 425 /* cache window 1: stack */ 426 if (!indirect) { 427 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 428 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 429 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 430 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 431 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 432 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 433 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 434 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 435 } else { 436 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 437 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); 438 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 439 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); 440 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 441 UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); 442 } 443 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 444 UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); 445 446 /* cache window 2: context */ 447 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 448 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 449 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 450 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 451 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 452 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); 453 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 454 UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); 455 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 456 UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); 457 458 /* non-cache window */ 459 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 460 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 461 lower_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect); 462 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 463 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 464 upper_32_bits(adev->vcn.inst->fw_shared_gpu_addr), 0, indirect); 465 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 466 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); 467 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 468 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 469 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); 470 471 /* VCN global tiling registers */ 472 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 473 UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); 474 } 475 476 /** 477 * vcn_v2_0_disable_clock_gating - disable VCN clock gating 478 * 479 * @adev: amdgpu_device pointer 480 * @sw: enable SW clock gating 481 * 482 * Disable clock gating for VCN block 483 */ 484 static void vcn_v2_0_disable_clock_gating(struct amdgpu_device *adev) 485 { 486 uint32_t data; 487 488 if (amdgpu_sriov_vf(adev)) 489 return; 490 491 /* UVD disable CGC */ 492 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 493 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 494 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 495 else 496 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 497 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 498 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 499 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 500 501 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 502 data &= ~(UVD_CGC_GATE__SYS_MASK 503 | UVD_CGC_GATE__UDEC_MASK 504 | UVD_CGC_GATE__MPEG2_MASK 505 | UVD_CGC_GATE__REGS_MASK 506 | UVD_CGC_GATE__RBC_MASK 507 | UVD_CGC_GATE__LMI_MC_MASK 508 | UVD_CGC_GATE__LMI_UMC_MASK 509 | UVD_CGC_GATE__IDCT_MASK 510 | UVD_CGC_GATE__MPRD_MASK 511 | UVD_CGC_GATE__MPC_MASK 512 | UVD_CGC_GATE__LBSI_MASK 513 | UVD_CGC_GATE__LRBBM_MASK 514 | UVD_CGC_GATE__UDEC_RE_MASK 515 | UVD_CGC_GATE__UDEC_CM_MASK 516 | UVD_CGC_GATE__UDEC_IT_MASK 517 | UVD_CGC_GATE__UDEC_DB_MASK 518 | UVD_CGC_GATE__UDEC_MP_MASK 519 | UVD_CGC_GATE__WCB_MASK 520 | UVD_CGC_GATE__VCPU_MASK 521 | UVD_CGC_GATE__SCPU_MASK); 522 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 523 524 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 525 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 526 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 527 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 528 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 529 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 530 | UVD_CGC_CTRL__SYS_MODE_MASK 531 | UVD_CGC_CTRL__UDEC_MODE_MASK 532 | UVD_CGC_CTRL__MPEG2_MODE_MASK 533 | UVD_CGC_CTRL__REGS_MODE_MASK 534 | UVD_CGC_CTRL__RBC_MODE_MASK 535 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 536 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 537 | UVD_CGC_CTRL__IDCT_MODE_MASK 538 | UVD_CGC_CTRL__MPRD_MODE_MASK 539 | UVD_CGC_CTRL__MPC_MODE_MASK 540 | UVD_CGC_CTRL__LBSI_MODE_MASK 541 | UVD_CGC_CTRL__LRBBM_MODE_MASK 542 | UVD_CGC_CTRL__WCB_MODE_MASK 543 | UVD_CGC_CTRL__VCPU_MODE_MASK 544 | UVD_CGC_CTRL__SCPU_MODE_MASK); 545 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 546 547 /* turn on */ 548 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 549 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 550 | UVD_SUVD_CGC_GATE__SIT_MASK 551 | UVD_SUVD_CGC_GATE__SMP_MASK 552 | UVD_SUVD_CGC_GATE__SCM_MASK 553 | UVD_SUVD_CGC_GATE__SDB_MASK 554 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 555 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 556 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 557 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 558 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 559 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 560 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 561 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 562 | UVD_SUVD_CGC_GATE__SCLR_MASK 563 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 564 | UVD_SUVD_CGC_GATE__ENT_MASK 565 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 566 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 567 | UVD_SUVD_CGC_GATE__SITE_MASK 568 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 569 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 570 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 571 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 572 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 573 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 574 575 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 576 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 577 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 578 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 579 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 580 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 581 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 582 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 583 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 584 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 585 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 586 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 587 } 588 589 static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev, 590 uint8_t sram_sel, uint8_t indirect) 591 { 592 uint32_t reg_data = 0; 593 594 /* enable sw clock gating control */ 595 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 596 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 597 else 598 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 599 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 600 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 601 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 602 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 603 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 604 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 605 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 606 UVD_CGC_CTRL__SYS_MODE_MASK | 607 UVD_CGC_CTRL__UDEC_MODE_MASK | 608 UVD_CGC_CTRL__MPEG2_MODE_MASK | 609 UVD_CGC_CTRL__REGS_MODE_MASK | 610 UVD_CGC_CTRL__RBC_MODE_MASK | 611 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 612 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 613 UVD_CGC_CTRL__IDCT_MODE_MASK | 614 UVD_CGC_CTRL__MPRD_MODE_MASK | 615 UVD_CGC_CTRL__MPC_MODE_MASK | 616 UVD_CGC_CTRL__LBSI_MODE_MASK | 617 UVD_CGC_CTRL__LRBBM_MODE_MASK | 618 UVD_CGC_CTRL__WCB_MODE_MASK | 619 UVD_CGC_CTRL__VCPU_MODE_MASK | 620 UVD_CGC_CTRL__SCPU_MODE_MASK); 621 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 622 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); 623 624 /* turn off clock gating */ 625 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 626 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); 627 628 /* turn on SUVD clock gating */ 629 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 630 UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); 631 632 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 633 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 634 UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); 635 } 636 637 /** 638 * vcn_v2_0_enable_clock_gating - enable VCN clock gating 639 * 640 * @adev: amdgpu_device pointer 641 * @sw: enable SW clock gating 642 * 643 * Enable clock gating for VCN block 644 */ 645 static void vcn_v2_0_enable_clock_gating(struct amdgpu_device *adev) 646 { 647 uint32_t data = 0; 648 649 if (amdgpu_sriov_vf(adev)) 650 return; 651 652 /* enable UVD CGC */ 653 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 654 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 655 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 656 else 657 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 658 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 659 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 660 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 661 662 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 663 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 664 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 665 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 666 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 667 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 668 | UVD_CGC_CTRL__SYS_MODE_MASK 669 | UVD_CGC_CTRL__UDEC_MODE_MASK 670 | UVD_CGC_CTRL__MPEG2_MODE_MASK 671 | UVD_CGC_CTRL__REGS_MODE_MASK 672 | UVD_CGC_CTRL__RBC_MODE_MASK 673 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 674 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 675 | UVD_CGC_CTRL__IDCT_MODE_MASK 676 | UVD_CGC_CTRL__MPRD_MODE_MASK 677 | UVD_CGC_CTRL__MPC_MODE_MASK 678 | UVD_CGC_CTRL__LBSI_MODE_MASK 679 | UVD_CGC_CTRL__LRBBM_MODE_MASK 680 | UVD_CGC_CTRL__WCB_MODE_MASK 681 | UVD_CGC_CTRL__VCPU_MODE_MASK 682 | UVD_CGC_CTRL__SCPU_MODE_MASK); 683 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 684 685 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 686 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 687 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 688 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 689 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 690 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 691 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 692 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 693 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 694 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 695 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 696 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 697 } 698 699 static void vcn_v2_0_disable_static_power_gating(struct amdgpu_device *adev) 700 { 701 uint32_t data = 0; 702 703 if (amdgpu_sriov_vf(adev)) 704 return; 705 706 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 707 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 708 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 709 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 710 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 711 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 712 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 713 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 714 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 715 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 716 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 717 718 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 719 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 720 UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0, 0xFFFFF); 721 } else { 722 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 723 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 724 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 725 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 726 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 727 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 728 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 729 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 730 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 731 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 732 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 733 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF); 734 } 735 736 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS, 737 * UVDU_PWR_STATUS are 0 (power on) */ 738 739 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 740 data &= ~0x103; 741 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 742 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | 743 UVD_POWER_STATUS__UVD_PG_EN_MASK; 744 745 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 746 } 747 748 static void vcn_v2_0_enable_static_power_gating(struct amdgpu_device *adev) 749 { 750 uint32_t data = 0; 751 752 if (amdgpu_sriov_vf(adev)) 753 return; 754 755 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 756 /* Before power off, this indicator has to be turned on */ 757 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 758 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 759 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 760 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 761 762 763 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 764 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 765 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 766 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 767 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 768 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 769 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 770 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 771 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 772 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT); 773 774 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 775 776 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 777 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 778 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 779 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 780 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 781 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 782 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 783 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 784 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 785 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT); 786 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF); 787 } 788 } 789 790 static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect) 791 { 792 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr; 793 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 794 uint32_t rb_bufsz, tmp; 795 796 vcn_v2_0_enable_static_power_gating(adev); 797 798 /* enable dynamic power gating mode */ 799 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 800 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 801 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 802 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 803 804 if (indirect) 805 adev->vcn.inst->dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst->dpg_sram_cpu_addr; 806 807 /* enable clock gating */ 808 vcn_v2_0_clock_gating_dpg_mode(adev, 0, indirect); 809 810 /* enable VCPU clock */ 811 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 812 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 813 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 814 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 815 UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); 816 817 /* disable master interupt */ 818 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 819 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); 820 821 /* setup mmUVD_LMI_CTRL */ 822 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 823 UVD_LMI_CTRL__REQ_MODE_MASK | 824 UVD_LMI_CTRL__CRC_RESET_MASK | 825 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 826 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 827 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 828 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 829 0x00100000L); 830 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 831 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); 832 833 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 834 UVD, 0, mmUVD_MPC_CNTL), 835 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect); 836 837 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 838 UVD, 0, mmUVD_MPC_SET_MUXA0), 839 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 840 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 841 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 842 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 843 844 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 845 UVD, 0, mmUVD_MPC_SET_MUXB0), 846 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 847 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 848 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 849 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect); 850 851 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 852 UVD, 0, mmUVD_MPC_SET_MUX), 853 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 854 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 855 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect); 856 857 vcn_v2_0_mc_resume_dpg_mode(adev, indirect); 858 859 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 860 UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); 861 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 862 UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); 863 864 /* release VCPU reset to boot */ 865 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 866 UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect); 867 868 /* enable LMI MC and UMC channels */ 869 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 870 UVD, 0, mmUVD_LMI_CTRL2), 871 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect); 872 873 /* enable master interrupt */ 874 WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( 875 UVD, 0, mmUVD_MASTINT_EN), 876 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect); 877 878 if (indirect) 879 psp_update_vcn_sram(adev, 0, adev->vcn.inst->dpg_sram_gpu_addr, 880 (uint32_t)((uintptr_t)adev->vcn.inst->dpg_sram_curr_addr - 881 (uintptr_t)adev->vcn.inst->dpg_sram_cpu_addr)); 882 883 /* force RBC into idle state */ 884 rb_bufsz = order_base_2(ring->ring_size); 885 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 886 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 887 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 888 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 889 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 890 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 891 892 /* Stall DPG before WPTR/RPTR reset */ 893 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 894 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 895 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 896 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 897 898 /* set the write pointer delay */ 899 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 900 901 /* set the wb address */ 902 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 903 (upper_32_bits(ring->gpu_addr) >> 2)); 904 905 /* program the RB_BASE for ring buffer */ 906 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 907 lower_32_bits(ring->gpu_addr)); 908 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 909 upper_32_bits(ring->gpu_addr)); 910 911 /* Initialize the ring buffer's read and write pointers */ 912 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 913 914 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 915 916 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 917 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 918 lower_32_bits(ring->wptr)); 919 920 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 921 /* Unstall DPG */ 922 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 923 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 924 return 0; 925 } 926 927 static int vcn_v2_0_start(struct amdgpu_device *adev) 928 { 929 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr; 930 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 931 uint32_t rb_bufsz, tmp; 932 uint32_t lmi_swap_cntl; 933 int i, j, r; 934 935 if (adev->pm.dpm_enabled) 936 amdgpu_dpm_enable_uvd(adev, true); 937 938 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 939 return vcn_v2_0_start_dpg_mode(adev, adev->vcn.indirect_sram); 940 941 vcn_v2_0_disable_static_power_gating(adev); 942 943 /* set uvd status busy */ 944 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 945 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 946 947 /*SW clock gating */ 948 vcn_v2_0_disable_clock_gating(adev); 949 950 /* enable VCPU clock */ 951 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 952 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK); 953 954 /* disable master interrupt */ 955 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 956 ~UVD_MASTINT_EN__VCPU_EN_MASK); 957 958 /* setup mmUVD_LMI_CTRL */ 959 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 960 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 961 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 962 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 963 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 964 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 965 966 /* setup mmUVD_MPC_CNTL */ 967 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 968 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 969 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 970 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); 971 972 /* setup UVD_MPC_SET_MUXA0 */ 973 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 974 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 975 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 976 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 977 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 978 979 /* setup UVD_MPC_SET_MUXB0 */ 980 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 981 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 982 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 983 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 984 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 985 986 /* setup mmUVD_MPC_SET_MUX */ 987 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 988 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 989 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 990 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 991 992 vcn_v2_0_mc_resume(adev); 993 994 /* release VCPU reset to boot */ 995 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 996 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 997 998 /* enable LMI MC and UMC channels */ 999 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 1000 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1001 1002 tmp = RREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET); 1003 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 1004 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 1005 WREG32_SOC15(VCN, 0, mmUVD_SOFT_RESET, tmp); 1006 1007 /* disable byte swapping */ 1008 lmi_swap_cntl = 0; 1009 #ifdef __BIG_ENDIAN 1010 /* swap (8 in 32) RB and IB */ 1011 lmi_swap_cntl = 0xa; 1012 #endif 1013 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1014 1015 for (i = 0; i < 10; ++i) { 1016 uint32_t status; 1017 1018 for (j = 0; j < 100; ++j) { 1019 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 1020 if (status & 2) 1021 break; 1022 mdelay(10); 1023 } 1024 r = 0; 1025 if (status & 2) 1026 break; 1027 1028 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 1029 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1030 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1031 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1032 mdelay(10); 1033 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 1034 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1035 mdelay(10); 1036 r = -1; 1037 } 1038 1039 if (r) { 1040 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 1041 return r; 1042 } 1043 1044 /* enable master interrupt */ 1045 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 1046 UVD_MASTINT_EN__VCPU_EN_MASK, 1047 ~UVD_MASTINT_EN__VCPU_EN_MASK); 1048 1049 /* clear the busy bit of VCN_STATUS */ 1050 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, 1051 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1052 1053 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_VMID, 0); 1054 1055 /* force RBC into idle state */ 1056 rb_bufsz = order_base_2(ring->ring_size); 1057 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1058 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1059 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1060 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1061 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1062 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1063 1064 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1065 /* program the RB_BASE for ring buffer */ 1066 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1067 lower_32_bits(ring->gpu_addr)); 1068 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1069 upper_32_bits(ring->gpu_addr)); 1070 1071 /* Initialize the ring buffer's read and write pointers */ 1072 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1073 1074 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1075 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1076 lower_32_bits(ring->wptr)); 1077 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1078 1079 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1080 ring = &adev->vcn.inst->ring_enc[0]; 1081 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1082 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1083 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1084 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1085 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1086 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1087 1088 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1089 ring = &adev->vcn.inst->ring_enc[1]; 1090 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1091 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1092 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1093 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1094 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1095 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1096 1097 return 0; 1098 } 1099 1100 static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev) 1101 { 1102 uint32_t tmp; 1103 1104 /* Wait for power status to be 1 */ 1105 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1106 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1107 1108 /* wait for read ptr to be equal to write ptr */ 1109 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1110 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1111 1112 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1113 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1114 1115 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1116 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1117 1118 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, 1119 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1120 1121 /* disable dynamic power gating mode */ 1122 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1123 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1124 1125 return 0; 1126 } 1127 1128 static int vcn_v2_0_stop(struct amdgpu_device *adev) 1129 { 1130 uint32_t tmp; 1131 int r; 1132 1133 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1134 r = vcn_v2_0_stop_dpg_mode(adev); 1135 if (r) 1136 return r; 1137 goto power_off; 1138 } 1139 1140 /* wait for uvd idle */ 1141 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1142 if (r) 1143 return r; 1144 1145 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1146 UVD_LMI_STATUS__READ_CLEAN_MASK | 1147 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1148 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1149 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); 1150 if (r) 1151 return r; 1152 1153 /* stall UMC channel */ 1154 tmp = RREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2); 1155 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK; 1156 WREG32_SOC15(VCN, 0, mmUVD_LMI_CTRL2, tmp); 1157 1158 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK| 1159 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1160 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); 1161 if (r) 1162 return r; 1163 1164 /* disable VCPU clock */ 1165 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1166 ~(UVD_VCPU_CNTL__CLK_EN_MASK)); 1167 1168 /* reset LMI UMC */ 1169 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1170 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1171 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1172 1173 /* reset LMI */ 1174 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1175 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1176 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1177 1178 /* reset VCPU */ 1179 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1180 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1181 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1182 1183 /* clear status */ 1184 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); 1185 1186 vcn_v2_0_enable_clock_gating(adev); 1187 vcn_v2_0_enable_static_power_gating(adev); 1188 1189 power_off: 1190 if (adev->pm.dpm_enabled) 1191 amdgpu_dpm_enable_uvd(adev, false); 1192 1193 return 0; 1194 } 1195 1196 static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev, 1197 int inst_idx, struct dpg_pause_state *new_state) 1198 { 1199 struct amdgpu_ring *ring; 1200 uint32_t reg_data = 0; 1201 int ret_code; 1202 1203 /* pause/unpause if state is changed */ 1204 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1205 DRM_DEBUG("dpg pause state changed %d -> %d", 1206 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); 1207 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1208 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1209 1210 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1211 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1, 1212 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1213 1214 if (!ret_code) { 1215 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared_cpu_addr; 1216 /* pause DPG */ 1217 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1218 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1219 1220 /* wait for ACK */ 1221 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1222 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1223 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1224 1225 /* Stall DPG before WPTR/RPTR reset */ 1226 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1227 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK, 1228 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1229 /* Restore */ 1230 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET; 1231 ring = &adev->vcn.inst->ring_enc[0]; 1232 ring->wptr = 0; 1233 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1234 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1235 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1236 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1237 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1238 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET; 1239 1240 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET; 1241 ring = &adev->vcn.inst->ring_enc[1]; 1242 ring->wptr = 0; 1243 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1244 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1245 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1246 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1247 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1248 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET; 1249 1250 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET; 1251 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1252 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1253 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET; 1254 /* Unstall DPG */ 1255 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 1256 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK); 1257 1258 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1259 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1260 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1261 } 1262 } else { 1263 /* unpause dpg, no need to wait */ 1264 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1265 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1266 } 1267 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1268 } 1269 1270 return 0; 1271 } 1272 1273 static bool vcn_v2_0_is_idle(void *handle) 1274 { 1275 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1276 1277 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1278 } 1279 1280 static int vcn_v2_0_wait_for_idle(void *handle) 1281 { 1282 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1283 int ret; 1284 1285 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1286 UVD_STATUS__IDLE); 1287 1288 return ret; 1289 } 1290 1291 static int vcn_v2_0_set_clockgating_state(void *handle, 1292 enum amd_clockgating_state state) 1293 { 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1295 bool enable = (state == AMD_CG_STATE_GATE); 1296 1297 if (amdgpu_sriov_vf(adev)) 1298 return 0; 1299 1300 if (enable) { 1301 /* wait for STATUS to clear */ 1302 if (!vcn_v2_0_is_idle(handle)) 1303 return -EBUSY; 1304 vcn_v2_0_enable_clock_gating(adev); 1305 } else { 1306 /* disable HW gating and enable Sw gating */ 1307 vcn_v2_0_disable_clock_gating(adev); 1308 } 1309 return 0; 1310 } 1311 1312 /** 1313 * vcn_v2_0_dec_ring_get_rptr - get read pointer 1314 * 1315 * @ring: amdgpu_ring pointer 1316 * 1317 * Returns the current hardware read pointer 1318 */ 1319 static uint64_t vcn_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1320 { 1321 struct amdgpu_device *adev = ring->adev; 1322 1323 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1324 } 1325 1326 /** 1327 * vcn_v2_0_dec_ring_get_wptr - get write pointer 1328 * 1329 * @ring: amdgpu_ring pointer 1330 * 1331 * Returns the current hardware write pointer 1332 */ 1333 static uint64_t vcn_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1334 { 1335 struct amdgpu_device *adev = ring->adev; 1336 1337 if (ring->use_doorbell) 1338 return adev->wb.wb[ring->wptr_offs]; 1339 else 1340 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1341 } 1342 1343 /** 1344 * vcn_v2_0_dec_ring_set_wptr - set write pointer 1345 * 1346 * @ring: amdgpu_ring pointer 1347 * 1348 * Commits the write pointer to the hardware 1349 */ 1350 static void vcn_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1351 { 1352 struct amdgpu_device *adev = ring->adev; 1353 1354 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1355 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1356 lower_32_bits(ring->wptr) | 0x80000000); 1357 1358 if (ring->use_doorbell) { 1359 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1360 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1361 } else { 1362 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1363 } 1364 } 1365 1366 /** 1367 * vcn_v2_0_dec_ring_insert_start - insert a start command 1368 * 1369 * @ring: amdgpu_ring pointer 1370 * 1371 * Write a start command to the ring. 1372 */ 1373 void vcn_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1374 { 1375 struct amdgpu_device *adev = ring->adev; 1376 1377 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1378 amdgpu_ring_write(ring, 0); 1379 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1380 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1381 } 1382 1383 /** 1384 * vcn_v2_0_dec_ring_insert_end - insert a end command 1385 * 1386 * @ring: amdgpu_ring pointer 1387 * 1388 * Write a end command to the ring. 1389 */ 1390 void vcn_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1391 { 1392 struct amdgpu_device *adev = ring->adev; 1393 1394 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1395 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1)); 1396 } 1397 1398 /** 1399 * vcn_v2_0_dec_ring_insert_nop - insert a nop command 1400 * 1401 * @ring: amdgpu_ring pointer 1402 * 1403 * Write a nop command to the ring. 1404 */ 1405 void vcn_v2_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1406 { 1407 struct amdgpu_device *adev = ring->adev; 1408 int i; 1409 1410 WARN_ON(ring->wptr % 2 || count % 2); 1411 1412 for (i = 0; i < count / 2; i++) { 1413 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0)); 1414 amdgpu_ring_write(ring, 0); 1415 } 1416 } 1417 1418 /** 1419 * vcn_v2_0_dec_ring_emit_fence - emit an fence & trap command 1420 * 1421 * @ring: amdgpu_ring pointer 1422 * @fence: fence to emit 1423 * 1424 * Write a fence and a trap command to the ring. 1425 */ 1426 void vcn_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1427 unsigned flags) 1428 { 1429 struct amdgpu_device *adev = ring->adev; 1430 1431 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1432 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0)); 1433 amdgpu_ring_write(ring, seq); 1434 1435 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1436 amdgpu_ring_write(ring, addr & 0xffffffff); 1437 1438 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1439 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1440 1441 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1442 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_FENCE << 1)); 1443 1444 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1445 amdgpu_ring_write(ring, 0); 1446 1447 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1448 amdgpu_ring_write(ring, 0); 1449 1450 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1451 1452 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_TRAP << 1)); 1453 } 1454 1455 /** 1456 * vcn_v2_0_dec_ring_emit_ib - execute indirect buffer 1457 * 1458 * @ring: amdgpu_ring pointer 1459 * @ib: indirect buffer to execute 1460 * 1461 * Write ring commands to execute the indirect buffer 1462 */ 1463 void vcn_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1464 struct amdgpu_job *job, 1465 struct amdgpu_ib *ib, 1466 uint32_t flags) 1467 { 1468 struct amdgpu_device *adev = ring->adev; 1469 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1470 1471 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_vmid, 0)); 1472 amdgpu_ring_write(ring, vmid); 1473 1474 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_low, 0)); 1475 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1476 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_bar_high, 0)); 1477 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1478 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.ib_size, 0)); 1479 amdgpu_ring_write(ring, ib->length_dw); 1480 } 1481 1482 void vcn_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1483 uint32_t val, uint32_t mask) 1484 { 1485 struct amdgpu_device *adev = ring->adev; 1486 1487 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1488 amdgpu_ring_write(ring, reg << 2); 1489 1490 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1491 amdgpu_ring_write(ring, val); 1492 1493 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.gp_scratch8, 0)); 1494 amdgpu_ring_write(ring, mask); 1495 1496 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1497 1498 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_REG_READ_COND_WAIT << 1)); 1499 } 1500 1501 void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1502 unsigned vmid, uint64_t pd_addr) 1503 { 1504 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1505 uint32_t data0, data1, mask; 1506 1507 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1508 1509 /* wait for register write */ 1510 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1511 data1 = lower_32_bits(pd_addr); 1512 mask = 0xffffffff; 1513 vcn_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1514 } 1515 1516 void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1517 uint32_t reg, uint32_t val) 1518 { 1519 struct amdgpu_device *adev = ring->adev; 1520 1521 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0)); 1522 amdgpu_ring_write(ring, reg << 2); 1523 1524 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0)); 1525 amdgpu_ring_write(ring, val); 1526 1527 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1528 1529 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_WRITE_REG << 1)); 1530 } 1531 1532 /** 1533 * vcn_v2_0_enc_ring_get_rptr - get enc read pointer 1534 * 1535 * @ring: amdgpu_ring pointer 1536 * 1537 * Returns the current hardware enc read pointer 1538 */ 1539 static uint64_t vcn_v2_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1540 { 1541 struct amdgpu_device *adev = ring->adev; 1542 1543 if (ring == &adev->vcn.inst->ring_enc[0]) 1544 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1545 else 1546 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1547 } 1548 1549 /** 1550 * vcn_v2_0_enc_ring_get_wptr - get enc write pointer 1551 * 1552 * @ring: amdgpu_ring pointer 1553 * 1554 * Returns the current hardware enc write pointer 1555 */ 1556 static uint64_t vcn_v2_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1557 { 1558 struct amdgpu_device *adev = ring->adev; 1559 1560 if (ring == &adev->vcn.inst->ring_enc[0]) { 1561 if (ring->use_doorbell) 1562 return adev->wb.wb[ring->wptr_offs]; 1563 else 1564 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1565 } else { 1566 if (ring->use_doorbell) 1567 return adev->wb.wb[ring->wptr_offs]; 1568 else 1569 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1570 } 1571 } 1572 1573 /** 1574 * vcn_v2_0_enc_ring_set_wptr - set enc write pointer 1575 * 1576 * @ring: amdgpu_ring pointer 1577 * 1578 * Commits the enc write pointer to the hardware 1579 */ 1580 static void vcn_v2_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1581 { 1582 struct amdgpu_device *adev = ring->adev; 1583 1584 if (ring == &adev->vcn.inst->ring_enc[0]) { 1585 if (ring->use_doorbell) { 1586 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1587 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1588 } else { 1589 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1590 } 1591 } else { 1592 if (ring->use_doorbell) { 1593 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 1594 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 1595 } else { 1596 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1597 } 1598 } 1599 } 1600 1601 /** 1602 * vcn_v2_0_enc_ring_emit_fence - emit an enc fence & trap command 1603 * 1604 * @ring: amdgpu_ring pointer 1605 * @fence: fence to emit 1606 * 1607 * Write enc a fence and a trap command to the ring. 1608 */ 1609 void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1610 u64 seq, unsigned flags) 1611 { 1612 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1613 1614 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1615 amdgpu_ring_write(ring, addr); 1616 amdgpu_ring_write(ring, upper_32_bits(addr)); 1617 amdgpu_ring_write(ring, seq); 1618 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1619 } 1620 1621 void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1622 { 1623 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1624 } 1625 1626 /** 1627 * vcn_v2_0_enc_ring_emit_ib - enc execute indirect buffer 1628 * 1629 * @ring: amdgpu_ring pointer 1630 * @ib: indirect buffer to execute 1631 * 1632 * Write enc ring commands to execute the indirect buffer 1633 */ 1634 void vcn_v2_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1635 struct amdgpu_job *job, 1636 struct amdgpu_ib *ib, 1637 uint32_t flags) 1638 { 1639 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1640 1641 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1642 amdgpu_ring_write(ring, vmid); 1643 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1644 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1645 amdgpu_ring_write(ring, ib->length_dw); 1646 } 1647 1648 void vcn_v2_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1649 uint32_t val, uint32_t mask) 1650 { 1651 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1652 amdgpu_ring_write(ring, reg << 2); 1653 amdgpu_ring_write(ring, mask); 1654 amdgpu_ring_write(ring, val); 1655 } 1656 1657 void vcn_v2_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1658 unsigned int vmid, uint64_t pd_addr) 1659 { 1660 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1661 1662 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1663 1664 /* wait for reg writes */ 1665 vcn_v2_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1666 vmid * hub->ctx_addr_distance, 1667 lower_32_bits(pd_addr), 0xffffffff); 1668 } 1669 1670 void vcn_v2_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val) 1671 { 1672 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1673 amdgpu_ring_write(ring, reg << 2); 1674 amdgpu_ring_write(ring, val); 1675 } 1676 1677 static int vcn_v2_0_set_interrupt_state(struct amdgpu_device *adev, 1678 struct amdgpu_irq_src *source, 1679 unsigned type, 1680 enum amdgpu_interrupt_state state) 1681 { 1682 return 0; 1683 } 1684 1685 static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev, 1686 struct amdgpu_irq_src *source, 1687 struct amdgpu_iv_entry *entry) 1688 { 1689 DRM_DEBUG("IH: VCN TRAP\n"); 1690 1691 switch (entry->src_id) { 1692 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT: 1693 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1694 break; 1695 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE: 1696 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1697 break; 1698 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY: 1699 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1700 break; 1701 default: 1702 DRM_ERROR("Unhandled interrupt: %d %d\n", 1703 entry->src_id, entry->src_data[0]); 1704 break; 1705 } 1706 1707 return 0; 1708 } 1709 1710 int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring) 1711 { 1712 struct amdgpu_device *adev = ring->adev; 1713 uint32_t tmp = 0; 1714 unsigned i; 1715 int r; 1716 1717 if (amdgpu_sriov_vf(adev)) 1718 return 0; 1719 1720 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD); 1721 r = amdgpu_ring_alloc(ring, 4); 1722 if (r) 1723 return r; 1724 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0)); 1725 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1)); 1726 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0)); 1727 amdgpu_ring_write(ring, 0xDEADBEEF); 1728 amdgpu_ring_commit(ring); 1729 for (i = 0; i < adev->usec_timeout; i++) { 1730 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9); 1731 if (tmp == 0xDEADBEEF) 1732 break; 1733 udelay(1); 1734 } 1735 1736 if (i >= adev->usec_timeout) 1737 r = -ETIMEDOUT; 1738 1739 return r; 1740 } 1741 1742 1743 static int vcn_v2_0_set_powergating_state(void *handle, 1744 enum amd_powergating_state state) 1745 { 1746 /* This doesn't actually powergate the VCN block. 1747 * That's done in the dpm code via the SMC. This 1748 * just re-inits the block as necessary. The actual 1749 * gating still happens in the dpm code. We should 1750 * revisit this when there is a cleaner line between 1751 * the smc and the hw blocks 1752 */ 1753 int ret; 1754 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1755 1756 if (amdgpu_sriov_vf(adev)) { 1757 adev->vcn.cur_state = AMD_PG_STATE_UNGATE; 1758 return 0; 1759 } 1760 1761 if (state == adev->vcn.cur_state) 1762 return 0; 1763 1764 if (state == AMD_PG_STATE_GATE) 1765 ret = vcn_v2_0_stop(adev); 1766 else 1767 ret = vcn_v2_0_start(adev); 1768 1769 if (!ret) 1770 adev->vcn.cur_state = state; 1771 return ret; 1772 } 1773 1774 static int vcn_v2_0_start_mmsch(struct amdgpu_device *adev, 1775 struct amdgpu_mm_table *table) 1776 { 1777 uint32_t data = 0, loop; 1778 uint64_t addr = table->gpu_addr; 1779 struct mmsch_v2_0_init_header *header; 1780 uint32_t size; 1781 int i; 1782 1783 header = (struct mmsch_v2_0_init_header *)table->cpu_addr; 1784 size = header->header_size + header->vcn_table_size; 1785 1786 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr 1787 * of memory descriptor location 1788 */ 1789 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 1790 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 1791 1792 /* 2, update vmid of descriptor */ 1793 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID); 1794 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK; 1795 /* use domain0 for MM scheduler */ 1796 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); 1797 WREG32_SOC15(UVD, 0, mmMMSCH_VF_VMID, data); 1798 1799 /* 3, notify mmsch about the size of this descriptor */ 1800 WREG32_SOC15(UVD, 0, mmMMSCH_VF_CTX_SIZE, size); 1801 1802 /* 4, set resp to zero */ 1803 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP, 0); 1804 1805 adev->vcn.inst->ring_dec.wptr = 0; 1806 adev->vcn.inst->ring_dec.wptr_old = 0; 1807 vcn_v2_0_dec_ring_set_wptr(&adev->vcn.inst->ring_dec); 1808 1809 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 1810 adev->vcn.inst->ring_enc[i].wptr = 0; 1811 adev->vcn.inst->ring_enc[i].wptr_old = 0; 1812 vcn_v2_0_enc_ring_set_wptr(&adev->vcn.inst->ring_enc[i]); 1813 } 1814 1815 /* 5, kick off the initialization and wait until 1816 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero 1817 */ 1818 WREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); 1819 1820 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); 1821 loop = 1000; 1822 while ((data & 0x10000002) != 0x10000002) { 1823 udelay(10); 1824 data = RREG32_SOC15(UVD, 0, mmMMSCH_VF_MAILBOX_RESP); 1825 loop--; 1826 if (!loop) 1827 break; 1828 } 1829 1830 if (!loop) { 1831 DRM_ERROR("failed to init MMSCH, " \ 1832 "mmMMSCH_VF_MAILBOX_RESP = 0x%08x\n", data); 1833 return -EBUSY; 1834 } 1835 1836 return 0; 1837 } 1838 1839 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) 1840 { 1841 int r; 1842 uint32_t tmp; 1843 struct amdgpu_ring *ring; 1844 uint32_t offset, size; 1845 uint32_t table_size = 0; 1846 struct mmsch_v2_0_cmd_direct_write direct_wt = { {0} }; 1847 struct mmsch_v2_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 1848 struct mmsch_v2_0_cmd_end end = { {0} }; 1849 struct mmsch_v2_0_init_header *header; 1850 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 1851 uint8_t i = 0; 1852 1853 header = (struct mmsch_v2_0_init_header *)init_table; 1854 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 1855 direct_rd_mod_wt.cmd_header.command_type = 1856 MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 1857 end.cmd_header.command_type = MMSCH_COMMAND__END; 1858 1859 if (header->vcn_table_offset == 0 && header->vcn_table_size == 0) { 1860 header->version = MMSCH_VERSION; 1861 header->header_size = sizeof(struct mmsch_v2_0_init_header) >> 2; 1862 1863 header->vcn_table_offset = header->header_size; 1864 1865 init_table += header->vcn_table_offset; 1866 1867 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 1868 1869 MMSCH_V2_0_INSERT_DIRECT_RD_MOD_WT( 1870 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 1871 0xFFFFFFFF, 0x00000004); 1872 1873 /* mc resume*/ 1874 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1875 tmp = AMDGPU_UCODE_ID_VCN; 1876 MMSCH_V2_0_INSERT_DIRECT_WT( 1877 SOC15_REG_OFFSET(UVD, i, 1878 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1879 adev->firmware.ucode[tmp].tmr_mc_addr_lo); 1880 MMSCH_V2_0_INSERT_DIRECT_WT( 1881 SOC15_REG_OFFSET(UVD, i, 1882 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1883 adev->firmware.ucode[tmp].tmr_mc_addr_hi); 1884 offset = 0; 1885 } else { 1886 MMSCH_V2_0_INSERT_DIRECT_WT( 1887 SOC15_REG_OFFSET(UVD, i, 1888 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 1889 lower_32_bits(adev->vcn.inst->gpu_addr)); 1890 MMSCH_V2_0_INSERT_DIRECT_WT( 1891 SOC15_REG_OFFSET(UVD, i, 1892 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 1893 upper_32_bits(adev->vcn.inst->gpu_addr)); 1894 offset = size; 1895 } 1896 1897 MMSCH_V2_0_INSERT_DIRECT_WT( 1898 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0), 1899 0); 1900 MMSCH_V2_0_INSERT_DIRECT_WT( 1901 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), 1902 size); 1903 1904 MMSCH_V2_0_INSERT_DIRECT_WT( 1905 SOC15_REG_OFFSET(UVD, i, 1906 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 1907 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 1908 MMSCH_V2_0_INSERT_DIRECT_WT( 1909 SOC15_REG_OFFSET(UVD, i, 1910 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 1911 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 1912 MMSCH_V2_0_INSERT_DIRECT_WT( 1913 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), 1914 0); 1915 MMSCH_V2_0_INSERT_DIRECT_WT( 1916 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), 1917 AMDGPU_VCN_STACK_SIZE); 1918 1919 MMSCH_V2_0_INSERT_DIRECT_WT( 1920 SOC15_REG_OFFSET(UVD, i, 1921 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 1922 lower_32_bits(adev->vcn.inst->gpu_addr + offset + 1923 AMDGPU_VCN_STACK_SIZE)); 1924 MMSCH_V2_0_INSERT_DIRECT_WT( 1925 SOC15_REG_OFFSET(UVD, i, 1926 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 1927 upper_32_bits(adev->vcn.inst->gpu_addr + offset + 1928 AMDGPU_VCN_STACK_SIZE)); 1929 MMSCH_V2_0_INSERT_DIRECT_WT( 1930 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), 1931 0); 1932 MMSCH_V2_0_INSERT_DIRECT_WT( 1933 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 1934 AMDGPU_VCN_CONTEXT_SIZE); 1935 1936 for (r = 0; r < adev->vcn.num_enc_rings; ++r) { 1937 ring = &adev->vcn.inst->ring_enc[r]; 1938 ring->wptr = 0; 1939 MMSCH_V2_0_INSERT_DIRECT_WT( 1940 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), 1941 lower_32_bits(ring->gpu_addr)); 1942 MMSCH_V2_0_INSERT_DIRECT_WT( 1943 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), 1944 upper_32_bits(ring->gpu_addr)); 1945 MMSCH_V2_0_INSERT_DIRECT_WT( 1946 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), 1947 ring->ring_size / 4); 1948 } 1949 1950 ring = &adev->vcn.inst->ring_dec; 1951 ring->wptr = 0; 1952 MMSCH_V2_0_INSERT_DIRECT_WT( 1953 SOC15_REG_OFFSET(UVD, i, 1954 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW), 1955 lower_32_bits(ring->gpu_addr)); 1956 MMSCH_V2_0_INSERT_DIRECT_WT( 1957 SOC15_REG_OFFSET(UVD, i, 1958 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH), 1959 upper_32_bits(ring->gpu_addr)); 1960 /* force RBC into idle state */ 1961 tmp = order_base_2(ring->ring_size); 1962 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp); 1963 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1964 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1965 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1966 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1967 MMSCH_V2_0_INSERT_DIRECT_WT( 1968 SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 1969 1970 /* add end packet */ 1971 tmp = sizeof(struct mmsch_v2_0_cmd_end); 1972 memcpy((void *)init_table, &end, tmp); 1973 table_size += (tmp / 4); 1974 header->vcn_table_size = table_size; 1975 1976 } 1977 return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table); 1978 } 1979 1980 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { 1981 .name = "vcn_v2_0", 1982 .early_init = vcn_v2_0_early_init, 1983 .late_init = NULL, 1984 .sw_init = vcn_v2_0_sw_init, 1985 .sw_fini = vcn_v2_0_sw_fini, 1986 .hw_init = vcn_v2_0_hw_init, 1987 .hw_fini = vcn_v2_0_hw_fini, 1988 .suspend = vcn_v2_0_suspend, 1989 .resume = vcn_v2_0_resume, 1990 .is_idle = vcn_v2_0_is_idle, 1991 .wait_for_idle = vcn_v2_0_wait_for_idle, 1992 .check_soft_reset = NULL, 1993 .pre_soft_reset = NULL, 1994 .soft_reset = NULL, 1995 .post_soft_reset = NULL, 1996 .set_clockgating_state = vcn_v2_0_set_clockgating_state, 1997 .set_powergating_state = vcn_v2_0_set_powergating_state, 1998 }; 1999 2000 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { 2001 .type = AMDGPU_RING_TYPE_VCN_DEC, 2002 .align_mask = 0xf, 2003 .vmhub = AMDGPU_MMHUB_0, 2004 .get_rptr = vcn_v2_0_dec_ring_get_rptr, 2005 .get_wptr = vcn_v2_0_dec_ring_get_wptr, 2006 .set_wptr = vcn_v2_0_dec_ring_set_wptr, 2007 .emit_frame_size = 2008 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 2009 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 2010 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ 2011 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ 2012 6, 2013 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ 2014 .emit_ib = vcn_v2_0_dec_ring_emit_ib, 2015 .emit_fence = vcn_v2_0_dec_ring_emit_fence, 2016 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, 2017 .test_ring = vcn_v2_0_dec_ring_test_ring, 2018 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2019 .insert_nop = vcn_v2_0_dec_ring_insert_nop, 2020 .insert_start = vcn_v2_0_dec_ring_insert_start, 2021 .insert_end = vcn_v2_0_dec_ring_insert_end, 2022 .pad_ib = amdgpu_ring_generic_pad_ib, 2023 .begin_use = amdgpu_vcn_ring_begin_use, 2024 .end_use = amdgpu_vcn_ring_end_use, 2025 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, 2026 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, 2027 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2028 }; 2029 2030 static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { 2031 .type = AMDGPU_RING_TYPE_VCN_ENC, 2032 .align_mask = 0x3f, 2033 .nop = VCN_ENC_CMD_NO_OP, 2034 .vmhub = AMDGPU_MMHUB_0, 2035 .get_rptr = vcn_v2_0_enc_ring_get_rptr, 2036 .get_wptr = vcn_v2_0_enc_ring_get_wptr, 2037 .set_wptr = vcn_v2_0_enc_ring_set_wptr, 2038 .emit_frame_size = 2039 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2040 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2041 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ 2042 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ 2043 1, /* vcn_v2_0_enc_ring_insert_end */ 2044 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ 2045 .emit_ib = vcn_v2_0_enc_ring_emit_ib, 2046 .emit_fence = vcn_v2_0_enc_ring_emit_fence, 2047 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, 2048 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2049 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2050 .insert_nop = amdgpu_ring_insert_nop, 2051 .insert_end = vcn_v2_0_enc_ring_insert_end, 2052 .pad_ib = amdgpu_ring_generic_pad_ib, 2053 .begin_use = amdgpu_vcn_ring_begin_use, 2054 .end_use = amdgpu_vcn_ring_end_use, 2055 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, 2056 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, 2057 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2058 }; 2059 2060 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2061 { 2062 adev->vcn.inst->ring_dec.funcs = &vcn_v2_0_dec_ring_vm_funcs; 2063 DRM_INFO("VCN decode is enabled in VM mode\n"); 2064 } 2065 2066 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2067 { 2068 int i; 2069 2070 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 2071 adev->vcn.inst->ring_enc[i].funcs = &vcn_v2_0_enc_ring_vm_funcs; 2072 2073 DRM_INFO("VCN encode is enabled in VM mode\n"); 2074 } 2075 2076 static const struct amdgpu_irq_src_funcs vcn_v2_0_irq_funcs = { 2077 .set = vcn_v2_0_set_interrupt_state, 2078 .process = vcn_v2_0_process_interrupt, 2079 }; 2080 2081 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev) 2082 { 2083 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 1; 2084 adev->vcn.inst->irq.funcs = &vcn_v2_0_irq_funcs; 2085 } 2086 2087 const struct amdgpu_ip_block_version vcn_v2_0_ip_block = 2088 { 2089 .type = AMD_IP_BLOCK_TYPE_VCN, 2090 .major = 2, 2091 .minor = 0, 2092 .rev = 0, 2093 .funcs = &vcn_v2_0_ip_funcs, 2094 }; 2095