1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_cs.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "soc15_common.h" 33 34 #include "vcn/vcn_1_0_offset.h" 35 #include "vcn/vcn_1_0_sh_mask.h" 36 #include "mmhub/mmhub_9_1_offset.h" 37 #include "mmhub/mmhub_9_1_sh_mask.h" 38 39 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 40 #include "jpeg_v1_0.h" 41 #include "vcn_v1_0.h" 42 43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab 44 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1 45 #define mmUVD_REG_XX_MASK_1_0 0x05ac 46 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1 47 48 static int vcn_v1_0_stop(struct amdgpu_device *adev); 49 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 50 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 51 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 52 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); 53 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 54 int inst_idx, struct dpg_pause_state *new_state); 55 56 static void vcn_v1_0_idle_work_handler(struct work_struct *work); 57 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring); 58 59 /** 60 * vcn_v1_0_early_init - set function pointers and load microcode 61 * 62 * @handle: amdgpu_device pointer 63 * 64 * Set ring and irq function pointers 65 * Load microcode from filesystem 66 */ 67 static int vcn_v1_0_early_init(void *handle) 68 { 69 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 70 71 adev->vcn.num_enc_rings = 2; 72 73 vcn_v1_0_set_dec_ring_funcs(adev); 74 vcn_v1_0_set_enc_ring_funcs(adev); 75 vcn_v1_0_set_irq_funcs(adev); 76 77 jpeg_v1_0_early_init(handle); 78 79 return amdgpu_vcn_early_init(adev); 80 } 81 82 /** 83 * vcn_v1_0_sw_init - sw init for VCN block 84 * 85 * @handle: amdgpu_device pointer 86 * 87 * Load firmware and sw initialization 88 */ 89 static int vcn_v1_0_sw_init(void *handle) 90 { 91 struct amdgpu_ring *ring; 92 int i, r; 93 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 94 95 /* VCN DEC TRAP */ 96 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 97 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq); 98 if (r) 99 return r; 100 101 /* VCN ENC TRAP */ 102 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 103 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 104 &adev->vcn.inst->irq); 105 if (r) 106 return r; 107 } 108 109 r = amdgpu_vcn_sw_init(adev); 110 if (r) 111 return r; 112 113 /* Override the work func */ 114 #ifdef __linux__ 115 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler; 116 #else 117 task_set(&adev->vcn.idle_work.work.task, 118 (void (*)(void *))vcn_v1_0_idle_work_handler, 119 &adev->vcn.idle_work.work); 120 #endif 121 122 amdgpu_vcn_setup_ucode(adev); 123 124 r = amdgpu_vcn_resume(adev); 125 if (r) 126 return r; 127 128 ring = &adev->vcn.inst->ring_dec; 129 ring->vm_hub = AMDGPU_MMHUB0(0); 130 snprintf(ring->name, sizeof(ring->name), "vcn_dec"); 131 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 132 AMDGPU_RING_PRIO_DEFAULT, NULL); 133 if (r) 134 return r; 135 136 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 = 137 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 138 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 = 139 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 140 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 = 141 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 142 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd = 143 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 144 adev->vcn.internal.nop = adev->vcn.inst->external.nop = 145 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 146 147 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 148 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 149 150 ring = &adev->vcn.inst->ring_enc[i]; 151 ring->vm_hub = AMDGPU_MMHUB0(0); 152 snprintf(ring->name, sizeof(ring->name), "vcn_enc%d", i); 153 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 154 hw_prio, NULL); 155 if (r) 156 return r; 157 } 158 159 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode; 160 161 if (amdgpu_vcnfw_log) { 162 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 163 164 fw_shared->present_flag_0 = 0; 165 amdgpu_vcn_fwlog_init(adev->vcn.inst); 166 } 167 168 r = jpeg_v1_0_sw_init(handle); 169 170 return r; 171 } 172 173 /** 174 * vcn_v1_0_sw_fini - sw fini for VCN block 175 * 176 * @handle: amdgpu_device pointer 177 * 178 * VCN suspend and free up sw allocation 179 */ 180 static int vcn_v1_0_sw_fini(void *handle) 181 { 182 int r; 183 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 184 185 r = amdgpu_vcn_suspend(adev); 186 if (r) 187 return r; 188 189 jpeg_v1_0_sw_fini(handle); 190 191 r = amdgpu_vcn_sw_fini(adev); 192 193 return r; 194 } 195 196 /** 197 * vcn_v1_0_hw_init - start and test VCN block 198 * 199 * @handle: amdgpu_device pointer 200 * 201 * Initialize the hardware, boot up the VCPU and do some testing 202 */ 203 static int vcn_v1_0_hw_init(void *handle) 204 { 205 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 206 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 207 int i, r; 208 209 r = amdgpu_ring_test_helper(ring); 210 if (r) 211 goto done; 212 213 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 214 ring = &adev->vcn.inst->ring_enc[i]; 215 r = amdgpu_ring_test_helper(ring); 216 if (r) 217 goto done; 218 } 219 220 ring = adev->jpeg.inst->ring_dec; 221 r = amdgpu_ring_test_helper(ring); 222 if (r) 223 goto done; 224 225 done: 226 if (!r) 227 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 228 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 229 230 return r; 231 } 232 233 /** 234 * vcn_v1_0_hw_fini - stop the hardware block 235 * 236 * @handle: amdgpu_device pointer 237 * 238 * Stop the VCN block, mark ring as not ready any more 239 */ 240 static int vcn_v1_0_hw_fini(void *handle) 241 { 242 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 243 244 cancel_delayed_work_sync(&adev->vcn.idle_work); 245 246 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 247 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 248 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { 249 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 250 } 251 252 return 0; 253 } 254 255 /** 256 * vcn_v1_0_suspend - suspend VCN block 257 * 258 * @handle: amdgpu_device pointer 259 * 260 * HW fini and suspend VCN block 261 */ 262 static int vcn_v1_0_suspend(void *handle) 263 { 264 int r; 265 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 266 bool idle_work_unexecuted; 267 268 idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work); 269 if (idle_work_unexecuted) { 270 if (adev->pm.dpm_enabled) 271 amdgpu_dpm_enable_uvd(adev, false); 272 } 273 274 r = vcn_v1_0_hw_fini(adev); 275 if (r) 276 return r; 277 278 r = amdgpu_vcn_suspend(adev); 279 280 return r; 281 } 282 283 /** 284 * vcn_v1_0_resume - resume VCN block 285 * 286 * @handle: amdgpu_device pointer 287 * 288 * Resume firmware and hw init VCN block 289 */ 290 static int vcn_v1_0_resume(void *handle) 291 { 292 int r; 293 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 294 295 r = amdgpu_vcn_resume(adev); 296 if (r) 297 return r; 298 299 r = vcn_v1_0_hw_init(adev); 300 301 return r; 302 } 303 304 /** 305 * vcn_v1_0_mc_resume_spg_mode - memory controller programming 306 * 307 * @adev: amdgpu_device pointer 308 * 309 * Let the VCN memory controller know it's offsets 310 */ 311 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 312 { 313 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 314 uint32_t offset; 315 316 /* cache window 0: fw */ 317 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 318 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 319 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 320 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 321 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 322 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 323 offset = 0; 324 } else { 325 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 326 lower_32_bits(adev->vcn.inst->gpu_addr)); 327 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 328 upper_32_bits(adev->vcn.inst->gpu_addr)); 329 offset = size; 330 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 331 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 332 } 333 334 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 335 336 /* cache window 1: stack */ 337 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 338 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 339 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 340 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 341 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 342 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 343 344 /* cache window 2: context */ 345 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 346 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 347 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 348 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 349 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 350 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 351 352 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 353 adev->gfx.config.gb_addr_config); 354 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 355 adev->gfx.config.gb_addr_config); 356 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 357 adev->gfx.config.gb_addr_config); 358 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 359 adev->gfx.config.gb_addr_config); 360 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 361 adev->gfx.config.gb_addr_config); 362 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 363 adev->gfx.config.gb_addr_config); 364 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 365 adev->gfx.config.gb_addr_config); 366 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 367 adev->gfx.config.gb_addr_config); 368 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 369 adev->gfx.config.gb_addr_config); 370 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 371 adev->gfx.config.gb_addr_config); 372 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 373 adev->gfx.config.gb_addr_config); 374 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 375 adev->gfx.config.gb_addr_config); 376 } 377 378 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 379 { 380 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 381 uint32_t offset; 382 383 /* cache window 0: fw */ 384 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 385 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 386 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 387 0xFFFFFFFF, 0); 388 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 389 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 390 0xFFFFFFFF, 0); 391 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, 392 0xFFFFFFFF, 0); 393 offset = 0; 394 } else { 395 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 396 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 397 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 398 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 399 offset = size; 400 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 401 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); 402 } 403 404 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); 405 406 /* cache window 1: stack */ 407 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 408 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 409 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 410 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 411 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, 412 0xFFFFFFFF, 0); 413 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, 414 0xFFFFFFFF, 0); 415 416 /* cache window 2: context */ 417 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 418 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 419 0xFFFFFFFF, 0); 420 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 421 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 422 0xFFFFFFFF, 0); 423 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); 424 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 425 0xFFFFFFFF, 0); 426 427 /* VCN global tiling registers */ 428 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 429 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 430 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 431 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 432 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 433 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 434 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 435 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 436 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 437 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 438 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 439 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 440 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 441 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 442 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 443 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 444 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 445 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 446 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 447 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 448 } 449 450 /** 451 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 452 * 453 * @adev: amdgpu_device pointer 454 * 455 * Disable clock gating for VCN block 456 */ 457 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) 458 { 459 uint32_t data; 460 461 /* JPEG disable CGC */ 462 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 463 464 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 465 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 466 else 467 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 468 469 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 470 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 471 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 472 473 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 474 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 475 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 476 477 /* UVD disable CGC */ 478 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 479 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 480 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 481 else 482 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 483 484 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 485 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 486 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 487 488 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 489 data &= ~(UVD_CGC_GATE__SYS_MASK 490 | UVD_CGC_GATE__UDEC_MASK 491 | UVD_CGC_GATE__MPEG2_MASK 492 | UVD_CGC_GATE__REGS_MASK 493 | UVD_CGC_GATE__RBC_MASK 494 | UVD_CGC_GATE__LMI_MC_MASK 495 | UVD_CGC_GATE__LMI_UMC_MASK 496 | UVD_CGC_GATE__IDCT_MASK 497 | UVD_CGC_GATE__MPRD_MASK 498 | UVD_CGC_GATE__MPC_MASK 499 | UVD_CGC_GATE__LBSI_MASK 500 | UVD_CGC_GATE__LRBBM_MASK 501 | UVD_CGC_GATE__UDEC_RE_MASK 502 | UVD_CGC_GATE__UDEC_CM_MASK 503 | UVD_CGC_GATE__UDEC_IT_MASK 504 | UVD_CGC_GATE__UDEC_DB_MASK 505 | UVD_CGC_GATE__UDEC_MP_MASK 506 | UVD_CGC_GATE__WCB_MASK 507 | UVD_CGC_GATE__VCPU_MASK 508 | UVD_CGC_GATE__SCPU_MASK); 509 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 510 511 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 512 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 513 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 514 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 515 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 516 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 517 | UVD_CGC_CTRL__SYS_MODE_MASK 518 | UVD_CGC_CTRL__UDEC_MODE_MASK 519 | UVD_CGC_CTRL__MPEG2_MODE_MASK 520 | UVD_CGC_CTRL__REGS_MODE_MASK 521 | UVD_CGC_CTRL__RBC_MODE_MASK 522 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 523 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 524 | UVD_CGC_CTRL__IDCT_MODE_MASK 525 | UVD_CGC_CTRL__MPRD_MODE_MASK 526 | UVD_CGC_CTRL__MPC_MODE_MASK 527 | UVD_CGC_CTRL__LBSI_MODE_MASK 528 | UVD_CGC_CTRL__LRBBM_MODE_MASK 529 | UVD_CGC_CTRL__WCB_MODE_MASK 530 | UVD_CGC_CTRL__VCPU_MODE_MASK 531 | UVD_CGC_CTRL__SCPU_MODE_MASK); 532 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 533 534 /* turn on */ 535 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 536 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 537 | UVD_SUVD_CGC_GATE__SIT_MASK 538 | UVD_SUVD_CGC_GATE__SMP_MASK 539 | UVD_SUVD_CGC_GATE__SCM_MASK 540 | UVD_SUVD_CGC_GATE__SDB_MASK 541 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 542 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 543 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 544 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 545 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 546 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 547 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 548 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 549 | UVD_SUVD_CGC_GATE__SCLR_MASK 550 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 551 | UVD_SUVD_CGC_GATE__ENT_MASK 552 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 553 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 554 | UVD_SUVD_CGC_GATE__SITE_MASK 555 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 556 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 557 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 558 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 559 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 560 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 561 562 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 563 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 564 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 565 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 566 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 567 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 568 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 569 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 570 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 571 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 572 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 573 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 574 } 575 576 /** 577 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 578 * 579 * @adev: amdgpu_device pointer 580 * 581 * Enable clock gating for VCN block 582 */ 583 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) 584 { 585 uint32_t data = 0; 586 587 /* enable JPEG CGC */ 588 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 589 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 590 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 591 else 592 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 593 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 594 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 595 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 596 597 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 598 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 599 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 600 601 /* enable UVD CGC */ 602 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 603 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 604 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 605 else 606 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 607 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 608 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 609 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 610 611 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 612 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 613 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 614 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 615 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 616 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 617 | UVD_CGC_CTRL__SYS_MODE_MASK 618 | UVD_CGC_CTRL__UDEC_MODE_MASK 619 | UVD_CGC_CTRL__MPEG2_MODE_MASK 620 | UVD_CGC_CTRL__REGS_MODE_MASK 621 | UVD_CGC_CTRL__RBC_MODE_MASK 622 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 623 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 624 | UVD_CGC_CTRL__IDCT_MODE_MASK 625 | UVD_CGC_CTRL__MPRD_MODE_MASK 626 | UVD_CGC_CTRL__MPC_MODE_MASK 627 | UVD_CGC_CTRL__LBSI_MODE_MASK 628 | UVD_CGC_CTRL__LRBBM_MODE_MASK 629 | UVD_CGC_CTRL__WCB_MODE_MASK 630 | UVD_CGC_CTRL__VCPU_MODE_MASK 631 | UVD_CGC_CTRL__SCPU_MODE_MASK); 632 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 633 634 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 635 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 636 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 637 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 638 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 639 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 640 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 641 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 642 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 643 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 644 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 645 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 646 } 647 648 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) 649 { 650 uint32_t reg_data = 0; 651 652 /* disable JPEG CGC */ 653 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 654 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 655 else 656 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 657 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 658 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 659 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 660 661 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 662 663 /* enable sw clock gating control */ 664 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 665 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 666 else 667 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 668 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 669 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 670 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 671 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 672 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 673 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 674 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 675 UVD_CGC_CTRL__SYS_MODE_MASK | 676 UVD_CGC_CTRL__UDEC_MODE_MASK | 677 UVD_CGC_CTRL__MPEG2_MODE_MASK | 678 UVD_CGC_CTRL__REGS_MODE_MASK | 679 UVD_CGC_CTRL__RBC_MODE_MASK | 680 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 681 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 682 UVD_CGC_CTRL__IDCT_MODE_MASK | 683 UVD_CGC_CTRL__MPRD_MODE_MASK | 684 UVD_CGC_CTRL__MPC_MODE_MASK | 685 UVD_CGC_CTRL__LBSI_MODE_MASK | 686 UVD_CGC_CTRL__LRBBM_MODE_MASK | 687 UVD_CGC_CTRL__WCB_MODE_MASK | 688 UVD_CGC_CTRL__VCPU_MODE_MASK | 689 UVD_CGC_CTRL__SCPU_MODE_MASK); 690 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 691 692 /* turn off clock gating */ 693 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 694 695 /* turn on SUVD clock gating */ 696 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); 697 698 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 699 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); 700 } 701 702 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 703 { 704 uint32_t data = 0; 705 706 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 707 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 708 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 709 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 710 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 711 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 712 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 713 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 714 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 715 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 716 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 717 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 718 719 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 720 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF); 721 } else { 722 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 723 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 724 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 725 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 726 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 727 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 728 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 729 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 730 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 731 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 732 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 733 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 734 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF); 735 } 736 737 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ 738 739 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 740 data &= ~0x103; 741 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 742 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; 743 744 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 745 } 746 747 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 748 { 749 uint32_t data = 0; 750 751 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 752 /* Before power off, this indicator has to be turned on */ 753 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 754 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 755 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 756 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 757 758 759 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 760 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 761 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 762 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 763 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 764 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 765 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 766 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 767 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 768 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 769 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 770 771 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 772 773 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 774 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 775 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 776 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 777 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 778 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 779 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 780 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 781 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 782 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 783 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); 784 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF); 785 } 786 } 787 788 /** 789 * vcn_v1_0_start_spg_mode - start VCN block 790 * 791 * @adev: amdgpu_device pointer 792 * 793 * Setup and start the VCN block 794 */ 795 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 796 { 797 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 798 uint32_t rb_bufsz, tmp; 799 uint32_t lmi_swap_cntl; 800 int i, j, r; 801 802 /* disable byte swapping */ 803 lmi_swap_cntl = 0; 804 805 vcn_1_0_disable_static_power_gating(adev); 806 807 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 808 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 809 810 /* disable clock gating */ 811 vcn_v1_0_disable_clock_gating(adev); 812 813 /* disable interupt */ 814 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 815 ~UVD_MASTINT_EN__VCPU_EN_MASK); 816 817 /* initialize VCN memory controller */ 818 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 819 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 820 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 821 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 822 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 823 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 824 825 #ifdef __BIG_ENDIAN 826 /* swap (8 in 32) RB and IB */ 827 lmi_swap_cntl = 0xa; 828 #endif 829 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 830 831 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 832 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 833 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 834 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); 835 836 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 837 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 838 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 839 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 840 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 841 842 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 843 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 844 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 845 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 846 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 847 848 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 849 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 850 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 851 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 852 853 vcn_v1_0_mc_resume_spg_mode(adev); 854 855 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10); 856 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0, 857 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3); 858 859 /* enable VCPU clock */ 860 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 861 862 /* boot up the VCPU */ 863 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 864 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 865 866 /* enable UMC */ 867 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 868 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 869 870 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 871 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 872 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 873 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 874 875 for (i = 0; i < 10; ++i) { 876 uint32_t status; 877 878 for (j = 0; j < 100; ++j) { 879 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 880 if (status & UVD_STATUS__IDLE) 881 break; 882 mdelay(10); 883 } 884 r = 0; 885 if (status & UVD_STATUS__IDLE) 886 break; 887 888 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 889 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 890 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 891 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 892 mdelay(10); 893 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 894 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 895 mdelay(10); 896 r = -1; 897 } 898 899 if (r) { 900 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 901 return r; 902 } 903 /* enable master interrupt */ 904 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 905 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); 906 907 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 908 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 909 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 910 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 911 912 /* clear the busy bit of UVD_STATUS */ 913 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; 914 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 915 916 /* force RBC into idle state */ 917 rb_bufsz = order_base_2(ring->ring_size); 918 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 919 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 920 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 921 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 922 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 923 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 924 925 /* set the write pointer delay */ 926 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 927 928 /* set the wb address */ 929 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 930 (upper_32_bits(ring->gpu_addr) >> 2)); 931 932 /* program the RB_BASE for ring buffer */ 933 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 934 lower_32_bits(ring->gpu_addr)); 935 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 936 upper_32_bits(ring->gpu_addr)); 937 938 /* Initialize the ring buffer's read and write pointers */ 939 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 940 941 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 942 943 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 944 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 945 lower_32_bits(ring->wptr)); 946 947 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 948 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 949 950 ring = &adev->vcn.inst->ring_enc[0]; 951 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 952 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 953 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 954 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 955 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 956 957 ring = &adev->vcn.inst->ring_enc[1]; 958 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 959 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 960 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 961 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 962 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 963 964 jpeg_v1_0_start(adev, 0); 965 966 return 0; 967 } 968 969 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 970 { 971 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 972 uint32_t rb_bufsz, tmp; 973 uint32_t lmi_swap_cntl; 974 975 /* disable byte swapping */ 976 lmi_swap_cntl = 0; 977 978 vcn_1_0_enable_static_power_gating(adev); 979 980 /* enable dynamic power gating mode */ 981 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 982 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 983 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 984 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 985 986 /* enable clock gating */ 987 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 988 989 /* enable VCPU clock */ 990 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 991 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 992 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 993 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); 994 995 /* disable interupt */ 996 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, 997 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 998 999 /* initialize VCN memory controller */ 1000 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, 1001 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1002 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1003 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1004 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1005 UVD_LMI_CTRL__REQ_MODE_MASK | 1006 UVD_LMI_CTRL__CRC_RESET_MASK | 1007 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1008 0x00100000L, 0xFFFFFFFF, 0); 1009 1010 #ifdef __BIG_ENDIAN 1011 /* swap (8 in 32) RB and IB */ 1012 lmi_swap_cntl = 0xa; 1013 #endif 1014 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 1015 1016 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL, 1017 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); 1018 1019 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0, 1020 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1021 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1022 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1023 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); 1024 1025 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0, 1026 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1027 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1028 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1029 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); 1030 1031 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX, 1032 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1033 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1034 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); 1035 1036 vcn_v1_0_mc_resume_dpg_mode(adev); 1037 1038 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); 1039 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); 1040 1041 /* boot up the VCPU */ 1042 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1043 1044 /* enable UMC */ 1045 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2, 1046 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 1047 0xFFFFFFFF, 0); 1048 1049 /* enable master interrupt */ 1050 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, 1051 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 1052 1053 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1054 /* setup mmUVD_LMI_CTRL */ 1055 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, 1056 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1057 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1058 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1059 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1060 UVD_LMI_CTRL__REQ_MODE_MASK | 1061 UVD_LMI_CTRL__CRC_RESET_MASK | 1062 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1063 0x00100000L, 0xFFFFFFFF, 1); 1064 1065 tmp = adev->gfx.config.gb_addr_config; 1066 /* setup VCN global tiling registers */ 1067 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1068 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1069 1070 /* enable System Interrupt for JRBC */ 1071 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN, 1072 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); 1073 1074 /* force RBC into idle state */ 1075 rb_bufsz = order_base_2(ring->ring_size); 1076 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1077 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1078 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1079 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1080 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1081 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1082 1083 /* set the write pointer delay */ 1084 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1085 1086 /* set the wb address */ 1087 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1088 (upper_32_bits(ring->gpu_addr) >> 2)); 1089 1090 /* program the RB_BASE for ring buffer */ 1091 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1092 lower_32_bits(ring->gpu_addr)); 1093 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1094 upper_32_bits(ring->gpu_addr)); 1095 1096 /* Initialize the ring buffer's read and write pointers */ 1097 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1098 1099 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1100 1101 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1102 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1103 lower_32_bits(ring->wptr)); 1104 1105 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 1106 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1107 1108 jpeg_v1_0_start(adev, 1); 1109 1110 return 0; 1111 } 1112 1113 static int vcn_v1_0_start(struct amdgpu_device *adev) 1114 { 1115 return (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ? 1116 vcn_v1_0_start_dpg_mode(adev) : vcn_v1_0_start_spg_mode(adev); 1117 } 1118 1119 /** 1120 * vcn_v1_0_stop_spg_mode - stop VCN block 1121 * 1122 * @adev: amdgpu_device pointer 1123 * 1124 * stop the VCN block 1125 */ 1126 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1127 { 1128 int tmp; 1129 1130 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1131 1132 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1133 UVD_LMI_STATUS__READ_CLEAN_MASK | 1134 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1135 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1136 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); 1137 1138 /* stall UMC channel */ 1139 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 1140 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1141 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1142 1143 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1144 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1145 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); 1146 1147 /* disable VCPU clock */ 1148 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1149 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1150 1151 /* reset LMI UMC/LMI */ 1152 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1153 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1154 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1155 1156 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1157 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1158 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1159 1160 /* put VCPU into reset */ 1161 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1162 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1163 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1164 1165 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); 1166 1167 vcn_v1_0_enable_clock_gating(adev); 1168 vcn_1_0_enable_static_power_gating(adev); 1169 return 0; 1170 } 1171 1172 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1173 { 1174 uint32_t tmp; 1175 1176 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1177 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1178 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1179 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1180 1181 /* wait for read ptr to be equal to write ptr */ 1182 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1183 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1184 1185 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1186 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1187 1188 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1189 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF); 1190 1191 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1192 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1193 1194 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1195 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1196 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1197 1198 /* disable dynamic power gating mode */ 1199 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1200 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1201 1202 return 0; 1203 } 1204 1205 static int vcn_v1_0_stop(struct amdgpu_device *adev) 1206 { 1207 int r; 1208 1209 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1210 r = vcn_v1_0_stop_dpg_mode(adev); 1211 else 1212 r = vcn_v1_0_stop_spg_mode(adev); 1213 1214 return r; 1215 } 1216 1217 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 1218 int inst_idx, struct dpg_pause_state *new_state) 1219 { 1220 int ret_code; 1221 uint32_t reg_data = 0; 1222 uint32_t reg_data2 = 0; 1223 struct amdgpu_ring *ring; 1224 1225 /* pause/unpause if state is changed */ 1226 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1227 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1228 adev->vcn.inst[inst_idx].pause_state.fw_based, 1229 adev->vcn.inst[inst_idx].pause_state.jpeg, 1230 new_state->fw_based, new_state->jpeg); 1231 1232 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1233 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1234 1235 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1236 ret_code = 0; 1237 1238 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) 1239 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1240 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1241 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1242 1243 if (!ret_code) { 1244 /* pause DPG non-jpeg */ 1245 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1246 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1247 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1248 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1249 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1250 1251 /* Restore */ 1252 ring = &adev->vcn.inst->ring_enc[0]; 1253 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1254 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1255 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1256 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1257 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1258 1259 ring = &adev->vcn.inst->ring_enc[1]; 1260 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1261 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1262 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1263 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1264 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1265 1266 ring = &adev->vcn.inst->ring_dec; 1267 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1268 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1269 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1270 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1271 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1272 } 1273 } else { 1274 /* unpause dpg non-jpeg, no need to wait */ 1275 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1276 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1277 } 1278 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1279 } 1280 1281 /* pause/unpause if state is changed */ 1282 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { 1283 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1284 adev->vcn.inst[inst_idx].pause_state.fw_based, 1285 adev->vcn.inst[inst_idx].pause_state.jpeg, 1286 new_state->fw_based, new_state->jpeg); 1287 1288 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1289 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1290 1291 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { 1292 ret_code = 0; 1293 1294 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) 1295 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1296 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1297 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1298 1299 if (!ret_code) { 1300 /* Make sure JPRG Snoop is disabled before sending the pause */ 1301 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 1302 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; 1303 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); 1304 1305 /* pause DPG jpeg */ 1306 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1307 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1308 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1309 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, 1310 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1311 1312 /* Restore */ 1313 ring = adev->jpeg.inst->ring_dec; 1314 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 1315 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1316 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 1317 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1318 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 1319 lower_32_bits(ring->gpu_addr)); 1320 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 1321 upper_32_bits(ring->gpu_addr)); 1322 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); 1323 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); 1324 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1325 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1326 1327 ring = &adev->vcn.inst->ring_dec; 1328 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1329 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1330 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1331 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1332 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1333 } 1334 } else { 1335 /* unpause dpg jpeg, no need to wait */ 1336 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1337 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1338 } 1339 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; 1340 } 1341 1342 return 0; 1343 } 1344 1345 static bool vcn_v1_0_is_idle(void *handle) 1346 { 1347 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1348 1349 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1350 } 1351 1352 static int vcn_v1_0_wait_for_idle(void *handle) 1353 { 1354 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1355 int ret; 1356 1357 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1358 UVD_STATUS__IDLE); 1359 1360 return ret; 1361 } 1362 1363 static int vcn_v1_0_set_clockgating_state(void *handle, 1364 enum amd_clockgating_state state) 1365 { 1366 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1367 bool enable = (state == AMD_CG_STATE_GATE); 1368 1369 if (enable) { 1370 /* wait for STATUS to clear */ 1371 if (!vcn_v1_0_is_idle(handle)) 1372 return -EBUSY; 1373 vcn_v1_0_enable_clock_gating(adev); 1374 } else { 1375 /* disable HW gating and enable Sw gating */ 1376 vcn_v1_0_disable_clock_gating(adev); 1377 } 1378 return 0; 1379 } 1380 1381 /** 1382 * vcn_v1_0_dec_ring_get_rptr - get read pointer 1383 * 1384 * @ring: amdgpu_ring pointer 1385 * 1386 * Returns the current hardware read pointer 1387 */ 1388 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1389 { 1390 struct amdgpu_device *adev = ring->adev; 1391 1392 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1393 } 1394 1395 /** 1396 * vcn_v1_0_dec_ring_get_wptr - get write pointer 1397 * 1398 * @ring: amdgpu_ring pointer 1399 * 1400 * Returns the current hardware write pointer 1401 */ 1402 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1403 { 1404 struct amdgpu_device *adev = ring->adev; 1405 1406 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1407 } 1408 1409 /** 1410 * vcn_v1_0_dec_ring_set_wptr - set write pointer 1411 * 1412 * @ring: amdgpu_ring pointer 1413 * 1414 * Commits the write pointer to the hardware 1415 */ 1416 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1417 { 1418 struct amdgpu_device *adev = ring->adev; 1419 1420 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1421 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1422 lower_32_bits(ring->wptr) | 0x80000000); 1423 1424 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1425 } 1426 1427 /** 1428 * vcn_v1_0_dec_ring_insert_start - insert a start command 1429 * 1430 * @ring: amdgpu_ring pointer 1431 * 1432 * Write a start command to the ring. 1433 */ 1434 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1435 { 1436 struct amdgpu_device *adev = ring->adev; 1437 1438 amdgpu_ring_write(ring, 1439 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1440 amdgpu_ring_write(ring, 0); 1441 amdgpu_ring_write(ring, 1442 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1443 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 1444 } 1445 1446 /** 1447 * vcn_v1_0_dec_ring_insert_end - insert a end command 1448 * 1449 * @ring: amdgpu_ring pointer 1450 * 1451 * Write a end command to the ring. 1452 */ 1453 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1454 { 1455 struct amdgpu_device *adev = ring->adev; 1456 1457 amdgpu_ring_write(ring, 1458 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1459 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 1460 } 1461 1462 /** 1463 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 1464 * 1465 * @ring: amdgpu_ring pointer 1466 * @addr: address 1467 * @seq: sequence number 1468 * @flags: fence related flags 1469 * 1470 * Write a fence and a trap command to the ring. 1471 */ 1472 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1473 unsigned flags) 1474 { 1475 struct amdgpu_device *adev = ring->adev; 1476 1477 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1478 1479 amdgpu_ring_write(ring, 1480 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 1481 amdgpu_ring_write(ring, seq); 1482 amdgpu_ring_write(ring, 1483 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1484 amdgpu_ring_write(ring, addr & 0xffffffff); 1485 amdgpu_ring_write(ring, 1486 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1487 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1488 amdgpu_ring_write(ring, 1489 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1490 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 1491 1492 amdgpu_ring_write(ring, 1493 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1494 amdgpu_ring_write(ring, 0); 1495 amdgpu_ring_write(ring, 1496 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1497 amdgpu_ring_write(ring, 0); 1498 amdgpu_ring_write(ring, 1499 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1500 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 1501 } 1502 1503 /** 1504 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 1505 * 1506 * @ring: amdgpu_ring pointer 1507 * @job: job to retrieve vmid from 1508 * @ib: indirect buffer to execute 1509 * @flags: unused 1510 * 1511 * Write ring commands to execute the indirect buffer 1512 */ 1513 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1514 struct amdgpu_job *job, 1515 struct amdgpu_ib *ib, 1516 uint32_t flags) 1517 { 1518 struct amdgpu_device *adev = ring->adev; 1519 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1520 1521 amdgpu_ring_write(ring, 1522 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1523 amdgpu_ring_write(ring, vmid); 1524 1525 amdgpu_ring_write(ring, 1526 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1527 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1528 amdgpu_ring_write(ring, 1529 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1530 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1531 amdgpu_ring_write(ring, 1532 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 1533 amdgpu_ring_write(ring, ib->length_dw); 1534 } 1535 1536 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1537 uint32_t reg, uint32_t val, 1538 uint32_t mask) 1539 { 1540 struct amdgpu_device *adev = ring->adev; 1541 1542 amdgpu_ring_write(ring, 1543 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1544 amdgpu_ring_write(ring, reg << 2); 1545 amdgpu_ring_write(ring, 1546 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1547 amdgpu_ring_write(ring, val); 1548 amdgpu_ring_write(ring, 1549 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 1550 amdgpu_ring_write(ring, mask); 1551 amdgpu_ring_write(ring, 1552 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1553 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1554 } 1555 1556 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1557 unsigned vmid, uint64_t pd_addr) 1558 { 1559 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1560 uint32_t data0, data1, mask; 1561 1562 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1563 1564 /* wait for register write */ 1565 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1566 data1 = lower_32_bits(pd_addr); 1567 mask = 0xffffffff; 1568 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1569 } 1570 1571 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1572 uint32_t reg, uint32_t val) 1573 { 1574 struct amdgpu_device *adev = ring->adev; 1575 1576 amdgpu_ring_write(ring, 1577 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1578 amdgpu_ring_write(ring, reg << 2); 1579 amdgpu_ring_write(ring, 1580 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1581 amdgpu_ring_write(ring, val); 1582 amdgpu_ring_write(ring, 1583 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1584 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1585 } 1586 1587 /** 1588 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 1589 * 1590 * @ring: amdgpu_ring pointer 1591 * 1592 * Returns the current hardware enc read pointer 1593 */ 1594 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1595 { 1596 struct amdgpu_device *adev = ring->adev; 1597 1598 if (ring == &adev->vcn.inst->ring_enc[0]) 1599 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1600 else 1601 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1602 } 1603 1604 /** 1605 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 1606 * 1607 * @ring: amdgpu_ring pointer 1608 * 1609 * Returns the current hardware enc write pointer 1610 */ 1611 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1612 { 1613 struct amdgpu_device *adev = ring->adev; 1614 1615 if (ring == &adev->vcn.inst->ring_enc[0]) 1616 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1617 else 1618 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1619 } 1620 1621 /** 1622 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 1623 * 1624 * @ring: amdgpu_ring pointer 1625 * 1626 * Commits the enc write pointer to the hardware 1627 */ 1628 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1629 { 1630 struct amdgpu_device *adev = ring->adev; 1631 1632 if (ring == &adev->vcn.inst->ring_enc[0]) 1633 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, 1634 lower_32_bits(ring->wptr)); 1635 else 1636 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, 1637 lower_32_bits(ring->wptr)); 1638 } 1639 1640 /** 1641 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 1642 * 1643 * @ring: amdgpu_ring pointer 1644 * @addr: address 1645 * @seq: sequence number 1646 * @flags: fence related flags 1647 * 1648 * Write enc a fence and a trap command to the ring. 1649 */ 1650 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1651 u64 seq, unsigned flags) 1652 { 1653 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1654 1655 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1656 amdgpu_ring_write(ring, addr); 1657 amdgpu_ring_write(ring, upper_32_bits(addr)); 1658 amdgpu_ring_write(ring, seq); 1659 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1660 } 1661 1662 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1663 { 1664 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1665 } 1666 1667 /** 1668 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 1669 * 1670 * @ring: amdgpu_ring pointer 1671 * @job: job to retrive vmid from 1672 * @ib: indirect buffer to execute 1673 * @flags: unused 1674 * 1675 * Write enc ring commands to execute the indirect buffer 1676 */ 1677 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1678 struct amdgpu_job *job, 1679 struct amdgpu_ib *ib, 1680 uint32_t flags) 1681 { 1682 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1683 1684 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1685 amdgpu_ring_write(ring, vmid); 1686 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1687 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1688 amdgpu_ring_write(ring, ib->length_dw); 1689 } 1690 1691 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1692 uint32_t reg, uint32_t val, 1693 uint32_t mask) 1694 { 1695 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1696 amdgpu_ring_write(ring, reg << 2); 1697 amdgpu_ring_write(ring, mask); 1698 amdgpu_ring_write(ring, val); 1699 } 1700 1701 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1702 unsigned int vmid, uint64_t pd_addr) 1703 { 1704 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; 1705 1706 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1707 1708 /* wait for reg writes */ 1709 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1710 vmid * hub->ctx_addr_distance, 1711 lower_32_bits(pd_addr), 0xffffffff); 1712 } 1713 1714 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1715 uint32_t reg, uint32_t val) 1716 { 1717 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1718 amdgpu_ring_write(ring, reg << 2); 1719 amdgpu_ring_write(ring, val); 1720 } 1721 1722 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1723 struct amdgpu_irq_src *source, 1724 unsigned type, 1725 enum amdgpu_interrupt_state state) 1726 { 1727 return 0; 1728 } 1729 1730 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 1731 struct amdgpu_irq_src *source, 1732 struct amdgpu_iv_entry *entry) 1733 { 1734 DRM_DEBUG("IH: VCN TRAP\n"); 1735 1736 switch (entry->src_id) { 1737 case 124: 1738 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1739 break; 1740 case 119: 1741 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1742 break; 1743 case 120: 1744 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1745 break; 1746 default: 1747 DRM_ERROR("Unhandled interrupt: %d %d\n", 1748 entry->src_id, entry->src_data[0]); 1749 break; 1750 } 1751 1752 return 0; 1753 } 1754 1755 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1756 { 1757 struct amdgpu_device *adev = ring->adev; 1758 int i; 1759 1760 WARN_ON(ring->wptr % 2 || count % 2); 1761 1762 for (i = 0; i < count / 2; i++) { 1763 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); 1764 amdgpu_ring_write(ring, 0); 1765 } 1766 } 1767 1768 static int vcn_v1_0_set_powergating_state(void *handle, 1769 enum amd_powergating_state state) 1770 { 1771 /* This doesn't actually powergate the VCN block. 1772 * That's done in the dpm code via the SMC. This 1773 * just re-inits the block as necessary. The actual 1774 * gating still happens in the dpm code. We should 1775 * revisit this when there is a cleaner line between 1776 * the smc and the hw blocks 1777 */ 1778 int ret; 1779 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1780 1781 if (state == adev->vcn.cur_state) 1782 return 0; 1783 1784 if (state == AMD_PG_STATE_GATE) 1785 ret = vcn_v1_0_stop(adev); 1786 else 1787 ret = vcn_v1_0_start(adev); 1788 1789 if (!ret) 1790 adev->vcn.cur_state = state; 1791 return ret; 1792 } 1793 1794 static void vcn_v1_0_idle_work_handler(struct work_struct *work) 1795 { 1796 struct amdgpu_device *adev = 1797 container_of(work, struct amdgpu_device, vcn.idle_work.work); 1798 unsigned int fences = 0, i; 1799 1800 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1801 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1802 1803 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1804 struct dpg_pause_state new_state; 1805 1806 if (fences) 1807 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1808 else 1809 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1810 1811 if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec)) 1812 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1813 else 1814 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1815 1816 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1817 } 1818 1819 fences += amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec); 1820 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec); 1821 1822 if (fences == 0) { 1823 amdgpu_gfx_off_ctrl(adev, true); 1824 if (adev->pm.dpm_enabled) 1825 amdgpu_dpm_enable_uvd(adev, false); 1826 else 1827 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1828 AMD_PG_STATE_GATE); 1829 } else { 1830 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1831 } 1832 } 1833 1834 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring) 1835 { 1836 struct amdgpu_device *adev = ring->adev; 1837 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 1838 1839 mutex_lock(&adev->vcn.vcn1_jpeg1_workaround); 1840 1841 if (amdgpu_fence_wait_empty(ring->adev->jpeg.inst->ring_dec)) 1842 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n"); 1843 1844 vcn_v1_0_set_pg_for_begin_use(ring, set_clocks); 1845 1846 } 1847 1848 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks) 1849 { 1850 struct amdgpu_device *adev = ring->adev; 1851 1852 if (set_clocks) { 1853 amdgpu_gfx_off_ctrl(adev, false); 1854 if (adev->pm.dpm_enabled) 1855 amdgpu_dpm_enable_uvd(adev, true); 1856 else 1857 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1858 AMD_PG_STATE_UNGATE); 1859 } 1860 1861 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1862 struct dpg_pause_state new_state; 1863 unsigned int fences = 0, i; 1864 1865 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1866 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1867 1868 if (fences) 1869 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1870 else 1871 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1872 1873 if (amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec)) 1874 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1875 else 1876 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1877 1878 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 1879 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1880 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 1881 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1882 1883 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1884 } 1885 } 1886 1887 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring) 1888 { 1889 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1890 mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround); 1891 } 1892 1893 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 1894 .name = "vcn_v1_0", 1895 .early_init = vcn_v1_0_early_init, 1896 .late_init = NULL, 1897 .sw_init = vcn_v1_0_sw_init, 1898 .sw_fini = vcn_v1_0_sw_fini, 1899 .hw_init = vcn_v1_0_hw_init, 1900 .hw_fini = vcn_v1_0_hw_fini, 1901 .suspend = vcn_v1_0_suspend, 1902 .resume = vcn_v1_0_resume, 1903 .is_idle = vcn_v1_0_is_idle, 1904 .wait_for_idle = vcn_v1_0_wait_for_idle, 1905 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 1906 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 1907 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 1908 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 1909 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 1910 .set_powergating_state = vcn_v1_0_set_powergating_state, 1911 }; 1912 1913 /* 1914 * It is a hardware issue that VCN can't handle a GTT TMZ buffer on 1915 * CHIP_RAVEN series ASIC. Move such a GTT TMZ buffer to VRAM domain 1916 * before command submission as a workaround. 1917 */ 1918 static int vcn_v1_0_validate_bo(struct amdgpu_cs_parser *parser, 1919 struct amdgpu_job *job, 1920 uint64_t addr) 1921 { 1922 struct ttm_operation_ctx ctx = { false, false }; 1923 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; 1924 struct amdgpu_vm *vm = &fpriv->vm; 1925 struct amdgpu_bo_va_mapping *mapping; 1926 struct amdgpu_bo *bo; 1927 int r; 1928 1929 addr &= AMDGPU_GMC_HOLE_MASK; 1930 if (addr & 0x7) { 1931 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1932 return -EINVAL; 1933 } 1934 1935 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr/AMDGPU_GPU_PAGE_SIZE); 1936 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo) 1937 return -EINVAL; 1938 1939 bo = mapping->bo_va->base.bo; 1940 if (!(bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED)) 1941 return 0; 1942 1943 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 1944 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1945 if (r) { 1946 DRM_ERROR("Failed to validate the VCN message BO (%d)!\n", r); 1947 return r; 1948 } 1949 1950 return r; 1951 } 1952 1953 static int vcn_v1_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1954 struct amdgpu_job *job, 1955 struct amdgpu_ib *ib) 1956 { 1957 uint32_t msg_lo = 0, msg_hi = 0; 1958 int i, r; 1959 1960 if (!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) 1961 return 0; 1962 1963 for (i = 0; i < ib->length_dw; i += 2) { 1964 uint32_t reg = amdgpu_ib_get_value(ib, i); 1965 uint32_t val = amdgpu_ib_get_value(ib, i + 1); 1966 1967 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) { 1968 msg_lo = val; 1969 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) { 1970 msg_hi = val; 1971 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0)) { 1972 r = vcn_v1_0_validate_bo(p, job, 1973 ((u64)msg_hi) << 32 | msg_lo); 1974 if (r) 1975 return r; 1976 } 1977 } 1978 1979 return 0; 1980 } 1981 1982 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 1983 .type = AMDGPU_RING_TYPE_VCN_DEC, 1984 .align_mask = 0xf, 1985 .support_64bit_ptrs = false, 1986 .no_user_fence = true, 1987 .secure_submission_supported = true, 1988 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 1989 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 1990 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 1991 .patch_cs_in_place = vcn_v1_0_ring_patch_cs_in_place, 1992 .emit_frame_size = 1993 6 + 6 + /* hdp invalidate / flush */ 1994 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1995 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1996 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 1997 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 1998 6, 1999 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 2000 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 2001 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 2002 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 2003 .test_ring = amdgpu_vcn_dec_ring_test_ring, 2004 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2005 .insert_nop = vcn_v1_0_dec_ring_insert_nop, 2006 .insert_start = vcn_v1_0_dec_ring_insert_start, 2007 .insert_end = vcn_v1_0_dec_ring_insert_end, 2008 .pad_ib = amdgpu_ring_generic_pad_ib, 2009 .begin_use = vcn_v1_0_ring_begin_use, 2010 .end_use = vcn_v1_0_ring_end_use, 2011 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, 2012 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, 2013 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2014 }; 2015 2016 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 2017 .type = AMDGPU_RING_TYPE_VCN_ENC, 2018 .align_mask = 0x3f, 2019 .nop = VCN_ENC_CMD_NO_OP, 2020 .support_64bit_ptrs = false, 2021 .no_user_fence = true, 2022 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 2023 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 2024 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 2025 .emit_frame_size = 2026 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2027 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2028 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ 2029 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 2030 1, /* vcn_v1_0_enc_ring_insert_end */ 2031 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 2032 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 2033 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 2034 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 2035 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2036 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2037 .insert_nop = amdgpu_ring_insert_nop, 2038 .insert_end = vcn_v1_0_enc_ring_insert_end, 2039 .pad_ib = amdgpu_ring_generic_pad_ib, 2040 .begin_use = vcn_v1_0_ring_begin_use, 2041 .end_use = vcn_v1_0_ring_end_use, 2042 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, 2043 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, 2044 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2045 }; 2046 2047 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2048 { 2049 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 2050 DRM_INFO("VCN decode is enabled in VM mode\n"); 2051 } 2052 2053 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2054 { 2055 int i; 2056 2057 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 2058 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 2059 2060 DRM_INFO("VCN encode is enabled in VM mode\n"); 2061 } 2062 2063 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 2064 .set = vcn_v1_0_set_interrupt_state, 2065 .process = vcn_v1_0_process_interrupt, 2066 }; 2067 2068 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 2069 { 2070 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; 2071 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs; 2072 } 2073 2074 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = { 2075 .type = AMD_IP_BLOCK_TYPE_VCN, 2076 .major = 1, 2077 .minor = 0, 2078 .rev = 0, 2079 .funcs = &vcn_v1_0_ip_funcs, 2080 }; 2081