1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_vcn.h" 28 #include "amdgpu_pm.h" 29 #include "soc15.h" 30 #include "soc15d.h" 31 #include "soc15_common.h" 32 33 #include "vcn/vcn_1_0_offset.h" 34 #include "vcn/vcn_1_0_sh_mask.h" 35 #include "mmhub/mmhub_9_1_offset.h" 36 #include "mmhub/mmhub_9_1_sh_mask.h" 37 38 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 39 #include "jpeg_v1_0.h" 40 #include "vcn_v1_0.h" 41 42 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab 43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1 44 #define mmUVD_REG_XX_MASK_1_0 0x05ac 45 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1 46 47 static int vcn_v1_0_stop(struct amdgpu_device *adev); 48 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 49 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 50 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 51 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); 52 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 53 int inst_idx, struct dpg_pause_state *new_state); 54 55 static void vcn_v1_0_idle_work_handler(struct work_struct *work); 56 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring); 57 58 /** 59 * vcn_v1_0_early_init - set function pointers 60 * 61 * @handle: amdgpu_device pointer 62 * 63 * Set ring and irq function pointers 64 */ 65 static int vcn_v1_0_early_init(void *handle) 66 { 67 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 68 69 adev->vcn.num_vcn_inst = 1; 70 adev->vcn.num_enc_rings = 2; 71 72 vcn_v1_0_set_dec_ring_funcs(adev); 73 vcn_v1_0_set_enc_ring_funcs(adev); 74 vcn_v1_0_set_irq_funcs(adev); 75 76 jpeg_v1_0_early_init(handle); 77 78 return 0; 79 } 80 81 /** 82 * vcn_v1_0_sw_init - sw init for VCN block 83 * 84 * @handle: amdgpu_device pointer 85 * 86 * Load firmware and sw initialization 87 */ 88 static int vcn_v1_0_sw_init(void *handle) 89 { 90 struct amdgpu_ring *ring; 91 int i, r; 92 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 93 94 /* VCN DEC TRAP */ 95 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 96 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq); 97 if (r) 98 return r; 99 100 /* VCN ENC TRAP */ 101 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 102 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 103 &adev->vcn.inst->irq); 104 if (r) 105 return r; 106 } 107 108 r = amdgpu_vcn_sw_init(adev); 109 if (r) 110 return r; 111 112 /* Override the work func */ 113 #ifdef __linux__ 114 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler; 115 #else 116 task_set(&adev->vcn.idle_work.work.task, 117 (void (*)(void *))vcn_v1_0_idle_work_handler, 118 &adev->vcn.idle_work.work); 119 #endif 120 121 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 122 const struct common_firmware_header *hdr; 123 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 124 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 125 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 126 adev->firmware.fw_size += 127 roundup2(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 128 dev_info(adev->dev, "Will use PSP to load VCN firmware\n"); 129 } 130 131 r = amdgpu_vcn_resume(adev); 132 if (r) 133 return r; 134 135 ring = &adev->vcn.inst->ring_dec; 136 snprintf(ring->name, sizeof(ring->name), "vcn_dec"); 137 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 138 AMDGPU_RING_PRIO_DEFAULT, NULL); 139 if (r) 140 return r; 141 142 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 = 143 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 144 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 = 145 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 146 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 = 147 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 148 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd = 149 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 150 adev->vcn.internal.nop = adev->vcn.inst->external.nop = 151 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 152 153 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 154 ring = &adev->vcn.inst->ring_enc[i]; 155 snprintf(ring->name, sizeof(ring->name), "vcn_enc%d", i); 156 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 157 AMDGPU_RING_PRIO_DEFAULT, NULL); 158 if (r) 159 return r; 160 } 161 162 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode; 163 164 r = jpeg_v1_0_sw_init(handle); 165 166 return r; 167 } 168 169 /** 170 * vcn_v1_0_sw_fini - sw fini for VCN block 171 * 172 * @handle: amdgpu_device pointer 173 * 174 * VCN suspend and free up sw allocation 175 */ 176 static int vcn_v1_0_sw_fini(void *handle) 177 { 178 int r; 179 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 180 181 r = amdgpu_vcn_suspend(adev); 182 if (r) 183 return r; 184 185 jpeg_v1_0_sw_fini(handle); 186 187 r = amdgpu_vcn_sw_fini(adev); 188 189 return r; 190 } 191 192 /** 193 * vcn_v1_0_hw_init - start and test VCN block 194 * 195 * @handle: amdgpu_device pointer 196 * 197 * Initialize the hardware, boot up the VCPU and do some testing 198 */ 199 static int vcn_v1_0_hw_init(void *handle) 200 { 201 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 202 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 203 int i, r; 204 205 r = amdgpu_ring_test_helper(ring); 206 if (r) 207 goto done; 208 209 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 210 ring = &adev->vcn.inst->ring_enc[i]; 211 r = amdgpu_ring_test_helper(ring); 212 if (r) 213 goto done; 214 } 215 216 ring = &adev->jpeg.inst->ring_dec; 217 r = amdgpu_ring_test_helper(ring); 218 if (r) 219 goto done; 220 221 done: 222 if (!r) 223 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 224 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 225 226 return r; 227 } 228 229 /** 230 * vcn_v1_0_hw_fini - stop the hardware block 231 * 232 * @handle: amdgpu_device pointer 233 * 234 * Stop the VCN block, mark ring as not ready any more 235 */ 236 static int vcn_v1_0_hw_fini(void *handle) 237 { 238 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 239 240 cancel_delayed_work_sync(&adev->vcn.idle_work); 241 242 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 243 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 244 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { 245 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 246 } 247 248 return 0; 249 } 250 251 /** 252 * vcn_v1_0_suspend - suspend VCN block 253 * 254 * @handle: amdgpu_device pointer 255 * 256 * HW fini and suspend VCN block 257 */ 258 static int vcn_v1_0_suspend(void *handle) 259 { 260 int r; 261 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 262 bool idle_work_unexecuted; 263 264 idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work); 265 if (idle_work_unexecuted) { 266 if (adev->pm.dpm_enabled) 267 amdgpu_dpm_enable_uvd(adev, false); 268 } 269 270 r = vcn_v1_0_hw_fini(adev); 271 if (r) 272 return r; 273 274 r = amdgpu_vcn_suspend(adev); 275 276 return r; 277 } 278 279 /** 280 * vcn_v1_0_resume - resume VCN block 281 * 282 * @handle: amdgpu_device pointer 283 * 284 * Resume firmware and hw init VCN block 285 */ 286 static int vcn_v1_0_resume(void *handle) 287 { 288 int r; 289 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 290 291 r = amdgpu_vcn_resume(adev); 292 if (r) 293 return r; 294 295 r = vcn_v1_0_hw_init(adev); 296 297 return r; 298 } 299 300 /** 301 * vcn_v1_0_mc_resume_spg_mode - memory controller programming 302 * 303 * @adev: amdgpu_device pointer 304 * 305 * Let the VCN memory controller know it's offsets 306 */ 307 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 308 { 309 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 310 uint32_t offset; 311 312 /* cache window 0: fw */ 313 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 314 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 315 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 316 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 317 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 318 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 319 offset = 0; 320 } else { 321 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 322 lower_32_bits(adev->vcn.inst->gpu_addr)); 323 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 324 upper_32_bits(adev->vcn.inst->gpu_addr)); 325 offset = size; 326 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 327 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 328 } 329 330 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 331 332 /* cache window 1: stack */ 333 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 334 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 335 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 336 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 337 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 338 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 339 340 /* cache window 2: context */ 341 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 342 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 343 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 344 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 345 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 346 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 347 348 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 349 adev->gfx.config.gb_addr_config); 350 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 351 adev->gfx.config.gb_addr_config); 352 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 353 adev->gfx.config.gb_addr_config); 354 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 355 adev->gfx.config.gb_addr_config); 356 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 357 adev->gfx.config.gb_addr_config); 358 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 359 adev->gfx.config.gb_addr_config); 360 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 361 adev->gfx.config.gb_addr_config); 362 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 363 adev->gfx.config.gb_addr_config); 364 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 365 adev->gfx.config.gb_addr_config); 366 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 367 adev->gfx.config.gb_addr_config); 368 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 369 adev->gfx.config.gb_addr_config); 370 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 371 adev->gfx.config.gb_addr_config); 372 } 373 374 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 375 { 376 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 377 uint32_t offset; 378 379 /* cache window 0: fw */ 380 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 381 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 382 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 383 0xFFFFFFFF, 0); 384 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 385 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 386 0xFFFFFFFF, 0); 387 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, 388 0xFFFFFFFF, 0); 389 offset = 0; 390 } else { 391 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 392 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 393 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 394 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 395 offset = size; 396 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 397 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); 398 } 399 400 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); 401 402 /* cache window 1: stack */ 403 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 404 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 405 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 406 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 407 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, 408 0xFFFFFFFF, 0); 409 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, 410 0xFFFFFFFF, 0); 411 412 /* cache window 2: context */ 413 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 414 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 415 0xFFFFFFFF, 0); 416 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 417 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 418 0xFFFFFFFF, 0); 419 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); 420 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 421 0xFFFFFFFF, 0); 422 423 /* VCN global tiling registers */ 424 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 425 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 426 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 427 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 428 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 429 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 430 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 431 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 432 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 433 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 434 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 435 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 436 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 437 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 438 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 439 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 440 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 441 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 442 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 443 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 444 } 445 446 /** 447 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 448 * 449 * @adev: amdgpu_device pointer 450 * 451 * Disable clock gating for VCN block 452 */ 453 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) 454 { 455 uint32_t data; 456 457 /* JPEG disable CGC */ 458 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 459 460 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 461 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 462 else 463 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 464 465 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 466 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 467 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 468 469 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 470 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 471 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 472 473 /* UVD disable CGC */ 474 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 475 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 476 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 477 else 478 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 479 480 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 481 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 482 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 483 484 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 485 data &= ~(UVD_CGC_GATE__SYS_MASK 486 | UVD_CGC_GATE__UDEC_MASK 487 | UVD_CGC_GATE__MPEG2_MASK 488 | UVD_CGC_GATE__REGS_MASK 489 | UVD_CGC_GATE__RBC_MASK 490 | UVD_CGC_GATE__LMI_MC_MASK 491 | UVD_CGC_GATE__LMI_UMC_MASK 492 | UVD_CGC_GATE__IDCT_MASK 493 | UVD_CGC_GATE__MPRD_MASK 494 | UVD_CGC_GATE__MPC_MASK 495 | UVD_CGC_GATE__LBSI_MASK 496 | UVD_CGC_GATE__LRBBM_MASK 497 | UVD_CGC_GATE__UDEC_RE_MASK 498 | UVD_CGC_GATE__UDEC_CM_MASK 499 | UVD_CGC_GATE__UDEC_IT_MASK 500 | UVD_CGC_GATE__UDEC_DB_MASK 501 | UVD_CGC_GATE__UDEC_MP_MASK 502 | UVD_CGC_GATE__WCB_MASK 503 | UVD_CGC_GATE__VCPU_MASK 504 | UVD_CGC_GATE__SCPU_MASK); 505 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 506 507 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 508 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 509 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 510 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 511 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 512 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 513 | UVD_CGC_CTRL__SYS_MODE_MASK 514 | UVD_CGC_CTRL__UDEC_MODE_MASK 515 | UVD_CGC_CTRL__MPEG2_MODE_MASK 516 | UVD_CGC_CTRL__REGS_MODE_MASK 517 | UVD_CGC_CTRL__RBC_MODE_MASK 518 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 519 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 520 | UVD_CGC_CTRL__IDCT_MODE_MASK 521 | UVD_CGC_CTRL__MPRD_MODE_MASK 522 | UVD_CGC_CTRL__MPC_MODE_MASK 523 | UVD_CGC_CTRL__LBSI_MODE_MASK 524 | UVD_CGC_CTRL__LRBBM_MODE_MASK 525 | UVD_CGC_CTRL__WCB_MODE_MASK 526 | UVD_CGC_CTRL__VCPU_MODE_MASK 527 | UVD_CGC_CTRL__SCPU_MODE_MASK); 528 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 529 530 /* turn on */ 531 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 532 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 533 | UVD_SUVD_CGC_GATE__SIT_MASK 534 | UVD_SUVD_CGC_GATE__SMP_MASK 535 | UVD_SUVD_CGC_GATE__SCM_MASK 536 | UVD_SUVD_CGC_GATE__SDB_MASK 537 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 538 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 539 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 540 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 541 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 542 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 543 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 544 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 545 | UVD_SUVD_CGC_GATE__SCLR_MASK 546 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 547 | UVD_SUVD_CGC_GATE__ENT_MASK 548 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 549 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 550 | UVD_SUVD_CGC_GATE__SITE_MASK 551 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 552 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 553 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 554 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 555 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 556 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 557 558 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 559 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 560 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 561 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 562 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 563 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 564 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 565 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 566 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 567 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 568 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 569 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 570 } 571 572 /** 573 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 574 * 575 * @adev: amdgpu_device pointer 576 * 577 * Enable clock gating for VCN block 578 */ 579 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) 580 { 581 uint32_t data = 0; 582 583 /* enable JPEG CGC */ 584 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 585 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 586 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 587 else 588 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 589 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 590 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 591 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 592 593 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 594 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 595 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 596 597 /* enable UVD CGC */ 598 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 599 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 600 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 601 else 602 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 603 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 604 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 605 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 606 607 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 608 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 609 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 610 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 611 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 612 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 613 | UVD_CGC_CTRL__SYS_MODE_MASK 614 | UVD_CGC_CTRL__UDEC_MODE_MASK 615 | UVD_CGC_CTRL__MPEG2_MODE_MASK 616 | UVD_CGC_CTRL__REGS_MODE_MASK 617 | UVD_CGC_CTRL__RBC_MODE_MASK 618 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 619 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 620 | UVD_CGC_CTRL__IDCT_MODE_MASK 621 | UVD_CGC_CTRL__MPRD_MODE_MASK 622 | UVD_CGC_CTRL__MPC_MODE_MASK 623 | UVD_CGC_CTRL__LBSI_MODE_MASK 624 | UVD_CGC_CTRL__LRBBM_MODE_MASK 625 | UVD_CGC_CTRL__WCB_MODE_MASK 626 | UVD_CGC_CTRL__VCPU_MODE_MASK 627 | UVD_CGC_CTRL__SCPU_MODE_MASK); 628 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 629 630 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 631 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 632 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 633 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 634 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 635 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 636 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 637 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 638 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 639 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 640 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 641 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 642 } 643 644 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) 645 { 646 uint32_t reg_data = 0; 647 648 /* disable JPEG CGC */ 649 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 650 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 651 else 652 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 653 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 654 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 655 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 656 657 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 658 659 /* enable sw clock gating control */ 660 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 661 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 662 else 663 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 664 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 665 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 666 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 667 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 668 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 669 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 670 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 671 UVD_CGC_CTRL__SYS_MODE_MASK | 672 UVD_CGC_CTRL__UDEC_MODE_MASK | 673 UVD_CGC_CTRL__MPEG2_MODE_MASK | 674 UVD_CGC_CTRL__REGS_MODE_MASK | 675 UVD_CGC_CTRL__RBC_MODE_MASK | 676 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 677 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 678 UVD_CGC_CTRL__IDCT_MODE_MASK | 679 UVD_CGC_CTRL__MPRD_MODE_MASK | 680 UVD_CGC_CTRL__MPC_MODE_MASK | 681 UVD_CGC_CTRL__LBSI_MODE_MASK | 682 UVD_CGC_CTRL__LRBBM_MODE_MASK | 683 UVD_CGC_CTRL__WCB_MODE_MASK | 684 UVD_CGC_CTRL__VCPU_MODE_MASK | 685 UVD_CGC_CTRL__SCPU_MODE_MASK); 686 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 687 688 /* turn off clock gating */ 689 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 690 691 /* turn on SUVD clock gating */ 692 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); 693 694 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 695 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); 696 } 697 698 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 699 { 700 uint32_t data = 0; 701 702 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 703 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 704 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 705 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 706 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 707 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 708 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 709 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 710 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 711 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 712 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 713 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 714 715 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 716 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF); 717 } else { 718 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 719 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 720 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 721 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 722 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 723 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 724 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 725 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 726 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 727 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 728 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 729 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 730 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF); 731 } 732 733 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ 734 735 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 736 data &= ~0x103; 737 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 738 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; 739 740 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 741 } 742 743 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 744 { 745 uint32_t data = 0; 746 747 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 748 /* Before power off, this indicator has to be turned on */ 749 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 750 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 751 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 752 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 753 754 755 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 756 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 757 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 758 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 759 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 760 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 761 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 762 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 763 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 764 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 765 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 766 767 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 768 769 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 770 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 771 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 772 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 773 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 774 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 775 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 776 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 777 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 778 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 779 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); 780 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF); 781 } 782 } 783 784 /** 785 * vcn_v1_0_start_spg_mode - start VCN block 786 * 787 * @adev: amdgpu_device pointer 788 * 789 * Setup and start the VCN block 790 */ 791 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 792 { 793 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 794 uint32_t rb_bufsz, tmp; 795 uint32_t lmi_swap_cntl; 796 int i, j, r; 797 798 /* disable byte swapping */ 799 lmi_swap_cntl = 0; 800 801 vcn_1_0_disable_static_power_gating(adev); 802 803 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 804 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 805 806 /* disable clock gating */ 807 vcn_v1_0_disable_clock_gating(adev); 808 809 /* disable interupt */ 810 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 811 ~UVD_MASTINT_EN__VCPU_EN_MASK); 812 813 /* initialize VCN memory controller */ 814 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 815 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 816 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 817 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 818 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 819 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 820 821 #ifdef __BIG_ENDIAN 822 /* swap (8 in 32) RB and IB */ 823 lmi_swap_cntl = 0xa; 824 #endif 825 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 826 827 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 828 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 829 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 830 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); 831 832 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 833 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 834 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 835 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 836 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 837 838 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 839 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 840 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 841 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 842 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 843 844 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 845 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 846 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 847 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 848 849 vcn_v1_0_mc_resume_spg_mode(adev); 850 851 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10); 852 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0, 853 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3); 854 855 /* enable VCPU clock */ 856 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 857 858 /* boot up the VCPU */ 859 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 860 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 861 862 /* enable UMC */ 863 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 864 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 865 866 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 867 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 868 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 869 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 870 871 for (i = 0; i < 10; ++i) { 872 uint32_t status; 873 874 for (j = 0; j < 100; ++j) { 875 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 876 if (status & UVD_STATUS__IDLE) 877 break; 878 mdelay(10); 879 } 880 r = 0; 881 if (status & UVD_STATUS__IDLE) 882 break; 883 884 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 885 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 886 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 887 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 888 mdelay(10); 889 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 890 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 891 mdelay(10); 892 r = -1; 893 } 894 895 if (r) { 896 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 897 return r; 898 } 899 /* enable master interrupt */ 900 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 901 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); 902 903 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 904 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 905 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 906 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 907 908 /* clear the busy bit of UVD_STATUS */ 909 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; 910 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 911 912 /* force RBC into idle state */ 913 rb_bufsz = order_base_2(ring->ring_size); 914 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 915 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 916 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 917 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 918 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 919 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 920 921 /* set the write pointer delay */ 922 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 923 924 /* set the wb address */ 925 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 926 (upper_32_bits(ring->gpu_addr) >> 2)); 927 928 /* program the RB_BASE for ring buffer */ 929 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 930 lower_32_bits(ring->gpu_addr)); 931 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 932 upper_32_bits(ring->gpu_addr)); 933 934 /* Initialize the ring buffer's read and write pointers */ 935 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 936 937 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 938 939 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 940 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 941 lower_32_bits(ring->wptr)); 942 943 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 944 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 945 946 ring = &adev->vcn.inst->ring_enc[0]; 947 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 948 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 949 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 950 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 951 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 952 953 ring = &adev->vcn.inst->ring_enc[1]; 954 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 955 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 956 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 957 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 958 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 959 960 jpeg_v1_0_start(adev, 0); 961 962 return 0; 963 } 964 965 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 966 { 967 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 968 uint32_t rb_bufsz, tmp; 969 uint32_t lmi_swap_cntl; 970 971 /* disable byte swapping */ 972 lmi_swap_cntl = 0; 973 974 vcn_1_0_enable_static_power_gating(adev); 975 976 /* enable dynamic power gating mode */ 977 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 978 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 979 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 980 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 981 982 /* enable clock gating */ 983 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 984 985 /* enable VCPU clock */ 986 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 987 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 988 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 989 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); 990 991 /* disable interupt */ 992 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, 993 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 994 995 /* initialize VCN memory controller */ 996 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, 997 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 998 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 999 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1000 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1001 UVD_LMI_CTRL__REQ_MODE_MASK | 1002 UVD_LMI_CTRL__CRC_RESET_MASK | 1003 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1004 0x00100000L, 0xFFFFFFFF, 0); 1005 1006 #ifdef __BIG_ENDIAN 1007 /* swap (8 in 32) RB and IB */ 1008 lmi_swap_cntl = 0xa; 1009 #endif 1010 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 1011 1012 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL, 1013 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); 1014 1015 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0, 1016 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1017 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1018 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1019 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); 1020 1021 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0, 1022 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1023 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1024 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1025 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); 1026 1027 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX, 1028 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1029 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1030 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); 1031 1032 vcn_v1_0_mc_resume_dpg_mode(adev); 1033 1034 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); 1035 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); 1036 1037 /* boot up the VCPU */ 1038 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1039 1040 /* enable UMC */ 1041 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2, 1042 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 1043 0xFFFFFFFF, 0); 1044 1045 /* enable master interrupt */ 1046 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, 1047 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 1048 1049 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1050 /* setup mmUVD_LMI_CTRL */ 1051 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, 1052 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1053 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1054 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1055 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1056 UVD_LMI_CTRL__REQ_MODE_MASK | 1057 UVD_LMI_CTRL__CRC_RESET_MASK | 1058 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1059 0x00100000L, 0xFFFFFFFF, 1); 1060 1061 tmp = adev->gfx.config.gb_addr_config; 1062 /* setup VCN global tiling registers */ 1063 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1064 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1065 1066 /* enable System Interrupt for JRBC */ 1067 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN, 1068 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); 1069 1070 /* force RBC into idle state */ 1071 rb_bufsz = order_base_2(ring->ring_size); 1072 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1073 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1074 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1075 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1076 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1077 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1078 1079 /* set the write pointer delay */ 1080 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1081 1082 /* set the wb address */ 1083 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1084 (upper_32_bits(ring->gpu_addr) >> 2)); 1085 1086 /* program the RB_BASE for ring buffer */ 1087 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1088 lower_32_bits(ring->gpu_addr)); 1089 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1090 upper_32_bits(ring->gpu_addr)); 1091 1092 /* Initialize the ring buffer's read and write pointers */ 1093 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1094 1095 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1096 1097 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1098 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1099 lower_32_bits(ring->wptr)); 1100 1101 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 1102 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1103 1104 jpeg_v1_0_start(adev, 1); 1105 1106 return 0; 1107 } 1108 1109 static int vcn_v1_0_start(struct amdgpu_device *adev) 1110 { 1111 int r; 1112 1113 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1114 r = vcn_v1_0_start_dpg_mode(adev); 1115 else 1116 r = vcn_v1_0_start_spg_mode(adev); 1117 return r; 1118 } 1119 1120 /** 1121 * vcn_v1_0_stop_spg_mode - stop VCN block 1122 * 1123 * @adev: amdgpu_device pointer 1124 * 1125 * stop the VCN block 1126 */ 1127 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1128 { 1129 int tmp; 1130 1131 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1132 1133 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1134 UVD_LMI_STATUS__READ_CLEAN_MASK | 1135 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1136 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1137 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); 1138 1139 /* stall UMC channel */ 1140 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 1141 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1142 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1143 1144 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1145 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1146 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); 1147 1148 /* disable VCPU clock */ 1149 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1150 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1151 1152 /* reset LMI UMC/LMI */ 1153 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1154 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1155 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1156 1157 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1158 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1159 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1160 1161 /* put VCPU into reset */ 1162 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1163 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1164 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1165 1166 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); 1167 1168 vcn_v1_0_enable_clock_gating(adev); 1169 vcn_1_0_enable_static_power_gating(adev); 1170 return 0; 1171 } 1172 1173 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1174 { 1175 uint32_t tmp; 1176 1177 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1178 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1179 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1180 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1181 1182 /* wait for read ptr to be equal to write ptr */ 1183 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1184 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1185 1186 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1187 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1188 1189 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1190 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF); 1191 1192 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1193 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1194 1195 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1196 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1197 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1198 1199 /* disable dynamic power gating mode */ 1200 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1201 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1202 1203 return 0; 1204 } 1205 1206 static int vcn_v1_0_stop(struct amdgpu_device *adev) 1207 { 1208 int r; 1209 1210 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1211 r = vcn_v1_0_stop_dpg_mode(adev); 1212 else 1213 r = vcn_v1_0_stop_spg_mode(adev); 1214 1215 return r; 1216 } 1217 1218 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 1219 int inst_idx, struct dpg_pause_state *new_state) 1220 { 1221 int ret_code; 1222 uint32_t reg_data = 0; 1223 uint32_t reg_data2 = 0; 1224 struct amdgpu_ring *ring; 1225 1226 /* pause/unpause if state is changed */ 1227 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1228 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1229 adev->vcn.inst[inst_idx].pause_state.fw_based, 1230 adev->vcn.inst[inst_idx].pause_state.jpeg, 1231 new_state->fw_based, new_state->jpeg); 1232 1233 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1234 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1235 1236 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1237 ret_code = 0; 1238 1239 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) 1240 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1241 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1242 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1243 1244 if (!ret_code) { 1245 /* pause DPG non-jpeg */ 1246 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1247 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1248 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1249 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1250 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1251 1252 /* Restore */ 1253 ring = &adev->vcn.inst->ring_enc[0]; 1254 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1255 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1256 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1257 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1258 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1259 1260 ring = &adev->vcn.inst->ring_enc[1]; 1261 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1262 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1263 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1264 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1265 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1266 1267 ring = &adev->vcn.inst->ring_dec; 1268 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1269 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1270 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1271 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1272 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1273 } 1274 } else { 1275 /* unpause dpg non-jpeg, no need to wait */ 1276 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1277 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1278 } 1279 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1280 } 1281 1282 /* pause/unpause if state is changed */ 1283 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { 1284 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1285 adev->vcn.inst[inst_idx].pause_state.fw_based, 1286 adev->vcn.inst[inst_idx].pause_state.jpeg, 1287 new_state->fw_based, new_state->jpeg); 1288 1289 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1290 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1291 1292 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { 1293 ret_code = 0; 1294 1295 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) 1296 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1297 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1298 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1299 1300 if (!ret_code) { 1301 /* Make sure JPRG Snoop is disabled before sending the pause */ 1302 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 1303 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; 1304 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); 1305 1306 /* pause DPG jpeg */ 1307 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1308 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1309 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1310 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, 1311 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1312 1313 /* Restore */ 1314 ring = &adev->jpeg.inst->ring_dec; 1315 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 1316 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1317 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 1318 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1319 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 1320 lower_32_bits(ring->gpu_addr)); 1321 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 1322 upper_32_bits(ring->gpu_addr)); 1323 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); 1324 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); 1325 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1326 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1327 1328 ring = &adev->vcn.inst->ring_dec; 1329 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1330 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1331 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1332 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1333 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1334 } 1335 } else { 1336 /* unpause dpg jpeg, no need to wait */ 1337 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1338 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1339 } 1340 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; 1341 } 1342 1343 return 0; 1344 } 1345 1346 static bool vcn_v1_0_is_idle(void *handle) 1347 { 1348 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1349 1350 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1351 } 1352 1353 static int vcn_v1_0_wait_for_idle(void *handle) 1354 { 1355 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1356 int ret; 1357 1358 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1359 UVD_STATUS__IDLE); 1360 1361 return ret; 1362 } 1363 1364 static int vcn_v1_0_set_clockgating_state(void *handle, 1365 enum amd_clockgating_state state) 1366 { 1367 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1368 bool enable = (state == AMD_CG_STATE_GATE); 1369 1370 if (enable) { 1371 /* wait for STATUS to clear */ 1372 if (!vcn_v1_0_is_idle(handle)) 1373 return -EBUSY; 1374 vcn_v1_0_enable_clock_gating(adev); 1375 } else { 1376 /* disable HW gating and enable Sw gating */ 1377 vcn_v1_0_disable_clock_gating(adev); 1378 } 1379 return 0; 1380 } 1381 1382 /** 1383 * vcn_v1_0_dec_ring_get_rptr - get read pointer 1384 * 1385 * @ring: amdgpu_ring pointer 1386 * 1387 * Returns the current hardware read pointer 1388 */ 1389 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1390 { 1391 struct amdgpu_device *adev = ring->adev; 1392 1393 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1394 } 1395 1396 /** 1397 * vcn_v1_0_dec_ring_get_wptr - get write pointer 1398 * 1399 * @ring: amdgpu_ring pointer 1400 * 1401 * Returns the current hardware write pointer 1402 */ 1403 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1404 { 1405 struct amdgpu_device *adev = ring->adev; 1406 1407 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1408 } 1409 1410 /** 1411 * vcn_v1_0_dec_ring_set_wptr - set write pointer 1412 * 1413 * @ring: amdgpu_ring pointer 1414 * 1415 * Commits the write pointer to the hardware 1416 */ 1417 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1418 { 1419 struct amdgpu_device *adev = ring->adev; 1420 1421 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1422 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1423 lower_32_bits(ring->wptr) | 0x80000000); 1424 1425 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1426 } 1427 1428 /** 1429 * vcn_v1_0_dec_ring_insert_start - insert a start command 1430 * 1431 * @ring: amdgpu_ring pointer 1432 * 1433 * Write a start command to the ring. 1434 */ 1435 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1436 { 1437 struct amdgpu_device *adev = ring->adev; 1438 1439 amdgpu_ring_write(ring, 1440 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1441 amdgpu_ring_write(ring, 0); 1442 amdgpu_ring_write(ring, 1443 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1444 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 1445 } 1446 1447 /** 1448 * vcn_v1_0_dec_ring_insert_end - insert a end command 1449 * 1450 * @ring: amdgpu_ring pointer 1451 * 1452 * Write a end command to the ring. 1453 */ 1454 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1455 { 1456 struct amdgpu_device *adev = ring->adev; 1457 1458 amdgpu_ring_write(ring, 1459 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1460 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 1461 } 1462 1463 /** 1464 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 1465 * 1466 * @ring: amdgpu_ring pointer 1467 * @addr: address 1468 * @seq: sequence number 1469 * @flags: fence related flags 1470 * 1471 * Write a fence and a trap command to the ring. 1472 */ 1473 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1474 unsigned flags) 1475 { 1476 struct amdgpu_device *adev = ring->adev; 1477 1478 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1479 1480 amdgpu_ring_write(ring, 1481 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 1482 amdgpu_ring_write(ring, seq); 1483 amdgpu_ring_write(ring, 1484 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1485 amdgpu_ring_write(ring, addr & 0xffffffff); 1486 amdgpu_ring_write(ring, 1487 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1488 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1489 amdgpu_ring_write(ring, 1490 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1491 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 1492 1493 amdgpu_ring_write(ring, 1494 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1495 amdgpu_ring_write(ring, 0); 1496 amdgpu_ring_write(ring, 1497 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1498 amdgpu_ring_write(ring, 0); 1499 amdgpu_ring_write(ring, 1500 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1501 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 1502 } 1503 1504 /** 1505 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 1506 * 1507 * @ring: amdgpu_ring pointer 1508 * @job: job to retrieve vmid from 1509 * @ib: indirect buffer to execute 1510 * @flags: unused 1511 * 1512 * Write ring commands to execute the indirect buffer 1513 */ 1514 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1515 struct amdgpu_job *job, 1516 struct amdgpu_ib *ib, 1517 uint32_t flags) 1518 { 1519 struct amdgpu_device *adev = ring->adev; 1520 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1521 1522 amdgpu_ring_write(ring, 1523 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1524 amdgpu_ring_write(ring, vmid); 1525 1526 amdgpu_ring_write(ring, 1527 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1528 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1529 amdgpu_ring_write(ring, 1530 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1531 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1532 amdgpu_ring_write(ring, 1533 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 1534 amdgpu_ring_write(ring, ib->length_dw); 1535 } 1536 1537 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1538 uint32_t reg, uint32_t val, 1539 uint32_t mask) 1540 { 1541 struct amdgpu_device *adev = ring->adev; 1542 1543 amdgpu_ring_write(ring, 1544 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1545 amdgpu_ring_write(ring, reg << 2); 1546 amdgpu_ring_write(ring, 1547 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1548 amdgpu_ring_write(ring, val); 1549 amdgpu_ring_write(ring, 1550 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 1551 amdgpu_ring_write(ring, mask); 1552 amdgpu_ring_write(ring, 1553 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1554 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1555 } 1556 1557 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1558 unsigned vmid, uint64_t pd_addr) 1559 { 1560 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1561 uint32_t data0, data1, mask; 1562 1563 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1564 1565 /* wait for register write */ 1566 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1567 data1 = lower_32_bits(pd_addr); 1568 mask = 0xffffffff; 1569 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1570 } 1571 1572 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1573 uint32_t reg, uint32_t val) 1574 { 1575 struct amdgpu_device *adev = ring->adev; 1576 1577 amdgpu_ring_write(ring, 1578 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1579 amdgpu_ring_write(ring, reg << 2); 1580 amdgpu_ring_write(ring, 1581 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1582 amdgpu_ring_write(ring, val); 1583 amdgpu_ring_write(ring, 1584 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1585 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1586 } 1587 1588 /** 1589 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 1590 * 1591 * @ring: amdgpu_ring pointer 1592 * 1593 * Returns the current hardware enc read pointer 1594 */ 1595 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1596 { 1597 struct amdgpu_device *adev = ring->adev; 1598 1599 if (ring == &adev->vcn.inst->ring_enc[0]) 1600 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1601 else 1602 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1603 } 1604 1605 /** 1606 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 1607 * 1608 * @ring: amdgpu_ring pointer 1609 * 1610 * Returns the current hardware enc write pointer 1611 */ 1612 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1613 { 1614 struct amdgpu_device *adev = ring->adev; 1615 1616 if (ring == &adev->vcn.inst->ring_enc[0]) 1617 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1618 else 1619 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1620 } 1621 1622 /** 1623 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 1624 * 1625 * @ring: amdgpu_ring pointer 1626 * 1627 * Commits the enc write pointer to the hardware 1628 */ 1629 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1630 { 1631 struct amdgpu_device *adev = ring->adev; 1632 1633 if (ring == &adev->vcn.inst->ring_enc[0]) 1634 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, 1635 lower_32_bits(ring->wptr)); 1636 else 1637 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, 1638 lower_32_bits(ring->wptr)); 1639 } 1640 1641 /** 1642 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 1643 * 1644 * @ring: amdgpu_ring pointer 1645 * @addr: address 1646 * @seq: sequence number 1647 * @flags: fence related flags 1648 * 1649 * Write enc a fence and a trap command to the ring. 1650 */ 1651 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1652 u64 seq, unsigned flags) 1653 { 1654 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1655 1656 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1657 amdgpu_ring_write(ring, addr); 1658 amdgpu_ring_write(ring, upper_32_bits(addr)); 1659 amdgpu_ring_write(ring, seq); 1660 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1661 } 1662 1663 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1664 { 1665 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1666 } 1667 1668 /** 1669 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 1670 * 1671 * @ring: amdgpu_ring pointer 1672 * @job: job to retrive vmid from 1673 * @ib: indirect buffer to execute 1674 * @flags: unused 1675 * 1676 * Write enc ring commands to execute the indirect buffer 1677 */ 1678 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1679 struct amdgpu_job *job, 1680 struct amdgpu_ib *ib, 1681 uint32_t flags) 1682 { 1683 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1684 1685 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1686 amdgpu_ring_write(ring, vmid); 1687 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1688 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1689 amdgpu_ring_write(ring, ib->length_dw); 1690 } 1691 1692 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1693 uint32_t reg, uint32_t val, 1694 uint32_t mask) 1695 { 1696 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1697 amdgpu_ring_write(ring, reg << 2); 1698 amdgpu_ring_write(ring, mask); 1699 amdgpu_ring_write(ring, val); 1700 } 1701 1702 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1703 unsigned int vmid, uint64_t pd_addr) 1704 { 1705 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1706 1707 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1708 1709 /* wait for reg writes */ 1710 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1711 vmid * hub->ctx_addr_distance, 1712 lower_32_bits(pd_addr), 0xffffffff); 1713 } 1714 1715 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1716 uint32_t reg, uint32_t val) 1717 { 1718 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1719 amdgpu_ring_write(ring, reg << 2); 1720 amdgpu_ring_write(ring, val); 1721 } 1722 1723 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1724 struct amdgpu_irq_src *source, 1725 unsigned type, 1726 enum amdgpu_interrupt_state state) 1727 { 1728 return 0; 1729 } 1730 1731 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 1732 struct amdgpu_irq_src *source, 1733 struct amdgpu_iv_entry *entry) 1734 { 1735 DRM_DEBUG("IH: VCN TRAP\n"); 1736 1737 switch (entry->src_id) { 1738 case 124: 1739 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1740 break; 1741 case 119: 1742 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1743 break; 1744 case 120: 1745 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1746 break; 1747 default: 1748 DRM_ERROR("Unhandled interrupt: %d %d\n", 1749 entry->src_id, entry->src_data[0]); 1750 break; 1751 } 1752 1753 return 0; 1754 } 1755 1756 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1757 { 1758 struct amdgpu_device *adev = ring->adev; 1759 int i; 1760 1761 WARN_ON(ring->wptr % 2 || count % 2); 1762 1763 for (i = 0; i < count / 2; i++) { 1764 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); 1765 amdgpu_ring_write(ring, 0); 1766 } 1767 } 1768 1769 static int vcn_v1_0_set_powergating_state(void *handle, 1770 enum amd_powergating_state state) 1771 { 1772 /* This doesn't actually powergate the VCN block. 1773 * That's done in the dpm code via the SMC. This 1774 * just re-inits the block as necessary. The actual 1775 * gating still happens in the dpm code. We should 1776 * revisit this when there is a cleaner line between 1777 * the smc and the hw blocks 1778 */ 1779 int ret; 1780 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1781 1782 if(state == adev->vcn.cur_state) 1783 return 0; 1784 1785 if (state == AMD_PG_STATE_GATE) 1786 ret = vcn_v1_0_stop(adev); 1787 else 1788 ret = vcn_v1_0_start(adev); 1789 1790 if(!ret) 1791 adev->vcn.cur_state = state; 1792 return ret; 1793 } 1794 1795 static void vcn_v1_0_idle_work_handler(struct work_struct *work) 1796 { 1797 struct amdgpu_device *adev = 1798 container_of(work, struct amdgpu_device, vcn.idle_work.work); 1799 unsigned int fences = 0, i; 1800 1801 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1802 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1803 1804 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1805 struct dpg_pause_state new_state; 1806 1807 if (fences) 1808 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1809 else 1810 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1811 1812 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1813 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1814 else 1815 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1816 1817 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1818 } 1819 1820 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec); 1821 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec); 1822 1823 if (fences == 0) { 1824 amdgpu_gfx_off_ctrl(adev, true); 1825 if (adev->pm.dpm_enabled) 1826 amdgpu_dpm_enable_uvd(adev, false); 1827 else 1828 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1829 AMD_PG_STATE_GATE); 1830 } else { 1831 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1832 } 1833 } 1834 1835 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring) 1836 { 1837 struct amdgpu_device *adev = ring->adev; 1838 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 1839 1840 mutex_lock(&adev->vcn.vcn1_jpeg1_workaround); 1841 1842 if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec)) 1843 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n"); 1844 1845 vcn_v1_0_set_pg_for_begin_use(ring, set_clocks); 1846 1847 } 1848 1849 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks) 1850 { 1851 struct amdgpu_device *adev = ring->adev; 1852 1853 if (set_clocks) { 1854 amdgpu_gfx_off_ctrl(adev, false); 1855 if (adev->pm.dpm_enabled) 1856 amdgpu_dpm_enable_uvd(adev, true); 1857 else 1858 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1859 AMD_PG_STATE_UNGATE); 1860 } 1861 1862 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1863 struct dpg_pause_state new_state; 1864 unsigned int fences = 0, i; 1865 1866 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1867 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1868 1869 if (fences) 1870 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1871 else 1872 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1873 1874 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1875 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1876 else 1877 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1878 1879 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 1880 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1881 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 1882 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1883 1884 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1885 } 1886 } 1887 1888 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring) 1889 { 1890 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1891 mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround); 1892 } 1893 1894 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 1895 .name = "vcn_v1_0", 1896 .early_init = vcn_v1_0_early_init, 1897 .late_init = NULL, 1898 .sw_init = vcn_v1_0_sw_init, 1899 .sw_fini = vcn_v1_0_sw_fini, 1900 .hw_init = vcn_v1_0_hw_init, 1901 .hw_fini = vcn_v1_0_hw_fini, 1902 .suspend = vcn_v1_0_suspend, 1903 .resume = vcn_v1_0_resume, 1904 .is_idle = vcn_v1_0_is_idle, 1905 .wait_for_idle = vcn_v1_0_wait_for_idle, 1906 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 1907 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 1908 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 1909 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 1910 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 1911 .set_powergating_state = vcn_v1_0_set_powergating_state, 1912 }; 1913 1914 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 1915 .type = AMDGPU_RING_TYPE_VCN_DEC, 1916 .align_mask = 0xf, 1917 .support_64bit_ptrs = false, 1918 .no_user_fence = true, 1919 .vmhub = AMDGPU_MMHUB_0, 1920 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 1921 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 1922 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 1923 .emit_frame_size = 1924 6 + 6 + /* hdp invalidate / flush */ 1925 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1926 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1927 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 1928 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 1929 6, 1930 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 1931 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 1932 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 1933 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 1934 .test_ring = amdgpu_vcn_dec_ring_test_ring, 1935 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1936 .insert_nop = vcn_v1_0_dec_ring_insert_nop, 1937 .insert_start = vcn_v1_0_dec_ring_insert_start, 1938 .insert_end = vcn_v1_0_dec_ring_insert_end, 1939 .pad_ib = amdgpu_ring_generic_pad_ib, 1940 .begin_use = vcn_v1_0_ring_begin_use, 1941 .end_use = vcn_v1_0_ring_end_use, 1942 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, 1943 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, 1944 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1945 }; 1946 1947 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 1948 .type = AMDGPU_RING_TYPE_VCN_ENC, 1949 .align_mask = 0x3f, 1950 .nop = VCN_ENC_CMD_NO_OP, 1951 .support_64bit_ptrs = false, 1952 .no_user_fence = true, 1953 .vmhub = AMDGPU_MMHUB_0, 1954 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 1955 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 1956 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 1957 .emit_frame_size = 1958 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1959 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1960 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ 1961 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 1962 1, /* vcn_v1_0_enc_ring_insert_end */ 1963 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 1964 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 1965 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 1966 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 1967 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1968 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1969 .insert_nop = amdgpu_ring_insert_nop, 1970 .insert_end = vcn_v1_0_enc_ring_insert_end, 1971 .pad_ib = amdgpu_ring_generic_pad_ib, 1972 .begin_use = vcn_v1_0_ring_begin_use, 1973 .end_use = vcn_v1_0_ring_end_use, 1974 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, 1975 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, 1976 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1977 }; 1978 1979 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1980 { 1981 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 1982 DRM_INFO("VCN decode is enabled in VM mode\n"); 1983 } 1984 1985 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1986 { 1987 int i; 1988 1989 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1990 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 1991 1992 DRM_INFO("VCN encode is enabled in VM mode\n"); 1993 } 1994 1995 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 1996 .set = vcn_v1_0_set_interrupt_state, 1997 .process = vcn_v1_0_process_interrupt, 1998 }; 1999 2000 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 2001 { 2002 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; 2003 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs; 2004 } 2005 2006 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = 2007 { 2008 .type = AMD_IP_BLOCK_TYPE_VCN, 2009 .major = 1, 2010 .minor = 0, 2011 .rev = 0, 2012 .funcs = &vcn_v1_0_ip_funcs, 2013 }; 2014