1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_cs.h" 28 #include "amdgpu_vcn.h" 29 #include "amdgpu_pm.h" 30 #include "soc15.h" 31 #include "soc15d.h" 32 #include "soc15_common.h" 33 34 #include "vcn/vcn_1_0_offset.h" 35 #include "vcn/vcn_1_0_sh_mask.h" 36 #include "mmhub/mmhub_9_1_offset.h" 37 #include "mmhub/mmhub_9_1_sh_mask.h" 38 39 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 40 #include "jpeg_v1_0.h" 41 #include "vcn_v1_0.h" 42 43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab 44 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1 45 #define mmUVD_REG_XX_MASK_1_0 0x05ac 46 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1 47 48 static int vcn_v1_0_stop(struct amdgpu_device *adev); 49 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 50 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 51 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 52 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); 53 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 54 int inst_idx, struct dpg_pause_state *new_state); 55 56 static void vcn_v1_0_idle_work_handler(struct work_struct *work); 57 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring); 58 59 /** 60 * vcn_v1_0_early_init - set function pointers 61 * 62 * @handle: amdgpu_device pointer 63 * 64 * Set ring and irq function pointers 65 */ 66 static int vcn_v1_0_early_init(void *handle) 67 { 68 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 69 70 adev->vcn.num_enc_rings = 2; 71 72 vcn_v1_0_set_dec_ring_funcs(adev); 73 vcn_v1_0_set_enc_ring_funcs(adev); 74 vcn_v1_0_set_irq_funcs(adev); 75 76 jpeg_v1_0_early_init(handle); 77 78 return 0; 79 } 80 81 /** 82 * vcn_v1_0_sw_init - sw init for VCN block 83 * 84 * @handle: amdgpu_device pointer 85 * 86 * Load firmware and sw initialization 87 */ 88 static int vcn_v1_0_sw_init(void *handle) 89 { 90 struct amdgpu_ring *ring; 91 int i, r; 92 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 93 94 /* VCN DEC TRAP */ 95 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 96 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq); 97 if (r) 98 return r; 99 100 /* VCN ENC TRAP */ 101 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 102 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 103 &adev->vcn.inst->irq); 104 if (r) 105 return r; 106 } 107 108 r = amdgpu_vcn_sw_init(adev); 109 if (r) 110 return r; 111 112 /* Override the work func */ 113 #ifdef __linux__ 114 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler; 115 #else 116 task_set(&adev->vcn.idle_work.work.task, 117 (void (*)(void *))vcn_v1_0_idle_work_handler, 118 &adev->vcn.idle_work.work); 119 #endif 120 121 amdgpu_vcn_setup_ucode(adev); 122 123 r = amdgpu_vcn_resume(adev); 124 if (r) 125 return r; 126 127 ring = &adev->vcn.inst->ring_dec; 128 snprintf(ring->name, sizeof(ring->name), "vcn_dec"); 129 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 130 AMDGPU_RING_PRIO_DEFAULT, NULL); 131 if (r) 132 return r; 133 134 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 = 135 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 136 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 = 137 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 138 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 = 139 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 140 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd = 141 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 142 adev->vcn.internal.nop = adev->vcn.inst->external.nop = 143 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 144 145 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 146 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i); 147 148 ring = &adev->vcn.inst->ring_enc[i]; 149 snprintf(ring->name, sizeof(ring->name), "vcn_enc%d", i); 150 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0, 151 hw_prio, NULL); 152 if (r) 153 return r; 154 } 155 156 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode; 157 158 if (amdgpu_vcnfw_log) { 159 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; 160 161 fw_shared->present_flag_0 = 0; 162 amdgpu_vcn_fwlog_init(adev->vcn.inst); 163 } 164 165 r = jpeg_v1_0_sw_init(handle); 166 167 return r; 168 } 169 170 /** 171 * vcn_v1_0_sw_fini - sw fini for VCN block 172 * 173 * @handle: amdgpu_device pointer 174 * 175 * VCN suspend and free up sw allocation 176 */ 177 static int vcn_v1_0_sw_fini(void *handle) 178 { 179 int r; 180 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 181 182 r = amdgpu_vcn_suspend(adev); 183 if (r) 184 return r; 185 186 jpeg_v1_0_sw_fini(handle); 187 188 r = amdgpu_vcn_sw_fini(adev); 189 190 return r; 191 } 192 193 /** 194 * vcn_v1_0_hw_init - start and test VCN block 195 * 196 * @handle: amdgpu_device pointer 197 * 198 * Initialize the hardware, boot up the VCPU and do some testing 199 */ 200 static int vcn_v1_0_hw_init(void *handle) 201 { 202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 203 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 204 int i, r; 205 206 r = amdgpu_ring_test_helper(ring); 207 if (r) 208 goto done; 209 210 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 211 ring = &adev->vcn.inst->ring_enc[i]; 212 r = amdgpu_ring_test_helper(ring); 213 if (r) 214 goto done; 215 } 216 217 ring = &adev->jpeg.inst->ring_dec; 218 r = amdgpu_ring_test_helper(ring); 219 if (r) 220 goto done; 221 222 done: 223 if (!r) 224 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 225 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 226 227 return r; 228 } 229 230 /** 231 * vcn_v1_0_hw_fini - stop the hardware block 232 * 233 * @handle: amdgpu_device pointer 234 * 235 * Stop the VCN block, mark ring as not ready any more 236 */ 237 static int vcn_v1_0_hw_fini(void *handle) 238 { 239 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 240 241 cancel_delayed_work_sync(&adev->vcn.idle_work); 242 243 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 244 (adev->vcn.cur_state != AMD_PG_STATE_GATE && 245 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { 246 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 247 } 248 249 return 0; 250 } 251 252 /** 253 * vcn_v1_0_suspend - suspend VCN block 254 * 255 * @handle: amdgpu_device pointer 256 * 257 * HW fini and suspend VCN block 258 */ 259 static int vcn_v1_0_suspend(void *handle) 260 { 261 int r; 262 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 263 bool idle_work_unexecuted; 264 265 idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work); 266 if (idle_work_unexecuted) { 267 if (adev->pm.dpm_enabled) 268 amdgpu_dpm_enable_uvd(adev, false); 269 } 270 271 r = vcn_v1_0_hw_fini(adev); 272 if (r) 273 return r; 274 275 r = amdgpu_vcn_suspend(adev); 276 277 return r; 278 } 279 280 /** 281 * vcn_v1_0_resume - resume VCN block 282 * 283 * @handle: amdgpu_device pointer 284 * 285 * Resume firmware and hw init VCN block 286 */ 287 static int vcn_v1_0_resume(void *handle) 288 { 289 int r; 290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 291 292 r = amdgpu_vcn_resume(adev); 293 if (r) 294 return r; 295 296 r = vcn_v1_0_hw_init(adev); 297 298 return r; 299 } 300 301 /** 302 * vcn_v1_0_mc_resume_spg_mode - memory controller programming 303 * 304 * @adev: amdgpu_device pointer 305 * 306 * Let the VCN memory controller know it's offsets 307 */ 308 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 309 { 310 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 311 uint32_t offset; 312 313 /* cache window 0: fw */ 314 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 315 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 316 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 317 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 318 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 319 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 320 offset = 0; 321 } else { 322 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 323 lower_32_bits(adev->vcn.inst->gpu_addr)); 324 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 325 upper_32_bits(adev->vcn.inst->gpu_addr)); 326 offset = size; 327 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 328 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 329 } 330 331 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 332 333 /* cache window 1: stack */ 334 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 335 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 336 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 337 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 338 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 339 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 340 341 /* cache window 2: context */ 342 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 343 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 344 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 345 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 346 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 347 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 348 349 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 350 adev->gfx.config.gb_addr_config); 351 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 352 adev->gfx.config.gb_addr_config); 353 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 354 adev->gfx.config.gb_addr_config); 355 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 356 adev->gfx.config.gb_addr_config); 357 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 358 adev->gfx.config.gb_addr_config); 359 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 360 adev->gfx.config.gb_addr_config); 361 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 362 adev->gfx.config.gb_addr_config); 363 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 364 adev->gfx.config.gb_addr_config); 365 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 366 adev->gfx.config.gb_addr_config); 367 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 368 adev->gfx.config.gb_addr_config); 369 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 370 adev->gfx.config.gb_addr_config); 371 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 372 adev->gfx.config.gb_addr_config); 373 } 374 375 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 376 { 377 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 378 uint32_t offset; 379 380 /* cache window 0: fw */ 381 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 382 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 383 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 384 0xFFFFFFFF, 0); 385 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 386 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 387 0xFFFFFFFF, 0); 388 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, 389 0xFFFFFFFF, 0); 390 offset = 0; 391 } else { 392 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 393 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 394 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 395 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 396 offset = size; 397 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 398 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); 399 } 400 401 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); 402 403 /* cache window 1: stack */ 404 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 405 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 406 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 407 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 408 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, 409 0xFFFFFFFF, 0); 410 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, 411 0xFFFFFFFF, 0); 412 413 /* cache window 2: context */ 414 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 415 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 416 0xFFFFFFFF, 0); 417 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 418 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 419 0xFFFFFFFF, 0); 420 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); 421 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 422 0xFFFFFFFF, 0); 423 424 /* VCN global tiling registers */ 425 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 426 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 427 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 428 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 429 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 430 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 431 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 432 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 433 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 434 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 435 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 436 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 437 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 438 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 439 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 440 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 441 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 442 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 443 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 444 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 445 } 446 447 /** 448 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 449 * 450 * @adev: amdgpu_device pointer 451 * 452 * Disable clock gating for VCN block 453 */ 454 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) 455 { 456 uint32_t data; 457 458 /* JPEG disable CGC */ 459 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 460 461 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 462 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 463 else 464 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 465 466 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 467 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 468 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 469 470 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 471 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 472 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 473 474 /* UVD disable CGC */ 475 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 476 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 477 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 478 else 479 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 480 481 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 482 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 483 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 484 485 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 486 data &= ~(UVD_CGC_GATE__SYS_MASK 487 | UVD_CGC_GATE__UDEC_MASK 488 | UVD_CGC_GATE__MPEG2_MASK 489 | UVD_CGC_GATE__REGS_MASK 490 | UVD_CGC_GATE__RBC_MASK 491 | UVD_CGC_GATE__LMI_MC_MASK 492 | UVD_CGC_GATE__LMI_UMC_MASK 493 | UVD_CGC_GATE__IDCT_MASK 494 | UVD_CGC_GATE__MPRD_MASK 495 | UVD_CGC_GATE__MPC_MASK 496 | UVD_CGC_GATE__LBSI_MASK 497 | UVD_CGC_GATE__LRBBM_MASK 498 | UVD_CGC_GATE__UDEC_RE_MASK 499 | UVD_CGC_GATE__UDEC_CM_MASK 500 | UVD_CGC_GATE__UDEC_IT_MASK 501 | UVD_CGC_GATE__UDEC_DB_MASK 502 | UVD_CGC_GATE__UDEC_MP_MASK 503 | UVD_CGC_GATE__WCB_MASK 504 | UVD_CGC_GATE__VCPU_MASK 505 | UVD_CGC_GATE__SCPU_MASK); 506 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 507 508 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 509 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 510 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 511 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 512 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 513 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 514 | UVD_CGC_CTRL__SYS_MODE_MASK 515 | UVD_CGC_CTRL__UDEC_MODE_MASK 516 | UVD_CGC_CTRL__MPEG2_MODE_MASK 517 | UVD_CGC_CTRL__REGS_MODE_MASK 518 | UVD_CGC_CTRL__RBC_MODE_MASK 519 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 520 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 521 | UVD_CGC_CTRL__IDCT_MODE_MASK 522 | UVD_CGC_CTRL__MPRD_MODE_MASK 523 | UVD_CGC_CTRL__MPC_MODE_MASK 524 | UVD_CGC_CTRL__LBSI_MODE_MASK 525 | UVD_CGC_CTRL__LRBBM_MODE_MASK 526 | UVD_CGC_CTRL__WCB_MODE_MASK 527 | UVD_CGC_CTRL__VCPU_MODE_MASK 528 | UVD_CGC_CTRL__SCPU_MODE_MASK); 529 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 530 531 /* turn on */ 532 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 533 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 534 | UVD_SUVD_CGC_GATE__SIT_MASK 535 | UVD_SUVD_CGC_GATE__SMP_MASK 536 | UVD_SUVD_CGC_GATE__SCM_MASK 537 | UVD_SUVD_CGC_GATE__SDB_MASK 538 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 539 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 540 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 541 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 542 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 543 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 544 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 545 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 546 | UVD_SUVD_CGC_GATE__SCLR_MASK 547 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 548 | UVD_SUVD_CGC_GATE__ENT_MASK 549 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 550 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 551 | UVD_SUVD_CGC_GATE__SITE_MASK 552 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 553 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 554 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 555 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 556 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 557 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 558 559 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 560 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 561 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 562 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 563 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 564 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 565 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 566 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 567 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 568 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 569 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 570 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 571 } 572 573 /** 574 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 575 * 576 * @adev: amdgpu_device pointer 577 * 578 * Enable clock gating for VCN block 579 */ 580 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) 581 { 582 uint32_t data = 0; 583 584 /* enable JPEG CGC */ 585 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 586 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 587 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 588 else 589 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 590 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 591 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 592 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 593 594 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 595 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 596 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 597 598 /* enable UVD CGC */ 599 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 600 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 601 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 602 else 603 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 604 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 605 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 606 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 607 608 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 609 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 610 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 611 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 612 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 613 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 614 | UVD_CGC_CTRL__SYS_MODE_MASK 615 | UVD_CGC_CTRL__UDEC_MODE_MASK 616 | UVD_CGC_CTRL__MPEG2_MODE_MASK 617 | UVD_CGC_CTRL__REGS_MODE_MASK 618 | UVD_CGC_CTRL__RBC_MODE_MASK 619 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 620 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 621 | UVD_CGC_CTRL__IDCT_MODE_MASK 622 | UVD_CGC_CTRL__MPRD_MODE_MASK 623 | UVD_CGC_CTRL__MPC_MODE_MASK 624 | UVD_CGC_CTRL__LBSI_MODE_MASK 625 | UVD_CGC_CTRL__LRBBM_MODE_MASK 626 | UVD_CGC_CTRL__WCB_MODE_MASK 627 | UVD_CGC_CTRL__VCPU_MODE_MASK 628 | UVD_CGC_CTRL__SCPU_MODE_MASK); 629 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 630 631 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 632 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 633 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 634 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 635 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 636 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 637 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 638 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 639 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 640 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 641 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 642 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 643 } 644 645 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) 646 { 647 uint32_t reg_data = 0; 648 649 /* disable JPEG CGC */ 650 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 651 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 652 else 653 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 654 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 655 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 656 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 657 658 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 659 660 /* enable sw clock gating control */ 661 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 662 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 663 else 664 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 665 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 666 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 667 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 668 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 669 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 670 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 671 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 672 UVD_CGC_CTRL__SYS_MODE_MASK | 673 UVD_CGC_CTRL__UDEC_MODE_MASK | 674 UVD_CGC_CTRL__MPEG2_MODE_MASK | 675 UVD_CGC_CTRL__REGS_MODE_MASK | 676 UVD_CGC_CTRL__RBC_MODE_MASK | 677 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 678 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 679 UVD_CGC_CTRL__IDCT_MODE_MASK | 680 UVD_CGC_CTRL__MPRD_MODE_MASK | 681 UVD_CGC_CTRL__MPC_MODE_MASK | 682 UVD_CGC_CTRL__LBSI_MODE_MASK | 683 UVD_CGC_CTRL__LRBBM_MODE_MASK | 684 UVD_CGC_CTRL__WCB_MODE_MASK | 685 UVD_CGC_CTRL__VCPU_MODE_MASK | 686 UVD_CGC_CTRL__SCPU_MODE_MASK); 687 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 688 689 /* turn off clock gating */ 690 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 691 692 /* turn on SUVD clock gating */ 693 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); 694 695 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 696 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); 697 } 698 699 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 700 { 701 uint32_t data = 0; 702 703 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 704 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 705 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 706 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 707 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 708 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 709 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 710 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 711 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 712 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 713 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 714 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 715 716 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 717 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF); 718 } else { 719 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 720 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 721 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 722 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 723 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 724 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 725 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 726 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 727 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 728 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 729 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 730 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 731 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF); 732 } 733 734 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ 735 736 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 737 data &= ~0x103; 738 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 739 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; 740 741 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 742 } 743 744 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 745 { 746 uint32_t data = 0; 747 748 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 749 /* Before power off, this indicator has to be turned on */ 750 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 751 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 752 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 753 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 754 755 756 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 757 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 758 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 759 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 760 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 761 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 762 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 763 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 764 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 765 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 766 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 767 768 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 769 770 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 771 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 772 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 773 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 774 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 775 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 776 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 777 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 778 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 779 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 780 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); 781 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF); 782 } 783 } 784 785 /** 786 * vcn_v1_0_start_spg_mode - start VCN block 787 * 788 * @adev: amdgpu_device pointer 789 * 790 * Setup and start the VCN block 791 */ 792 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 793 { 794 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 795 uint32_t rb_bufsz, tmp; 796 uint32_t lmi_swap_cntl; 797 int i, j, r; 798 799 /* disable byte swapping */ 800 lmi_swap_cntl = 0; 801 802 vcn_1_0_disable_static_power_gating(adev); 803 804 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 805 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 806 807 /* disable clock gating */ 808 vcn_v1_0_disable_clock_gating(adev); 809 810 /* disable interupt */ 811 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 812 ~UVD_MASTINT_EN__VCPU_EN_MASK); 813 814 /* initialize VCN memory controller */ 815 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 816 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 817 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 818 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 819 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 820 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 821 822 #ifdef __BIG_ENDIAN 823 /* swap (8 in 32) RB and IB */ 824 lmi_swap_cntl = 0xa; 825 #endif 826 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 827 828 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 829 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 830 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 831 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); 832 833 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 834 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 835 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 836 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 837 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 838 839 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 840 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 841 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 842 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 843 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 844 845 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 846 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 847 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 848 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 849 850 vcn_v1_0_mc_resume_spg_mode(adev); 851 852 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10); 853 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0, 854 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3); 855 856 /* enable VCPU clock */ 857 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 858 859 /* boot up the VCPU */ 860 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 861 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 862 863 /* enable UMC */ 864 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 865 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 866 867 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 868 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 869 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 870 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 871 872 for (i = 0; i < 10; ++i) { 873 uint32_t status; 874 875 for (j = 0; j < 100; ++j) { 876 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 877 if (status & UVD_STATUS__IDLE) 878 break; 879 mdelay(10); 880 } 881 r = 0; 882 if (status & UVD_STATUS__IDLE) 883 break; 884 885 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 886 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 887 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 888 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 889 mdelay(10); 890 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 891 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 892 mdelay(10); 893 r = -1; 894 } 895 896 if (r) { 897 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 898 return r; 899 } 900 /* enable master interrupt */ 901 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 902 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); 903 904 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 905 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 906 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 907 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 908 909 /* clear the busy bit of UVD_STATUS */ 910 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; 911 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 912 913 /* force RBC into idle state */ 914 rb_bufsz = order_base_2(ring->ring_size); 915 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 916 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 917 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 918 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 919 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 920 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 921 922 /* set the write pointer delay */ 923 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 924 925 /* set the wb address */ 926 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 927 (upper_32_bits(ring->gpu_addr) >> 2)); 928 929 /* program the RB_BASE for ring buffer */ 930 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 931 lower_32_bits(ring->gpu_addr)); 932 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 933 upper_32_bits(ring->gpu_addr)); 934 935 /* Initialize the ring buffer's read and write pointers */ 936 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 937 938 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 939 940 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 941 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 942 lower_32_bits(ring->wptr)); 943 944 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 945 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 946 947 ring = &adev->vcn.inst->ring_enc[0]; 948 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 949 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 950 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 951 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 952 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 953 954 ring = &adev->vcn.inst->ring_enc[1]; 955 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 956 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 957 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 958 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 959 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 960 961 jpeg_v1_0_start(adev, 0); 962 963 return 0; 964 } 965 966 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 967 { 968 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 969 uint32_t rb_bufsz, tmp; 970 uint32_t lmi_swap_cntl; 971 972 /* disable byte swapping */ 973 lmi_swap_cntl = 0; 974 975 vcn_1_0_enable_static_power_gating(adev); 976 977 /* enable dynamic power gating mode */ 978 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 979 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 980 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 981 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 982 983 /* enable clock gating */ 984 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 985 986 /* enable VCPU clock */ 987 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 988 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 989 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 990 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); 991 992 /* disable interupt */ 993 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, 994 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 995 996 /* initialize VCN memory controller */ 997 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, 998 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 999 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1000 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1001 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1002 UVD_LMI_CTRL__REQ_MODE_MASK | 1003 UVD_LMI_CTRL__CRC_RESET_MASK | 1004 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1005 0x00100000L, 0xFFFFFFFF, 0); 1006 1007 #ifdef __BIG_ENDIAN 1008 /* swap (8 in 32) RB and IB */ 1009 lmi_swap_cntl = 0xa; 1010 #endif 1011 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 1012 1013 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL, 1014 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); 1015 1016 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0, 1017 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1018 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1019 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1020 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); 1021 1022 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0, 1023 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1024 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1025 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1026 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); 1027 1028 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX, 1029 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1030 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1031 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); 1032 1033 vcn_v1_0_mc_resume_dpg_mode(adev); 1034 1035 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); 1036 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); 1037 1038 /* boot up the VCPU */ 1039 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1040 1041 /* enable UMC */ 1042 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2, 1043 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 1044 0xFFFFFFFF, 0); 1045 1046 /* enable master interrupt */ 1047 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN, 1048 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 1049 1050 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1051 /* setup mmUVD_LMI_CTRL */ 1052 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL, 1053 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1054 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1055 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1056 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1057 UVD_LMI_CTRL__REQ_MODE_MASK | 1058 UVD_LMI_CTRL__CRC_RESET_MASK | 1059 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1060 0x00100000L, 0xFFFFFFFF, 1); 1061 1062 tmp = adev->gfx.config.gb_addr_config; 1063 /* setup VCN global tiling registers */ 1064 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1065 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1066 1067 /* enable System Interrupt for JRBC */ 1068 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN, 1069 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); 1070 1071 /* force RBC into idle state */ 1072 rb_bufsz = order_base_2(ring->ring_size); 1073 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1074 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1075 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1076 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1077 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1078 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1079 1080 /* set the write pointer delay */ 1081 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1082 1083 /* set the wb address */ 1084 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1085 (upper_32_bits(ring->gpu_addr) >> 2)); 1086 1087 /* program the RB_BASE for ring buffer */ 1088 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1089 lower_32_bits(ring->gpu_addr)); 1090 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1091 upper_32_bits(ring->gpu_addr)); 1092 1093 /* Initialize the ring buffer's read and write pointers */ 1094 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1095 1096 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1097 1098 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1099 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1100 lower_32_bits(ring->wptr)); 1101 1102 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 1103 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1104 1105 jpeg_v1_0_start(adev, 1); 1106 1107 return 0; 1108 } 1109 1110 static int vcn_v1_0_start(struct amdgpu_device *adev) 1111 { 1112 return (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ? 1113 vcn_v1_0_start_dpg_mode(adev) : vcn_v1_0_start_spg_mode(adev); 1114 } 1115 1116 /** 1117 * vcn_v1_0_stop_spg_mode - stop VCN block 1118 * 1119 * @adev: amdgpu_device pointer 1120 * 1121 * stop the VCN block 1122 */ 1123 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1124 { 1125 int tmp; 1126 1127 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); 1128 1129 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1130 UVD_LMI_STATUS__READ_CLEAN_MASK | 1131 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1132 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1133 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); 1134 1135 /* stall UMC channel */ 1136 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 1137 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1138 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1139 1140 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1141 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1142 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); 1143 1144 /* disable VCPU clock */ 1145 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1146 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1147 1148 /* reset LMI UMC/LMI */ 1149 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1150 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1151 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1152 1153 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1154 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1155 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1156 1157 /* put VCPU into reset */ 1158 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1159 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1160 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1161 1162 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); 1163 1164 vcn_v1_0_enable_clock_gating(adev); 1165 vcn_1_0_enable_static_power_gating(adev); 1166 return 0; 1167 } 1168 1169 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1170 { 1171 uint32_t tmp; 1172 1173 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1174 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1175 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1176 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1177 1178 /* wait for read ptr to be equal to write ptr */ 1179 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1180 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); 1181 1182 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1183 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); 1184 1185 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1186 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF); 1187 1188 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1189 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); 1190 1191 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1192 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1193 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1194 1195 /* disable dynamic power gating mode */ 1196 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1197 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1198 1199 return 0; 1200 } 1201 1202 static int vcn_v1_0_stop(struct amdgpu_device *adev) 1203 { 1204 int r; 1205 1206 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1207 r = vcn_v1_0_stop_dpg_mode(adev); 1208 else 1209 r = vcn_v1_0_stop_spg_mode(adev); 1210 1211 return r; 1212 } 1213 1214 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 1215 int inst_idx, struct dpg_pause_state *new_state) 1216 { 1217 int ret_code; 1218 uint32_t reg_data = 0; 1219 uint32_t reg_data2 = 0; 1220 struct amdgpu_ring *ring; 1221 1222 /* pause/unpause if state is changed */ 1223 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1224 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1225 adev->vcn.inst[inst_idx].pause_state.fw_based, 1226 adev->vcn.inst[inst_idx].pause_state.jpeg, 1227 new_state->fw_based, new_state->jpeg); 1228 1229 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1230 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1231 1232 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1233 ret_code = 0; 1234 1235 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) 1236 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1237 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1238 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1239 1240 if (!ret_code) { 1241 /* pause DPG non-jpeg */ 1242 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1243 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1244 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1245 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1246 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1247 1248 /* Restore */ 1249 ring = &adev->vcn.inst->ring_enc[0]; 1250 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1251 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1252 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1253 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1254 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1255 1256 ring = &adev->vcn.inst->ring_enc[1]; 1257 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1258 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1259 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1260 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1261 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1262 1263 ring = &adev->vcn.inst->ring_dec; 1264 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1265 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1266 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1267 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1268 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1269 } 1270 } else { 1271 /* unpause dpg non-jpeg, no need to wait */ 1272 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1273 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1274 } 1275 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1276 } 1277 1278 /* pause/unpause if state is changed */ 1279 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { 1280 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1281 adev->vcn.inst[inst_idx].pause_state.fw_based, 1282 adev->vcn.inst[inst_idx].pause_state.jpeg, 1283 new_state->fw_based, new_state->jpeg); 1284 1285 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1286 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1287 1288 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { 1289 ret_code = 0; 1290 1291 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) 1292 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1293 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1294 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1295 1296 if (!ret_code) { 1297 /* Make sure JPRG Snoop is disabled before sending the pause */ 1298 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 1299 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; 1300 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); 1301 1302 /* pause DPG jpeg */ 1303 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1304 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1305 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1306 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, 1307 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1308 1309 /* Restore */ 1310 ring = &adev->jpeg.inst->ring_dec; 1311 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 1312 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1313 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 1314 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1315 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 1316 lower_32_bits(ring->gpu_addr)); 1317 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 1318 upper_32_bits(ring->gpu_addr)); 1319 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); 1320 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); 1321 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1322 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1323 1324 ring = &adev->vcn.inst->ring_dec; 1325 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1326 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1327 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1328 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1329 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK); 1330 } 1331 } else { 1332 /* unpause dpg jpeg, no need to wait */ 1333 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1334 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1335 } 1336 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; 1337 } 1338 1339 return 0; 1340 } 1341 1342 static bool vcn_v1_0_is_idle(void *handle) 1343 { 1344 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1345 1346 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1347 } 1348 1349 static int vcn_v1_0_wait_for_idle(void *handle) 1350 { 1351 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1352 int ret; 1353 1354 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1355 UVD_STATUS__IDLE); 1356 1357 return ret; 1358 } 1359 1360 static int vcn_v1_0_set_clockgating_state(void *handle, 1361 enum amd_clockgating_state state) 1362 { 1363 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1364 bool enable = (state == AMD_CG_STATE_GATE); 1365 1366 if (enable) { 1367 /* wait for STATUS to clear */ 1368 if (!vcn_v1_0_is_idle(handle)) 1369 return -EBUSY; 1370 vcn_v1_0_enable_clock_gating(adev); 1371 } else { 1372 /* disable HW gating and enable Sw gating */ 1373 vcn_v1_0_disable_clock_gating(adev); 1374 } 1375 return 0; 1376 } 1377 1378 /** 1379 * vcn_v1_0_dec_ring_get_rptr - get read pointer 1380 * 1381 * @ring: amdgpu_ring pointer 1382 * 1383 * Returns the current hardware read pointer 1384 */ 1385 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1386 { 1387 struct amdgpu_device *adev = ring->adev; 1388 1389 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1390 } 1391 1392 /** 1393 * vcn_v1_0_dec_ring_get_wptr - get write pointer 1394 * 1395 * @ring: amdgpu_ring pointer 1396 * 1397 * Returns the current hardware write pointer 1398 */ 1399 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1400 { 1401 struct amdgpu_device *adev = ring->adev; 1402 1403 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1404 } 1405 1406 /** 1407 * vcn_v1_0_dec_ring_set_wptr - set write pointer 1408 * 1409 * @ring: amdgpu_ring pointer 1410 * 1411 * Commits the write pointer to the hardware 1412 */ 1413 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1414 { 1415 struct amdgpu_device *adev = ring->adev; 1416 1417 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1418 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1419 lower_32_bits(ring->wptr) | 0x80000000); 1420 1421 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1422 } 1423 1424 /** 1425 * vcn_v1_0_dec_ring_insert_start - insert a start command 1426 * 1427 * @ring: amdgpu_ring pointer 1428 * 1429 * Write a start command to the ring. 1430 */ 1431 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1432 { 1433 struct amdgpu_device *adev = ring->adev; 1434 1435 amdgpu_ring_write(ring, 1436 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1437 amdgpu_ring_write(ring, 0); 1438 amdgpu_ring_write(ring, 1439 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1440 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 1441 } 1442 1443 /** 1444 * vcn_v1_0_dec_ring_insert_end - insert a end command 1445 * 1446 * @ring: amdgpu_ring pointer 1447 * 1448 * Write a end command to the ring. 1449 */ 1450 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1451 { 1452 struct amdgpu_device *adev = ring->adev; 1453 1454 amdgpu_ring_write(ring, 1455 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1456 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 1457 } 1458 1459 /** 1460 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 1461 * 1462 * @ring: amdgpu_ring pointer 1463 * @addr: address 1464 * @seq: sequence number 1465 * @flags: fence related flags 1466 * 1467 * Write a fence and a trap command to the ring. 1468 */ 1469 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1470 unsigned flags) 1471 { 1472 struct amdgpu_device *adev = ring->adev; 1473 1474 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1475 1476 amdgpu_ring_write(ring, 1477 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 1478 amdgpu_ring_write(ring, seq); 1479 amdgpu_ring_write(ring, 1480 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1481 amdgpu_ring_write(ring, addr & 0xffffffff); 1482 amdgpu_ring_write(ring, 1483 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1484 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1485 amdgpu_ring_write(ring, 1486 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1487 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 1488 1489 amdgpu_ring_write(ring, 1490 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1491 amdgpu_ring_write(ring, 0); 1492 amdgpu_ring_write(ring, 1493 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1494 amdgpu_ring_write(ring, 0); 1495 amdgpu_ring_write(ring, 1496 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1497 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 1498 } 1499 1500 /** 1501 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 1502 * 1503 * @ring: amdgpu_ring pointer 1504 * @job: job to retrieve vmid from 1505 * @ib: indirect buffer to execute 1506 * @flags: unused 1507 * 1508 * Write ring commands to execute the indirect buffer 1509 */ 1510 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1511 struct amdgpu_job *job, 1512 struct amdgpu_ib *ib, 1513 uint32_t flags) 1514 { 1515 struct amdgpu_device *adev = ring->adev; 1516 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1517 1518 amdgpu_ring_write(ring, 1519 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1520 amdgpu_ring_write(ring, vmid); 1521 1522 amdgpu_ring_write(ring, 1523 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1524 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1525 amdgpu_ring_write(ring, 1526 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1527 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1528 amdgpu_ring_write(ring, 1529 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 1530 amdgpu_ring_write(ring, ib->length_dw); 1531 } 1532 1533 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1534 uint32_t reg, uint32_t val, 1535 uint32_t mask) 1536 { 1537 struct amdgpu_device *adev = ring->adev; 1538 1539 amdgpu_ring_write(ring, 1540 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1541 amdgpu_ring_write(ring, reg << 2); 1542 amdgpu_ring_write(ring, 1543 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1544 amdgpu_ring_write(ring, val); 1545 amdgpu_ring_write(ring, 1546 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 1547 amdgpu_ring_write(ring, mask); 1548 amdgpu_ring_write(ring, 1549 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1550 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1551 } 1552 1553 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1554 unsigned vmid, uint64_t pd_addr) 1555 { 1556 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1557 uint32_t data0, data1, mask; 1558 1559 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1560 1561 /* wait for register write */ 1562 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1563 data1 = lower_32_bits(pd_addr); 1564 mask = 0xffffffff; 1565 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1566 } 1567 1568 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1569 uint32_t reg, uint32_t val) 1570 { 1571 struct amdgpu_device *adev = ring->adev; 1572 1573 amdgpu_ring_write(ring, 1574 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1575 amdgpu_ring_write(ring, reg << 2); 1576 amdgpu_ring_write(ring, 1577 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1578 amdgpu_ring_write(ring, val); 1579 amdgpu_ring_write(ring, 1580 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1581 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1582 } 1583 1584 /** 1585 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 1586 * 1587 * @ring: amdgpu_ring pointer 1588 * 1589 * Returns the current hardware enc read pointer 1590 */ 1591 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1592 { 1593 struct amdgpu_device *adev = ring->adev; 1594 1595 if (ring == &adev->vcn.inst->ring_enc[0]) 1596 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1597 else 1598 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1599 } 1600 1601 /** 1602 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 1603 * 1604 * @ring: amdgpu_ring pointer 1605 * 1606 * Returns the current hardware enc write pointer 1607 */ 1608 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1609 { 1610 struct amdgpu_device *adev = ring->adev; 1611 1612 if (ring == &adev->vcn.inst->ring_enc[0]) 1613 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1614 else 1615 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1616 } 1617 1618 /** 1619 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 1620 * 1621 * @ring: amdgpu_ring pointer 1622 * 1623 * Commits the enc write pointer to the hardware 1624 */ 1625 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1626 { 1627 struct amdgpu_device *adev = ring->adev; 1628 1629 if (ring == &adev->vcn.inst->ring_enc[0]) 1630 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, 1631 lower_32_bits(ring->wptr)); 1632 else 1633 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, 1634 lower_32_bits(ring->wptr)); 1635 } 1636 1637 /** 1638 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 1639 * 1640 * @ring: amdgpu_ring pointer 1641 * @addr: address 1642 * @seq: sequence number 1643 * @flags: fence related flags 1644 * 1645 * Write enc a fence and a trap command to the ring. 1646 */ 1647 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1648 u64 seq, unsigned flags) 1649 { 1650 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1651 1652 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1653 amdgpu_ring_write(ring, addr); 1654 amdgpu_ring_write(ring, upper_32_bits(addr)); 1655 amdgpu_ring_write(ring, seq); 1656 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1657 } 1658 1659 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1660 { 1661 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1662 } 1663 1664 /** 1665 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 1666 * 1667 * @ring: amdgpu_ring pointer 1668 * @job: job to retrive vmid from 1669 * @ib: indirect buffer to execute 1670 * @flags: unused 1671 * 1672 * Write enc ring commands to execute the indirect buffer 1673 */ 1674 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1675 struct amdgpu_job *job, 1676 struct amdgpu_ib *ib, 1677 uint32_t flags) 1678 { 1679 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1680 1681 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1682 amdgpu_ring_write(ring, vmid); 1683 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1684 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1685 amdgpu_ring_write(ring, ib->length_dw); 1686 } 1687 1688 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1689 uint32_t reg, uint32_t val, 1690 uint32_t mask) 1691 { 1692 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1693 amdgpu_ring_write(ring, reg << 2); 1694 amdgpu_ring_write(ring, mask); 1695 amdgpu_ring_write(ring, val); 1696 } 1697 1698 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1699 unsigned int vmid, uint64_t pd_addr) 1700 { 1701 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1702 1703 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1704 1705 /* wait for reg writes */ 1706 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1707 vmid * hub->ctx_addr_distance, 1708 lower_32_bits(pd_addr), 0xffffffff); 1709 } 1710 1711 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1712 uint32_t reg, uint32_t val) 1713 { 1714 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1715 amdgpu_ring_write(ring, reg << 2); 1716 amdgpu_ring_write(ring, val); 1717 } 1718 1719 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1720 struct amdgpu_irq_src *source, 1721 unsigned type, 1722 enum amdgpu_interrupt_state state) 1723 { 1724 return 0; 1725 } 1726 1727 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 1728 struct amdgpu_irq_src *source, 1729 struct amdgpu_iv_entry *entry) 1730 { 1731 DRM_DEBUG("IH: VCN TRAP\n"); 1732 1733 switch (entry->src_id) { 1734 case 124: 1735 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1736 break; 1737 case 119: 1738 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1739 break; 1740 case 120: 1741 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1742 break; 1743 default: 1744 DRM_ERROR("Unhandled interrupt: %d %d\n", 1745 entry->src_id, entry->src_data[0]); 1746 break; 1747 } 1748 1749 return 0; 1750 } 1751 1752 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1753 { 1754 struct amdgpu_device *adev = ring->adev; 1755 int i; 1756 1757 WARN_ON(ring->wptr % 2 || count % 2); 1758 1759 for (i = 0; i < count / 2; i++) { 1760 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); 1761 amdgpu_ring_write(ring, 0); 1762 } 1763 } 1764 1765 static int vcn_v1_0_set_powergating_state(void *handle, 1766 enum amd_powergating_state state) 1767 { 1768 /* This doesn't actually powergate the VCN block. 1769 * That's done in the dpm code via the SMC. This 1770 * just re-inits the block as necessary. The actual 1771 * gating still happens in the dpm code. We should 1772 * revisit this when there is a cleaner line between 1773 * the smc and the hw blocks 1774 */ 1775 int ret; 1776 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1777 1778 if(state == adev->vcn.cur_state) 1779 return 0; 1780 1781 if (state == AMD_PG_STATE_GATE) 1782 ret = vcn_v1_0_stop(adev); 1783 else 1784 ret = vcn_v1_0_start(adev); 1785 1786 if(!ret) 1787 adev->vcn.cur_state = state; 1788 return ret; 1789 } 1790 1791 static void vcn_v1_0_idle_work_handler(struct work_struct *work) 1792 { 1793 struct amdgpu_device *adev = 1794 container_of(work, struct amdgpu_device, vcn.idle_work.work); 1795 unsigned int fences = 0, i; 1796 1797 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1798 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1799 1800 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1801 struct dpg_pause_state new_state; 1802 1803 if (fences) 1804 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1805 else 1806 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1807 1808 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1809 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1810 else 1811 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1812 1813 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1814 } 1815 1816 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec); 1817 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec); 1818 1819 if (fences == 0) { 1820 amdgpu_gfx_off_ctrl(adev, true); 1821 if (adev->pm.dpm_enabled) 1822 amdgpu_dpm_enable_uvd(adev, false); 1823 else 1824 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1825 AMD_PG_STATE_GATE); 1826 } else { 1827 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1828 } 1829 } 1830 1831 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring) 1832 { 1833 struct amdgpu_device *adev = ring->adev; 1834 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 1835 1836 mutex_lock(&adev->vcn.vcn1_jpeg1_workaround); 1837 1838 if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec)) 1839 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n"); 1840 1841 vcn_v1_0_set_pg_for_begin_use(ring, set_clocks); 1842 1843 } 1844 1845 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks) 1846 { 1847 struct amdgpu_device *adev = ring->adev; 1848 1849 if (set_clocks) { 1850 amdgpu_gfx_off_ctrl(adev, false); 1851 if (adev->pm.dpm_enabled) 1852 amdgpu_dpm_enable_uvd(adev, true); 1853 else 1854 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1855 AMD_PG_STATE_UNGATE); 1856 } 1857 1858 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1859 struct dpg_pause_state new_state; 1860 unsigned int fences = 0, i; 1861 1862 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1863 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1864 1865 if (fences) 1866 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1867 else 1868 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1869 1870 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1871 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1872 else 1873 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1874 1875 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 1876 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1877 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 1878 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1879 1880 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1881 } 1882 } 1883 1884 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring) 1885 { 1886 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1887 mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround); 1888 } 1889 1890 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 1891 .name = "vcn_v1_0", 1892 .early_init = vcn_v1_0_early_init, 1893 .late_init = NULL, 1894 .sw_init = vcn_v1_0_sw_init, 1895 .sw_fini = vcn_v1_0_sw_fini, 1896 .hw_init = vcn_v1_0_hw_init, 1897 .hw_fini = vcn_v1_0_hw_fini, 1898 .suspend = vcn_v1_0_suspend, 1899 .resume = vcn_v1_0_resume, 1900 .is_idle = vcn_v1_0_is_idle, 1901 .wait_for_idle = vcn_v1_0_wait_for_idle, 1902 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 1903 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 1904 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 1905 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 1906 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 1907 .set_powergating_state = vcn_v1_0_set_powergating_state, 1908 }; 1909 1910 /* 1911 * It is a hardware issue that VCN can't handle a GTT TMZ buffer on 1912 * CHIP_RAVEN series ASIC. Move such a GTT TMZ buffer to VRAM domain 1913 * before command submission as a workaround. 1914 */ 1915 static int vcn_v1_0_validate_bo(struct amdgpu_cs_parser *parser, 1916 struct amdgpu_job *job, 1917 uint64_t addr) 1918 { 1919 struct ttm_operation_ctx ctx = { false, false }; 1920 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv; 1921 struct amdgpu_vm *vm = &fpriv->vm; 1922 struct amdgpu_bo_va_mapping *mapping; 1923 struct amdgpu_bo *bo; 1924 int r; 1925 1926 addr &= AMDGPU_GMC_HOLE_MASK; 1927 if (addr & 0x7) { 1928 DRM_ERROR("VCN messages must be 8 byte aligned!\n"); 1929 return -EINVAL; 1930 } 1931 1932 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr/AMDGPU_GPU_PAGE_SIZE); 1933 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo) 1934 return -EINVAL; 1935 1936 bo = mapping->bo_va->base.bo; 1937 if (!(bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED)) 1938 return 0; 1939 1940 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 1941 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1942 if (r) { 1943 DRM_ERROR("Failed to validate the VCN message BO (%d)!\n", r); 1944 return r; 1945 } 1946 1947 return r; 1948 } 1949 1950 static int vcn_v1_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1951 struct amdgpu_job *job, 1952 struct amdgpu_ib *ib) 1953 { 1954 uint32_t msg_lo = 0, msg_hi = 0; 1955 int i, r; 1956 1957 if (!(ib->flags & AMDGPU_IB_FLAGS_SECURE)) 1958 return 0; 1959 1960 for (i = 0; i < ib->length_dw; i += 2) { 1961 uint32_t reg = amdgpu_ib_get_value(ib, i); 1962 uint32_t val = amdgpu_ib_get_value(ib, i + 1); 1963 1964 if (reg == PACKET0(p->adev->vcn.internal.data0, 0)) { 1965 msg_lo = val; 1966 } else if (reg == PACKET0(p->adev->vcn.internal.data1, 0)) { 1967 msg_hi = val; 1968 } else if (reg == PACKET0(p->adev->vcn.internal.cmd, 0)) { 1969 r = vcn_v1_0_validate_bo(p, job, 1970 ((u64)msg_hi) << 32 | msg_lo); 1971 if (r) 1972 return r; 1973 } 1974 } 1975 1976 return 0; 1977 } 1978 1979 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 1980 .type = AMDGPU_RING_TYPE_VCN_DEC, 1981 .align_mask = 0xf, 1982 .support_64bit_ptrs = false, 1983 .no_user_fence = true, 1984 .secure_submission_supported = true, 1985 .vmhub = AMDGPU_MMHUB_0, 1986 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 1987 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 1988 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 1989 .patch_cs_in_place = vcn_v1_0_ring_patch_cs_in_place, 1990 .emit_frame_size = 1991 6 + 6 + /* hdp invalidate / flush */ 1992 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1993 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1994 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 1995 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 1996 6, 1997 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 1998 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 1999 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 2000 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 2001 .test_ring = amdgpu_vcn_dec_ring_test_ring, 2002 .test_ib = amdgpu_vcn_dec_ring_test_ib, 2003 .insert_nop = vcn_v1_0_dec_ring_insert_nop, 2004 .insert_start = vcn_v1_0_dec_ring_insert_start, 2005 .insert_end = vcn_v1_0_dec_ring_insert_end, 2006 .pad_ib = amdgpu_ring_generic_pad_ib, 2007 .begin_use = vcn_v1_0_ring_begin_use, 2008 .end_use = vcn_v1_0_ring_end_use, 2009 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, 2010 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, 2011 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2012 }; 2013 2014 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 2015 .type = AMDGPU_RING_TYPE_VCN_ENC, 2016 .align_mask = 0x3f, 2017 .nop = VCN_ENC_CMD_NO_OP, 2018 .support_64bit_ptrs = false, 2019 .no_user_fence = true, 2020 .vmhub = AMDGPU_MMHUB_0, 2021 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 2022 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 2023 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 2024 .emit_frame_size = 2025 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 2026 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 2027 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ 2028 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 2029 1, /* vcn_v1_0_enc_ring_insert_end */ 2030 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 2031 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 2032 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 2033 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 2034 .test_ring = amdgpu_vcn_enc_ring_test_ring, 2035 .test_ib = amdgpu_vcn_enc_ring_test_ib, 2036 .insert_nop = amdgpu_ring_insert_nop, 2037 .insert_end = vcn_v1_0_enc_ring_insert_end, 2038 .pad_ib = amdgpu_ring_generic_pad_ib, 2039 .begin_use = vcn_v1_0_ring_begin_use, 2040 .end_use = vcn_v1_0_ring_end_use, 2041 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, 2042 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, 2043 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 2044 }; 2045 2046 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 2047 { 2048 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 2049 DRM_INFO("VCN decode is enabled in VM mode\n"); 2050 } 2051 2052 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 2053 { 2054 int i; 2055 2056 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 2057 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 2058 2059 DRM_INFO("VCN encode is enabled in VM mode\n"); 2060 } 2061 2062 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 2063 .set = vcn_v1_0_set_interrupt_state, 2064 .process = vcn_v1_0_process_interrupt, 2065 }; 2066 2067 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 2068 { 2069 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; 2070 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs; 2071 } 2072 2073 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = 2074 { 2075 .type = AMD_IP_BLOCK_TYPE_VCN, 2076 .major = 1, 2077 .minor = 0, 2078 .rev = 0, 2079 .funcs = &vcn_v1_0_ip_funcs, 2080 }; 2081