1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 26 #include "amdgpu.h" 27 #include "amdgpu_uvd.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "soc15_common.h" 31 #include "mmsch_v1_0.h" 32 33 #include "uvd/uvd_7_0_offset.h" 34 #include "uvd/uvd_7_0_sh_mask.h" 35 #include "vce/vce_4_0_offset.h" 36 #include "vce/vce_4_0_default.h" 37 #include "vce/vce_4_0_sh_mask.h" 38 #include "nbif/nbif_6_1_offset.h" 39 #include "mmhub/mmhub_1_0_offset.h" 40 #include "mmhub/mmhub_1_0_sh_mask.h" 41 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h" 42 43 #define mmUVD_PG0_CC_UVD_HARVESTING 0x00c7 44 #define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX 1 45 //UVD_PG0_CC_UVD_HARVESTING 46 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 47 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 48 49 #define UVD7_MAX_HW_INSTANCES_VEGA20 2 50 51 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev); 52 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev); 53 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev); 54 static int uvd_v7_0_start(struct amdgpu_device *adev); 55 static void uvd_v7_0_stop(struct amdgpu_device *adev); 56 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev); 57 58 static int amdgpu_ih_clientid_uvds[] = { 59 SOC15_IH_CLIENTID_UVD, 60 SOC15_IH_CLIENTID_UVD1 61 }; 62 63 /** 64 * uvd_v7_0_ring_get_rptr - get read pointer 65 * 66 * @ring: amdgpu_ring pointer 67 * 68 * Returns the current hardware read pointer 69 */ 70 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring) 71 { 72 struct amdgpu_device *adev = ring->adev; 73 74 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR); 75 } 76 77 /** 78 * uvd_v7_0_enc_ring_get_rptr - get enc read pointer 79 * 80 * @ring: amdgpu_ring pointer 81 * 82 * Returns the current hardware enc read pointer 83 */ 84 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 85 { 86 struct amdgpu_device *adev = ring->adev; 87 88 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 89 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); 90 else 91 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); 92 } 93 94 /** 95 * uvd_v7_0_ring_get_wptr - get write pointer 96 * 97 * @ring: amdgpu_ring pointer 98 * 99 * Returns the current hardware write pointer 100 */ 101 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring) 102 { 103 struct amdgpu_device *adev = ring->adev; 104 105 return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR); 106 } 107 108 /** 109 * uvd_v7_0_enc_ring_get_wptr - get enc write pointer 110 * 111 * @ring: amdgpu_ring pointer 112 * 113 * Returns the current hardware enc write pointer 114 */ 115 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 116 { 117 struct amdgpu_device *adev = ring->adev; 118 119 if (ring->use_doorbell) 120 return adev->wb.wb[ring->wptr_offs]; 121 122 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 123 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); 124 else 125 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); 126 } 127 128 /** 129 * uvd_v7_0_ring_set_wptr - set write pointer 130 * 131 * @ring: amdgpu_ring pointer 132 * 133 * Commits the write pointer to the hardware 134 */ 135 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring) 136 { 137 struct amdgpu_device *adev = ring->adev; 138 139 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 140 } 141 142 /** 143 * uvd_v7_0_enc_ring_set_wptr - set enc write pointer 144 * 145 * @ring: amdgpu_ring pointer 146 * 147 * Commits the enc write pointer to the hardware 148 */ 149 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 150 { 151 struct amdgpu_device *adev = ring->adev; 152 153 if (ring->use_doorbell) { 154 /* XXX check if swapping is necessary on BE */ 155 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); 156 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); 157 return; 158 } 159 160 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) 161 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, 162 lower_32_bits(ring->wptr)); 163 else 164 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, 165 lower_32_bits(ring->wptr)); 166 } 167 168 /** 169 * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working 170 * 171 * @ring: the engine to test on 172 * 173 */ 174 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) 175 { 176 struct amdgpu_device *adev = ring->adev; 177 uint32_t rptr; 178 unsigned i; 179 int r; 180 181 if (amdgpu_sriov_vf(adev)) 182 return 0; 183 184 r = amdgpu_ring_alloc(ring, 16); 185 if (r) 186 return r; 187 188 rptr = amdgpu_ring_get_rptr(ring); 189 190 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 191 amdgpu_ring_commit(ring); 192 193 for (i = 0; i < adev->usec_timeout; i++) { 194 if (amdgpu_ring_get_rptr(ring) != rptr) 195 break; 196 udelay(1); 197 } 198 199 if (i >= adev->usec_timeout) 200 r = -ETIMEDOUT; 201 202 return r; 203 } 204 205 /** 206 * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg 207 * 208 * @ring: ring we should submit the msg to 209 * @handle: session handle to use 210 * @bo: amdgpu object for which we query the offset 211 * @fence: optional fence to return 212 * 213 * Open up a stream for HW test 214 */ 215 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 216 struct amdgpu_bo *bo, 217 struct dma_fence **fence) 218 { 219 const unsigned ib_size_dw = 16; 220 struct amdgpu_job *job; 221 struct amdgpu_ib *ib; 222 struct dma_fence *f = NULL; 223 uint64_t addr; 224 int i, r; 225 226 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 227 AMDGPU_IB_POOL_DIRECT, &job); 228 if (r) 229 return r; 230 231 ib = &job->ibs[0]; 232 addr = amdgpu_bo_gpu_offset(bo); 233 234 ib->length_dw = 0; 235 ib->ptr[ib->length_dw++] = 0x00000018; 236 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */ 237 ib->ptr[ib->length_dw++] = handle; 238 ib->ptr[ib->length_dw++] = 0x00000000; 239 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 240 ib->ptr[ib->length_dw++] = addr; 241 242 ib->ptr[ib->length_dw++] = 0x00000014; 243 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */ 244 ib->ptr[ib->length_dw++] = 0x0000001c; 245 ib->ptr[ib->length_dw++] = 0x00000000; 246 ib->ptr[ib->length_dw++] = 0x00000000; 247 248 ib->ptr[ib->length_dw++] = 0x00000008; 249 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */ 250 251 for (i = ib->length_dw; i < ib_size_dw; ++i) 252 ib->ptr[i] = 0x0; 253 254 r = amdgpu_job_submit_direct(job, ring, &f); 255 if (r) 256 goto err; 257 258 if (fence) 259 *fence = dma_fence_get(f); 260 dma_fence_put(f); 261 return 0; 262 263 err: 264 amdgpu_job_free(job); 265 return r; 266 } 267 268 /** 269 * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg 270 * 271 * @ring: ring we should submit the msg to 272 * @handle: session handle to use 273 * @bo: amdgpu object for which we query the offset 274 * @fence: optional fence to return 275 * 276 * Close up a stream for HW test or if userspace failed to do so 277 */ 278 static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 279 struct amdgpu_bo *bo, 280 struct dma_fence **fence) 281 { 282 const unsigned ib_size_dw = 16; 283 struct amdgpu_job *job; 284 struct amdgpu_ib *ib; 285 struct dma_fence *f = NULL; 286 uint64_t addr; 287 int i, r; 288 289 r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, 290 AMDGPU_IB_POOL_DIRECT, &job); 291 if (r) 292 return r; 293 294 ib = &job->ibs[0]; 295 addr = amdgpu_bo_gpu_offset(bo); 296 297 ib->length_dw = 0; 298 ib->ptr[ib->length_dw++] = 0x00000018; 299 ib->ptr[ib->length_dw++] = 0x00000001; 300 ib->ptr[ib->length_dw++] = handle; 301 ib->ptr[ib->length_dw++] = 0x00000000; 302 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 303 ib->ptr[ib->length_dw++] = addr; 304 305 ib->ptr[ib->length_dw++] = 0x00000014; 306 ib->ptr[ib->length_dw++] = 0x00000002; 307 ib->ptr[ib->length_dw++] = 0x0000001c; 308 ib->ptr[ib->length_dw++] = 0x00000000; 309 ib->ptr[ib->length_dw++] = 0x00000000; 310 311 ib->ptr[ib->length_dw++] = 0x00000008; 312 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */ 313 314 for (i = ib->length_dw; i < ib_size_dw; ++i) 315 ib->ptr[i] = 0x0; 316 317 r = amdgpu_job_submit_direct(job, ring, &f); 318 if (r) 319 goto err; 320 321 if (fence) 322 *fence = dma_fence_get(f); 323 dma_fence_put(f); 324 return 0; 325 326 err: 327 amdgpu_job_free(job); 328 return r; 329 } 330 331 /** 332 * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working 333 * 334 * @ring: the engine to test on 335 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT 336 * 337 */ 338 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) 339 { 340 struct dma_fence *fence = NULL; 341 struct amdgpu_bo *bo = NULL; 342 long r; 343 344 r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE, 345 AMDGPU_GEM_DOMAIN_VRAM, 346 &bo, NULL, NULL); 347 if (r) 348 return r; 349 350 r = uvd_v7_0_enc_get_create_msg(ring, 1, bo, NULL); 351 if (r) 352 goto error; 353 354 r = uvd_v7_0_enc_get_destroy_msg(ring, 1, bo, &fence); 355 if (r) 356 goto error; 357 358 r = dma_fence_wait_timeout(fence, false, timeout); 359 if (r == 0) 360 r = -ETIMEDOUT; 361 else if (r > 0) 362 r = 0; 363 364 error: 365 dma_fence_put(fence); 366 amdgpu_bo_unpin(bo); 367 amdgpu_bo_unreserve(bo); 368 amdgpu_bo_unref(&bo); 369 return r; 370 } 371 372 static int uvd_v7_0_early_init(void *handle) 373 { 374 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 375 376 if (adev->asic_type == CHIP_VEGA20) { 377 u32 harvest; 378 int i; 379 380 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20; 381 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 382 harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING); 383 if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) { 384 adev->uvd.harvest_config |= 1 << i; 385 } 386 } 387 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 | 388 AMDGPU_UVD_HARVEST_UVD1)) 389 /* both instances are harvested, disable the block */ 390 return -ENOENT; 391 } else { 392 adev->uvd.num_uvd_inst = 1; 393 } 394 395 if (amdgpu_sriov_vf(adev)) 396 adev->uvd.num_enc_rings = 1; 397 else 398 adev->uvd.num_enc_rings = 2; 399 uvd_v7_0_set_ring_funcs(adev); 400 uvd_v7_0_set_enc_ring_funcs(adev); 401 uvd_v7_0_set_irq_funcs(adev); 402 403 return 0; 404 } 405 406 static int uvd_v7_0_sw_init(void *handle) 407 { 408 struct amdgpu_ring *ring; 409 410 int i, j, r; 411 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 412 413 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 414 if (adev->uvd.harvest_config & (1 << j)) 415 continue; 416 /* UVD TRAP */ 417 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq); 418 if (r) 419 return r; 420 421 /* UVD ENC TRAP */ 422 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 423 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq); 424 if (r) 425 return r; 426 } 427 } 428 429 r = amdgpu_uvd_sw_init(adev); 430 if (r) 431 return r; 432 433 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 434 const struct common_firmware_header *hdr; 435 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 436 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD; 437 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw; 438 adev->firmware.fw_size += 439 roundup2(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 440 441 if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) { 442 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1; 443 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw; 444 adev->firmware.fw_size += 445 roundup2(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 446 } 447 DRM_INFO("PSP loading UVD firmware\n"); 448 } 449 450 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 451 if (adev->uvd.harvest_config & (1 << j)) 452 continue; 453 if (!amdgpu_sriov_vf(adev)) { 454 ring = &adev->uvd.inst[j].ring; 455 snprintf(ring->name, sizeof(ring->name), "uvd_%d", ring->me); 456 r = amdgpu_ring_init(adev, ring, 512, 457 &adev->uvd.inst[j].irq, 0, 458 AMDGPU_RING_PRIO_DEFAULT, NULL); 459 if (r) 460 return r; 461 } 462 463 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 464 ring = &adev->uvd.inst[j].ring_enc[i]; 465 snprintf(ring->name, sizeof(ring->name), "uvd_enc_%d.%d", ring->me, i); 466 if (amdgpu_sriov_vf(adev)) { 467 ring->use_doorbell = true; 468 469 /* currently only use the first enconding ring for 470 * sriov, so set unused location for other unused rings. 471 */ 472 if (i == 0) 473 ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring0_1 * 2; 474 else 475 ring->doorbell_index = adev->doorbell_index.uvd_vce.uvd_ring2_3 * 2 + 1; 476 } 477 r = amdgpu_ring_init(adev, ring, 512, 478 &adev->uvd.inst[j].irq, 0, 479 AMDGPU_RING_PRIO_DEFAULT, NULL); 480 if (r) 481 return r; 482 } 483 } 484 485 r = amdgpu_uvd_resume(adev); 486 if (r) 487 return r; 488 489 r = amdgpu_uvd_entity_init(adev); 490 if (r) 491 return r; 492 493 r = amdgpu_virt_alloc_mm_table(adev); 494 if (r) 495 return r; 496 497 return r; 498 } 499 500 static int uvd_v7_0_sw_fini(void *handle) 501 { 502 int i, j, r; 503 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 504 505 amdgpu_virt_free_mm_table(adev); 506 507 r = amdgpu_uvd_suspend(adev); 508 if (r) 509 return r; 510 511 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 512 if (adev->uvd.harvest_config & (1 << j)) 513 continue; 514 for (i = 0; i < adev->uvd.num_enc_rings; ++i) 515 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 516 } 517 return amdgpu_uvd_sw_fini(adev); 518 } 519 520 /** 521 * uvd_v7_0_hw_init - start and test UVD block 522 * 523 * @handle: handle used to pass amdgpu_device pointer 524 * 525 * Initialize the hardware, boot up the VCPU and do some testing 526 */ 527 static int uvd_v7_0_hw_init(void *handle) 528 { 529 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 530 struct amdgpu_ring *ring; 531 uint32_t tmp; 532 int i, j, r; 533 534 if (amdgpu_sriov_vf(adev)) 535 r = uvd_v7_0_sriov_start(adev); 536 else 537 r = uvd_v7_0_start(adev); 538 if (r) 539 goto done; 540 541 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 542 if (adev->uvd.harvest_config & (1 << j)) 543 continue; 544 ring = &adev->uvd.inst[j].ring; 545 546 if (!amdgpu_sriov_vf(adev)) { 547 r = amdgpu_ring_test_helper(ring); 548 if (r) 549 goto done; 550 551 r = amdgpu_ring_alloc(ring, 10); 552 if (r) { 553 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r); 554 goto done; 555 } 556 557 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 558 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0); 559 amdgpu_ring_write(ring, tmp); 560 amdgpu_ring_write(ring, 0xFFFFF); 561 562 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 563 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0); 564 amdgpu_ring_write(ring, tmp); 565 amdgpu_ring_write(ring, 0xFFFFF); 566 567 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, 568 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0); 569 amdgpu_ring_write(ring, tmp); 570 amdgpu_ring_write(ring, 0xFFFFF); 571 572 /* Clear timeout status bits */ 573 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 574 mmUVD_SEMA_TIMEOUT_STATUS), 0)); 575 amdgpu_ring_write(ring, 0x8); 576 577 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j, 578 mmUVD_SEMA_CNTL), 0)); 579 amdgpu_ring_write(ring, 3); 580 581 amdgpu_ring_commit(ring); 582 } 583 584 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 585 ring = &adev->uvd.inst[j].ring_enc[i]; 586 r = amdgpu_ring_test_helper(ring); 587 if (r) 588 goto done; 589 } 590 } 591 done: 592 if (!r) 593 DRM_INFO("UVD and UVD ENC initialized successfully.\n"); 594 595 return r; 596 } 597 598 /** 599 * uvd_v7_0_hw_fini - stop the hardware block 600 * 601 * @handle: handle used to pass amdgpu_device pointer 602 * 603 * Stop the UVD block, mark ring as not ready any more 604 */ 605 static int uvd_v7_0_hw_fini(void *handle) 606 { 607 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 608 609 cancel_delayed_work_sync(&adev->uvd.idle_work); 610 611 if (!amdgpu_sriov_vf(adev)) 612 uvd_v7_0_stop(adev); 613 else { 614 /* full access mode, so don't touch any UVD register */ 615 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n"); 616 } 617 618 return 0; 619 } 620 621 static int uvd_v7_0_suspend(void *handle) 622 { 623 int r; 624 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 625 626 /* 627 * Proper cleanups before halting the HW engine: 628 * - cancel the delayed idle work 629 * - enable powergating 630 * - enable clockgating 631 * - disable dpm 632 * 633 * TODO: to align with the VCN implementation, move the 634 * jobs for clockgating/powergating/dpm setting to 635 * ->set_powergating_state(). 636 */ 637 cancel_delayed_work_sync(&adev->uvd.idle_work); 638 639 if (adev->pm.dpm_enabled) { 640 amdgpu_dpm_enable_uvd(adev, false); 641 } else { 642 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 643 /* shutdown the UVD block */ 644 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 645 AMD_PG_STATE_GATE); 646 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 647 AMD_CG_STATE_GATE); 648 } 649 650 r = uvd_v7_0_hw_fini(adev); 651 if (r) 652 return r; 653 654 return amdgpu_uvd_suspend(adev); 655 } 656 657 static int uvd_v7_0_resume(void *handle) 658 { 659 int r; 660 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 661 662 r = amdgpu_uvd_resume(adev); 663 if (r) 664 return r; 665 666 return uvd_v7_0_hw_init(adev); 667 } 668 669 /** 670 * uvd_v7_0_mc_resume - memory controller programming 671 * 672 * @adev: amdgpu_device pointer 673 * 674 * Let the UVD memory controller know it's offsets 675 */ 676 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev) 677 { 678 uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 679 uint32_t offset; 680 int i; 681 682 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 683 if (adev->uvd.harvest_config & (1 << i)) 684 continue; 685 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 686 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 687 i == 0 ? 688 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo: 689 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo); 690 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 691 i == 0 ? 692 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi: 693 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi); 694 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); 695 offset = 0; 696 } else { 697 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 698 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 699 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 700 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 701 offset = size; 702 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 703 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 704 } 705 706 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); 707 708 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 709 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 710 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 711 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 712 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21)); 713 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE); 714 715 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 716 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 717 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 718 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 719 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21)); 720 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2, 721 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 722 723 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG, 724 adev->gfx.config.gb_addr_config); 725 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG, 726 adev->gfx.config.gb_addr_config); 727 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG, 728 adev->gfx.config.gb_addr_config); 729 730 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); 731 } 732 } 733 734 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev, 735 struct amdgpu_mm_table *table) 736 { 737 uint32_t data = 0, loop; 738 uint64_t addr = table->gpu_addr; 739 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr; 740 uint32_t size; 741 int i; 742 743 size = header->header_size + header->vce_table_size + header->uvd_table_size; 744 745 /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */ 746 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); 747 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); 748 749 /* 2, update vmid of descriptor */ 750 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID); 751 data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK; 752 data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */ 753 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data); 754 755 /* 3, notify mmsch about the size of this descriptor */ 756 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size); 757 758 /* 4, set resp to zero */ 759 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0); 760 761 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 762 if (adev->uvd.harvest_config & (1 << i)) 763 continue; 764 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0); 765 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0; 766 adev->uvd.inst[i].ring_enc[0].wptr = 0; 767 adev->uvd.inst[i].ring_enc[0].wptr_old = 0; 768 } 769 /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */ 770 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001); 771 772 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 773 loop = 1000; 774 while ((data & 0x10000002) != 0x10000002) { 775 udelay(10); 776 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP); 777 loop--; 778 if (!loop) 779 break; 780 } 781 782 if (!loop) { 783 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data); 784 return -EBUSY; 785 } 786 787 return 0; 788 } 789 790 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev) 791 { 792 struct amdgpu_ring *ring; 793 uint32_t offset, size, tmp; 794 uint32_t table_size = 0; 795 struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} }; 796 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} }; 797 struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} }; 798 struct mmsch_v1_0_cmd_end end = { {0} }; 799 uint32_t *init_table = adev->virt.mm_table.cpu_addr; 800 struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table; 801 uint8_t i = 0; 802 803 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE; 804 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; 805 direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING; 806 end.cmd_header.command_type = MMSCH_COMMAND__END; 807 808 if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) { 809 header->version = MMSCH_VERSION; 810 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2; 811 812 if (header->vce_table_offset == 0 && header->vce_table_size == 0) 813 header->uvd_table_offset = header->header_size; 814 else 815 header->uvd_table_offset = header->vce_table_size + header->vce_table_offset; 816 817 init_table += header->uvd_table_offset; 818 819 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 820 if (adev->uvd.harvest_config & (1 << i)) 821 continue; 822 ring = &adev->uvd.inst[i].ring; 823 ring->wptr = 0; 824 size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4); 825 826 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 827 0xFFFFFFFF, 0x00000004); 828 /* mc resume*/ 829 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 830 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, 831 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 832 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo); 833 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, 834 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 835 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi); 836 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0); 837 offset = 0; 838 } else { 839 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 840 lower_32_bits(adev->uvd.inst[i].gpu_addr)); 841 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 842 upper_32_bits(adev->uvd.inst[i].gpu_addr)); 843 offset = size; 844 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 845 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 846 847 } 848 849 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size); 850 851 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 852 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 853 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 854 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); 855 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21)); 856 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE); 857 858 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), 859 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 860 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), 861 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); 862 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21)); 863 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2), 864 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40)); 865 866 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); 867 /* mc resume end*/ 868 869 /* disable clock gating */ 870 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), 871 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0); 872 873 /* disable interupt */ 874 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 875 ~UVD_MASTINT_EN__VCPU_EN_MASK, 0); 876 877 /* stall UMC and register bus before resetting VCPU */ 878 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 879 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 880 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 881 882 /* put LMI, VCPU, RBC etc... into reset */ 883 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 884 (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 885 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 886 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 887 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 888 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 889 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 890 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 891 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK)); 892 893 /* initialize UVD memory controller */ 894 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL), 895 (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 896 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 897 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 898 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 899 UVD_LMI_CTRL__REQ_MODE_MASK | 900 0x00100000L)); 901 902 /* take all subblocks out of reset, except VCPU */ 903 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 904 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 905 906 /* enable VCPU clock */ 907 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL), 908 UVD_VCPU_CNTL__CLK_EN_MASK); 909 910 /* enable master interrupt */ 911 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), 912 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 913 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 914 915 /* clear the bit 4 of UVD_STATUS */ 916 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 917 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0); 918 919 /* force RBC into idle state */ 920 size = order_base_2(ring->ring_size); 921 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size); 922 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 923 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp); 924 925 ring = &adev->uvd.inst[i].ring_enc[0]; 926 ring->wptr = 0; 927 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); 928 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr)); 929 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); 930 931 /* boot up the VCPU */ 932 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0); 933 934 /* enable UMC */ 935 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 936 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); 937 938 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); 939 } 940 /* add end packet */ 941 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end)); 942 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4; 943 header->uvd_table_size = table_size; 944 945 } 946 return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table); 947 } 948 949 /** 950 * uvd_v7_0_start - start UVD block 951 * 952 * @adev: amdgpu_device pointer 953 * 954 * Setup and start the UVD block 955 */ 956 static int uvd_v7_0_start(struct amdgpu_device *adev) 957 { 958 struct amdgpu_ring *ring; 959 uint32_t rb_bufsz, tmp; 960 uint32_t lmi_swap_cntl; 961 uint32_t mp_swap_cntl; 962 int i, j, k, r; 963 964 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 965 if (adev->uvd.harvest_config & (1 << k)) 966 continue; 967 /* disable DPG */ 968 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0, 969 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 970 } 971 972 /* disable byte swapping */ 973 lmi_swap_cntl = 0; 974 mp_swap_cntl = 0; 975 976 uvd_v7_0_mc_resume(adev); 977 978 for (k = 0; k < adev->uvd.num_uvd_inst; ++k) { 979 if (adev->uvd.harvest_config & (1 << k)) 980 continue; 981 ring = &adev->uvd.inst[k].ring; 982 /* disable clock gating */ 983 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, 984 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK); 985 986 /* disable interupt */ 987 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0, 988 ~UVD_MASTINT_EN__VCPU_EN_MASK); 989 990 /* stall UMC and register bus before resetting VCPU */ 991 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 992 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 993 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 994 mdelay(1); 995 996 /* put LMI, VCPU, RBC etc... into reset */ 997 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 998 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 999 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | 1000 UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 1001 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | 1002 UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 1003 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | 1004 UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 1005 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1006 mdelay(5); 1007 1008 /* initialize UVD memory controller */ 1009 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL, 1010 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1011 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1012 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1013 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1014 UVD_LMI_CTRL__REQ_MODE_MASK | 1015 0x00100000L); 1016 1017 #ifdef __BIG_ENDIAN 1018 /* swap (8 in 32) RB and IB */ 1019 lmi_swap_cntl = 0xa; 1020 mp_swap_cntl = 0; 1021 #endif 1022 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 1023 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 1024 1025 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040); 1026 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0); 1027 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040); 1028 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0); 1029 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0); 1030 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88); 1031 1032 /* take all subblocks out of reset, except VCPU */ 1033 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 1034 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1035 mdelay(5); 1036 1037 /* enable VCPU clock */ 1038 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL, 1039 UVD_VCPU_CNTL__CLK_EN_MASK); 1040 1041 /* enable UMC */ 1042 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0, 1043 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1044 1045 /* boot up the VCPU */ 1046 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0); 1047 mdelay(10); 1048 1049 for (i = 0; i < 10; ++i) { 1050 uint32_t status; 1051 1052 for (j = 0; j < 100; ++j) { 1053 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); 1054 if (status & 2) 1055 break; 1056 mdelay(10); 1057 } 1058 r = 0; 1059 if (status & 2) 1060 break; 1061 1062 DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k); 1063 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 1064 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1065 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1066 mdelay(10); 1067 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0, 1068 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1069 mdelay(10); 1070 r = -1; 1071 } 1072 1073 if (r) { 1074 DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k); 1075 return r; 1076 } 1077 /* enable master interrupt */ 1078 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 1079 (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 1080 ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK)); 1081 1082 /* clear the bit 4 of UVD_STATUS */ 1083 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, 1084 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); 1085 1086 /* force RBC into idle state */ 1087 rb_bufsz = order_base_2(ring->ring_size); 1088 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1089 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1090 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1091 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 1092 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1093 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1094 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp); 1095 1096 /* set the write pointer delay */ 1097 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0); 1098 1099 /* set the wb address */ 1100 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR, 1101 (upper_32_bits(ring->gpu_addr) >> 2)); 1102 1103 /* program the RB_BASE for ring buffer */ 1104 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1105 lower_32_bits(ring->gpu_addr)); 1106 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1107 upper_32_bits(ring->gpu_addr)); 1108 1109 /* Initialize the ring buffer's read and write pointers */ 1110 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0); 1111 1112 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); 1113 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR, 1114 lower_32_bits(ring->wptr)); 1115 1116 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0, 1117 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1118 1119 ring = &adev->uvd.inst[k].ring_enc[0]; 1120 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1121 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1122 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); 1123 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1124 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); 1125 1126 ring = &adev->uvd.inst[k].ring_enc[1]; 1127 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1128 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1129 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1130 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1131 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4); 1132 } 1133 return 0; 1134 } 1135 1136 /** 1137 * uvd_v7_0_stop - stop UVD block 1138 * 1139 * @adev: amdgpu_device pointer 1140 * 1141 * stop the UVD block 1142 */ 1143 static void uvd_v7_0_stop(struct amdgpu_device *adev) 1144 { 1145 uint8_t i = 0; 1146 1147 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1148 if (adev->uvd.harvest_config & (1 << i)) 1149 continue; 1150 /* force RBC into idle state */ 1151 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101); 1152 1153 /* Stall UMC and register bus before resetting VCPU */ 1154 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 1155 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 1156 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1157 mdelay(1); 1158 1159 /* put VCPU into reset */ 1160 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET, 1161 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1162 mdelay(5); 1163 1164 /* disable VCPU clock */ 1165 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0); 1166 1167 /* Unstall UMC and register bus */ 1168 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0, 1169 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 1170 } 1171 } 1172 1173 /** 1174 * uvd_v7_0_ring_emit_fence - emit an fence & trap command 1175 * 1176 * @ring: amdgpu_ring pointer 1177 * @addr: address 1178 * @seq: sequence number 1179 * @flags: fence related flags 1180 * 1181 * Write a fence and a trap command to the ring. 1182 */ 1183 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1184 unsigned flags) 1185 { 1186 struct amdgpu_device *adev = ring->adev; 1187 1188 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1189 1190 amdgpu_ring_write(ring, 1191 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1192 amdgpu_ring_write(ring, seq); 1193 amdgpu_ring_write(ring, 1194 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1195 amdgpu_ring_write(ring, addr & 0xffffffff); 1196 amdgpu_ring_write(ring, 1197 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1198 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1199 amdgpu_ring_write(ring, 1200 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1201 amdgpu_ring_write(ring, 0); 1202 1203 amdgpu_ring_write(ring, 1204 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1205 amdgpu_ring_write(ring, 0); 1206 amdgpu_ring_write(ring, 1207 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1208 amdgpu_ring_write(ring, 0); 1209 amdgpu_ring_write(ring, 1210 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1211 amdgpu_ring_write(ring, 2); 1212 } 1213 1214 /** 1215 * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command 1216 * 1217 * @ring: amdgpu_ring pointer 1218 * @addr: address 1219 * @seq: sequence number 1220 * @flags: fence related flags 1221 * 1222 * Write enc a fence and a trap command to the ring. 1223 */ 1224 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1225 u64 seq, unsigned flags) 1226 { 1227 1228 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1229 1230 amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); 1231 amdgpu_ring_write(ring, addr); 1232 amdgpu_ring_write(ring, upper_32_bits(addr)); 1233 amdgpu_ring_write(ring, seq); 1234 amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP); 1235 } 1236 1237 /** 1238 * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing 1239 * 1240 * @ring: amdgpu_ring pointer 1241 */ 1242 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 1243 { 1244 /* The firmware doesn't seem to like touching registers at this point. */ 1245 } 1246 1247 /** 1248 * uvd_v7_0_ring_test_ring - register write test 1249 * 1250 * @ring: amdgpu_ring pointer 1251 * 1252 * Test if we can successfully write to the context register 1253 */ 1254 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring) 1255 { 1256 struct amdgpu_device *adev = ring->adev; 1257 uint32_t tmp = 0; 1258 unsigned i; 1259 int r; 1260 1261 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); 1262 r = amdgpu_ring_alloc(ring, 3); 1263 if (r) 1264 return r; 1265 1266 amdgpu_ring_write(ring, 1267 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); 1268 amdgpu_ring_write(ring, 0xDEADBEEF); 1269 amdgpu_ring_commit(ring); 1270 for (i = 0; i < adev->usec_timeout; i++) { 1271 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); 1272 if (tmp == 0xDEADBEEF) 1273 break; 1274 udelay(1); 1275 } 1276 1277 if (i >= adev->usec_timeout) 1278 r = -ETIMEDOUT; 1279 1280 return r; 1281 } 1282 1283 /** 1284 * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission. 1285 * 1286 * @p: the CS parser with the IBs 1287 * @ib_idx: which IB to patch 1288 * 1289 */ 1290 static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, 1291 uint32_t ib_idx) 1292 { 1293 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched); 1294 struct amdgpu_ib *ib = &p->job->ibs[ib_idx]; 1295 unsigned i; 1296 1297 /* No patching necessary for the first instance */ 1298 if (!ring->me) 1299 return 0; 1300 1301 for (i = 0; i < ib->length_dw; i += 2) { 1302 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i); 1303 1304 reg -= p->adev->reg_offset[UVD_HWIP][0][1]; 1305 reg += p->adev->reg_offset[UVD_HWIP][1][1]; 1306 1307 amdgpu_set_ib_value(p, ib_idx, i, reg); 1308 } 1309 return 0; 1310 } 1311 1312 /** 1313 * uvd_v7_0_ring_emit_ib - execute indirect buffer 1314 * 1315 * @ring: amdgpu_ring pointer 1316 * @job: job to retrieve vmid from 1317 * @ib: indirect buffer to execute 1318 * @flags: unused 1319 * 1320 * Write ring commands to execute the indirect buffer 1321 */ 1322 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, 1323 struct amdgpu_job *job, 1324 struct amdgpu_ib *ib, 1325 uint32_t flags) 1326 { 1327 struct amdgpu_device *adev = ring->adev; 1328 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1329 1330 amdgpu_ring_write(ring, 1331 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); 1332 amdgpu_ring_write(ring, vmid); 1333 1334 amdgpu_ring_write(ring, 1335 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1336 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1337 amdgpu_ring_write(ring, 1338 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1339 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1340 amdgpu_ring_write(ring, 1341 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0)); 1342 amdgpu_ring_write(ring, ib->length_dw); 1343 } 1344 1345 /** 1346 * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer 1347 * 1348 * @ring: amdgpu_ring pointer 1349 * @job: job to retrive vmid from 1350 * @ib: indirect buffer to execute 1351 * @flags: unused 1352 * 1353 * Write enc ring commands to execute the indirect buffer 1354 */ 1355 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1356 struct amdgpu_job *job, 1357 struct amdgpu_ib *ib, 1358 uint32_t flags) 1359 { 1360 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1361 1362 amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM); 1363 amdgpu_ring_write(ring, vmid); 1364 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1365 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1366 amdgpu_ring_write(ring, ib->length_dw); 1367 } 1368 1369 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, 1370 uint32_t reg, uint32_t val) 1371 { 1372 struct amdgpu_device *adev = ring->adev; 1373 1374 amdgpu_ring_write(ring, 1375 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1376 amdgpu_ring_write(ring, reg << 2); 1377 amdgpu_ring_write(ring, 1378 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1379 amdgpu_ring_write(ring, val); 1380 amdgpu_ring_write(ring, 1381 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1382 amdgpu_ring_write(ring, 8); 1383 } 1384 1385 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1386 uint32_t val, uint32_t mask) 1387 { 1388 struct amdgpu_device *adev = ring->adev; 1389 1390 amdgpu_ring_write(ring, 1391 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0)); 1392 amdgpu_ring_write(ring, reg << 2); 1393 amdgpu_ring_write(ring, 1394 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0)); 1395 amdgpu_ring_write(ring, val); 1396 amdgpu_ring_write(ring, 1397 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0)); 1398 amdgpu_ring_write(ring, mask); 1399 amdgpu_ring_write(ring, 1400 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0)); 1401 amdgpu_ring_write(ring, 12); 1402 } 1403 1404 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1405 unsigned vmid, uint64_t pd_addr) 1406 { 1407 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1408 uint32_t data0, data1, mask; 1409 1410 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1411 1412 /* wait for reg writes */ 1413 data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance; 1414 data1 = lower_32_bits(pd_addr); 1415 mask = 0xffffffff; 1416 uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask); 1417 } 1418 1419 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1420 { 1421 struct amdgpu_device *adev = ring->adev; 1422 int i; 1423 1424 WARN_ON(ring->wptr % 2 || count % 2); 1425 1426 for (i = 0; i < count / 2; i++) { 1427 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0)); 1428 amdgpu_ring_write(ring, 0); 1429 } 1430 } 1431 1432 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1433 { 1434 amdgpu_ring_write(ring, HEVC_ENC_CMD_END); 1435 } 1436 1437 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1438 uint32_t reg, uint32_t val, 1439 uint32_t mask) 1440 { 1441 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT); 1442 amdgpu_ring_write(ring, reg << 2); 1443 amdgpu_ring_write(ring, mask); 1444 amdgpu_ring_write(ring, val); 1445 } 1446 1447 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1448 unsigned int vmid, uint64_t pd_addr) 1449 { 1450 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1451 1452 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1453 1454 /* wait for reg writes */ 1455 uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + 1456 vmid * hub->ctx_addr_distance, 1457 lower_32_bits(pd_addr), 0xffffffff); 1458 } 1459 1460 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1461 uint32_t reg, uint32_t val) 1462 { 1463 amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); 1464 amdgpu_ring_write(ring, reg << 2); 1465 amdgpu_ring_write(ring, val); 1466 } 1467 1468 #if 0 1469 static bool uvd_v7_0_is_idle(void *handle) 1470 { 1471 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1472 1473 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 1474 } 1475 1476 static int uvd_v7_0_wait_for_idle(void *handle) 1477 { 1478 unsigned i; 1479 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1480 1481 for (i = 0; i < adev->usec_timeout; i++) { 1482 if (uvd_v7_0_is_idle(handle)) 1483 return 0; 1484 } 1485 return -ETIMEDOUT; 1486 } 1487 1488 #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd 1489 static bool uvd_v7_0_check_soft_reset(void *handle) 1490 { 1491 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1492 u32 srbm_soft_reset = 0; 1493 u32 tmp = RREG32(mmSRBM_STATUS); 1494 1495 if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) || 1496 REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) || 1497 (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) & 1498 AMDGPU_UVD_STATUS_BUSY_MASK)) 1499 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1500 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1); 1501 1502 if (srbm_soft_reset) { 1503 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset; 1504 return true; 1505 } else { 1506 adev->uvd.inst[ring->me].srbm_soft_reset = 0; 1507 return false; 1508 } 1509 } 1510 1511 static int uvd_v7_0_pre_soft_reset(void *handle) 1512 { 1513 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1514 1515 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1516 return 0; 1517 1518 uvd_v7_0_stop(adev); 1519 return 0; 1520 } 1521 1522 static int uvd_v7_0_soft_reset(void *handle) 1523 { 1524 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1525 u32 srbm_soft_reset; 1526 1527 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1528 return 0; 1529 srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset; 1530 1531 if (srbm_soft_reset) { 1532 u32 tmp; 1533 1534 tmp = RREG32(mmSRBM_SOFT_RESET); 1535 tmp |= srbm_soft_reset; 1536 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1537 WREG32(mmSRBM_SOFT_RESET, tmp); 1538 tmp = RREG32(mmSRBM_SOFT_RESET); 1539 1540 udelay(50); 1541 1542 tmp &= ~srbm_soft_reset; 1543 WREG32(mmSRBM_SOFT_RESET, tmp); 1544 tmp = RREG32(mmSRBM_SOFT_RESET); 1545 1546 /* Wait a little for things to settle down */ 1547 udelay(50); 1548 } 1549 1550 return 0; 1551 } 1552 1553 static int uvd_v7_0_post_soft_reset(void *handle) 1554 { 1555 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1556 1557 if (!adev->uvd.inst[ring->me].srbm_soft_reset) 1558 return 0; 1559 1560 mdelay(5); 1561 1562 return uvd_v7_0_start(adev); 1563 } 1564 #endif 1565 1566 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev, 1567 struct amdgpu_irq_src *source, 1568 unsigned type, 1569 enum amdgpu_interrupt_state state) 1570 { 1571 // TODO 1572 return 0; 1573 } 1574 1575 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev, 1576 struct amdgpu_irq_src *source, 1577 struct amdgpu_iv_entry *entry) 1578 { 1579 uint32_t ip_instance; 1580 1581 switch (entry->client_id) { 1582 case SOC15_IH_CLIENTID_UVD: 1583 ip_instance = 0; 1584 break; 1585 case SOC15_IH_CLIENTID_UVD1: 1586 ip_instance = 1; 1587 break; 1588 default: 1589 DRM_ERROR("Unhandled client id: %d\n", entry->client_id); 1590 return 0; 1591 } 1592 1593 DRM_DEBUG("IH: UVD TRAP\n"); 1594 1595 switch (entry->src_id) { 1596 case 124: 1597 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring); 1598 break; 1599 case 119: 1600 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]); 1601 break; 1602 case 120: 1603 if (!amdgpu_sriov_vf(adev)) 1604 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]); 1605 break; 1606 default: 1607 DRM_ERROR("Unhandled interrupt: %d %d\n", 1608 entry->src_id, entry->src_data[0]); 1609 break; 1610 } 1611 1612 return 0; 1613 } 1614 1615 #if 0 1616 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev) 1617 { 1618 uint32_t data, data1, data2, suvd_flags; 1619 1620 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL); 1621 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); 1622 data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL); 1623 1624 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 1625 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 1626 1627 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1628 UVD_SUVD_CGC_GATE__SIT_MASK | 1629 UVD_SUVD_CGC_GATE__SMP_MASK | 1630 UVD_SUVD_CGC_GATE__SCM_MASK | 1631 UVD_SUVD_CGC_GATE__SDB_MASK; 1632 1633 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 1634 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 1635 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 1636 1637 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 1638 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 1639 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 1640 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 1641 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 1642 UVD_CGC_CTRL__SYS_MODE_MASK | 1643 UVD_CGC_CTRL__UDEC_MODE_MASK | 1644 UVD_CGC_CTRL__MPEG2_MODE_MASK | 1645 UVD_CGC_CTRL__REGS_MODE_MASK | 1646 UVD_CGC_CTRL__RBC_MODE_MASK | 1647 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 1648 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 1649 UVD_CGC_CTRL__IDCT_MODE_MASK | 1650 UVD_CGC_CTRL__MPRD_MODE_MASK | 1651 UVD_CGC_CTRL__MPC_MODE_MASK | 1652 UVD_CGC_CTRL__LBSI_MODE_MASK | 1653 UVD_CGC_CTRL__LRBBM_MODE_MASK | 1654 UVD_CGC_CTRL__WCB_MODE_MASK | 1655 UVD_CGC_CTRL__VCPU_MODE_MASK | 1656 UVD_CGC_CTRL__JPEG_MODE_MASK | 1657 UVD_CGC_CTRL__JPEG2_MODE_MASK | 1658 UVD_CGC_CTRL__SCPU_MODE_MASK); 1659 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 1660 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 1661 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 1662 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 1663 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 1664 data1 |= suvd_flags; 1665 1666 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data); 1667 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0); 1668 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); 1669 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2); 1670 } 1671 1672 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev) 1673 { 1674 uint32_t data, data1, cgc_flags, suvd_flags; 1675 1676 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE); 1677 data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE); 1678 1679 cgc_flags = UVD_CGC_GATE__SYS_MASK | 1680 UVD_CGC_GATE__UDEC_MASK | 1681 UVD_CGC_GATE__MPEG2_MASK | 1682 UVD_CGC_GATE__RBC_MASK | 1683 UVD_CGC_GATE__LMI_MC_MASK | 1684 UVD_CGC_GATE__IDCT_MASK | 1685 UVD_CGC_GATE__MPRD_MASK | 1686 UVD_CGC_GATE__MPC_MASK | 1687 UVD_CGC_GATE__LBSI_MASK | 1688 UVD_CGC_GATE__LRBBM_MASK | 1689 UVD_CGC_GATE__UDEC_RE_MASK | 1690 UVD_CGC_GATE__UDEC_CM_MASK | 1691 UVD_CGC_GATE__UDEC_IT_MASK | 1692 UVD_CGC_GATE__UDEC_DB_MASK | 1693 UVD_CGC_GATE__UDEC_MP_MASK | 1694 UVD_CGC_GATE__WCB_MASK | 1695 UVD_CGC_GATE__VCPU_MASK | 1696 UVD_CGC_GATE__SCPU_MASK | 1697 UVD_CGC_GATE__JPEG_MASK | 1698 UVD_CGC_GATE__JPEG2_MASK; 1699 1700 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 1701 UVD_SUVD_CGC_GATE__SIT_MASK | 1702 UVD_SUVD_CGC_GATE__SMP_MASK | 1703 UVD_SUVD_CGC_GATE__SCM_MASK | 1704 UVD_SUVD_CGC_GATE__SDB_MASK; 1705 1706 data |= cgc_flags; 1707 data1 |= suvd_flags; 1708 1709 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data); 1710 WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1); 1711 } 1712 1713 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable) 1714 { 1715 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); 1716 1717 if (enable) 1718 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 1719 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 1720 else 1721 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK | 1722 GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK); 1723 1724 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); 1725 } 1726 1727 1728 static int uvd_v7_0_set_clockgating_state(void *handle, 1729 enum amd_clockgating_state state) 1730 { 1731 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1732 bool enable = (state == AMD_CG_STATE_GATE); 1733 1734 uvd_v7_0_set_bypass_mode(adev, enable); 1735 1736 if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) 1737 return 0; 1738 1739 if (enable) { 1740 /* disable HW gating and enable Sw gating */ 1741 uvd_v7_0_set_sw_clock_gating(adev); 1742 } else { 1743 /* wait for STATUS to clear */ 1744 if (uvd_v7_0_wait_for_idle(handle)) 1745 return -EBUSY; 1746 1747 /* enable HW gates because UVD is idle */ 1748 /* uvd_v7_0_set_hw_clock_gating(adev); */ 1749 } 1750 1751 return 0; 1752 } 1753 1754 static int uvd_v7_0_set_powergating_state(void *handle, 1755 enum amd_powergating_state state) 1756 { 1757 /* This doesn't actually powergate the UVD block. 1758 * That's done in the dpm code via the SMC. This 1759 * just re-inits the block as necessary. The actual 1760 * gating still happens in the dpm code. We should 1761 * revisit this when there is a cleaner line between 1762 * the smc and the hw blocks 1763 */ 1764 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1765 1766 if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD)) 1767 return 0; 1768 1769 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); 1770 1771 if (state == AMD_PG_STATE_GATE) { 1772 uvd_v7_0_stop(adev); 1773 return 0; 1774 } else { 1775 return uvd_v7_0_start(adev); 1776 } 1777 } 1778 #endif 1779 1780 static int uvd_v7_0_set_clockgating_state(void *handle, 1781 enum amd_clockgating_state state) 1782 { 1783 /* needed for driver unload*/ 1784 return 0; 1785 } 1786 1787 const struct amd_ip_funcs uvd_v7_0_ip_funcs = { 1788 .name = "uvd_v7_0", 1789 .early_init = uvd_v7_0_early_init, 1790 .late_init = NULL, 1791 .sw_init = uvd_v7_0_sw_init, 1792 .sw_fini = uvd_v7_0_sw_fini, 1793 .hw_init = uvd_v7_0_hw_init, 1794 .hw_fini = uvd_v7_0_hw_fini, 1795 .suspend = uvd_v7_0_suspend, 1796 .resume = uvd_v7_0_resume, 1797 .is_idle = NULL /* uvd_v7_0_is_idle */, 1798 .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */, 1799 .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */, 1800 .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */, 1801 .soft_reset = NULL /* uvd_v7_0_soft_reset */, 1802 .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */, 1803 .set_clockgating_state = uvd_v7_0_set_clockgating_state, 1804 .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */, 1805 }; 1806 1807 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { 1808 .type = AMDGPU_RING_TYPE_UVD, 1809 .align_mask = 0xf, 1810 .support_64bit_ptrs = false, 1811 .no_user_fence = true, 1812 .vmhub = AMDGPU_MMHUB_0, 1813 .get_rptr = uvd_v7_0_ring_get_rptr, 1814 .get_wptr = uvd_v7_0_ring_get_wptr, 1815 .set_wptr = uvd_v7_0_ring_set_wptr, 1816 .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place, 1817 .emit_frame_size = 1818 6 + /* hdp invalidate */ 1819 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1820 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1821 8 + /* uvd_v7_0_ring_emit_vm_flush */ 1822 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */ 1823 .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */ 1824 .emit_ib = uvd_v7_0_ring_emit_ib, 1825 .emit_fence = uvd_v7_0_ring_emit_fence, 1826 .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush, 1827 .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush, 1828 .test_ring = uvd_v7_0_ring_test_ring, 1829 .test_ib = amdgpu_uvd_ring_test_ib, 1830 .insert_nop = uvd_v7_0_ring_insert_nop, 1831 .pad_ib = amdgpu_ring_generic_pad_ib, 1832 .begin_use = amdgpu_uvd_ring_begin_use, 1833 .end_use = amdgpu_uvd_ring_end_use, 1834 .emit_wreg = uvd_v7_0_ring_emit_wreg, 1835 .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait, 1836 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1837 }; 1838 1839 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { 1840 .type = AMDGPU_RING_TYPE_UVD_ENC, 1841 .align_mask = 0x3f, 1842 .nop = HEVC_ENC_CMD_NO_OP, 1843 .support_64bit_ptrs = false, 1844 .no_user_fence = true, 1845 .vmhub = AMDGPU_MMHUB_0, 1846 .get_rptr = uvd_v7_0_enc_ring_get_rptr, 1847 .get_wptr = uvd_v7_0_enc_ring_get_wptr, 1848 .set_wptr = uvd_v7_0_enc_ring_set_wptr, 1849 .emit_frame_size = 1850 3 + 3 + /* hdp flush / invalidate */ 1851 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1852 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1853 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */ 1854 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */ 1855 1, /* uvd_v7_0_enc_ring_insert_end */ 1856 .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */ 1857 .emit_ib = uvd_v7_0_enc_ring_emit_ib, 1858 .emit_fence = uvd_v7_0_enc_ring_emit_fence, 1859 .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush, 1860 .test_ring = uvd_v7_0_enc_ring_test_ring, 1861 .test_ib = uvd_v7_0_enc_ring_test_ib, 1862 .insert_nop = amdgpu_ring_insert_nop, 1863 .insert_end = uvd_v7_0_enc_ring_insert_end, 1864 .pad_ib = amdgpu_ring_generic_pad_ib, 1865 .begin_use = amdgpu_uvd_ring_begin_use, 1866 .end_use = amdgpu_uvd_ring_end_use, 1867 .emit_wreg = uvd_v7_0_enc_ring_emit_wreg, 1868 .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait, 1869 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1870 }; 1871 1872 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev) 1873 { 1874 int i; 1875 1876 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1877 if (adev->uvd.harvest_config & (1 << i)) 1878 continue; 1879 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs; 1880 adev->uvd.inst[i].ring.me = i; 1881 DRM_INFO("UVD(%d) is enabled in VM mode\n", i); 1882 } 1883 } 1884 1885 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1886 { 1887 int i, j; 1888 1889 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 1890 if (adev->uvd.harvest_config & (1 << j)) 1891 continue; 1892 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { 1893 adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs; 1894 adev->uvd.inst[j].ring_enc[i].me = j; 1895 } 1896 1897 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j); 1898 } 1899 } 1900 1901 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = { 1902 .set = uvd_v7_0_set_interrupt_state, 1903 .process = uvd_v7_0_process_interrupt, 1904 }; 1905 1906 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev) 1907 { 1908 int i; 1909 1910 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 1911 if (adev->uvd.harvest_config & (1 << i)) 1912 continue; 1913 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1; 1914 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs; 1915 } 1916 } 1917 1918 const struct amdgpu_ip_block_version uvd_v7_0_ip_block = 1919 { 1920 .type = AMD_IP_BLOCK_TYPE_UVD, 1921 .major = 7, 1922 .minor = 0, 1923 .rev = 0, 1924 .funcs = &uvd_v7_0_ip_funcs, 1925 }; 1926