1 /* 2 * Copyright 2021 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_ih.h" 31 #include "amdgpu_uvd.h" 32 #include "amdgpu_vce.h" 33 #include "amdgpu_ucode.h" 34 #include "amdgpu_psp.h" 35 #include "amdgpu_smu.h" 36 #include "atom.h" 37 #include "amd_pcie.h" 38 39 #include "gc/gc_11_0_0_offset.h" 40 #include "gc/gc_11_0_0_sh_mask.h" 41 #include "mp/mp_13_0_0_offset.h" 42 43 #include "soc15.h" 44 #include "soc15_common.h" 45 #include "soc21.h" 46 47 static const struct amd_ip_funcs soc21_common_ip_funcs; 48 49 /* SOC21 */ 50 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = 51 { 52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 54 }; 55 56 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = 57 { 58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 60 }; 61 62 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = 63 { 64 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0), 65 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0, 66 }; 67 68 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = 69 { 70 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1), 71 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1, 72 }; 73 74 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = 75 { 76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 78 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 79 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 80 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 81 }; 82 83 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 89 }; 90 91 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = 92 { 93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0), 94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0, 95 }; 96 97 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = 98 { 99 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1), 100 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1, 101 }; 102 103 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode, 104 const struct amdgpu_video_codecs **codecs) 105 { 106 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config)) 107 return -EINVAL; 108 109 switch (adev->ip_versions[UVD_HWIP][0]) { 110 case IP_VERSION(4, 0, 0): 111 case IP_VERSION(4, 0, 2): 112 case IP_VERSION(4, 0, 4): 113 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) { 114 if (encode) 115 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1; 116 else 117 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1; 118 } else { 119 if (encode) 120 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0; 121 else 122 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0; 123 } 124 return 0; 125 default: 126 return -EINVAL; 127 } 128 } 129 /* 130 * Indirect registers accessor 131 */ 132 static u32 soc21_pcie_rreg(struct amdgpu_device *adev, u32 reg) 133 { 134 unsigned long address, data; 135 address = adev->nbio.funcs->get_pcie_index_offset(adev); 136 data = adev->nbio.funcs->get_pcie_data_offset(adev); 137 138 return amdgpu_device_indirect_rreg(adev, address, data, reg); 139 } 140 141 static void soc21_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 142 { 143 unsigned long address, data; 144 145 address = adev->nbio.funcs->get_pcie_index_offset(adev); 146 data = adev->nbio.funcs->get_pcie_data_offset(adev); 147 148 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 149 } 150 151 static u64 soc21_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 152 { 153 unsigned long address, data; 154 address = adev->nbio.funcs->get_pcie_index_offset(adev); 155 data = adev->nbio.funcs->get_pcie_data_offset(adev); 156 157 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 158 } 159 160 static void soc21_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 161 { 162 unsigned long address, data; 163 164 address = adev->nbio.funcs->get_pcie_index_offset(adev); 165 data = adev->nbio.funcs->get_pcie_data_offset(adev); 166 167 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 168 } 169 170 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg) 171 { 172 unsigned long flags, address, data; 173 u32 r; 174 175 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 176 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 177 178 spin_lock_irqsave(&adev->didt_idx_lock, flags); 179 WREG32(address, (reg)); 180 r = RREG32(data); 181 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 182 return r; 183 } 184 185 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 186 { 187 unsigned long flags, address, data; 188 189 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX); 190 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA); 191 192 spin_lock_irqsave(&adev->didt_idx_lock, flags); 193 WREG32(address, (reg)); 194 WREG32(data, (v)); 195 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 196 } 197 198 static u32 soc21_get_config_memsize(struct amdgpu_device *adev) 199 { 200 return adev->nbio.funcs->get_memsize(adev); 201 } 202 203 static u32 soc21_get_xclk(struct amdgpu_device *adev) 204 { 205 return adev->clock.spll.reference_freq; 206 } 207 208 209 void soc21_grbm_select(struct amdgpu_device *adev, 210 u32 me, u32 pipe, u32 queue, u32 vmid) 211 { 212 u32 grbm_gfx_cntl = 0; 213 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 214 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 215 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 216 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 217 218 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl); 219 } 220 221 static void soc21_vga_set_state(struct amdgpu_device *adev, bool state) 222 { 223 /* todo */ 224 } 225 226 static bool soc21_read_disabled_bios(struct amdgpu_device *adev) 227 { 228 /* todo */ 229 return false; 230 } 231 232 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = { 233 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)}, 234 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)}, 235 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)}, 236 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)}, 237 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)}, 238 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)}, 239 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)}, 240 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)}, 241 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)}, 242 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)}, 243 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)}, 244 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)}, 245 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)}, 246 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)}, 247 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)}, 248 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)}, 249 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)}, 250 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)}, 251 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)}, 252 }; 253 254 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 255 u32 sh_num, u32 reg_offset) 256 { 257 uint32_t val; 258 259 mutex_lock(&adev->grbm_idx_mutex); 260 if (se_num != 0xffffffff || sh_num != 0xffffffff) 261 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 262 263 val = RREG32(reg_offset); 264 265 if (se_num != 0xffffffff || sh_num != 0xffffffff) 266 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 267 mutex_unlock(&adev->grbm_idx_mutex); 268 return val; 269 } 270 271 static uint32_t soc21_get_register_value(struct amdgpu_device *adev, 272 bool indexed, u32 se_num, 273 u32 sh_num, u32 reg_offset) 274 { 275 if (indexed) { 276 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); 277 } else { 278 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config) 279 return adev->gfx.config.gb_addr_config; 280 return RREG32(reg_offset); 281 } 282 } 283 284 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num, 285 u32 sh_num, u32 reg_offset, u32 *value) 286 { 287 uint32_t i; 288 struct soc15_allowed_register_entry *en; 289 290 *value = 0; 291 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) { 292 en = &soc21_allowed_read_registers[i]; 293 if (!adev->reg_offset[en->hwip][en->inst]) 294 continue; 295 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 296 + en->reg_offset)) 297 continue; 298 299 *value = soc21_get_register_value(adev, 300 soc21_allowed_read_registers[i].grbm_indexed, 301 se_num, sh_num, reg_offset); 302 return 0; 303 } 304 return -EINVAL; 305 } 306 307 #if 0 308 static int soc21_asic_mode1_reset(struct amdgpu_device *adev) 309 { 310 u32 i; 311 int ret = 0; 312 313 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 314 315 /* disable BM */ 316 pci_clear_master(adev->pdev); 317 318 amdgpu_device_cache_pci_state(adev->pdev); 319 320 if (amdgpu_dpm_is_mode1_reset_supported(adev)) { 321 dev_info(adev->dev, "GPU smu mode1 reset\n"); 322 ret = amdgpu_dpm_mode1_reset(adev); 323 } else { 324 dev_info(adev->dev, "GPU psp mode1 reset\n"); 325 ret = psp_gpu_reset(adev); 326 } 327 328 if (ret) 329 dev_err(adev->dev, "GPU mode1 reset failed\n"); 330 amdgpu_device_load_pci_state(adev->pdev); 331 332 /* wait for asic to come out of reset */ 333 for (i = 0; i < adev->usec_timeout; i++) { 334 u32 memsize = adev->nbio.funcs->get_memsize(adev); 335 336 if (memsize != 0xffffffff) 337 break; 338 udelay(1); 339 } 340 341 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 342 343 return ret; 344 } 345 #endif 346 347 static enum amd_reset_method 348 soc21_asic_reset_method(struct amdgpu_device *adev) 349 { 350 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 351 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 352 amdgpu_reset_method == AMD_RESET_METHOD_BACO) 353 return amdgpu_reset_method; 354 355 if (amdgpu_reset_method != -1) 356 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 357 amdgpu_reset_method); 358 359 switch (adev->ip_versions[MP1_HWIP][0]) { 360 case IP_VERSION(13, 0, 0): 361 case IP_VERSION(13, 0, 7): 362 case IP_VERSION(13, 0, 10): 363 return AMD_RESET_METHOD_MODE1; 364 case IP_VERSION(13, 0, 4): 365 case IP_VERSION(13, 0, 11): 366 return AMD_RESET_METHOD_MODE2; 367 default: 368 if (amdgpu_dpm_is_baco_supported(adev)) 369 return AMD_RESET_METHOD_BACO; 370 else 371 return AMD_RESET_METHOD_MODE1; 372 } 373 } 374 375 static int soc21_asic_reset(struct amdgpu_device *adev) 376 { 377 int ret = 0; 378 379 switch (soc21_asic_reset_method(adev)) { 380 case AMD_RESET_METHOD_PCI: 381 dev_info(adev->dev, "PCI reset\n"); 382 ret = amdgpu_device_pci_reset(adev); 383 break; 384 case AMD_RESET_METHOD_BACO: 385 dev_info(adev->dev, "BACO reset\n"); 386 ret = amdgpu_dpm_baco_reset(adev); 387 break; 388 case AMD_RESET_METHOD_MODE2: 389 dev_info(adev->dev, "MODE2 reset\n"); 390 ret = amdgpu_dpm_mode2_reset(adev); 391 break; 392 default: 393 dev_info(adev->dev, "MODE1 reset\n"); 394 ret = amdgpu_device_mode1_reset(adev); 395 break; 396 } 397 398 return ret; 399 } 400 401 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 402 { 403 /* todo */ 404 return 0; 405 } 406 407 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 408 { 409 /* todo */ 410 return 0; 411 } 412 413 static void soc21_pcie_gen3_enable(struct amdgpu_device *adev) 414 { 415 if (pci_is_root_bus(adev->pdev->bus)) 416 return; 417 418 if (amdgpu_pcie_gen2 == 0) 419 return; 420 421 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 422 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 423 return; 424 425 /* todo */ 426 } 427 428 static void soc21_program_aspm(struct amdgpu_device *adev) 429 { 430 if (!amdgpu_device_should_use_aspm(adev)) 431 return; 432 433 if (!(adev->flags & AMD_IS_APU) && 434 (adev->nbio.funcs->program_aspm)) 435 adev->nbio.funcs->program_aspm(adev); 436 } 437 438 static void soc21_enable_doorbell_aperture(struct amdgpu_device *adev, 439 bool enable) 440 { 441 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 442 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 443 } 444 445 const struct amdgpu_ip_block_version soc21_common_ip_block = 446 { 447 .type = AMD_IP_BLOCK_TYPE_COMMON, 448 .major = 1, 449 .minor = 0, 450 .rev = 0, 451 .funcs = &soc21_common_ip_funcs, 452 }; 453 454 static uint32_t soc21_get_rev_id(struct amdgpu_device *adev) 455 { 456 return adev->nbio.funcs->get_rev_id(adev); 457 } 458 459 static bool soc21_need_full_reset(struct amdgpu_device *adev) 460 { 461 switch (adev->ip_versions[GC_HWIP][0]) { 462 case IP_VERSION(11, 0, 0): 463 return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC); 464 case IP_VERSION(11, 0, 2): 465 case IP_VERSION(11, 0, 3): 466 return false; 467 default: 468 return true; 469 } 470 } 471 472 static bool soc21_need_reset_on_init(struct amdgpu_device *adev) 473 { 474 u32 sol_reg; 475 476 if (adev->flags & AMD_IS_APU) 477 return false; 478 479 /* Check sOS sign of life register to confirm sys driver and sOS 480 * are already been loaded. 481 */ 482 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 483 if (sol_reg) 484 return true; 485 486 return false; 487 } 488 489 static uint64_t soc21_get_pcie_replay_count(struct amdgpu_device *adev) 490 { 491 492 /* TODO 493 * dummy implement for pcie_replay_count sysfs interface 494 * */ 495 496 return 0; 497 } 498 499 static void soc21_init_doorbell_index(struct amdgpu_device *adev) 500 { 501 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 502 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 503 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 504 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 505 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 506 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 507 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 508 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 509 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 510 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 511 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 512 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 513 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 514 adev->doorbell_index.gfx_userqueue_start = 515 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 516 adev->doorbell_index.gfx_userqueue_end = 517 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 518 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 519 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 520 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 521 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 522 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 523 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 524 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 525 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 526 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 527 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 528 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 529 530 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 531 adev->doorbell_index.sdma_doorbell_range = 20; 532 } 533 534 static void soc21_pre_asic_init(struct amdgpu_device *adev) 535 { 536 } 537 538 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev, 539 bool enter) 540 { 541 if (enter) 542 amdgpu_gfx_rlc_enter_safe_mode(adev); 543 else 544 amdgpu_gfx_rlc_exit_safe_mode(adev); 545 546 if (adev->gfx.funcs->update_perfmon_mgcg) 547 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 548 549 return 0; 550 } 551 552 static const struct amdgpu_asic_funcs soc21_asic_funcs = 553 { 554 .read_disabled_bios = &soc21_read_disabled_bios, 555 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 556 .read_register = &soc21_read_register, 557 .reset = &soc21_asic_reset, 558 .reset_method = &soc21_asic_reset_method, 559 .set_vga_state = &soc21_vga_set_state, 560 .get_xclk = &soc21_get_xclk, 561 .set_uvd_clocks = &soc21_set_uvd_clocks, 562 .set_vce_clocks = &soc21_set_vce_clocks, 563 .get_config_memsize = &soc21_get_config_memsize, 564 .init_doorbell_index = &soc21_init_doorbell_index, 565 .need_full_reset = &soc21_need_full_reset, 566 .need_reset_on_init = &soc21_need_reset_on_init, 567 .get_pcie_replay_count = &soc21_get_pcie_replay_count, 568 .supports_baco = &amdgpu_dpm_is_baco_supported, 569 .pre_asic_init = &soc21_pre_asic_init, 570 .query_video_codecs = &soc21_query_video_codecs, 571 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, 572 }; 573 574 static int soc21_common_early_init(void *handle) 575 { 576 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 577 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 578 579 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 580 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 581 adev->smc_rreg = NULL; 582 adev->smc_wreg = NULL; 583 adev->pcie_rreg = &soc21_pcie_rreg; 584 adev->pcie_wreg = &soc21_pcie_wreg; 585 adev->pcie_rreg64 = &soc21_pcie_rreg64; 586 adev->pcie_wreg64 = &soc21_pcie_wreg64; 587 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 588 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 589 590 /* TODO: will add them during VCN v2 implementation */ 591 adev->uvd_ctx_rreg = NULL; 592 adev->uvd_ctx_wreg = NULL; 593 594 adev->didt_rreg = &soc21_didt_rreg; 595 adev->didt_wreg = &soc21_didt_wreg; 596 597 adev->asic_funcs = &soc21_asic_funcs; 598 599 adev->rev_id = soc21_get_rev_id(adev); 600 adev->external_rev_id = 0xff; 601 switch (adev->ip_versions[GC_HWIP][0]) { 602 case IP_VERSION(11, 0, 0): 603 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG | 604 AMD_CG_SUPPORT_GFX_CGLS | 605 #if 0 606 AMD_CG_SUPPORT_GFX_3D_CGCG | 607 AMD_CG_SUPPORT_GFX_3D_CGLS | 608 #endif 609 AMD_CG_SUPPORT_GFX_MGCG | 610 AMD_CG_SUPPORT_REPEATER_FGCG | 611 AMD_CG_SUPPORT_GFX_FGCG | 612 AMD_CG_SUPPORT_GFX_PERF_CLK | 613 AMD_CG_SUPPORT_VCN_MGCG | 614 AMD_CG_SUPPORT_JPEG_MGCG | 615 AMD_CG_SUPPORT_ATHUB_MGCG | 616 AMD_CG_SUPPORT_ATHUB_LS | 617 AMD_CG_SUPPORT_MC_MGCG | 618 AMD_CG_SUPPORT_MC_LS | 619 AMD_CG_SUPPORT_IH_CG | 620 AMD_CG_SUPPORT_HDP_SD; 621 adev->pg_flags = AMD_PG_SUPPORT_VCN | 622 AMD_PG_SUPPORT_VCN_DPG | 623 AMD_PG_SUPPORT_JPEG | 624 AMD_PG_SUPPORT_ATHUB | 625 AMD_PG_SUPPORT_MMHUB; 626 if (amdgpu_sriov_vf(adev)) { 627 adev->cg_flags = 0; 628 adev->pg_flags = 0; 629 } 630 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update 631 break; 632 case IP_VERSION(11, 0, 2): 633 adev->cg_flags = 634 AMD_CG_SUPPORT_GFX_CGCG | 635 AMD_CG_SUPPORT_GFX_CGLS | 636 AMD_CG_SUPPORT_REPEATER_FGCG | 637 AMD_CG_SUPPORT_VCN_MGCG | 638 AMD_CG_SUPPORT_JPEG_MGCG | 639 AMD_CG_SUPPORT_ATHUB_MGCG | 640 AMD_CG_SUPPORT_ATHUB_LS | 641 AMD_CG_SUPPORT_IH_CG | 642 AMD_CG_SUPPORT_HDP_SD; 643 adev->pg_flags = 644 AMD_PG_SUPPORT_VCN | 645 AMD_PG_SUPPORT_VCN_DPG | 646 AMD_PG_SUPPORT_JPEG | 647 AMD_PG_SUPPORT_ATHUB | 648 AMD_PG_SUPPORT_MMHUB; 649 adev->external_rev_id = adev->rev_id + 0x10; 650 break; 651 case IP_VERSION(11, 0, 1): 652 adev->cg_flags = 653 AMD_CG_SUPPORT_GFX_CGCG | 654 AMD_CG_SUPPORT_GFX_CGLS | 655 AMD_CG_SUPPORT_GFX_MGCG | 656 AMD_CG_SUPPORT_GFX_FGCG | 657 AMD_CG_SUPPORT_REPEATER_FGCG | 658 AMD_CG_SUPPORT_GFX_PERF_CLK | 659 AMD_CG_SUPPORT_MC_MGCG | 660 AMD_CG_SUPPORT_MC_LS | 661 AMD_CG_SUPPORT_HDP_MGCG | 662 AMD_CG_SUPPORT_HDP_LS | 663 AMD_CG_SUPPORT_ATHUB_MGCG | 664 AMD_CG_SUPPORT_ATHUB_LS | 665 AMD_CG_SUPPORT_IH_CG | 666 AMD_CG_SUPPORT_BIF_MGCG | 667 AMD_CG_SUPPORT_BIF_LS | 668 AMD_CG_SUPPORT_VCN_MGCG | 669 AMD_CG_SUPPORT_JPEG_MGCG; 670 adev->pg_flags = 671 AMD_PG_SUPPORT_GFX_PG | 672 AMD_PG_SUPPORT_VCN | 673 AMD_PG_SUPPORT_VCN_DPG | 674 AMD_PG_SUPPORT_JPEG; 675 adev->external_rev_id = adev->rev_id + 0x1; 676 break; 677 case IP_VERSION(11, 0, 3): 678 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG | 679 AMD_CG_SUPPORT_JPEG_MGCG | 680 AMD_CG_SUPPORT_GFX_CGCG | 681 AMD_CG_SUPPORT_GFX_CGLS | 682 AMD_CG_SUPPORT_REPEATER_FGCG | 683 AMD_CG_SUPPORT_GFX_MGCG | 684 AMD_CG_SUPPORT_HDP_SD; 685 adev->pg_flags = AMD_PG_SUPPORT_VCN | 686 AMD_PG_SUPPORT_VCN_DPG | 687 AMD_PG_SUPPORT_JPEG; 688 if (amdgpu_sriov_vf(adev)) { 689 /* hypervisor control CG and PG enablement */ 690 adev->cg_flags = 0; 691 adev->pg_flags = 0; 692 } 693 adev->external_rev_id = adev->rev_id + 0x20; 694 break; 695 case IP_VERSION(11, 0, 4): 696 adev->cg_flags = 697 AMD_CG_SUPPORT_GFX_CGCG | 698 AMD_CG_SUPPORT_GFX_CGLS | 699 AMD_CG_SUPPORT_GFX_MGCG | 700 AMD_CG_SUPPORT_GFX_FGCG | 701 AMD_CG_SUPPORT_REPEATER_FGCG | 702 AMD_CG_SUPPORT_GFX_PERF_CLK | 703 AMD_CG_SUPPORT_MC_MGCG | 704 AMD_CG_SUPPORT_MC_LS | 705 AMD_CG_SUPPORT_HDP_MGCG | 706 AMD_CG_SUPPORT_HDP_LS | 707 AMD_CG_SUPPORT_ATHUB_MGCG | 708 AMD_CG_SUPPORT_ATHUB_LS | 709 AMD_CG_SUPPORT_IH_CG | 710 AMD_CG_SUPPORT_BIF_MGCG | 711 AMD_CG_SUPPORT_BIF_LS | 712 AMD_CG_SUPPORT_VCN_MGCG | 713 AMD_CG_SUPPORT_JPEG_MGCG; 714 adev->pg_flags = AMD_PG_SUPPORT_VCN | 715 AMD_PG_SUPPORT_VCN_DPG | 716 AMD_PG_SUPPORT_GFX_PG | 717 AMD_PG_SUPPORT_JPEG; 718 adev->external_rev_id = adev->rev_id + 0x80; 719 break; 720 721 default: 722 /* FIXME: not supported yet */ 723 return -EINVAL; 724 } 725 726 return 0; 727 } 728 729 static int soc21_common_late_init(void *handle) 730 { 731 return 0; 732 } 733 734 static int soc21_common_sw_init(void *handle) 735 { 736 return 0; 737 } 738 739 static int soc21_common_sw_fini(void *handle) 740 { 741 return 0; 742 } 743 744 static int soc21_common_hw_init(void *handle) 745 { 746 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 747 748 /* enable pcie gen2/3 link */ 749 soc21_pcie_gen3_enable(adev); 750 /* enable aspm */ 751 soc21_program_aspm(adev); 752 /* setup nbio registers */ 753 adev->nbio.funcs->init_registers(adev); 754 /* remap HDP registers to a hole in mmio space, 755 * for the purpose of expose those registers 756 * to process space 757 */ 758 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 759 adev->nbio.funcs->remap_hdp_registers(adev); 760 /* enable the doorbell aperture */ 761 soc21_enable_doorbell_aperture(adev, true); 762 763 return 0; 764 } 765 766 static int soc21_common_hw_fini(void *handle) 767 { 768 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 769 770 /* disable the doorbell aperture */ 771 soc21_enable_doorbell_aperture(adev, false); 772 773 return 0; 774 } 775 776 static int soc21_common_suspend(void *handle) 777 { 778 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 779 780 return soc21_common_hw_fini(adev); 781 } 782 783 static int soc21_common_resume(void *handle) 784 { 785 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 786 787 return soc21_common_hw_init(adev); 788 } 789 790 static bool soc21_common_is_idle(void *handle) 791 { 792 return true; 793 } 794 795 static int soc21_common_wait_for_idle(void *handle) 796 { 797 return 0; 798 } 799 800 static int soc21_common_soft_reset(void *handle) 801 { 802 return 0; 803 } 804 805 static int soc21_common_set_clockgating_state(void *handle, 806 enum amd_clockgating_state state) 807 { 808 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 809 810 switch (adev->ip_versions[NBIO_HWIP][0]) { 811 case IP_VERSION(4, 3, 0): 812 case IP_VERSION(4, 3, 1): 813 case IP_VERSION(7, 7, 0): 814 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 815 state == AMD_CG_STATE_GATE); 816 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 817 state == AMD_CG_STATE_GATE); 818 adev->hdp.funcs->update_clock_gating(adev, 819 state == AMD_CG_STATE_GATE); 820 break; 821 default: 822 break; 823 } 824 return 0; 825 } 826 827 static int soc21_common_set_powergating_state(void *handle, 828 enum amd_powergating_state state) 829 { 830 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 831 832 switch (adev->ip_versions[LSDMA_HWIP][0]) { 833 case IP_VERSION(6, 0, 0): 834 case IP_VERSION(6, 0, 2): 835 adev->lsdma.funcs->update_memory_power_gating(adev, 836 state == AMD_PG_STATE_GATE); 837 break; 838 default: 839 break; 840 } 841 842 return 0; 843 } 844 845 static void soc21_common_get_clockgating_state(void *handle, u64 *flags) 846 { 847 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 848 849 adev->nbio.funcs->get_clockgating_state(adev, flags); 850 851 adev->hdp.funcs->get_clock_gating_state(adev, flags); 852 853 return; 854 } 855 856 static const struct amd_ip_funcs soc21_common_ip_funcs = { 857 .name = "soc21_common", 858 .early_init = soc21_common_early_init, 859 .late_init = soc21_common_late_init, 860 .sw_init = soc21_common_sw_init, 861 .sw_fini = soc21_common_sw_fini, 862 .hw_init = soc21_common_hw_init, 863 .hw_fini = soc21_common_hw_fini, 864 .suspend = soc21_common_suspend, 865 .resume = soc21_common_resume, 866 .is_idle = soc21_common_is_idle, 867 .wait_for_idle = soc21_common_wait_for_idle, 868 .soft_reset = soc21_common_soft_reset, 869 .set_clockgating_state = soc21_common_set_clockgating_state, 870 .set_powergating_state = soc21_common_set_powergating_state, 871 .get_clockgating_state = soc21_common_get_clockgating_state, 872 }; 873