1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_1_0_offset.h" 34 #include "gc/gc_10_1_0_sh_mask.h" 35 #include "hdp/hdp_5_0_0_offset.h" 36 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 37 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "navi10_sdma_pkt_open.h" 42 #include "nbio_v2_3.h" 43 #include "sdma_v5_0.h" 44 45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); 47 48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); 50 51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin"); 53 54 #define SDMA1_REG_OFFSET 0x600 55 #define SDMA0_HYP_DEC_REG_START 0x5880 56 #define SDMA0_HYP_DEC_REG_END 0x5893 57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 58 59 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); 60 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); 61 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); 62 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); 63 64 static const struct soc15_reg_golden golden_settings_sdma_5[] = { 65 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00), 77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00) 89 }; 90 91 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { 92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 94 }; 95 96 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = { 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 99 }; 100 101 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = { 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 104 }; 105 106 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 107 { 108 u32 base; 109 110 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 111 internal_offset <= SDMA0_HYP_DEC_REG_END) { 112 base = adev->reg_offset[GC_HWIP][0][1]; 113 if (instance == 1) 114 internal_offset += SDMA1_HYP_DEC_REG_OFFSET; 115 } else { 116 base = adev->reg_offset[GC_HWIP][0][0]; 117 if (instance == 1) 118 internal_offset += SDMA1_REG_OFFSET; 119 } 120 121 return base + internal_offset; 122 } 123 124 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) 125 { 126 switch (adev->asic_type) { 127 case CHIP_NAVI10: 128 soc15_program_register_sequence(adev, 129 golden_settings_sdma_5, 130 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 131 soc15_program_register_sequence(adev, 132 golden_settings_sdma_nv10, 133 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); 134 break; 135 case CHIP_NAVI14: 136 soc15_program_register_sequence(adev, 137 golden_settings_sdma_5, 138 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 139 soc15_program_register_sequence(adev, 140 golden_settings_sdma_nv14, 141 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14)); 142 break; 143 case CHIP_NAVI12: 144 soc15_program_register_sequence(adev, 145 golden_settings_sdma_5, 146 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 147 soc15_program_register_sequence(adev, 148 golden_settings_sdma_nv12, 149 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12)); 150 break; 151 default: 152 break; 153 } 154 } 155 156 /** 157 * sdma_v5_0_init_microcode - load ucode images from disk 158 * 159 * @adev: amdgpu_device pointer 160 * 161 * Use the firmware interface to load the ucode images into 162 * the driver (not loaded into hw). 163 * Returns 0 on success, error on failure. 164 */ 165 166 // emulation only, won't work on real chip 167 // navi10 real chip need to use PSP to load firmware 168 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) 169 { 170 const char *chip_name; 171 char fw_name[30]; 172 int err = 0, i; 173 struct amdgpu_firmware_info *info = NULL; 174 const struct common_firmware_header *header = NULL; 175 const struct sdma_firmware_header_v1_0 *hdr; 176 177 DRM_DEBUG("\n"); 178 179 switch (adev->asic_type) { 180 case CHIP_NAVI10: 181 chip_name = "navi10"; 182 break; 183 case CHIP_NAVI14: 184 chip_name = "navi14"; 185 break; 186 case CHIP_NAVI12: 187 chip_name = "navi12"; 188 break; 189 default: 190 BUG(); 191 } 192 193 for (i = 0; i < adev->sdma.num_instances; i++) { 194 if (i == 0) 195 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 196 else 197 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 198 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 199 if (err) 200 goto out; 201 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 202 if (err) 203 goto out; 204 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 205 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 206 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 207 if (adev->sdma.instance[i].feature_version >= 20) 208 adev->sdma.instance[i].burst_nop = true; 209 DRM_DEBUG("psp_load == '%s'\n", 210 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 211 212 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 213 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 214 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 215 info->fw = adev->sdma.instance[i].fw; 216 header = (const struct common_firmware_header *)info->fw->data; 217 adev->firmware.fw_size += 218 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 219 } 220 } 221 out: 222 if (err) { 223 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name); 224 for (i = 0; i < adev->sdma.num_instances; i++) { 225 release_firmware(adev->sdma.instance[i].fw); 226 adev->sdma.instance[i].fw = NULL; 227 } 228 } 229 return err; 230 } 231 232 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring) 233 { 234 unsigned ret; 235 236 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 237 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 238 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 239 amdgpu_ring_write(ring, 1); 240 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 241 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 242 243 return ret; 244 } 245 246 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 247 unsigned offset) 248 { 249 unsigned cur; 250 251 BUG_ON(offset > ring->buf_mask); 252 BUG_ON(ring->ring[offset] != 0x55aa55aa); 253 254 cur = (ring->wptr - 1) & ring->buf_mask; 255 if (cur > offset) 256 ring->ring[offset] = cur - offset; 257 else 258 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 259 } 260 261 /** 262 * sdma_v5_0_ring_get_rptr - get the current read pointer 263 * 264 * @ring: amdgpu ring pointer 265 * 266 * Get the current rptr from the hardware (NAVI10+). 267 */ 268 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 269 { 270 u64 *rptr; 271 272 /* XXX check if swapping is necessary on BE */ 273 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 274 275 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 276 return ((*rptr) >> 2); 277 } 278 279 /** 280 * sdma_v5_0_ring_get_wptr - get the current write pointer 281 * 282 * @ring: amdgpu ring pointer 283 * 284 * Get the current wptr from the hardware (NAVI10+). 285 */ 286 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 287 { 288 struct amdgpu_device *adev = ring->adev; 289 u64 wptr; 290 291 if (ring->use_doorbell) { 292 /* XXX check if swapping is necessary on BE */ 293 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 294 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 295 } else { 296 wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 297 wptr = wptr << 32; 298 wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); 299 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); 300 } 301 302 return wptr >> 2; 303 } 304 305 /** 306 * sdma_v5_0_ring_set_wptr - commit the write pointer 307 * 308 * @ring: amdgpu ring pointer 309 * 310 * Write the wptr back to the hardware (NAVI10+). 311 */ 312 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 313 { 314 struct amdgpu_device *adev = ring->adev; 315 316 DRM_DEBUG("Setting write pointer\n"); 317 if (ring->use_doorbell) { 318 DRM_DEBUG("Using doorbell -- " 319 "wptr_offs == 0x%08x " 320 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 321 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 322 ring->wptr_offs, 323 lower_32_bits(ring->wptr << 2), 324 upper_32_bits(ring->wptr << 2)); 325 /* XXX check if swapping is necessary on BE */ 326 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 327 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 328 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 329 ring->doorbell_index, ring->wptr << 2); 330 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 331 } else { 332 DRM_DEBUG("Not using doorbell -- " 333 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 334 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 335 ring->me, 336 lower_32_bits(ring->wptr << 2), 337 ring->me, 338 upper_32_bits(ring->wptr << 2)); 339 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 340 lower_32_bits(ring->wptr << 2)); 341 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 342 upper_32_bits(ring->wptr << 2)); 343 } 344 } 345 346 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 347 { 348 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 349 int i; 350 351 for (i = 0; i < count; i++) 352 if (sdma && sdma->burst_nop && (i == 0)) 353 amdgpu_ring_write(ring, ring->funcs->nop | 354 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 355 else 356 amdgpu_ring_write(ring, ring->funcs->nop); 357 } 358 359 /** 360 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine 361 * 362 * @ring: amdgpu ring pointer 363 * @ib: IB object to schedule 364 * 365 * Schedule an IB in the DMA ring (NAVI10). 366 */ 367 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 368 struct amdgpu_job *job, 369 struct amdgpu_ib *ib, 370 uint32_t flags) 371 { 372 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 373 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 374 375 /* Invalidate L2, because if we don't do it, we might get stale cache 376 * lines from previous IBs. 377 */ 378 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); 379 amdgpu_ring_write(ring, 0); 380 amdgpu_ring_write(ring, (SDMA_GCR_GL2_INV | 381 SDMA_GCR_GL2_WB | 382 SDMA_GCR_GLM_INV | 383 SDMA_GCR_GLM_WB) << 16); 384 amdgpu_ring_write(ring, 0xffffff80); 385 amdgpu_ring_write(ring, 0xffff); 386 387 /* An IB packet must end on a 8 DW boundary--the next dword 388 * must be on a 8-dword boundary. Our IB packet below is 6 389 * dwords long, thus add x number of NOPs, such that, in 390 * modular arithmetic, 391 * wptr + 6 + x = 8k, k >= 0, which in C is, 392 * (wptr + 6 + x) % 8 = 0. 393 * The expression below, is a solution of x. 394 */ 395 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 396 397 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 398 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 399 /* base must be 32 byte aligned */ 400 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 401 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 402 amdgpu_ring_write(ring, ib->length_dw); 403 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 404 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 405 } 406 407 /** 408 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 409 * 410 * @ring: amdgpu ring pointer 411 * 412 * Emit an hdp flush packet on the requested DMA ring. 413 */ 414 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 415 { 416 struct amdgpu_device *adev = ring->adev; 417 u32 ref_and_mask = 0; 418 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 419 420 if (ring->me == 0) 421 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 422 else 423 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 424 425 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 426 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 427 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 428 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 429 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 430 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 431 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 432 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 433 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 434 } 435 436 /** 437 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring 438 * 439 * @ring: amdgpu ring pointer 440 * @fence: amdgpu fence object 441 * 442 * Add a DMA fence packet to the ring to write 443 * the fence seq number and DMA trap packet to generate 444 * an interrupt if needed (NAVI10). 445 */ 446 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 447 unsigned flags) 448 { 449 struct amdgpu_device *adev = ring->adev; 450 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 451 /* write the fence */ 452 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 453 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 454 /* zero in first two bits */ 455 BUG_ON(addr & 0x3); 456 amdgpu_ring_write(ring, lower_32_bits(addr)); 457 amdgpu_ring_write(ring, upper_32_bits(addr)); 458 amdgpu_ring_write(ring, lower_32_bits(seq)); 459 460 /* optionally write high bits as well */ 461 if (write64bit) { 462 addr += 4; 463 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 464 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 465 /* zero in first two bits */ 466 BUG_ON(addr & 0x3); 467 amdgpu_ring_write(ring, lower_32_bits(addr)); 468 amdgpu_ring_write(ring, upper_32_bits(addr)); 469 amdgpu_ring_write(ring, upper_32_bits(seq)); 470 } 471 472 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 473 if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) { 474 /* generate an interrupt */ 475 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 476 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 477 } 478 } 479 480 481 /** 482 * sdma_v5_0_gfx_stop - stop the gfx async dma engines 483 * 484 * @adev: amdgpu_device pointer 485 * 486 * Stop the gfx async dma ring buffers (NAVI10). 487 */ 488 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev) 489 { 490 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 491 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 492 u32 rb_cntl, ib_cntl; 493 int i; 494 495 if ((adev->mman.buffer_funcs_ring == sdma0) || 496 (adev->mman.buffer_funcs_ring == sdma1)) 497 amdgpu_ttm_set_buffer_funcs_status(adev, false); 498 499 for (i = 0; i < adev->sdma.num_instances; i++) { 500 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 501 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 502 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 503 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 504 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 505 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 506 } 507 508 sdma0->sched.ready = false; 509 sdma1->sched.ready = false; 510 } 511 512 /** 513 * sdma_v5_0_rlc_stop - stop the compute async dma engines 514 * 515 * @adev: amdgpu_device pointer 516 * 517 * Stop the compute async dma queues (NAVI10). 518 */ 519 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) 520 { 521 /* XXX todo */ 522 } 523 524 /** 525 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 526 * 527 * @adev: amdgpu_device pointer 528 * @enable: enable/disable the DMA MEs context switch. 529 * 530 * Halt or unhalt the async dma engines context switch (NAVI10). 531 */ 532 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 533 { 534 u32 f32_cntl, phase_quantum = 0; 535 int i; 536 537 if (amdgpu_sdma_phase_quantum) { 538 unsigned value = amdgpu_sdma_phase_quantum; 539 unsigned unit = 0; 540 541 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 542 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 543 value = (value + 1) >> 1; 544 unit++; 545 } 546 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 547 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 548 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 549 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 550 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 551 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 552 WARN_ONCE(1, 553 "clamping sdma_phase_quantum to %uK clock cycles\n", 554 value << unit); 555 } 556 phase_quantum = 557 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 558 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 559 } 560 561 for (i = 0; i < adev->sdma.num_instances; i++) { 562 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 563 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 564 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 565 if (enable && amdgpu_sdma_phase_quantum) { 566 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 567 phase_quantum); 568 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 569 phase_quantum); 570 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 571 phase_quantum); 572 } 573 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 574 } 575 576 } 577 578 /** 579 * sdma_v5_0_enable - stop the async dma engines 580 * 581 * @adev: amdgpu_device pointer 582 * @enable: enable/disable the DMA MEs. 583 * 584 * Halt or unhalt the async dma engines (NAVI10). 585 */ 586 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) 587 { 588 u32 f32_cntl; 589 int i; 590 591 if (enable == false) { 592 sdma_v5_0_gfx_stop(adev); 593 sdma_v5_0_rlc_stop(adev); 594 } 595 596 for (i = 0; i < adev->sdma.num_instances; i++) { 597 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 598 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 599 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 600 } 601 } 602 603 /** 604 * sdma_v5_0_gfx_resume - setup and start the async dma engines 605 * 606 * @adev: amdgpu_device pointer 607 * 608 * Set up the gfx DMA ring buffers and enable them (NAVI10). 609 * Returns 0 for success, error for failure. 610 */ 611 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) 612 { 613 struct amdgpu_ring *ring; 614 u32 rb_cntl, ib_cntl; 615 u32 rb_bufsz; 616 u32 wb_offset; 617 u32 doorbell; 618 u32 doorbell_offset; 619 u32 temp; 620 u32 wptr_poll_cntl; 621 u64 wptr_gpu_addr; 622 int i, r; 623 624 for (i = 0; i < adev->sdma.num_instances; i++) { 625 ring = &adev->sdma.instance[i].ring; 626 wb_offset = (ring->rptr_offs * 4); 627 628 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 629 630 /* Set ring buffer size in dwords */ 631 rb_bufsz = order_base_2(ring->ring_size / 4); 632 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 633 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 634 #ifdef __BIG_ENDIAN 635 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 636 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 637 RPTR_WRITEBACK_SWAP_ENABLE, 1); 638 #endif 639 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 640 641 /* Initialize the ring buffer's read and write pointers */ 642 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 643 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 644 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 645 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 646 647 /* setup the wptr shadow polling */ 648 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 649 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 650 lower_32_bits(wptr_gpu_addr)); 651 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 652 upper_32_bits(wptr_gpu_addr)); 653 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, 654 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 655 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 656 SDMA0_GFX_RB_WPTR_POLL_CNTL, 657 F32_POLL_ENABLE, 1); 658 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 659 wptr_poll_cntl); 660 661 /* set the wb address whether it's enabled or not */ 662 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 663 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 664 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 665 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 666 667 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 668 669 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 670 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 671 672 ring->wptr = 0; 673 674 /* before programing wptr to a less value, need set minor_ptr_update first */ 675 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 676 677 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 678 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 679 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 680 } 681 682 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 683 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 684 685 if (ring->use_doorbell) { 686 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 687 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 688 OFFSET, ring->doorbell_index); 689 } else { 690 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 691 } 692 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 693 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 694 695 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 696 ring->doorbell_index, 20); 697 698 if (amdgpu_sriov_vf(adev)) 699 sdma_v5_0_ring_set_wptr(ring); 700 701 /* set minor_ptr_update to 0 after wptr programed */ 702 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 703 704 /* set utc l1 enable flag always to 1 */ 705 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 706 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 707 708 /* enable MCBP */ 709 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 710 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 711 712 /* Set up RESP_MODE to non-copy addresses */ 713 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 714 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 715 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 716 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 717 718 /* program default cache read and write policy */ 719 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 720 /* clean read policy and write policy bits */ 721 temp &= 0xFF0FFF; 722 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 723 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 724 725 if (!amdgpu_sriov_vf(adev)) { 726 /* unhalt engine */ 727 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 728 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 729 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 730 } 731 732 /* enable DMA RB */ 733 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 734 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 735 736 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 737 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 738 #ifdef __BIG_ENDIAN 739 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 740 #endif 741 /* enable DMA IBs */ 742 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 743 744 ring->sched.ready = true; 745 746 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 747 sdma_v5_0_ctx_switch_enable(adev, true); 748 sdma_v5_0_enable(adev, true); 749 } 750 751 r = amdgpu_ring_test_helper(ring); 752 if (r) 753 return r; 754 755 if (adev->mman.buffer_funcs_ring == ring) 756 amdgpu_ttm_set_buffer_funcs_status(adev, true); 757 } 758 759 return 0; 760 } 761 762 /** 763 * sdma_v5_0_rlc_resume - setup and start the async dma engines 764 * 765 * @adev: amdgpu_device pointer 766 * 767 * Set up the compute DMA queues and enable them (NAVI10). 768 * Returns 0 for success, error for failure. 769 */ 770 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev) 771 { 772 return 0; 773 } 774 775 /** 776 * sdma_v5_0_load_microcode - load the sDMA ME ucode 777 * 778 * @adev: amdgpu_device pointer 779 * 780 * Loads the sDMA0/1 ucode. 781 * Returns 0 for success, -EINVAL if the ucode is not available. 782 */ 783 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev) 784 { 785 const struct sdma_firmware_header_v1_0 *hdr; 786 const __le32 *fw_data; 787 u32 fw_size; 788 int i, j; 789 790 /* halt the MEs */ 791 sdma_v5_0_enable(adev, false); 792 793 for (i = 0; i < adev->sdma.num_instances; i++) { 794 if (!adev->sdma.instance[i].fw) 795 return -EINVAL; 796 797 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 798 amdgpu_ucode_print_sdma_hdr(&hdr->header); 799 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 800 801 fw_data = (const __le32 *) 802 (adev->sdma.instance[i].fw->data + 803 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 804 805 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 806 807 for (j = 0; j < fw_size; j++) { 808 if (amdgpu_emu_mode == 1 && j % 500 == 0) 809 drm_msleep(1); 810 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 811 } 812 813 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 814 } 815 816 return 0; 817 } 818 819 /** 820 * sdma_v5_0_start - setup and start the async dma engines 821 * 822 * @adev: amdgpu_device pointer 823 * 824 * Set up the DMA engines and enable them (NAVI10). 825 * Returns 0 for success, error for failure. 826 */ 827 static int sdma_v5_0_start(struct amdgpu_device *adev) 828 { 829 int r = 0; 830 831 if (amdgpu_sriov_vf(adev)) { 832 sdma_v5_0_ctx_switch_enable(adev, false); 833 sdma_v5_0_enable(adev, false); 834 835 /* set RB registers */ 836 r = sdma_v5_0_gfx_resume(adev); 837 return r; 838 } 839 840 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 841 r = sdma_v5_0_load_microcode(adev); 842 if (r) 843 return r; 844 845 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 846 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d) 847 drm_msleep(1000); 848 } 849 850 /* unhalt the MEs */ 851 sdma_v5_0_enable(adev, true); 852 /* enable sdma ring preemption */ 853 sdma_v5_0_ctx_switch_enable(adev, true); 854 855 /* start the gfx rings and rlc compute queues */ 856 r = sdma_v5_0_gfx_resume(adev); 857 if (r) 858 return r; 859 r = sdma_v5_0_rlc_resume(adev); 860 861 return r; 862 } 863 864 /** 865 * sdma_v5_0_ring_test_ring - simple async dma engine test 866 * 867 * @ring: amdgpu_ring structure holding ring information 868 * 869 * Test the DMA engine by writing using it to write an 870 * value to memory. (NAVI10). 871 * Returns 0 for success, error for failure. 872 */ 873 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) 874 { 875 struct amdgpu_device *adev = ring->adev; 876 unsigned i; 877 unsigned index; 878 int r; 879 u32 tmp; 880 u64 gpu_addr; 881 882 r = amdgpu_device_wb_get(adev, &index); 883 if (r) { 884 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 885 return r; 886 } 887 888 gpu_addr = adev->wb.gpu_addr + (index * 4); 889 tmp = 0xCAFEDEAD; 890 adev->wb.wb[index] = cpu_to_le32(tmp); 891 892 r = amdgpu_ring_alloc(ring, 5); 893 if (r) { 894 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 895 amdgpu_device_wb_free(adev, index); 896 return r; 897 } 898 899 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 900 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 901 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 902 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 903 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 904 amdgpu_ring_write(ring, 0xDEADBEEF); 905 amdgpu_ring_commit(ring); 906 907 for (i = 0; i < adev->usec_timeout; i++) { 908 tmp = le32_to_cpu(adev->wb.wb[index]); 909 if (tmp == 0xDEADBEEF) 910 break; 911 if (amdgpu_emu_mode == 1) 912 drm_msleep(1); 913 else 914 udelay(1); 915 } 916 917 if (i >= adev->usec_timeout) 918 r = -ETIMEDOUT; 919 920 amdgpu_device_wb_free(adev, index); 921 922 return r; 923 } 924 925 /** 926 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine 927 * 928 * @ring: amdgpu_ring structure holding ring information 929 * 930 * Test a simple IB in the DMA ring (NAVI10). 931 * Returns 0 on success, error on failure. 932 */ 933 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 934 { 935 struct amdgpu_device *adev = ring->adev; 936 struct amdgpu_ib ib; 937 struct dma_fence *f = NULL; 938 unsigned index; 939 long r; 940 u32 tmp = 0; 941 u64 gpu_addr; 942 943 r = amdgpu_device_wb_get(adev, &index); 944 if (r) { 945 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 946 return r; 947 } 948 949 gpu_addr = adev->wb.gpu_addr + (index * 4); 950 tmp = 0xCAFEDEAD; 951 adev->wb.wb[index] = cpu_to_le32(tmp); 952 memset(&ib, 0, sizeof(ib)); 953 r = amdgpu_ib_get(adev, NULL, 256, &ib); 954 if (r) { 955 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 956 goto err0; 957 } 958 959 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 960 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 961 ib.ptr[1] = lower_32_bits(gpu_addr); 962 ib.ptr[2] = upper_32_bits(gpu_addr); 963 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 964 ib.ptr[4] = 0xDEADBEEF; 965 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 966 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 967 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 968 ib.length_dw = 8; 969 970 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 971 if (r) 972 goto err1; 973 974 r = dma_fence_wait_timeout(f, false, timeout); 975 if (r == 0) { 976 DRM_ERROR("amdgpu: IB test timed out\n"); 977 r = -ETIMEDOUT; 978 goto err1; 979 } else if (r < 0) { 980 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 981 goto err1; 982 } 983 tmp = le32_to_cpu(adev->wb.wb[index]); 984 if (tmp == 0xDEADBEEF) 985 r = 0; 986 else 987 r = -EINVAL; 988 989 err1: 990 amdgpu_ib_free(adev, &ib, NULL); 991 dma_fence_put(f); 992 err0: 993 amdgpu_device_wb_free(adev, index); 994 return r; 995 } 996 997 998 /** 999 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART 1000 * 1001 * @ib: indirect buffer to fill with commands 1002 * @pe: addr of the page entry 1003 * @src: src addr to copy from 1004 * @count: number of page entries to update 1005 * 1006 * Update PTEs by copying them from the GART using sDMA (NAVI10). 1007 */ 1008 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib, 1009 uint64_t pe, uint64_t src, 1010 unsigned count) 1011 { 1012 unsigned bytes = count * 8; 1013 1014 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1015 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1016 ib->ptr[ib->length_dw++] = bytes - 1; 1017 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1018 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1019 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1020 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1021 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1022 1023 } 1024 1025 /** 1026 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually 1027 * 1028 * @ib: indirect buffer to fill with commands 1029 * @pe: addr of the page entry 1030 * @addr: dst addr to write into pe 1031 * @count: number of page entries to update 1032 * @incr: increase next addr by incr bytes 1033 * @flags: access flags 1034 * 1035 * Update PTEs by writing them manually using sDMA (NAVI10). 1036 */ 1037 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1038 uint64_t value, unsigned count, 1039 uint32_t incr) 1040 { 1041 unsigned ndw = count * 2; 1042 1043 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1044 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1045 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1046 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1047 ib->ptr[ib->length_dw++] = ndw - 1; 1048 for (; ndw > 0; ndw -= 2) { 1049 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1050 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1051 value += incr; 1052 } 1053 } 1054 1055 /** 1056 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA 1057 * 1058 * @ib: indirect buffer to fill with commands 1059 * @pe: addr of the page entry 1060 * @addr: dst addr to write into pe 1061 * @count: number of page entries to update 1062 * @incr: increase next addr by incr bytes 1063 * @flags: access flags 1064 * 1065 * Update the page tables using sDMA (NAVI10). 1066 */ 1067 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1068 uint64_t pe, 1069 uint64_t addr, unsigned count, 1070 uint32_t incr, uint64_t flags) 1071 { 1072 /* for physically contiguous pages (vram) */ 1073 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1074 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1075 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1076 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1077 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1078 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1079 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1080 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1081 ib->ptr[ib->length_dw++] = 0; 1082 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1083 } 1084 1085 /** 1086 * sdma_v5_0_ring_pad_ib - pad the IB 1087 * @ib: indirect buffer to fill with padding 1088 * 1089 * Pad the IB with NOPs to a boundary multiple of 8. 1090 */ 1091 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1092 { 1093 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1094 u32 pad_count; 1095 int i; 1096 1097 pad_count = (-ib->length_dw) & 0x7; 1098 for (i = 0; i < pad_count; i++) 1099 if (sdma && sdma->burst_nop && (i == 0)) 1100 ib->ptr[ib->length_dw++] = 1101 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1102 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1103 else 1104 ib->ptr[ib->length_dw++] = 1105 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1106 } 1107 1108 1109 /** 1110 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline 1111 * 1112 * @ring: amdgpu_ring pointer 1113 * 1114 * Make sure all previous operations are completed (CIK). 1115 */ 1116 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1117 { 1118 uint32_t seq = ring->fence_drv.sync_seq; 1119 uint64_t addr = ring->fence_drv.gpu_addr; 1120 1121 /* wait for idle */ 1122 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1123 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1124 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1125 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1126 amdgpu_ring_write(ring, addr & 0xfffffffc); 1127 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1128 amdgpu_ring_write(ring, seq); /* reference */ 1129 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1130 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1131 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1132 } 1133 1134 1135 /** 1136 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA 1137 * 1138 * @ring: amdgpu_ring pointer 1139 * @vm: amdgpu_vm pointer 1140 * 1141 * Update the page table base and flush the VM TLB 1142 * using sDMA (NAVI10). 1143 */ 1144 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1145 unsigned vmid, uint64_t pd_addr) 1146 { 1147 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1148 } 1149 1150 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring, 1151 uint32_t reg, uint32_t val) 1152 { 1153 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1154 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1155 amdgpu_ring_write(ring, reg); 1156 amdgpu_ring_write(ring, val); 1157 } 1158 1159 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1160 uint32_t val, uint32_t mask) 1161 { 1162 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1163 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1164 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1165 amdgpu_ring_write(ring, reg << 2); 1166 amdgpu_ring_write(ring, 0); 1167 amdgpu_ring_write(ring, val); /* reference */ 1168 amdgpu_ring_write(ring, mask); /* mask */ 1169 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1170 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1171 } 1172 1173 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1174 uint32_t reg0, uint32_t reg1, 1175 uint32_t ref, uint32_t mask) 1176 { 1177 amdgpu_ring_emit_wreg(ring, reg0, ref); 1178 /* wait for a cycle to reset vm_inv_eng*_ack */ 1179 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1180 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1181 } 1182 1183 static int sdma_v5_0_early_init(void *handle) 1184 { 1185 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1186 1187 adev->sdma.num_instances = 2; 1188 1189 sdma_v5_0_set_ring_funcs(adev); 1190 sdma_v5_0_set_buffer_funcs(adev); 1191 sdma_v5_0_set_vm_pte_funcs(adev); 1192 sdma_v5_0_set_irq_funcs(adev); 1193 1194 return 0; 1195 } 1196 1197 1198 static int sdma_v5_0_sw_init(void *handle) 1199 { 1200 struct amdgpu_ring *ring; 1201 int r, i; 1202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1203 1204 /* SDMA trap event */ 1205 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 1206 SDMA0_5_0__SRCID__SDMA_TRAP, 1207 &adev->sdma.trap_irq); 1208 if (r) 1209 return r; 1210 1211 /* SDMA trap event */ 1212 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 1213 SDMA1_5_0__SRCID__SDMA_TRAP, 1214 &adev->sdma.trap_irq); 1215 if (r) 1216 return r; 1217 1218 r = sdma_v5_0_init_microcode(adev); 1219 if (r) { 1220 DRM_ERROR("Failed to load sdma firmware!\n"); 1221 return r; 1222 } 1223 1224 for (i = 0; i < adev->sdma.num_instances; i++) { 1225 ring = &adev->sdma.instance[i].ring; 1226 ring->ring_obj = NULL; 1227 ring->use_doorbell = true; 1228 1229 DRM_INFO("use_doorbell being set to: [%s]\n", 1230 ring->use_doorbell?"true":"false"); 1231 1232 ring->doorbell_index = (i == 0) ? 1233 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset 1234 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset 1235 1236 snprintf(ring->name, sizeof(ring->name), "sdma%d", i); 1237 r = amdgpu_ring_init(adev, ring, 1024, 1238 &adev->sdma.trap_irq, 1239 (i == 0) ? 1240 AMDGPU_SDMA_IRQ_INSTANCE0 : 1241 AMDGPU_SDMA_IRQ_INSTANCE1); 1242 if (r) 1243 return r; 1244 } 1245 1246 return r; 1247 } 1248 1249 static int sdma_v5_0_sw_fini(void *handle) 1250 { 1251 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1252 int i; 1253 1254 for (i = 0; i < adev->sdma.num_instances; i++) { 1255 if (adev->sdma.instance[i].fw != NULL) 1256 release_firmware(adev->sdma.instance[i].fw); 1257 1258 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1259 } 1260 1261 return 0; 1262 } 1263 1264 static int sdma_v5_0_hw_init(void *handle) 1265 { 1266 int r; 1267 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1268 1269 sdma_v5_0_init_golden_registers(adev); 1270 1271 r = sdma_v5_0_start(adev); 1272 1273 return r; 1274 } 1275 1276 static int sdma_v5_0_hw_fini(void *handle) 1277 { 1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1279 1280 if (amdgpu_sriov_vf(adev)) 1281 return 0; 1282 1283 sdma_v5_0_ctx_switch_enable(adev, false); 1284 sdma_v5_0_enable(adev, false); 1285 1286 return 0; 1287 } 1288 1289 static int sdma_v5_0_suspend(void *handle) 1290 { 1291 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1292 1293 return sdma_v5_0_hw_fini(adev); 1294 } 1295 1296 static int sdma_v5_0_resume(void *handle) 1297 { 1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1299 1300 return sdma_v5_0_hw_init(adev); 1301 } 1302 1303 static bool sdma_v5_0_is_idle(void *handle) 1304 { 1305 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1306 u32 i; 1307 1308 for (i = 0; i < adev->sdma.num_instances; i++) { 1309 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1310 1311 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1312 return false; 1313 } 1314 1315 return true; 1316 } 1317 1318 static int sdma_v5_0_wait_for_idle(void *handle) 1319 { 1320 unsigned i; 1321 u32 sdma0, sdma1; 1322 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1323 1324 for (i = 0; i < adev->usec_timeout; i++) { 1325 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1326 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1327 1328 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1329 return 0; 1330 udelay(1); 1331 } 1332 return -ETIMEDOUT; 1333 } 1334 1335 static int sdma_v5_0_soft_reset(void *handle) 1336 { 1337 /* todo */ 1338 1339 return 0; 1340 } 1341 1342 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring) 1343 { 1344 int i, r = 0; 1345 struct amdgpu_device *adev = ring->adev; 1346 u32 index = 0; 1347 u64 sdma_gfx_preempt; 1348 1349 amdgpu_sdma_get_index_from_ring(ring, &index); 1350 if (index == 0) 1351 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT; 1352 else 1353 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT; 1354 1355 /* assert preemption condition */ 1356 amdgpu_ring_set_preempt_cond_exec(ring, false); 1357 1358 /* emit the trailing fence */ 1359 ring->trail_seq += 1; 1360 amdgpu_ring_alloc(ring, 10); 1361 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1362 ring->trail_seq, 0); 1363 amdgpu_ring_commit(ring); 1364 1365 /* assert IB preemption */ 1366 WREG32(sdma_gfx_preempt, 1); 1367 1368 /* poll the trailing fence */ 1369 for (i = 0; i < adev->usec_timeout; i++) { 1370 if (ring->trail_seq == 1371 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1372 break; 1373 udelay(1); 1374 } 1375 1376 if (i >= adev->usec_timeout) { 1377 r = -EINVAL; 1378 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1379 } 1380 1381 /* deassert IB preemption */ 1382 WREG32(sdma_gfx_preempt, 0); 1383 1384 /* deassert the preemption condition */ 1385 amdgpu_ring_set_preempt_cond_exec(ring, true); 1386 return r; 1387 } 1388 1389 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev, 1390 struct amdgpu_irq_src *source, 1391 unsigned type, 1392 enum amdgpu_interrupt_state state) 1393 { 1394 u32 sdma_cntl; 1395 1396 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? 1397 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1398 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1399 1400 sdma_cntl = RREG32(reg_offset); 1401 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1402 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1403 WREG32(reg_offset, sdma_cntl); 1404 1405 return 0; 1406 } 1407 1408 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, 1409 struct amdgpu_irq_src *source, 1410 struct amdgpu_iv_entry *entry) 1411 { 1412 DRM_DEBUG("IH: SDMA trap\n"); 1413 switch (entry->client_id) { 1414 case SOC15_IH_CLIENTID_SDMA0: 1415 switch (entry->ring_id) { 1416 case 0: 1417 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1418 break; 1419 case 1: 1420 /* XXX compute */ 1421 break; 1422 case 2: 1423 /* XXX compute */ 1424 break; 1425 case 3: 1426 /* XXX page queue*/ 1427 break; 1428 } 1429 break; 1430 case SOC15_IH_CLIENTID_SDMA1: 1431 switch (entry->ring_id) { 1432 case 0: 1433 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1434 break; 1435 case 1: 1436 /* XXX compute */ 1437 break; 1438 case 2: 1439 /* XXX compute */ 1440 break; 1441 case 3: 1442 /* XXX page queue*/ 1443 break; 1444 } 1445 break; 1446 } 1447 return 0; 1448 } 1449 1450 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1451 struct amdgpu_irq_src *source, 1452 struct amdgpu_iv_entry *entry) 1453 { 1454 return 0; 1455 } 1456 1457 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1458 bool enable) 1459 { 1460 uint32_t data, def; 1461 int i; 1462 1463 for (i = 0; i < adev->sdma.num_instances; i++) { 1464 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1465 /* Enable sdma clock gating */ 1466 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1467 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1468 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1469 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1470 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1471 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1472 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1473 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1474 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1475 if (def != data) 1476 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1477 } else { 1478 /* Disable sdma clock gating */ 1479 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1480 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1481 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1482 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1483 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1484 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1485 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1486 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1487 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1488 if (def != data) 1489 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1490 } 1491 } 1492 } 1493 1494 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1495 bool enable) 1496 { 1497 uint32_t data, def; 1498 int i; 1499 1500 for (i = 0; i < adev->sdma.num_instances; i++) { 1501 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1502 /* Enable sdma mem light sleep */ 1503 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1504 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1505 if (def != data) 1506 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1507 1508 } else { 1509 /* Disable sdma mem light sleep */ 1510 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1511 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1512 if (def != data) 1513 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1514 1515 } 1516 } 1517 } 1518 1519 static int sdma_v5_0_set_clockgating_state(void *handle, 1520 enum amd_clockgating_state state) 1521 { 1522 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1523 1524 if (amdgpu_sriov_vf(adev)) 1525 return 0; 1526 1527 switch (adev->asic_type) { 1528 case CHIP_NAVI10: 1529 case CHIP_NAVI14: 1530 case CHIP_NAVI12: 1531 sdma_v5_0_update_medium_grain_clock_gating(adev, 1532 state == AMD_CG_STATE_GATE); 1533 sdma_v5_0_update_medium_grain_light_sleep(adev, 1534 state == AMD_CG_STATE_GATE); 1535 break; 1536 default: 1537 break; 1538 } 1539 1540 return 0; 1541 } 1542 1543 static int sdma_v5_0_set_powergating_state(void *handle, 1544 enum amd_powergating_state state) 1545 { 1546 return 0; 1547 } 1548 1549 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags) 1550 { 1551 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1552 int data; 1553 1554 if (amdgpu_sriov_vf(adev)) 1555 *flags = 0; 1556 1557 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1558 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1559 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1560 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1561 1562 /* AMD_CG_SUPPORT_SDMA_LS */ 1563 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1564 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1565 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1566 } 1567 1568 const struct amd_ip_funcs sdma_v5_0_ip_funcs = { 1569 .name = "sdma_v5_0", 1570 .early_init = sdma_v5_0_early_init, 1571 .late_init = NULL, 1572 .sw_init = sdma_v5_0_sw_init, 1573 .sw_fini = sdma_v5_0_sw_fini, 1574 .hw_init = sdma_v5_0_hw_init, 1575 .hw_fini = sdma_v5_0_hw_fini, 1576 .suspend = sdma_v5_0_suspend, 1577 .resume = sdma_v5_0_resume, 1578 .is_idle = sdma_v5_0_is_idle, 1579 .wait_for_idle = sdma_v5_0_wait_for_idle, 1580 .soft_reset = sdma_v5_0_soft_reset, 1581 .set_clockgating_state = sdma_v5_0_set_clockgating_state, 1582 .set_powergating_state = sdma_v5_0_set_powergating_state, 1583 .get_clockgating_state = sdma_v5_0_get_clockgating_state, 1584 }; 1585 1586 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 1587 .type = AMDGPU_RING_TYPE_SDMA, 1588 .align_mask = 0xf, 1589 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1590 .support_64bit_ptrs = true, 1591 .vmhub = AMDGPU_GFXHUB_0, 1592 .get_rptr = sdma_v5_0_ring_get_rptr, 1593 .get_wptr = sdma_v5_0_ring_get_wptr, 1594 .set_wptr = sdma_v5_0_ring_set_wptr, 1595 .emit_frame_size = 1596 5 + /* sdma_v5_0_ring_init_cond_exec */ 1597 6 + /* sdma_v5_0_ring_emit_hdp_flush */ 1598 3 + /* hdp_invalidate */ 1599 6 + /* sdma_v5_0_ring_emit_pipeline_sync */ 1600 /* sdma_v5_0_ring_emit_vm_flush */ 1601 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1602 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 + 1603 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ 1604 .emit_ib_size = 5 + 7 + 6, /* sdma_v5_0_ring_emit_ib */ 1605 .emit_ib = sdma_v5_0_ring_emit_ib, 1606 .emit_fence = sdma_v5_0_ring_emit_fence, 1607 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync, 1608 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush, 1609 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush, 1610 .test_ring = sdma_v5_0_ring_test_ring, 1611 .test_ib = sdma_v5_0_ring_test_ib, 1612 .insert_nop = sdma_v5_0_ring_insert_nop, 1613 .pad_ib = sdma_v5_0_ring_pad_ib, 1614 .emit_wreg = sdma_v5_0_ring_emit_wreg, 1615 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait, 1616 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait, 1617 .init_cond_exec = sdma_v5_0_ring_init_cond_exec, 1618 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec, 1619 .preempt_ib = sdma_v5_0_ring_preempt_ib, 1620 }; 1621 1622 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) 1623 { 1624 int i; 1625 1626 for (i = 0; i < adev->sdma.num_instances; i++) { 1627 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; 1628 adev->sdma.instance[i].ring.me = i; 1629 } 1630 } 1631 1632 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = { 1633 .set = sdma_v5_0_set_trap_irq_state, 1634 .process = sdma_v5_0_process_trap_irq, 1635 }; 1636 1637 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = { 1638 .process = sdma_v5_0_process_illegal_inst_irq, 1639 }; 1640 1641 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev) 1642 { 1643 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1644 adev->sdma.num_instances; 1645 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; 1646 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; 1647 } 1648 1649 /** 1650 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine 1651 * 1652 * @ring: amdgpu_ring structure holding ring information 1653 * @src_offset: src GPU address 1654 * @dst_offset: dst GPU address 1655 * @byte_count: number of bytes to xfer 1656 * 1657 * Copy GPU buffers using the DMA engine (NAVI10). 1658 * Used by the amdgpu ttm implementation to move pages if 1659 * registered as the asic copy callback. 1660 */ 1661 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib, 1662 uint64_t src_offset, 1663 uint64_t dst_offset, 1664 uint32_t byte_count) 1665 { 1666 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1667 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1668 ib->ptr[ib->length_dw++] = byte_count - 1; 1669 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1670 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1671 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1672 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1673 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1674 } 1675 1676 /** 1677 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine 1678 * 1679 * @ring: amdgpu_ring structure holding ring information 1680 * @src_data: value to write to buffer 1681 * @dst_offset: dst GPU address 1682 * @byte_count: number of bytes to xfer 1683 * 1684 * Fill GPU buffers using the DMA engine (NAVI10). 1685 */ 1686 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib, 1687 uint32_t src_data, 1688 uint64_t dst_offset, 1689 uint32_t byte_count) 1690 { 1691 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1692 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1693 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1694 ib->ptr[ib->length_dw++] = src_data; 1695 ib->ptr[ib->length_dw++] = byte_count - 1; 1696 } 1697 1698 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { 1699 .copy_max_bytes = 0x400000, 1700 .copy_num_dw = 7, 1701 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer, 1702 1703 .fill_max_bytes = 0x400000, 1704 .fill_num_dw = 5, 1705 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer, 1706 }; 1707 1708 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) 1709 { 1710 if (adev->mman.buffer_funcs == NULL) { 1711 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; 1712 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1713 } 1714 } 1715 1716 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 1717 .copy_pte_num_dw = 7, 1718 .copy_pte = sdma_v5_0_vm_copy_pte, 1719 .write_pte = sdma_v5_0_vm_write_pte, 1720 .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 1721 }; 1722 1723 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1724 { 1725 unsigned i; 1726 1727 if (adev->vm_manager.vm_pte_funcs == NULL) { 1728 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; 1729 for (i = 0; i < adev->sdma.num_instances; i++) { 1730 adev->vm_manager.vm_pte_scheds[i] = 1731 &adev->sdma.instance[i].ring.sched; 1732 } 1733 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1734 } 1735 } 1736 1737 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { 1738 .type = AMD_IP_BLOCK_TYPE_SDMA, 1739 .major = 5, 1740 .minor = 0, 1741 .rev = 0, 1742 .funcs = &sdma_v5_0_ip_funcs, 1743 }; 1744