1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 30 #include "sdma0/sdma0_4_0_offset.h" 31 #include "sdma0/sdma0_4_0_sh_mask.h" 32 #include "sdma1/sdma1_4_0_offset.h" 33 #include "sdma1/sdma1_4_0_sh_mask.h" 34 #include "hdp/hdp_4_0_offset.h" 35 #include "sdma0/sdma0_4_1_default.h" 36 37 #include "soc15_common.h" 38 #include "soc15.h" 39 #include "vega10_sdma_pkt_open.h" 40 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h" 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h" 43 44 MODULE_FIRMWARE("amdgpu/vega10_sdma.bin"); 45 MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin"); 46 MODULE_FIRMWARE("amdgpu/vega12_sdma.bin"); 47 MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); 48 MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); 50 MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); 51 MODULE_FIRMWARE("amdgpu/picasso_sdma.bin"); 52 53 #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 54 #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 55 56 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev); 57 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev); 58 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev); 59 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev); 60 61 static const struct soc15_reg_golden golden_settings_sdma_4[] = { 62 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 63 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100), 64 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100), 65 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 66 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 67 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 68 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 69 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 70 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 71 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 72 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 73 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 74 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000), 75 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 76 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_IB_CNTL, 0x800f0100, 0x00000100), 77 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 78 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_IB_CNTL, 0x800f0100, 0x00000100), 79 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 80 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_POWER_CNTL, 0x003ff000, 0x0003c000), 81 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_IB_CNTL, 0x800f0100, 0x00000100), 82 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 83 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_IB_CNTL, 0x800f0100, 0x00000100), 84 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 85 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0), 86 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_WATERMK, 0xfc000000, 0x00000000) 87 }; 88 89 static const struct soc15_reg_golden golden_settings_sdma_vg10[] = { 90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002), 92 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 93 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104002), 94 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104002) 95 }; 96 97 static const struct soc15_reg_golden golden_settings_sdma_vg12[] = { 98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001), 100 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 101 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0018773f, 0x00104001), 102 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00104001) 103 }; 104 105 static const struct soc15_reg_golden golden_settings_sdma_4_1[] = 106 { 107 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 108 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 109 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100), 110 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 111 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 112 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100), 113 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 114 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100), 115 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 116 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 117 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_WATERMK, 0xfc000000, 0x00000000) 118 }; 119 120 static const struct soc15_reg_golden golden_settings_sdma_4_2[] = 121 { 122 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 123 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100), 124 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 125 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 126 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 127 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 128 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000), 129 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 130 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_UTCL1_PAGE, 0x000003ff, 0x000003c0), 131 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07), 132 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100), 133 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002), 134 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002), 135 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 136 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 137 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 138 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 139 SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_UTCL1_PAGE, 0x000003ff, 0x000003c0) 140 }; 141 142 static const struct soc15_reg_golden golden_settings_sdma_rv1[] = 143 { 144 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0018773f, 0x00000002), 145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0018773f, 0x00000002) 146 }; 147 148 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 149 u32 instance, u32 offset) 150 { 151 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : 152 (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); 153 } 154 155 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) 156 { 157 switch (adev->asic_type) { 158 case CHIP_VEGA10: 159 soc15_program_register_sequence(adev, 160 golden_settings_sdma_4, 161 ARRAY_SIZE(golden_settings_sdma_4)); 162 soc15_program_register_sequence(adev, 163 golden_settings_sdma_vg10, 164 ARRAY_SIZE(golden_settings_sdma_vg10)); 165 break; 166 case CHIP_VEGA12: 167 soc15_program_register_sequence(adev, 168 golden_settings_sdma_4, 169 ARRAY_SIZE(golden_settings_sdma_4)); 170 soc15_program_register_sequence(adev, 171 golden_settings_sdma_vg12, 172 ARRAY_SIZE(golden_settings_sdma_vg12)); 173 break; 174 case CHIP_VEGA20: 175 soc15_program_register_sequence(adev, 176 golden_settings_sdma_4_2, 177 ARRAY_SIZE(golden_settings_sdma_4_2)); 178 break; 179 case CHIP_RAVEN: 180 soc15_program_register_sequence(adev, 181 golden_settings_sdma_4_1, 182 ARRAY_SIZE(golden_settings_sdma_4_1)); 183 soc15_program_register_sequence(adev, 184 golden_settings_sdma_rv1, 185 ARRAY_SIZE(golden_settings_sdma_rv1)); 186 break; 187 default: 188 break; 189 } 190 } 191 192 /** 193 * sdma_v4_0_init_microcode - load ucode images from disk 194 * 195 * @adev: amdgpu_device pointer 196 * 197 * Use the firmware interface to load the ucode images into 198 * the driver (not loaded into hw). 199 * Returns 0 on success, error on failure. 200 */ 201 202 // emulation only, won't work on real chip 203 // vega10 real chip need to use PSP to load firmware 204 static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) 205 { 206 const char *chip_name; 207 char fw_name[30]; 208 int err = 0, i; 209 struct amdgpu_firmware_info *info = NULL; 210 const struct common_firmware_header *header = NULL; 211 const struct sdma_firmware_header_v1_0 *hdr; 212 213 DRM_DEBUG("\n"); 214 215 switch (adev->asic_type) { 216 case CHIP_VEGA10: 217 chip_name = "vega10"; 218 break; 219 case CHIP_VEGA12: 220 chip_name = "vega12"; 221 break; 222 case CHIP_VEGA20: 223 chip_name = "vega20"; 224 break; 225 case CHIP_RAVEN: 226 if (adev->pdev->device == 0x15d8) 227 chip_name = "picasso"; 228 else 229 chip_name = "raven"; 230 break; 231 default: 232 BUG(); 233 } 234 235 for (i = 0; i < adev->sdma.num_instances; i++) { 236 if (i == 0) 237 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 238 else 239 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 240 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 241 if (err) 242 goto out; 243 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 244 if (err) 245 goto out; 246 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 247 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 248 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 249 if (adev->sdma.instance[i].feature_version >= 20) 250 adev->sdma.instance[i].burst_nop = true; 251 DRM_DEBUG("psp_load == '%s'\n", 252 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 253 254 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 255 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 256 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 257 info->fw = adev->sdma.instance[i].fw; 258 header = (const struct common_firmware_header *)info->fw->data; 259 adev->firmware.fw_size += 260 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 261 } 262 } 263 out: 264 if (err) { 265 DRM_ERROR("sdma_v4_0: Failed to load firmware \"%s\"\n", fw_name); 266 for (i = 0; i < adev->sdma.num_instances; i++) { 267 release_firmware(adev->sdma.instance[i].fw); 268 adev->sdma.instance[i].fw = NULL; 269 } 270 } 271 return err; 272 } 273 274 /** 275 * sdma_v4_0_ring_get_rptr - get the current read pointer 276 * 277 * @ring: amdgpu ring pointer 278 * 279 * Get the current rptr from the hardware (VEGA10+). 280 */ 281 static uint64_t sdma_v4_0_ring_get_rptr(struct amdgpu_ring *ring) 282 { 283 u64 *rptr; 284 285 /* XXX check if swapping is necessary on BE */ 286 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 287 288 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 289 return ((*rptr) >> 2); 290 } 291 292 /** 293 * sdma_v4_0_ring_get_wptr - get the current write pointer 294 * 295 * @ring: amdgpu ring pointer 296 * 297 * Get the current wptr from the hardware (VEGA10+). 298 */ 299 static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring) 300 { 301 struct amdgpu_device *adev = ring->adev; 302 u64 wptr; 303 304 if (ring->use_doorbell) { 305 /* XXX check if swapping is necessary on BE */ 306 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); 307 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); 308 } else { 309 u32 lowbit, highbit; 310 311 lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2; 312 highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 313 314 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 315 ring->me, highbit, lowbit); 316 wptr = highbit; 317 wptr = wptr << 32; 318 wptr |= lowbit; 319 } 320 321 return wptr >> 2; 322 } 323 324 /** 325 * sdma_v4_0_ring_set_wptr - commit the write pointer 326 * 327 * @ring: amdgpu ring pointer 328 * 329 * Write the wptr back to the hardware (VEGA10+). 330 */ 331 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring) 332 { 333 struct amdgpu_device *adev = ring->adev; 334 335 DRM_DEBUG("Setting write pointer\n"); 336 if (ring->use_doorbell) { 337 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs]; 338 339 DRM_DEBUG("Using doorbell -- " 340 "wptr_offs == 0x%08x " 341 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 342 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 343 ring->wptr_offs, 344 lower_32_bits(ring->wptr << 2), 345 upper_32_bits(ring->wptr << 2)); 346 /* XXX check if swapping is necessary on BE */ 347 WRITE_ONCE(*wb, (ring->wptr << 2)); 348 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 349 ring->doorbell_index, ring->wptr << 2); 350 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 351 } else { 352 DRM_DEBUG("Not using doorbell -- " 353 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 354 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 355 ring->me, 356 lower_32_bits(ring->wptr << 2), 357 ring->me, 358 upper_32_bits(ring->wptr << 2)); 359 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); 360 WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); 361 } 362 } 363 364 static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 365 { 366 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 367 int i; 368 369 for (i = 0; i < count; i++) 370 if (sdma && sdma->burst_nop && (i == 0)) 371 amdgpu_ring_write(ring, ring->funcs->nop | 372 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 373 else 374 amdgpu_ring_write(ring, ring->funcs->nop); 375 } 376 377 /** 378 * sdma_v4_0_ring_emit_ib - Schedule an IB on the DMA engine 379 * 380 * @ring: amdgpu ring pointer 381 * @ib: IB object to schedule 382 * 383 * Schedule an IB in the DMA ring (VEGA10). 384 */ 385 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring, 386 struct amdgpu_ib *ib, 387 unsigned vmid, bool ctx_switch) 388 { 389 /* IB packet must end on a 8 DW boundary */ 390 sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8); 391 392 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 393 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 394 /* base must be 32 byte aligned */ 395 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 396 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 397 amdgpu_ring_write(ring, ib->length_dw); 398 amdgpu_ring_write(ring, 0); 399 amdgpu_ring_write(ring, 0); 400 401 } 402 403 static void sdma_v4_0_wait_reg_mem(struct amdgpu_ring *ring, 404 int mem_space, int hdp, 405 uint32_t addr0, uint32_t addr1, 406 uint32_t ref, uint32_t mask, 407 uint32_t inv) 408 { 409 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 410 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) | 411 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) | 412 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 413 if (mem_space) { 414 /* memory */ 415 amdgpu_ring_write(ring, addr0); 416 amdgpu_ring_write(ring, addr1); 417 } else { 418 /* registers */ 419 amdgpu_ring_write(ring, addr0 << 2); 420 amdgpu_ring_write(ring, addr1 << 2); 421 } 422 amdgpu_ring_write(ring, ref); /* reference */ 423 amdgpu_ring_write(ring, mask); /* mask */ 424 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 425 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ 426 } 427 428 /** 429 * sdma_v4_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 430 * 431 * @ring: amdgpu ring pointer 432 * 433 * Emit an hdp flush packet on the requested DMA ring. 434 */ 435 static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 436 { 437 struct amdgpu_device *adev = ring->adev; 438 u32 ref_and_mask = 0; 439 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 440 441 if (ring->me == 0) 442 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 443 else 444 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 445 446 sdma_v4_0_wait_reg_mem(ring, 0, 1, 447 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 448 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 449 ref_and_mask, ref_and_mask, 10); 450 } 451 452 /** 453 * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring 454 * 455 * @ring: amdgpu ring pointer 456 * @fence: amdgpu fence object 457 * 458 * Add a DMA fence packet to the ring to write 459 * the fence seq number and DMA trap packet to generate 460 * an interrupt if needed (VEGA10). 461 */ 462 static void sdma_v4_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 463 unsigned flags) 464 { 465 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 466 /* write the fence */ 467 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 468 /* zero in first two bits */ 469 BUG_ON(addr & 0x3); 470 amdgpu_ring_write(ring, lower_32_bits(addr)); 471 amdgpu_ring_write(ring, upper_32_bits(addr)); 472 amdgpu_ring_write(ring, lower_32_bits(seq)); 473 474 /* optionally write high bits as well */ 475 if (write64bit) { 476 addr += 4; 477 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)); 478 /* zero in first two bits */ 479 BUG_ON(addr & 0x3); 480 amdgpu_ring_write(ring, lower_32_bits(addr)); 481 amdgpu_ring_write(ring, upper_32_bits(addr)); 482 amdgpu_ring_write(ring, upper_32_bits(seq)); 483 } 484 485 /* generate an interrupt */ 486 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 487 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 488 } 489 490 491 /** 492 * sdma_v4_0_gfx_stop - stop the gfx async dma engines 493 * 494 * @adev: amdgpu_device pointer 495 * 496 * Stop the gfx async dma ring buffers (VEGA10). 497 */ 498 static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) 499 { 500 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 501 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 502 u32 rb_cntl, ib_cntl; 503 int i; 504 505 if ((adev->mman.buffer_funcs_ring == sdma0) || 506 (adev->mman.buffer_funcs_ring == sdma1)) 507 amdgpu_ttm_set_buffer_funcs_status(adev, false); 508 509 for (i = 0; i < adev->sdma.num_instances; i++) { 510 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 511 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 512 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 513 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 514 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 515 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 516 } 517 518 sdma0->ready = false; 519 sdma1->ready = false; 520 } 521 522 /** 523 * sdma_v4_0_rlc_stop - stop the compute async dma engines 524 * 525 * @adev: amdgpu_device pointer 526 * 527 * Stop the compute async dma queues (VEGA10). 528 */ 529 static void sdma_v4_0_rlc_stop(struct amdgpu_device *adev) 530 { 531 /* XXX todo */ 532 } 533 534 /** 535 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 536 * 537 * @adev: amdgpu_device pointer 538 * @enable: enable/disable the DMA MEs context switch. 539 * 540 * Halt or unhalt the async dma engines context switch (VEGA10). 541 */ 542 static void sdma_v4_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 543 { 544 u32 f32_cntl, phase_quantum = 0; 545 int i; 546 547 if (amdgpu_sdma_phase_quantum) { 548 unsigned value = amdgpu_sdma_phase_quantum; 549 unsigned unit = 0; 550 551 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 552 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 553 value = (value + 1) >> 1; 554 unit++; 555 } 556 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 557 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 558 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 559 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 560 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 561 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 562 WARN_ONCE(1, 563 "clamping sdma_phase_quantum to %uK clock cycles\n", 564 value << unit); 565 } 566 phase_quantum = 567 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 568 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 569 } 570 571 for (i = 0; i < adev->sdma.num_instances; i++) { 572 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 573 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 574 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 575 if (enable && amdgpu_sdma_phase_quantum) { 576 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 577 phase_quantum); 578 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 579 phase_quantum); 580 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 581 phase_quantum); 582 } 583 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 584 } 585 586 } 587 588 /** 589 * sdma_v4_0_enable - stop the async dma engines 590 * 591 * @adev: amdgpu_device pointer 592 * @enable: enable/disable the DMA MEs. 593 * 594 * Halt or unhalt the async dma engines (VEGA10). 595 */ 596 static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable) 597 { 598 u32 f32_cntl; 599 int i; 600 601 if (enable == false) { 602 sdma_v4_0_gfx_stop(adev); 603 sdma_v4_0_rlc_stop(adev); 604 } 605 606 for (i = 0; i < adev->sdma.num_instances; i++) { 607 f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 608 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 609 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 610 } 611 } 612 613 /** 614 * sdma_v4_0_gfx_resume - setup and start the async dma engines 615 * 616 * @adev: amdgpu_device pointer 617 * 618 * Set up the gfx DMA ring buffers and enable them (VEGA10). 619 * Returns 0 for success, error for failure. 620 */ 621 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) 622 { 623 struct amdgpu_ring *ring; 624 u32 rb_cntl, ib_cntl, wptr_poll_cntl; 625 u32 rb_bufsz; 626 u32 wb_offset; 627 u32 doorbell; 628 u32 doorbell_offset; 629 u32 temp; 630 u64 wptr_gpu_addr; 631 int i, r; 632 633 for (i = 0; i < adev->sdma.num_instances; i++) { 634 ring = &adev->sdma.instance[i].ring; 635 wb_offset = (ring->rptr_offs * 4); 636 637 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 638 639 /* Set ring buffer size in dwords */ 640 rb_bufsz = order_base_2(ring->ring_size / 4); 641 rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 642 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 643 #ifdef __BIG_ENDIAN 644 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 645 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 646 RPTR_WRITEBACK_SWAP_ENABLE, 1); 647 #endif 648 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 649 650 /* Initialize the ring buffer's read and write pointers */ 651 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 652 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 653 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 654 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 655 656 /* set the wb address whether it's enabled or not */ 657 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 658 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 659 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 660 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 661 662 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 663 664 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 665 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 666 667 ring->wptr = 0; 668 669 /* before programing wptr to a less value, need set minor_ptr_update first */ 670 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 671 672 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 673 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 674 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 675 } 676 677 doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 678 doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 679 680 if (ring->use_doorbell) { 681 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 682 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 683 OFFSET, ring->doorbell_index); 684 } else { 685 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 686 } 687 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 688 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 689 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 690 ring->doorbell_index); 691 692 if (amdgpu_sriov_vf(adev)) 693 sdma_v4_0_ring_set_wptr(ring); 694 695 /* set minor_ptr_update to 0 after wptr programed */ 696 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 697 698 /* set utc l1 enable flag always to 1 */ 699 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 700 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 701 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 702 703 if (!amdgpu_sriov_vf(adev)) { 704 /* unhalt engine */ 705 temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 706 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 707 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 708 } 709 710 /* setup the wptr shadow polling */ 711 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 712 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 713 lower_32_bits(wptr_gpu_addr)); 714 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 715 upper_32_bits(wptr_gpu_addr)); 716 wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 717 if (amdgpu_sriov_vf(adev)) 718 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1); 719 else 720 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0); 721 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl); 722 723 /* enable DMA RB */ 724 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 725 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 726 727 ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 728 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 729 #ifdef __BIG_ENDIAN 730 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 731 #endif 732 /* enable DMA IBs */ 733 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 734 735 ring->ready = true; 736 737 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 738 sdma_v4_0_ctx_switch_enable(adev, true); 739 sdma_v4_0_enable(adev, true); 740 } 741 742 r = amdgpu_ring_test_ring(ring); 743 if (r) { 744 ring->ready = false; 745 return r; 746 } 747 748 if (adev->mman.buffer_funcs_ring == ring) 749 amdgpu_ttm_set_buffer_funcs_status(adev, true); 750 751 } 752 753 return 0; 754 } 755 756 static void 757 sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable) 758 { 759 uint32_t def, data; 760 761 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) { 762 /* disable idle interrupt */ 763 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 764 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 765 766 if (data != def) 767 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 768 } else { 769 /* disable idle interrupt */ 770 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 771 data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 772 if (data != def) 773 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 774 } 775 } 776 777 static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev) 778 { 779 uint32_t def, data; 780 781 /* Enable HW based PG. */ 782 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 783 data |= SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK; 784 if (data != def) 785 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 786 787 /* enable interrupt */ 788 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL)); 789 data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK; 790 if (data != def) 791 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data); 792 793 /* Configure hold time to filter in-valid power on/off request. Use default right now */ 794 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 795 data &= ~SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK; 796 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK); 797 /* Configure switch time for hysteresis purpose. Use default right now */ 798 data &= ~SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK; 799 data |= (mmSDMA0_POWER_CNTL_DEFAULT & SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK); 800 if(data != def) 801 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 802 } 803 804 static void sdma_v4_0_init_pg(struct amdgpu_device *adev) 805 { 806 if (!(adev->pg_flags & AMD_PG_SUPPORT_SDMA)) 807 return; 808 809 switch (adev->asic_type) { 810 case CHIP_RAVEN: 811 sdma_v4_1_init_power_gating(adev); 812 sdma_v4_1_update_power_gating(adev, true); 813 break; 814 default: 815 break; 816 } 817 } 818 819 /** 820 * sdma_v4_0_rlc_resume - setup and start the async dma engines 821 * 822 * @adev: amdgpu_device pointer 823 * 824 * Set up the compute DMA queues and enable them (VEGA10). 825 * Returns 0 for success, error for failure. 826 */ 827 static int sdma_v4_0_rlc_resume(struct amdgpu_device *adev) 828 { 829 sdma_v4_0_init_pg(adev); 830 831 return 0; 832 } 833 834 /** 835 * sdma_v4_0_load_microcode - load the sDMA ME ucode 836 * 837 * @adev: amdgpu_device pointer 838 * 839 * Loads the sDMA0/1 ucode. 840 * Returns 0 for success, -EINVAL if the ucode is not available. 841 */ 842 static int sdma_v4_0_load_microcode(struct amdgpu_device *adev) 843 { 844 const struct sdma_firmware_header_v1_0 *hdr; 845 const __le32 *fw_data; 846 u32 fw_size; 847 int i, j; 848 849 /* halt the MEs */ 850 sdma_v4_0_enable(adev, false); 851 852 for (i = 0; i < adev->sdma.num_instances; i++) { 853 if (!adev->sdma.instance[i].fw) 854 return -EINVAL; 855 856 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 857 amdgpu_ucode_print_sdma_hdr(&hdr->header); 858 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 859 860 fw_data = (const __le32 *) 861 (adev->sdma.instance[i].fw->data + 862 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 863 864 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 865 866 for (j = 0; j < fw_size; j++) 867 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 868 869 WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 870 } 871 872 return 0; 873 } 874 875 /** 876 * sdma_v4_0_start - setup and start the async dma engines 877 * 878 * @adev: amdgpu_device pointer 879 * 880 * Set up the DMA engines and enable them (VEGA10). 881 * Returns 0 for success, error for failure. 882 */ 883 static int sdma_v4_0_start(struct amdgpu_device *adev) 884 { 885 int r = 0; 886 887 if (amdgpu_sriov_vf(adev)) { 888 sdma_v4_0_ctx_switch_enable(adev, false); 889 sdma_v4_0_enable(adev, false); 890 891 /* set RB registers */ 892 r = sdma_v4_0_gfx_resume(adev); 893 return r; 894 } 895 896 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 897 r = sdma_v4_0_load_microcode(adev); 898 if (r) 899 return r; 900 } 901 902 /* unhalt the MEs */ 903 sdma_v4_0_enable(adev, true); 904 /* enable sdma ring preemption */ 905 sdma_v4_0_ctx_switch_enable(adev, true); 906 907 /* start the gfx rings and rlc compute queues */ 908 r = sdma_v4_0_gfx_resume(adev); 909 if (r) 910 return r; 911 r = sdma_v4_0_rlc_resume(adev); 912 913 return r; 914 } 915 916 /** 917 * sdma_v4_0_ring_test_ring - simple async dma engine test 918 * 919 * @ring: amdgpu_ring structure holding ring information 920 * 921 * Test the DMA engine by writing using it to write an 922 * value to memory. (VEGA10). 923 * Returns 0 for success, error for failure. 924 */ 925 static int sdma_v4_0_ring_test_ring(struct amdgpu_ring *ring) 926 { 927 struct amdgpu_device *adev = ring->adev; 928 unsigned i; 929 unsigned index; 930 int r; 931 u32 tmp; 932 u64 gpu_addr; 933 934 r = amdgpu_device_wb_get(adev, &index); 935 if (r) { 936 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 937 return r; 938 } 939 940 gpu_addr = adev->wb.gpu_addr + (index * 4); 941 tmp = 0xCAFEDEAD; 942 adev->wb.wb[index] = cpu_to_le32(tmp); 943 944 r = amdgpu_ring_alloc(ring, 5); 945 if (r) { 946 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 947 amdgpu_device_wb_free(adev, index); 948 return r; 949 } 950 951 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 952 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 953 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 954 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 955 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 956 amdgpu_ring_write(ring, 0xDEADBEEF); 957 amdgpu_ring_commit(ring); 958 959 for (i = 0; i < adev->usec_timeout; i++) { 960 tmp = le32_to_cpu(adev->wb.wb[index]); 961 if (tmp == 0xDEADBEEF) 962 break; 963 DRM_UDELAY(1); 964 } 965 966 if (i < adev->usec_timeout) { 967 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i); 968 } else { 969 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 970 ring->idx, tmp); 971 r = -EINVAL; 972 } 973 amdgpu_device_wb_free(adev, index); 974 975 return r; 976 } 977 978 /** 979 * sdma_v4_0_ring_test_ib - test an IB on the DMA engine 980 * 981 * @ring: amdgpu_ring structure holding ring information 982 * 983 * Test a simple IB in the DMA ring (VEGA10). 984 * Returns 0 on success, error on failure. 985 */ 986 static int sdma_v4_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 987 { 988 struct amdgpu_device *adev = ring->adev; 989 struct amdgpu_ib ib; 990 struct dma_fence *f = NULL; 991 unsigned index; 992 long r; 993 u32 tmp = 0; 994 u64 gpu_addr; 995 996 r = amdgpu_device_wb_get(adev, &index); 997 if (r) { 998 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 999 return r; 1000 } 1001 1002 gpu_addr = adev->wb.gpu_addr + (index * 4); 1003 tmp = 0xCAFEDEAD; 1004 adev->wb.wb[index] = cpu_to_le32(tmp); 1005 memset(&ib, 0, sizeof(ib)); 1006 r = amdgpu_ib_get(adev, NULL, 256, &ib); 1007 if (r) { 1008 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 1009 goto err0; 1010 } 1011 1012 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1013 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1014 ib.ptr[1] = lower_32_bits(gpu_addr); 1015 ib.ptr[2] = upper_32_bits(gpu_addr); 1016 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 1017 ib.ptr[4] = 0xDEADBEEF; 1018 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1019 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1020 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 1021 ib.length_dw = 8; 1022 1023 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1024 if (r) 1025 goto err1; 1026 1027 r = dma_fence_wait_timeout(f, false, timeout); 1028 if (r == 0) { 1029 DRM_ERROR("amdgpu: IB test timed out\n"); 1030 r = -ETIMEDOUT; 1031 goto err1; 1032 } else if (r < 0) { 1033 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 1034 goto err1; 1035 } 1036 tmp = le32_to_cpu(adev->wb.wb[index]); 1037 if (tmp == 0xDEADBEEF) { 1038 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 1039 r = 0; 1040 } else { 1041 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 1042 r = -EINVAL; 1043 } 1044 err1: 1045 amdgpu_ib_free(adev, &ib, NULL); 1046 dma_fence_put(f); 1047 err0: 1048 amdgpu_device_wb_free(adev, index); 1049 return r; 1050 } 1051 1052 1053 /** 1054 * sdma_v4_0_vm_copy_pte - update PTEs by copying them from the GART 1055 * 1056 * @ib: indirect buffer to fill with commands 1057 * @pe: addr of the page entry 1058 * @src: src addr to copy from 1059 * @count: number of page entries to update 1060 * 1061 * Update PTEs by copying them from the GART using sDMA (VEGA10). 1062 */ 1063 static void sdma_v4_0_vm_copy_pte(struct amdgpu_ib *ib, 1064 uint64_t pe, uint64_t src, 1065 unsigned count) 1066 { 1067 unsigned bytes = count * 8; 1068 1069 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1070 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1071 ib->ptr[ib->length_dw++] = bytes - 1; 1072 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1073 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1074 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1075 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1076 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1077 1078 } 1079 1080 /** 1081 * sdma_v4_0_vm_write_pte - update PTEs by writing them manually 1082 * 1083 * @ib: indirect buffer to fill with commands 1084 * @pe: addr of the page entry 1085 * @addr: dst addr to write into pe 1086 * @count: number of page entries to update 1087 * @incr: increase next addr by incr bytes 1088 * @flags: access flags 1089 * 1090 * Update PTEs by writing them manually using sDMA (VEGA10). 1091 */ 1092 static void sdma_v4_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1093 uint64_t value, unsigned count, 1094 uint32_t incr) 1095 { 1096 unsigned ndw = count * 2; 1097 1098 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1099 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1100 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1101 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1102 ib->ptr[ib->length_dw++] = ndw - 1; 1103 for (; ndw > 0; ndw -= 2) { 1104 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1105 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1106 value += incr; 1107 } 1108 } 1109 1110 /** 1111 * sdma_v4_0_vm_set_pte_pde - update the page tables using sDMA 1112 * 1113 * @ib: indirect buffer to fill with commands 1114 * @pe: addr of the page entry 1115 * @addr: dst addr to write into pe 1116 * @count: number of page entries to update 1117 * @incr: increase next addr by incr bytes 1118 * @flags: access flags 1119 * 1120 * Update the page tables using sDMA (VEGA10). 1121 */ 1122 static void sdma_v4_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1123 uint64_t pe, 1124 uint64_t addr, unsigned count, 1125 uint32_t incr, uint64_t flags) 1126 { 1127 /* for physically contiguous pages (vram) */ 1128 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1129 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1130 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1131 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1132 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1133 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1134 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1135 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1136 ib->ptr[ib->length_dw++] = 0; 1137 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1138 } 1139 1140 /** 1141 * sdma_v4_0_ring_pad_ib - pad the IB to the required number of dw 1142 * 1143 * @ib: indirect buffer to fill with padding 1144 * 1145 */ 1146 static void sdma_v4_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1147 { 1148 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 1149 u32 pad_count; 1150 int i; 1151 1152 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 1153 for (i = 0; i < pad_count; i++) 1154 if (sdma && sdma->burst_nop && (i == 0)) 1155 ib->ptr[ib->length_dw++] = 1156 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1157 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1158 else 1159 ib->ptr[ib->length_dw++] = 1160 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1161 } 1162 1163 1164 /** 1165 * sdma_v4_0_ring_emit_pipeline_sync - sync the pipeline 1166 * 1167 * @ring: amdgpu_ring pointer 1168 * 1169 * Make sure all previous operations are completed (CIK). 1170 */ 1171 static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1172 { 1173 uint32_t seq = ring->fence_drv.sync_seq; 1174 uint64_t addr = ring->fence_drv.gpu_addr; 1175 1176 /* wait for idle */ 1177 sdma_v4_0_wait_reg_mem(ring, 1, 0, 1178 addr & 0xfffffffc, 1179 upper_32_bits(addr) & 0xffffffff, 1180 seq, 0xffffffff, 4); 1181 } 1182 1183 1184 /** 1185 * sdma_v4_0_ring_emit_vm_flush - vm flush using sDMA 1186 * 1187 * @ring: amdgpu_ring pointer 1188 * @vm: amdgpu_vm pointer 1189 * 1190 * Update the page table base and flush the VM TLB 1191 * using sDMA (VEGA10). 1192 */ 1193 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1194 unsigned vmid, uint64_t pd_addr) 1195 { 1196 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1197 } 1198 1199 static void sdma_v4_0_ring_emit_wreg(struct amdgpu_ring *ring, 1200 uint32_t reg, uint32_t val) 1201 { 1202 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1203 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1204 amdgpu_ring_write(ring, reg); 1205 amdgpu_ring_write(ring, val); 1206 } 1207 1208 static void sdma_v4_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1209 uint32_t val, uint32_t mask) 1210 { 1211 sdma_v4_0_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10); 1212 } 1213 1214 static int sdma_v4_0_early_init(void *handle) 1215 { 1216 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1217 1218 if (adev->asic_type == CHIP_RAVEN) 1219 adev->sdma.num_instances = 1; 1220 else 1221 adev->sdma.num_instances = 2; 1222 1223 sdma_v4_0_set_ring_funcs(adev); 1224 sdma_v4_0_set_buffer_funcs(adev); 1225 sdma_v4_0_set_vm_pte_funcs(adev); 1226 sdma_v4_0_set_irq_funcs(adev); 1227 1228 return 0; 1229 } 1230 1231 1232 static int sdma_v4_0_sw_init(void *handle) 1233 { 1234 struct amdgpu_ring *ring; 1235 int r, i; 1236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1237 1238 /* SDMA trap event */ 1239 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP, 1240 &adev->sdma.trap_irq); 1241 if (r) 1242 return r; 1243 1244 /* SDMA trap event */ 1245 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP, 1246 &adev->sdma.trap_irq); 1247 if (r) 1248 return r; 1249 1250 r = sdma_v4_0_init_microcode(adev); 1251 if (r) { 1252 DRM_ERROR("Failed to load sdma firmware!\n"); 1253 return r; 1254 } 1255 1256 for (i = 0; i < adev->sdma.num_instances; i++) { 1257 ring = &adev->sdma.instance[i].ring; 1258 ring->ring_obj = NULL; 1259 ring->use_doorbell = true; 1260 1261 DRM_INFO("use_doorbell being set to: [%s]\n", 1262 ring->use_doorbell?"true":"false"); 1263 1264 ring->doorbell_index = (i == 0) ? 1265 (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1) //get DWORD offset 1266 : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset 1267 1268 snprintf(ring->name, sizeof(ring->name), "sdma%d", i); 1269 r = amdgpu_ring_init(adev, ring, 1024, 1270 &adev->sdma.trap_irq, 1271 (i == 0) ? 1272 AMDGPU_SDMA_IRQ_TRAP0 : 1273 AMDGPU_SDMA_IRQ_TRAP1); 1274 if (r) 1275 return r; 1276 } 1277 1278 return r; 1279 } 1280 1281 static int sdma_v4_0_sw_fini(void *handle) 1282 { 1283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1284 int i; 1285 1286 for (i = 0; i < adev->sdma.num_instances; i++) 1287 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1288 1289 for (i = 0; i < adev->sdma.num_instances; i++) { 1290 release_firmware(adev->sdma.instance[i].fw); 1291 adev->sdma.instance[i].fw = NULL; 1292 } 1293 1294 return 0; 1295 } 1296 1297 static int sdma_v4_0_hw_init(void *handle) 1298 { 1299 int r; 1300 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1301 1302 sdma_v4_0_init_golden_registers(adev); 1303 1304 r = sdma_v4_0_start(adev); 1305 1306 return r; 1307 } 1308 1309 static int sdma_v4_0_hw_fini(void *handle) 1310 { 1311 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1312 1313 if (amdgpu_sriov_vf(adev)) 1314 return 0; 1315 1316 sdma_v4_0_ctx_switch_enable(adev, false); 1317 sdma_v4_0_enable(adev, false); 1318 1319 return 0; 1320 } 1321 1322 static int sdma_v4_0_suspend(void *handle) 1323 { 1324 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1325 1326 return sdma_v4_0_hw_fini(adev); 1327 } 1328 1329 static int sdma_v4_0_resume(void *handle) 1330 { 1331 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1332 1333 return sdma_v4_0_hw_init(adev); 1334 } 1335 1336 static bool sdma_v4_0_is_idle(void *handle) 1337 { 1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1339 u32 i; 1340 1341 for (i = 0; i < adev->sdma.num_instances; i++) { 1342 u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1343 1344 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1345 return false; 1346 } 1347 1348 return true; 1349 } 1350 1351 static int sdma_v4_0_wait_for_idle(void *handle) 1352 { 1353 unsigned i; 1354 u32 sdma0, sdma1; 1355 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1356 1357 for (i = 0; i < adev->usec_timeout; i++) { 1358 sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1359 sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1360 1361 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1362 return 0; 1363 udelay(1); 1364 } 1365 return -ETIMEDOUT; 1366 } 1367 1368 static int sdma_v4_0_soft_reset(void *handle) 1369 { 1370 /* todo */ 1371 1372 return 0; 1373 } 1374 1375 static int sdma_v4_0_set_trap_irq_state(struct amdgpu_device *adev, 1376 struct amdgpu_irq_src *source, 1377 unsigned type, 1378 enum amdgpu_interrupt_state state) 1379 { 1380 u32 sdma_cntl; 1381 1382 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? 1383 sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1384 sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1385 1386 sdma_cntl = RREG32(reg_offset); 1387 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1388 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1389 WREG32(reg_offset, sdma_cntl); 1390 1391 return 0; 1392 } 1393 1394 static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, 1395 struct amdgpu_irq_src *source, 1396 struct amdgpu_iv_entry *entry) 1397 { 1398 DRM_DEBUG("IH: SDMA trap\n"); 1399 switch (entry->client_id) { 1400 case SOC15_IH_CLIENTID_SDMA0: 1401 switch (entry->ring_id) { 1402 case 0: 1403 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1404 break; 1405 case 1: 1406 /* XXX compute */ 1407 break; 1408 case 2: 1409 /* XXX compute */ 1410 break; 1411 case 3: 1412 /* XXX page queue*/ 1413 break; 1414 } 1415 break; 1416 case SOC15_IH_CLIENTID_SDMA1: 1417 switch (entry->ring_id) { 1418 case 0: 1419 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1420 break; 1421 case 1: 1422 /* XXX compute */ 1423 break; 1424 case 2: 1425 /* XXX compute */ 1426 break; 1427 case 3: 1428 /* XXX page queue*/ 1429 break; 1430 } 1431 break; 1432 } 1433 return 0; 1434 } 1435 1436 static int sdma_v4_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1437 struct amdgpu_irq_src *source, 1438 struct amdgpu_iv_entry *entry) 1439 { 1440 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1441 schedule_work(&adev->reset_work); 1442 return 0; 1443 } 1444 1445 1446 static void sdma_v4_0_update_medium_grain_clock_gating( 1447 struct amdgpu_device *adev, 1448 bool enable) 1449 { 1450 uint32_t data, def; 1451 1452 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1453 /* enable sdma0 clock gating */ 1454 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1455 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1456 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1457 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1458 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1459 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1460 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1461 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1462 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1463 if (def != data) 1464 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1465 1466 if (adev->sdma.num_instances > 1) { 1467 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1468 data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1469 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1470 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1471 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1472 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1473 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1474 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1475 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1476 if (def != data) 1477 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1478 } 1479 } else { 1480 /* disable sdma0 clock gating */ 1481 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1482 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1483 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1484 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1485 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1486 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1487 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1488 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1489 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1490 1491 if (def != data) 1492 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data); 1493 1494 if (adev->sdma.num_instances > 1) { 1495 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL)); 1496 data |= (SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1497 SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1498 SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1499 SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1500 SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1501 SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1502 SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1503 SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1504 if (def != data) 1505 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data); 1506 } 1507 } 1508 } 1509 1510 1511 static void sdma_v4_0_update_medium_grain_light_sleep( 1512 struct amdgpu_device *adev, 1513 bool enable) 1514 { 1515 uint32_t data, def; 1516 1517 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1518 /* 1-not override: enable sdma0 mem light sleep */ 1519 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1520 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1521 if (def != data) 1522 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1523 1524 /* 1-not override: enable sdma1 mem light sleep */ 1525 if (adev->sdma.num_instances > 1) { 1526 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1527 data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1528 if (def != data) 1529 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1530 } 1531 } else { 1532 /* 0-override:disable sdma0 mem light sleep */ 1533 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1534 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1535 if (def != data) 1536 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1537 1538 /* 0-override:disable sdma1 mem light sleep */ 1539 if (adev->sdma.num_instances > 1) { 1540 def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL)); 1541 data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1542 if (def != data) 1543 WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data); 1544 } 1545 } 1546 } 1547 1548 static int sdma_v4_0_set_clockgating_state(void *handle, 1549 enum amd_clockgating_state state) 1550 { 1551 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1552 1553 if (amdgpu_sriov_vf(adev)) 1554 return 0; 1555 1556 switch (adev->asic_type) { 1557 case CHIP_VEGA10: 1558 case CHIP_VEGA12: 1559 case CHIP_VEGA20: 1560 case CHIP_RAVEN: 1561 sdma_v4_0_update_medium_grain_clock_gating(adev, 1562 state == AMD_CG_STATE_GATE ? true : false); 1563 sdma_v4_0_update_medium_grain_light_sleep(adev, 1564 state == AMD_CG_STATE_GATE ? true : false); 1565 break; 1566 default: 1567 break; 1568 } 1569 return 0; 1570 } 1571 1572 static int sdma_v4_0_set_powergating_state(void *handle, 1573 enum amd_powergating_state state) 1574 { 1575 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1576 1577 switch (adev->asic_type) { 1578 case CHIP_RAVEN: 1579 sdma_v4_1_update_power_gating(adev, 1580 state == AMD_PG_STATE_GATE ? true : false); 1581 break; 1582 default: 1583 break; 1584 } 1585 1586 return 0; 1587 } 1588 1589 static void sdma_v4_0_get_clockgating_state(void *handle, u32 *flags) 1590 { 1591 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1592 int data; 1593 1594 if (amdgpu_sriov_vf(adev)) 1595 *flags = 0; 1596 1597 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1598 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); 1599 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1600 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1601 1602 /* AMD_CG_SUPPORT_SDMA_LS */ 1603 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1604 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1605 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1606 } 1607 1608 const struct amd_ip_funcs sdma_v4_0_ip_funcs = { 1609 .name = "sdma_v4_0", 1610 .early_init = sdma_v4_0_early_init, 1611 .late_init = NULL, 1612 .sw_init = sdma_v4_0_sw_init, 1613 .sw_fini = sdma_v4_0_sw_fini, 1614 .hw_init = sdma_v4_0_hw_init, 1615 .hw_fini = sdma_v4_0_hw_fini, 1616 .suspend = sdma_v4_0_suspend, 1617 .resume = sdma_v4_0_resume, 1618 .is_idle = sdma_v4_0_is_idle, 1619 .wait_for_idle = sdma_v4_0_wait_for_idle, 1620 .soft_reset = sdma_v4_0_soft_reset, 1621 .set_clockgating_state = sdma_v4_0_set_clockgating_state, 1622 .set_powergating_state = sdma_v4_0_set_powergating_state, 1623 .get_clockgating_state = sdma_v4_0_get_clockgating_state, 1624 }; 1625 1626 static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { 1627 .type = AMDGPU_RING_TYPE_SDMA, 1628 .align_mask = 0xf, 1629 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1630 .support_64bit_ptrs = true, 1631 .vmhub = AMDGPU_MMHUB, 1632 .get_rptr = sdma_v4_0_ring_get_rptr, 1633 .get_wptr = sdma_v4_0_ring_get_wptr, 1634 .set_wptr = sdma_v4_0_ring_set_wptr, 1635 .emit_frame_size = 1636 6 + /* sdma_v4_0_ring_emit_hdp_flush */ 1637 3 + /* hdp invalidate */ 1638 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ 1639 /* sdma_v4_0_ring_emit_vm_flush */ 1640 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1641 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 + 1642 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ 1643 .emit_ib_size = 7 + 6, /* sdma_v4_0_ring_emit_ib */ 1644 .emit_ib = sdma_v4_0_ring_emit_ib, 1645 .emit_fence = sdma_v4_0_ring_emit_fence, 1646 .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, 1647 .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, 1648 .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, 1649 .test_ring = sdma_v4_0_ring_test_ring, 1650 .test_ib = sdma_v4_0_ring_test_ib, 1651 .insert_nop = sdma_v4_0_ring_insert_nop, 1652 .pad_ib = sdma_v4_0_ring_pad_ib, 1653 .emit_wreg = sdma_v4_0_ring_emit_wreg, 1654 .emit_reg_wait = sdma_v4_0_ring_emit_reg_wait, 1655 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1656 }; 1657 1658 static void sdma_v4_0_set_ring_funcs(struct amdgpu_device *adev) 1659 { 1660 int i; 1661 1662 for (i = 0; i < adev->sdma.num_instances; i++) { 1663 adev->sdma.instance[i].ring.funcs = &sdma_v4_0_ring_funcs; 1664 adev->sdma.instance[i].ring.me = i; 1665 } 1666 } 1667 1668 static const struct amdgpu_irq_src_funcs sdma_v4_0_trap_irq_funcs = { 1669 .set = sdma_v4_0_set_trap_irq_state, 1670 .process = sdma_v4_0_process_trap_irq, 1671 }; 1672 1673 static const struct amdgpu_irq_src_funcs sdma_v4_0_illegal_inst_irq_funcs = { 1674 .process = sdma_v4_0_process_illegal_inst_irq, 1675 }; 1676 1677 static void sdma_v4_0_set_irq_funcs(struct amdgpu_device *adev) 1678 { 1679 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1680 adev->sdma.trap_irq.funcs = &sdma_v4_0_trap_irq_funcs; 1681 adev->sdma.illegal_inst_irq.funcs = &sdma_v4_0_illegal_inst_irq_funcs; 1682 } 1683 1684 /** 1685 * sdma_v4_0_emit_copy_buffer - copy buffer using the sDMA engine 1686 * 1687 * @ring: amdgpu_ring structure holding ring information 1688 * @src_offset: src GPU address 1689 * @dst_offset: dst GPU address 1690 * @byte_count: number of bytes to xfer 1691 * 1692 * Copy GPU buffers using the DMA engine (VEGA10/12). 1693 * Used by the amdgpu ttm implementation to move pages if 1694 * registered as the asic copy callback. 1695 */ 1696 static void sdma_v4_0_emit_copy_buffer(struct amdgpu_ib *ib, 1697 uint64_t src_offset, 1698 uint64_t dst_offset, 1699 uint32_t byte_count) 1700 { 1701 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1702 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1703 ib->ptr[ib->length_dw++] = byte_count - 1; 1704 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1705 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1706 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1707 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1708 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1709 } 1710 1711 /** 1712 * sdma_v4_0_emit_fill_buffer - fill buffer using the sDMA engine 1713 * 1714 * @ring: amdgpu_ring structure holding ring information 1715 * @src_data: value to write to buffer 1716 * @dst_offset: dst GPU address 1717 * @byte_count: number of bytes to xfer 1718 * 1719 * Fill GPU buffers using the DMA engine (VEGA10/12). 1720 */ 1721 static void sdma_v4_0_emit_fill_buffer(struct amdgpu_ib *ib, 1722 uint32_t src_data, 1723 uint64_t dst_offset, 1724 uint32_t byte_count) 1725 { 1726 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1727 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1728 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1729 ib->ptr[ib->length_dw++] = src_data; 1730 ib->ptr[ib->length_dw++] = byte_count - 1; 1731 } 1732 1733 static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = { 1734 .copy_max_bytes = 0x400000, 1735 .copy_num_dw = 7, 1736 .emit_copy_buffer = sdma_v4_0_emit_copy_buffer, 1737 1738 .fill_max_bytes = 0x400000, 1739 .fill_num_dw = 5, 1740 .emit_fill_buffer = sdma_v4_0_emit_fill_buffer, 1741 }; 1742 1743 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev) 1744 { 1745 if (adev->mman.buffer_funcs == NULL) { 1746 adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs; 1747 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1748 } 1749 } 1750 1751 static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 1752 .copy_pte_num_dw = 7, 1753 .copy_pte = sdma_v4_0_vm_copy_pte, 1754 1755 .write_pte = sdma_v4_0_vm_write_pte, 1756 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 1757 }; 1758 1759 static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1760 { 1761 unsigned i; 1762 1763 if (adev->vm_manager.vm_pte_funcs == NULL) { 1764 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; 1765 for (i = 0; i < adev->sdma.num_instances; i++) 1766 adev->vm_manager.vm_pte_rings[i] = 1767 &adev->sdma.instance[i].ring; 1768 1769 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1770 } 1771 } 1772 1773 const struct amdgpu_ip_block_version sdma_v4_0_ip_block = { 1774 .type = AMD_IP_BLOCK_TYPE_SDMA, 1775 .major = 4, 1776 .minor = 0, 1777 .rev = 0, 1778 .funcs = &sdma_v4_0_ip_funcs, 1779 }; 1780