1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drm_drv.h> 24 #include <linux/vmalloc.h> 25 #include "amdgpu.h" 26 #include "amdgpu_psp.h" 27 #include "amdgpu_ucode.h" 28 #include "soc15_common.h" 29 #include "psp_v13_0.h" 30 31 #include "mp/mp_13_0_2_offset.h" 32 #include "mp/mp_13_0_2_sh_mask.h" 33 34 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin"); 35 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin"); 36 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin"); 37 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin"); 38 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin"); 39 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin"); 40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin"); 41 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin"); 42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin"); 43 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin"); 45 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin"); 46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin"); 47 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin"); 48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin"); 49 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin"); 50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin"); 51 52 /* For large FW files the time to complete can be very long */ 53 #define USBC_PD_POLLING_LIMIT_S 240 54 55 /* Read USB-PD from LFB */ 56 #define GFX_CMD_USB_PD_USE_LFB 0x480 57 58 /* VBIOS gfl defines */ 59 #define MBOX_READY_MASK 0x80000000 60 #define MBOX_STATUS_MASK 0x0000FFFF 61 #define MBOX_COMMAND_MASK 0x00FF0000 62 #define MBOX_READY_FLAG 0x80000000 63 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2 64 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3 65 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4 66 67 /* memory training timeout define */ 68 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 69 70 static int psp_v13_0_init_microcode(struct psp_context *psp) 71 { 72 struct amdgpu_device *adev = psp->adev; 73 const char *chip_name; 74 char ucode_prefix[30]; 75 int err = 0; 76 77 switch (adev->ip_versions[MP0_HWIP][0]) { 78 case IP_VERSION(13, 0, 2): 79 chip_name = "aldebaran"; 80 break; 81 case IP_VERSION(13, 0, 1): 82 case IP_VERSION(13, 0, 3): 83 chip_name = "yellow_carp"; 84 break; 85 default: 86 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); 87 chip_name = ucode_prefix; 88 break; 89 } 90 91 switch (adev->ip_versions[MP0_HWIP][0]) { 92 case IP_VERSION(13, 0, 2): 93 err = psp_init_sos_microcode(psp, chip_name); 94 if (err) 95 return err; 96 /* It's not necessary to load ras ta on Guest side */ 97 if (!amdgpu_sriov_vf(adev)) { 98 err = psp_init_ta_microcode(&adev->psp, chip_name); 99 if (err) 100 return err; 101 } 102 break; 103 case IP_VERSION(13, 0, 1): 104 case IP_VERSION(13, 0, 3): 105 case IP_VERSION(13, 0, 5): 106 case IP_VERSION(13, 0, 8): 107 case IP_VERSION(13, 0, 11): 108 err = psp_init_toc_microcode(psp, chip_name); 109 if (err) 110 return err; 111 err = psp_init_ta_microcode(psp, chip_name); 112 if (err) 113 return err; 114 break; 115 case IP_VERSION(13, 0, 0): 116 case IP_VERSION(13, 0, 7): 117 case IP_VERSION(13, 0, 10): 118 err = psp_init_sos_microcode(psp, chip_name); 119 if (err) 120 return err; 121 /* It's not necessary to load ras ta on Guest side */ 122 err = psp_init_ta_microcode(psp, chip_name); 123 if (err) 124 return err; 125 break; 126 default: 127 BUG(); 128 } 129 130 return 0; 131 } 132 133 static bool psp_v13_0_is_sos_alive(struct psp_context *psp) 134 { 135 struct amdgpu_device *adev = psp->adev; 136 uint32_t sol_reg; 137 138 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); 139 140 return sol_reg != 0x0; 141 } 142 143 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp) 144 { 145 struct amdgpu_device *adev = psp->adev; 146 147 int ret; 148 int retry_loop; 149 150 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 151 /* Wait for bootloader to signify that is 152 ready having bit 31 of C2PMSG_35 set to 1 */ 153 ret = psp_wait_for(psp, 154 SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 155 0x80000000, 156 0x80000000, 157 false); 158 159 if (ret == 0) 160 return 0; 161 } 162 163 return ret; 164 } 165 166 static int psp_v13_0_bootloader_load_component(struct psp_context *psp, 167 struct psp_bin_desc *bin_desc, 168 enum psp_bootloader_cmd bl_cmd) 169 { 170 int ret; 171 uint32_t psp_gfxdrv_command_reg = 0; 172 struct amdgpu_device *adev = psp->adev; 173 174 /* Check tOS sign of life register to confirm sys driver and sOS 175 * are already been loaded. 176 */ 177 if (psp_v13_0_is_sos_alive(psp)) 178 return 0; 179 180 ret = psp_v13_0_wait_for_bootloader(psp); 181 if (ret) 182 return ret; 183 184 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 185 186 /* Copy PSP KDB binary to memory */ 187 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes); 188 189 /* Provide the PSP KDB to bootloader */ 190 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 191 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 192 psp_gfxdrv_command_reg = bl_cmd; 193 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 194 psp_gfxdrv_command_reg); 195 196 ret = psp_v13_0_wait_for_bootloader(psp); 197 198 return ret; 199 } 200 201 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp) 202 { 203 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE); 204 } 205 206 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp) 207 { 208 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE); 209 } 210 211 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp) 212 { 213 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV); 214 } 215 216 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp) 217 { 218 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV); 219 } 220 221 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp) 222 { 223 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV); 224 } 225 226 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp) 227 { 228 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV); 229 } 230 231 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp) 232 { 233 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV); 234 } 235 236 237 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp) 238 { 239 int ret; 240 unsigned int psp_gfxdrv_command_reg = 0; 241 struct amdgpu_device *adev = psp->adev; 242 243 /* Check sOS sign of life register to confirm sys driver and sOS 244 * are already been loaded. 245 */ 246 if (psp_v13_0_is_sos_alive(psp)) 247 return 0; 248 249 ret = psp_v13_0_wait_for_bootloader(psp); 250 if (ret) 251 return ret; 252 253 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 254 255 /* Copy Secure OS binary to PSP memory */ 256 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes); 257 258 /* Provide the PSP secure OS to bootloader */ 259 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 260 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 261 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 262 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 263 psp_gfxdrv_command_reg); 264 265 /* there might be handshake issue with hardware which needs delay */ 266 mdelay(20); 267 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81), 268 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 269 0, true); 270 271 return ret; 272 } 273 274 static int psp_v13_0_ring_init(struct psp_context *psp, 275 enum psp_ring_type ring_type) 276 { 277 int ret = 0; 278 struct psp_ring *ring; 279 struct amdgpu_device *adev = psp->adev; 280 281 ring = &psp->km_ring; 282 283 ring->ring_type = ring_type; 284 285 /* allocate 4k Page of Local Frame Buffer memory for ring */ 286 ring->ring_size = 0x1000; 287 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 288 AMDGPU_GEM_DOMAIN_VRAM, 289 &adev->firmware.rbuf, 290 &ring->ring_mem_mc_addr, 291 (void **)&ring->ring_mem); 292 if (ret) { 293 ring->ring_size = 0; 294 return ret; 295 } 296 297 return 0; 298 } 299 300 static int psp_v13_0_ring_stop(struct psp_context *psp, 301 enum psp_ring_type ring_type) 302 { 303 int ret = 0; 304 struct amdgpu_device *adev = psp->adev; 305 306 if (amdgpu_sriov_vf(adev)) { 307 /* Write the ring destroy command*/ 308 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 309 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 310 /* there might be handshake issue with hardware which needs delay */ 311 mdelay(20); 312 /* Wait for response flag (bit 31) */ 313 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 314 0x80000000, 0x80000000, false); 315 } else { 316 /* Write the ring destroy command*/ 317 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 318 GFX_CTRL_CMD_ID_DESTROY_RINGS); 319 /* there might be handshake issue with hardware which needs delay */ 320 mdelay(20); 321 /* Wait for response flag (bit 31) */ 322 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 323 0x80000000, 0x80000000, false); 324 } 325 326 return ret; 327 } 328 329 static int psp_v13_0_ring_create(struct psp_context *psp, 330 enum psp_ring_type ring_type) 331 { 332 int ret = 0; 333 unsigned int psp_ring_reg = 0; 334 struct psp_ring *ring = &psp->km_ring; 335 struct amdgpu_device *adev = psp->adev; 336 337 if (amdgpu_sriov_vf(adev)) { 338 ret = psp_v13_0_ring_stop(psp, ring_type); 339 if (ret) { 340 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n"); 341 return ret; 342 } 343 344 /* Write low address of the ring to C2PMSG_102 */ 345 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 346 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 347 /* Write high address of the ring to C2PMSG_103 */ 348 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 349 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 350 351 /* Write the ring initialization command to C2PMSG_101 */ 352 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 353 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 354 355 /* there might be handshake issue with hardware which needs delay */ 356 mdelay(20); 357 358 /* Wait for response flag (bit 31) in C2PMSG_101 */ 359 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101), 360 0x80000000, 0x8000FFFF, false); 361 362 } else { 363 /* Wait for sOS ready for ring creation */ 364 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 365 0x80000000, 0x80000000, false); 366 if (ret) { 367 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n"); 368 return ret; 369 } 370 371 /* Write low address of the ring to C2PMSG_69 */ 372 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 373 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg); 374 /* Write high address of the ring to C2PMSG_70 */ 375 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 376 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg); 377 /* Write size of ring to C2PMSG_71 */ 378 psp_ring_reg = ring->ring_size; 379 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg); 380 /* Write the ring initialization command to C2PMSG_64 */ 381 psp_ring_reg = ring_type; 382 psp_ring_reg = psp_ring_reg << 16; 383 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg); 384 385 /* there might be handshake issue with hardware which needs delay */ 386 mdelay(20); 387 388 /* Wait for response flag (bit 31) in C2PMSG_64 */ 389 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64), 390 0x80000000, 0x8000FFFF, false); 391 } 392 393 return ret; 394 } 395 396 static int psp_v13_0_ring_destroy(struct psp_context *psp, 397 enum psp_ring_type ring_type) 398 { 399 int ret = 0; 400 struct psp_ring *ring = &psp->km_ring; 401 struct amdgpu_device *adev = psp->adev; 402 403 ret = psp_v13_0_ring_stop(psp, ring_type); 404 if (ret) 405 DRM_ERROR("Fail to stop psp ring\n"); 406 407 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 408 &ring->ring_mem_mc_addr, 409 (void **)&ring->ring_mem); 410 411 return ret; 412 } 413 414 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp) 415 { 416 uint32_t data; 417 struct amdgpu_device *adev = psp->adev; 418 419 if (amdgpu_sriov_vf(adev)) 420 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102); 421 else 422 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); 423 424 return data; 425 } 426 427 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 428 { 429 struct amdgpu_device *adev = psp->adev; 430 431 if (amdgpu_sriov_vf(adev)) { 432 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value); 433 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 434 GFX_CTRL_CMD_ID_CONSUME_CMD); 435 } else 436 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value); 437 } 438 439 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg) 440 { 441 int ret; 442 int i; 443 uint32_t data_32; 444 int max_wait; 445 struct amdgpu_device *adev = psp->adev; 446 447 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 448 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32); 449 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg); 450 451 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 452 for (i = 0; i < max_wait; i++) { 453 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 454 0x80000000, 0x80000000, false); 455 if (ret == 0) 456 break; 457 } 458 if (i < max_wait) 459 ret = 0; 460 else 461 ret = -ETIME; 462 463 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n", 464 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 465 (ret == 0) ? "succeed" : "failed", 466 i, adev->usec_timeout/1000); 467 return ret; 468 } 469 470 471 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops) 472 { 473 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 474 uint32_t *pcache = (uint32_t *)ctx->sys_cache; 475 struct amdgpu_device *adev = psp->adev; 476 uint32_t p2c_header[4]; 477 uint32_t sz; 478 void *buf; 479 int ret, idx; 480 481 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 482 dev_dbg(adev->dev, "Memory training is not supported.\n"); 483 return 0; 484 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 485 dev_err(adev->dev, "Memory training initialization failure.\n"); 486 return -EINVAL; 487 } 488 489 if (psp_v13_0_is_sos_alive(psp)) { 490 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n"); 491 return 0; 492 } 493 494 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 495 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 496 pcache[0], pcache[1], pcache[2], pcache[3], 497 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 498 499 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 500 dev_dbg(adev->dev, "Short training depends on restore.\n"); 501 ops |= PSP_MEM_TRAIN_RESTORE; 502 } 503 504 if ((ops & PSP_MEM_TRAIN_RESTORE) && 505 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 506 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n"); 507 ops |= PSP_MEM_TRAIN_SAVE; 508 } 509 510 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 511 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 512 pcache[3] == p2c_header[3])) { 513 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 514 ops |= PSP_MEM_TRAIN_SAVE; 515 } 516 517 if ((ops & PSP_MEM_TRAIN_SAVE) && 518 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 519 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n"); 520 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 521 } 522 523 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 524 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 525 ops |= PSP_MEM_TRAIN_SAVE; 526 } 527 528 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops); 529 530 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 531 /* 532 * Long training will encroach a certain amount on the bottom of VRAM; 533 * save the content from the bottom of VRAM to system memory 534 * before training, and restore it after training to avoid 535 * VRAM corruption. 536 */ 537 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 538 539 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 540 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 541 adev->gmc.visible_vram_size, 542 adev->mman.aper_base_kaddr); 543 return -EINVAL; 544 } 545 546 buf = vmalloc(sz); 547 if (!buf) { 548 dev_err(adev->dev, "failed to allocate system memory.\n"); 549 return -ENOMEM; 550 } 551 552 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 553 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 554 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 555 if (ret) { 556 DRM_ERROR("Send long training msg failed.\n"); 557 vfree(buf); 558 drm_dev_exit(idx); 559 return ret; 560 } 561 562 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 563 adev->hdp.funcs->flush_hdp(adev, NULL); 564 vfree(buf); 565 drm_dev_exit(idx); 566 } else { 567 vfree(buf); 568 return -ENODEV; 569 } 570 } 571 572 if (ops & PSP_MEM_TRAIN_SAVE) { 573 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 574 } 575 576 if (ops & PSP_MEM_TRAIN_RESTORE) { 577 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 578 } 579 580 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 581 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 582 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 583 if (ret) { 584 dev_err(adev->dev, "send training msg failed.\n"); 585 return ret; 586 } 587 } 588 ctx->training_cnt++; 589 return 0; 590 } 591 592 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr) 593 { 594 struct amdgpu_device *adev = psp->adev; 595 uint32_t reg_status; 596 int ret, i = 0; 597 598 /* 599 * LFB address which is aligned to 1MB address and has to be 600 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P 601 * register 602 */ 603 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20)); 604 605 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 606 0x80000000, 0x80000000, false); 607 if (ret) 608 return ret; 609 610 /* Fireup interrupt so PSP can pick up the address */ 611 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16)); 612 613 /* FW load takes very long time */ 614 do { 615 drm_msleep(1000); 616 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35); 617 618 if (reg_status & 0x80000000) 619 goto done; 620 621 } while (++i < USBC_PD_POLLING_LIMIT_S); 622 623 return -ETIME; 624 done: 625 626 if ((reg_status & 0xFFFF) != 0) { 627 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n", 628 reg_status & 0xFFFF); 629 return -EIO; 630 } 631 632 return 0; 633 } 634 635 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 636 { 637 struct amdgpu_device *adev = psp->adev; 638 int ret; 639 640 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 641 642 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35), 643 0x80000000, 0x80000000, false); 644 if (!ret) 645 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36); 646 647 return ret; 648 } 649 650 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd) 651 { 652 uint32_t reg_status = 0, reg_val = 0; 653 struct amdgpu_device *adev = psp->adev; 654 int ret; 655 656 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */ 657 reg_val |= (cmd << 16); 658 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val); 659 660 /* Ring the doorbell */ 661 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1); 662 663 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE) 664 return 0; 665 666 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 667 MBOX_READY_FLAG, MBOX_READY_MASK, false); 668 if (ret) { 669 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret); 670 return ret; 671 } 672 673 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 674 if ((reg_status & 0xFFFF) != 0) { 675 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n", 676 cmd, reg_status & 0xFFFF); 677 return -EIO; 678 } 679 680 return 0; 681 } 682 683 static int psp_v13_0_update_spirom(struct psp_context *psp, 684 uint64_t fw_pri_mc_addr) 685 { 686 struct amdgpu_device *adev = psp->adev; 687 int ret; 688 689 /* Confirm PSP is ready to start */ 690 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115), 691 MBOX_READY_FLAG, MBOX_READY_MASK, false); 692 if (ret) { 693 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret); 694 return ret; 695 } 696 697 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr)); 698 699 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO); 700 if (ret) 701 return ret; 702 703 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr)); 704 705 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI); 706 if (ret) 707 return ret; 708 709 psp->vbflash_done = true; 710 711 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE); 712 if (ret) 713 return ret; 714 715 return 0; 716 } 717 718 static int psp_v13_0_vbflash_status(struct psp_context *psp) 719 { 720 struct amdgpu_device *adev = psp->adev; 721 722 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115); 723 } 724 725 static const struct psp_funcs psp_v13_0_funcs = { 726 .init_microcode = psp_v13_0_init_microcode, 727 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb, 728 .bootloader_load_spl = psp_v13_0_bootloader_load_spl, 729 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv, 730 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv, 731 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv, 732 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv, 733 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv, 734 .bootloader_load_sos = psp_v13_0_bootloader_load_sos, 735 .ring_init = psp_v13_0_ring_init, 736 .ring_create = psp_v13_0_ring_create, 737 .ring_stop = psp_v13_0_ring_stop, 738 .ring_destroy = psp_v13_0_ring_destroy, 739 .ring_get_wptr = psp_v13_0_ring_get_wptr, 740 .ring_set_wptr = psp_v13_0_ring_set_wptr, 741 .mem_training = psp_v13_0_memory_training, 742 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw, 743 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw, 744 .update_spirom = psp_v13_0_update_spirom, 745 .vbflash_stat = psp_v13_0_vbflash_status 746 }; 747 748 void psp_v13_0_set_psp_funcs(struct psp_context *psp) 749 { 750 psp->funcs = &psp_v13_0_funcs; 751 } 752