1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 74 }; 75 76 static const struct amdgpu_video_codecs nv_video_codecs_encode = 77 { 78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 79 .codec_array = nv_video_codecs_encode_array, 80 }; 81 82 /* Navi1x */ 83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 92 }; 93 94 static const struct amdgpu_video_codecs nv_video_codecs_decode = 95 { 96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 97 .codec_array = nv_video_codecs_decode_array, 98 }; 99 100 /* Sienna Cichlid */ 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 102 { 103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 104 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 111 }; 112 113 static const struct amdgpu_video_codecs sc_video_codecs_decode = 114 { 115 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 116 .codec_array = sc_video_codecs_decode_array, 117 }; 118 119 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 120 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 121 { 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 124 }; 125 126 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = 127 { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4096, 3)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4096, 5)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4096, 4)}, 132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136 }; 137 138 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 139 { 140 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 141 .codec_array = sriov_sc_video_codecs_encode_array, 142 }; 143 144 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = 145 { 146 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), 147 .codec_array = sriov_sc_video_codecs_decode_array, 148 }; 149 150 /* Beige Goby*/ 151 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 153 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 154 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 155 }; 156 157 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 158 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 159 .codec_array = bg_video_codecs_decode_array, 160 }; 161 162 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 163 .codec_count = 0, 164 .codec_array = NULL, 165 }; 166 167 /* Yellow Carp*/ 168 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 169 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)}, 170 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 171 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 172 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 173 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 174 }; 175 176 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 177 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 178 .codec_array = yc_video_codecs_decode_array, 179 }; 180 181 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 182 const struct amdgpu_video_codecs **codecs) 183 { 184 switch (adev->ip_versions[UVD_HWIP][0]) { 185 case IP_VERSION(3, 0, 0): 186 case IP_VERSION(3, 0, 64): 187 case IP_VERSION(3, 0, 192): 188 if (amdgpu_sriov_vf(adev)) { 189 if (encode) 190 *codecs = &sriov_sc_video_codecs_encode; 191 else 192 *codecs = &sriov_sc_video_codecs_decode; 193 } else { 194 if (encode) 195 *codecs = &nv_video_codecs_encode; 196 else 197 *codecs = &sc_video_codecs_decode; 198 } 199 return 0; 200 case IP_VERSION(3, 0, 16): 201 case IP_VERSION(3, 0, 2): 202 if (encode) 203 *codecs = &nv_video_codecs_encode; 204 else 205 *codecs = &sc_video_codecs_decode; 206 return 0; 207 case IP_VERSION(3, 1, 1): 208 case IP_VERSION(3, 1, 2): 209 if (encode) 210 *codecs = &nv_video_codecs_encode; 211 else 212 *codecs = &yc_video_codecs_decode; 213 return 0; 214 case IP_VERSION(3, 0, 33): 215 if (encode) 216 *codecs = &bg_video_codecs_encode; 217 else 218 *codecs = &bg_video_codecs_decode; 219 return 0; 220 case IP_VERSION(2, 0, 0): 221 case IP_VERSION(2, 0, 2): 222 if (encode) 223 *codecs = &nv_video_codecs_encode; 224 else 225 *codecs = &nv_video_codecs_decode; 226 return 0; 227 default: 228 return -EINVAL; 229 } 230 } 231 232 /* 233 * Indirect registers accessor 234 */ 235 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 236 { 237 unsigned long address, data; 238 address = adev->nbio.funcs->get_pcie_index_offset(adev); 239 data = adev->nbio.funcs->get_pcie_data_offset(adev); 240 241 return amdgpu_device_indirect_rreg(adev, address, data, reg); 242 } 243 244 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 245 { 246 unsigned long address, data; 247 248 address = adev->nbio.funcs->get_pcie_index_offset(adev); 249 data = adev->nbio.funcs->get_pcie_data_offset(adev); 250 251 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 252 } 253 254 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 255 { 256 unsigned long address, data; 257 address = adev->nbio.funcs->get_pcie_index_offset(adev); 258 data = adev->nbio.funcs->get_pcie_data_offset(adev); 259 260 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 261 } 262 263 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 264 { 265 unsigned long address, data; 266 267 address = adev->nbio.funcs->get_pcie_index_offset(adev); 268 data = adev->nbio.funcs->get_pcie_data_offset(adev); 269 270 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 271 } 272 273 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 274 { 275 unsigned long flags, address, data; 276 u32 r; 277 278 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 279 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 280 281 spin_lock_irqsave(&adev->didt_idx_lock, flags); 282 WREG32(address, (reg)); 283 r = RREG32(data); 284 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 285 return r; 286 } 287 288 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 289 { 290 unsigned long flags, address, data; 291 292 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 293 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 294 295 spin_lock_irqsave(&adev->didt_idx_lock, flags); 296 WREG32(address, (reg)); 297 WREG32(data, (v)); 298 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 299 } 300 301 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 302 { 303 return adev->nbio.funcs->get_memsize(adev); 304 } 305 306 static u32 nv_get_xclk(struct amdgpu_device *adev) 307 { 308 return adev->clock.spll.reference_freq; 309 } 310 311 312 void nv_grbm_select(struct amdgpu_device *adev, 313 u32 me, u32 pipe, u32 queue, u32 vmid) 314 { 315 u32 grbm_gfx_cntl = 0; 316 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 317 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 318 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 319 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 320 321 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 322 } 323 324 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 325 { 326 /* todo */ 327 } 328 329 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 330 { 331 /* todo */ 332 return false; 333 } 334 335 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 336 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 337 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 338 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 339 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 340 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 341 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 342 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 343 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 344 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 345 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 346 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 347 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 348 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 349 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 350 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 351 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 352 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 353 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 354 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 355 }; 356 357 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 358 u32 sh_num, u32 reg_offset) 359 { 360 uint32_t val; 361 362 mutex_lock(&adev->grbm_idx_mutex); 363 if (se_num != 0xffffffff || sh_num != 0xffffffff) 364 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 365 366 val = RREG32(reg_offset); 367 368 if (se_num != 0xffffffff || sh_num != 0xffffffff) 369 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 370 mutex_unlock(&adev->grbm_idx_mutex); 371 return val; 372 } 373 374 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 375 bool indexed, u32 se_num, 376 u32 sh_num, u32 reg_offset) 377 { 378 if (indexed) { 379 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 380 } else { 381 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 382 return adev->gfx.config.gb_addr_config; 383 return RREG32(reg_offset); 384 } 385 } 386 387 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 388 u32 sh_num, u32 reg_offset, u32 *value) 389 { 390 uint32_t i; 391 struct soc15_allowed_register_entry *en; 392 393 *value = 0; 394 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 395 en = &nv_allowed_read_registers[i]; 396 if (!adev->reg_offset[en->hwip][en->inst]) 397 continue; 398 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] 399 + en->reg_offset)) 400 continue; 401 402 *value = nv_get_register_value(adev, 403 nv_allowed_read_registers[i].grbm_indexed, 404 se_num, sh_num, reg_offset); 405 return 0; 406 } 407 return -EINVAL; 408 } 409 410 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 411 { 412 u32 i; 413 int ret = 0; 414 415 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 416 417 /* disable BM */ 418 pci_clear_master(adev->pdev); 419 420 amdgpu_device_cache_pci_state(adev->pdev); 421 422 ret = amdgpu_dpm_mode2_reset(adev); 423 if (ret) 424 dev_err(adev->dev, "GPU mode2 reset failed\n"); 425 426 amdgpu_device_load_pci_state(adev->pdev); 427 428 /* wait for asic to come out of reset */ 429 for (i = 0; i < adev->usec_timeout; i++) { 430 u32 memsize = adev->nbio.funcs->get_memsize(adev); 431 432 if (memsize != 0xffffffff) 433 break; 434 udelay(1); 435 } 436 437 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 438 439 return ret; 440 } 441 442 static enum amd_reset_method 443 nv_asic_reset_method(struct amdgpu_device *adev) 444 { 445 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 446 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 447 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 448 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 449 return amdgpu_reset_method; 450 451 if (amdgpu_reset_method != -1) 452 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 453 amdgpu_reset_method); 454 455 switch (adev->ip_versions[MP1_HWIP][0]) { 456 case IP_VERSION(11, 5, 0): 457 case IP_VERSION(13, 0, 1): 458 case IP_VERSION(13, 0, 3): 459 case IP_VERSION(13, 0, 5): 460 case IP_VERSION(13, 0, 8): 461 return AMD_RESET_METHOD_MODE2; 462 case IP_VERSION(11, 0, 7): 463 case IP_VERSION(11, 0, 11): 464 case IP_VERSION(11, 0, 12): 465 case IP_VERSION(11, 0, 13): 466 return AMD_RESET_METHOD_MODE1; 467 default: 468 if (amdgpu_dpm_is_baco_supported(adev)) 469 return AMD_RESET_METHOD_BACO; 470 else 471 return AMD_RESET_METHOD_MODE1; 472 } 473 } 474 475 static int nv_asic_reset(struct amdgpu_device *adev) 476 { 477 int ret = 0; 478 479 switch (nv_asic_reset_method(adev)) { 480 case AMD_RESET_METHOD_PCI: 481 dev_info(adev->dev, "PCI reset\n"); 482 ret = amdgpu_device_pci_reset(adev); 483 break; 484 case AMD_RESET_METHOD_BACO: 485 dev_info(adev->dev, "BACO reset\n"); 486 ret = amdgpu_dpm_baco_reset(adev); 487 break; 488 case AMD_RESET_METHOD_MODE2: 489 dev_info(adev->dev, "MODE2 reset\n"); 490 ret = nv_asic_mode2_reset(adev); 491 break; 492 default: 493 dev_info(adev->dev, "MODE1 reset\n"); 494 ret = amdgpu_device_mode1_reset(adev); 495 break; 496 } 497 498 return ret; 499 } 500 501 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 502 { 503 /* todo */ 504 return 0; 505 } 506 507 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 508 { 509 /* todo */ 510 return 0; 511 } 512 513 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 514 { 515 if (pci_is_root_bus(adev->pdev->bus)) 516 return; 517 518 if (amdgpu_pcie_gen2 == 0) 519 return; 520 521 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 522 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 523 return; 524 525 /* todo */ 526 } 527 528 static void nv_program_aspm(struct amdgpu_device *adev) 529 { 530 if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_aspm_support_quirk()) 531 return; 532 533 if (!(adev->flags & AMD_IS_APU) && 534 (adev->nbio.funcs->program_aspm)) 535 adev->nbio.funcs->program_aspm(adev); 536 537 } 538 539 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 540 bool enable) 541 { 542 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 543 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 544 } 545 546 const struct amdgpu_ip_block_version nv_common_ip_block = 547 { 548 .type = AMD_IP_BLOCK_TYPE_COMMON, 549 .major = 1, 550 .minor = 0, 551 .rev = 0, 552 .funcs = &nv_common_ip_funcs, 553 }; 554 555 void nv_set_virt_ops(struct amdgpu_device *adev) 556 { 557 adev->virt.ops = &xgpu_nv_virt_ops; 558 } 559 560 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 561 { 562 return adev->nbio.funcs->get_rev_id(adev); 563 } 564 565 static bool nv_need_full_reset(struct amdgpu_device *adev) 566 { 567 return true; 568 } 569 570 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 571 { 572 u32 sol_reg; 573 574 if (adev->flags & AMD_IS_APU) 575 return false; 576 577 /* Check sOS sign of life register to confirm sys driver and sOS 578 * are already been loaded. 579 */ 580 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 581 if (sol_reg) 582 return true; 583 584 return false; 585 } 586 587 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 588 { 589 590 /* TODO 591 * dummy implement for pcie_replay_count sysfs interface 592 * */ 593 594 return 0; 595 } 596 597 static void nv_init_doorbell_index(struct amdgpu_device *adev) 598 { 599 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 600 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 601 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 602 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 603 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 604 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 605 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 606 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 607 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 608 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 609 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 610 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 611 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 612 adev->doorbell_index.gfx_userqueue_start = 613 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START; 614 adev->doorbell_index.gfx_userqueue_end = 615 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END; 616 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0; 617 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1; 618 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 619 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 620 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 621 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 622 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 623 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 624 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 625 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 626 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 627 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 628 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 629 630 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 631 adev->doorbell_index.sdma_doorbell_range = 20; 632 } 633 634 static void nv_pre_asic_init(struct amdgpu_device *adev) 635 { 636 } 637 638 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 639 bool enter) 640 { 641 if (enter) 642 amdgpu_gfx_rlc_enter_safe_mode(adev); 643 else 644 amdgpu_gfx_rlc_exit_safe_mode(adev); 645 646 if (adev->gfx.funcs->update_perfmon_mgcg) 647 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 648 649 if (!(adev->flags & AMD_IS_APU) && 650 (adev->nbio.funcs->enable_aspm) && 651 amdgpu_device_should_use_aspm(adev)) 652 adev->nbio.funcs->enable_aspm(adev, !enter); 653 654 return 0; 655 } 656 657 static const struct amdgpu_asic_funcs nv_asic_funcs = 658 { 659 .read_disabled_bios = &nv_read_disabled_bios, 660 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom, 661 .read_register = &nv_read_register, 662 .reset = &nv_asic_reset, 663 .reset_method = &nv_asic_reset_method, 664 .set_vga_state = &nv_vga_set_state, 665 .get_xclk = &nv_get_xclk, 666 .set_uvd_clocks = &nv_set_uvd_clocks, 667 .set_vce_clocks = &nv_set_vce_clocks, 668 .get_config_memsize = &nv_get_config_memsize, 669 .init_doorbell_index = &nv_init_doorbell_index, 670 .need_full_reset = &nv_need_full_reset, 671 .need_reset_on_init = &nv_need_reset_on_init, 672 .get_pcie_replay_count = &nv_get_pcie_replay_count, 673 .supports_baco = &amdgpu_dpm_is_baco_supported, 674 .pre_asic_init = &nv_pre_asic_init, 675 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 676 .query_video_codecs = &nv_query_video_codecs, 677 }; 678 679 static int nv_common_early_init(void *handle) 680 { 681 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 683 684 if (!amdgpu_sriov_vf(adev)) { 685 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 686 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 687 } 688 adev->smc_rreg = NULL; 689 adev->smc_wreg = NULL; 690 adev->pcie_rreg = &nv_pcie_rreg; 691 adev->pcie_wreg = &nv_pcie_wreg; 692 adev->pcie_rreg64 = &nv_pcie_rreg64; 693 adev->pcie_wreg64 = &nv_pcie_wreg64; 694 adev->pciep_rreg = amdgpu_device_pcie_port_rreg; 695 adev->pciep_wreg = amdgpu_device_pcie_port_wreg; 696 697 /* TODO: will add them during VCN v2 implementation */ 698 adev->uvd_ctx_rreg = NULL; 699 adev->uvd_ctx_wreg = NULL; 700 701 adev->didt_rreg = &nv_didt_rreg; 702 adev->didt_wreg = &nv_didt_wreg; 703 704 adev->asic_funcs = &nv_asic_funcs; 705 706 adev->rev_id = nv_get_rev_id(adev); 707 adev->external_rev_id = 0xff; 708 /* TODO: split the GC and PG flags based on the relevant IP version for which 709 * they are relevant. 710 */ 711 switch (adev->ip_versions[GC_HWIP][0]) { 712 case IP_VERSION(10, 1, 10): 713 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 714 AMD_CG_SUPPORT_GFX_CGCG | 715 AMD_CG_SUPPORT_IH_CG | 716 AMD_CG_SUPPORT_HDP_MGCG | 717 AMD_CG_SUPPORT_HDP_LS | 718 AMD_CG_SUPPORT_SDMA_MGCG | 719 AMD_CG_SUPPORT_SDMA_LS | 720 AMD_CG_SUPPORT_MC_MGCG | 721 AMD_CG_SUPPORT_MC_LS | 722 AMD_CG_SUPPORT_ATHUB_MGCG | 723 AMD_CG_SUPPORT_ATHUB_LS | 724 AMD_CG_SUPPORT_VCN_MGCG | 725 AMD_CG_SUPPORT_JPEG_MGCG | 726 AMD_CG_SUPPORT_BIF_MGCG | 727 AMD_CG_SUPPORT_BIF_LS; 728 adev->pg_flags = AMD_PG_SUPPORT_VCN | 729 AMD_PG_SUPPORT_VCN_DPG | 730 AMD_PG_SUPPORT_JPEG | 731 AMD_PG_SUPPORT_ATHUB; 732 adev->external_rev_id = adev->rev_id + 0x1; 733 break; 734 case IP_VERSION(10, 1, 1): 735 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 736 AMD_CG_SUPPORT_GFX_CGCG | 737 AMD_CG_SUPPORT_IH_CG | 738 AMD_CG_SUPPORT_HDP_MGCG | 739 AMD_CG_SUPPORT_HDP_LS | 740 AMD_CG_SUPPORT_SDMA_MGCG | 741 AMD_CG_SUPPORT_SDMA_LS | 742 AMD_CG_SUPPORT_MC_MGCG | 743 AMD_CG_SUPPORT_MC_LS | 744 AMD_CG_SUPPORT_ATHUB_MGCG | 745 AMD_CG_SUPPORT_ATHUB_LS | 746 AMD_CG_SUPPORT_VCN_MGCG | 747 AMD_CG_SUPPORT_JPEG_MGCG | 748 AMD_CG_SUPPORT_BIF_MGCG | 749 AMD_CG_SUPPORT_BIF_LS; 750 adev->pg_flags = AMD_PG_SUPPORT_VCN | 751 AMD_PG_SUPPORT_JPEG | 752 AMD_PG_SUPPORT_VCN_DPG; 753 adev->external_rev_id = adev->rev_id + 20; 754 break; 755 case IP_VERSION(10, 1, 2): 756 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 757 AMD_CG_SUPPORT_GFX_MGLS | 758 AMD_CG_SUPPORT_GFX_CGCG | 759 AMD_CG_SUPPORT_GFX_CP_LS | 760 AMD_CG_SUPPORT_GFX_RLC_LS | 761 AMD_CG_SUPPORT_IH_CG | 762 AMD_CG_SUPPORT_HDP_MGCG | 763 AMD_CG_SUPPORT_HDP_LS | 764 AMD_CG_SUPPORT_SDMA_MGCG | 765 AMD_CG_SUPPORT_SDMA_LS | 766 AMD_CG_SUPPORT_MC_MGCG | 767 AMD_CG_SUPPORT_MC_LS | 768 AMD_CG_SUPPORT_ATHUB_MGCG | 769 AMD_CG_SUPPORT_ATHUB_LS | 770 AMD_CG_SUPPORT_VCN_MGCG | 771 AMD_CG_SUPPORT_JPEG_MGCG; 772 adev->pg_flags = AMD_PG_SUPPORT_VCN | 773 AMD_PG_SUPPORT_VCN_DPG | 774 AMD_PG_SUPPORT_JPEG | 775 AMD_PG_SUPPORT_ATHUB; 776 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 777 * as a consequence, the rev_id and external_rev_id are wrong. 778 * workaround it by hardcoding rev_id to 0 (default value). 779 */ 780 if (amdgpu_sriov_vf(adev)) 781 adev->rev_id = 0; 782 adev->external_rev_id = adev->rev_id + 0xa; 783 break; 784 case IP_VERSION(10, 3, 0): 785 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 786 AMD_CG_SUPPORT_GFX_CGCG | 787 AMD_CG_SUPPORT_GFX_CGLS | 788 AMD_CG_SUPPORT_GFX_3D_CGCG | 789 AMD_CG_SUPPORT_MC_MGCG | 790 AMD_CG_SUPPORT_VCN_MGCG | 791 AMD_CG_SUPPORT_JPEG_MGCG | 792 AMD_CG_SUPPORT_HDP_MGCG | 793 AMD_CG_SUPPORT_HDP_LS | 794 AMD_CG_SUPPORT_IH_CG | 795 AMD_CG_SUPPORT_MC_LS; 796 adev->pg_flags = AMD_PG_SUPPORT_VCN | 797 AMD_PG_SUPPORT_VCN_DPG | 798 AMD_PG_SUPPORT_JPEG | 799 AMD_PG_SUPPORT_ATHUB | 800 AMD_PG_SUPPORT_MMHUB; 801 if (amdgpu_sriov_vf(adev)) { 802 /* hypervisor control CG and PG enablement */ 803 adev->cg_flags = 0; 804 adev->pg_flags = 0; 805 } 806 adev->external_rev_id = adev->rev_id + 0x28; 807 break; 808 case IP_VERSION(10, 3, 2): 809 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 810 AMD_CG_SUPPORT_GFX_CGCG | 811 AMD_CG_SUPPORT_GFX_CGLS | 812 AMD_CG_SUPPORT_GFX_3D_CGCG | 813 AMD_CG_SUPPORT_VCN_MGCG | 814 AMD_CG_SUPPORT_JPEG_MGCG | 815 AMD_CG_SUPPORT_MC_MGCG | 816 AMD_CG_SUPPORT_MC_LS | 817 AMD_CG_SUPPORT_HDP_MGCG | 818 AMD_CG_SUPPORT_HDP_LS | 819 AMD_CG_SUPPORT_IH_CG; 820 adev->pg_flags = AMD_PG_SUPPORT_VCN | 821 AMD_PG_SUPPORT_VCN_DPG | 822 AMD_PG_SUPPORT_JPEG | 823 AMD_PG_SUPPORT_ATHUB | 824 AMD_PG_SUPPORT_MMHUB; 825 adev->external_rev_id = adev->rev_id + 0x32; 826 break; 827 case IP_VERSION(10, 3, 1): 828 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 829 AMD_CG_SUPPORT_GFX_MGLS | 830 AMD_CG_SUPPORT_GFX_CP_LS | 831 AMD_CG_SUPPORT_GFX_RLC_LS | 832 AMD_CG_SUPPORT_GFX_CGCG | 833 AMD_CG_SUPPORT_GFX_CGLS | 834 AMD_CG_SUPPORT_GFX_3D_CGCG | 835 AMD_CG_SUPPORT_GFX_3D_CGLS | 836 AMD_CG_SUPPORT_MC_MGCG | 837 AMD_CG_SUPPORT_MC_LS | 838 AMD_CG_SUPPORT_GFX_FGCG | 839 AMD_CG_SUPPORT_VCN_MGCG | 840 AMD_CG_SUPPORT_SDMA_MGCG | 841 AMD_CG_SUPPORT_SDMA_LS | 842 AMD_CG_SUPPORT_JPEG_MGCG; 843 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 844 AMD_PG_SUPPORT_VCN | 845 AMD_PG_SUPPORT_VCN_DPG | 846 AMD_PG_SUPPORT_JPEG; 847 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 848 adev->external_rev_id = adev->rev_id + 0x01; 849 break; 850 case IP_VERSION(10, 3, 4): 851 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 852 AMD_CG_SUPPORT_GFX_CGCG | 853 AMD_CG_SUPPORT_GFX_CGLS | 854 AMD_CG_SUPPORT_GFX_3D_CGCG | 855 AMD_CG_SUPPORT_VCN_MGCG | 856 AMD_CG_SUPPORT_JPEG_MGCG | 857 AMD_CG_SUPPORT_MC_MGCG | 858 AMD_CG_SUPPORT_MC_LS | 859 AMD_CG_SUPPORT_HDP_MGCG | 860 AMD_CG_SUPPORT_HDP_LS | 861 AMD_CG_SUPPORT_IH_CG; 862 adev->pg_flags = AMD_PG_SUPPORT_VCN | 863 AMD_PG_SUPPORT_VCN_DPG | 864 AMD_PG_SUPPORT_JPEG | 865 AMD_PG_SUPPORT_ATHUB | 866 AMD_PG_SUPPORT_MMHUB; 867 adev->external_rev_id = adev->rev_id + 0x3c; 868 break; 869 case IP_VERSION(10, 3, 5): 870 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 871 AMD_CG_SUPPORT_GFX_CGCG | 872 AMD_CG_SUPPORT_GFX_CGLS | 873 AMD_CG_SUPPORT_GFX_3D_CGCG | 874 AMD_CG_SUPPORT_MC_MGCG | 875 AMD_CG_SUPPORT_MC_LS | 876 AMD_CG_SUPPORT_HDP_MGCG | 877 AMD_CG_SUPPORT_HDP_LS | 878 AMD_CG_SUPPORT_IH_CG | 879 AMD_CG_SUPPORT_VCN_MGCG; 880 adev->pg_flags = AMD_PG_SUPPORT_VCN | 881 AMD_PG_SUPPORT_VCN_DPG | 882 AMD_PG_SUPPORT_ATHUB | 883 AMD_PG_SUPPORT_MMHUB; 884 adev->external_rev_id = adev->rev_id + 0x46; 885 break; 886 case IP_VERSION(10, 3, 3): 887 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 888 AMD_CG_SUPPORT_GFX_MGLS | 889 AMD_CG_SUPPORT_GFX_CGCG | 890 AMD_CG_SUPPORT_GFX_CGLS | 891 AMD_CG_SUPPORT_GFX_3D_CGCG | 892 AMD_CG_SUPPORT_GFX_3D_CGLS | 893 AMD_CG_SUPPORT_GFX_RLC_LS | 894 AMD_CG_SUPPORT_GFX_CP_LS | 895 AMD_CG_SUPPORT_GFX_FGCG | 896 AMD_CG_SUPPORT_MC_MGCG | 897 AMD_CG_SUPPORT_MC_LS | 898 AMD_CG_SUPPORT_SDMA_LS | 899 AMD_CG_SUPPORT_HDP_MGCG | 900 AMD_CG_SUPPORT_HDP_LS | 901 AMD_CG_SUPPORT_ATHUB_MGCG | 902 AMD_CG_SUPPORT_ATHUB_LS | 903 AMD_CG_SUPPORT_IH_CG | 904 AMD_CG_SUPPORT_VCN_MGCG | 905 AMD_CG_SUPPORT_JPEG_MGCG; 906 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 907 AMD_PG_SUPPORT_VCN | 908 AMD_PG_SUPPORT_VCN_DPG | 909 AMD_PG_SUPPORT_JPEG; 910 if (adev->pdev->device == 0x1681) 911 adev->external_rev_id = 0x20; 912 else 913 adev->external_rev_id = adev->rev_id + 0x01; 914 break; 915 case IP_VERSION(10, 1, 3): 916 case IP_VERSION(10, 1, 4): 917 adev->cg_flags = 0; 918 adev->pg_flags = 0; 919 adev->external_rev_id = adev->rev_id + 0x82; 920 break; 921 case IP_VERSION(10, 3, 6): 922 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 923 AMD_CG_SUPPORT_GFX_MGLS | 924 AMD_CG_SUPPORT_GFX_CGCG | 925 AMD_CG_SUPPORT_GFX_CGLS | 926 AMD_CG_SUPPORT_GFX_3D_CGCG | 927 AMD_CG_SUPPORT_GFX_3D_CGLS | 928 AMD_CG_SUPPORT_GFX_RLC_LS | 929 AMD_CG_SUPPORT_GFX_CP_LS | 930 AMD_CG_SUPPORT_GFX_FGCG | 931 AMD_CG_SUPPORT_MC_MGCG | 932 AMD_CG_SUPPORT_MC_LS | 933 AMD_CG_SUPPORT_SDMA_LS | 934 AMD_CG_SUPPORT_HDP_MGCG | 935 AMD_CG_SUPPORT_HDP_LS | 936 AMD_CG_SUPPORT_ATHUB_MGCG | 937 AMD_CG_SUPPORT_ATHUB_LS | 938 AMD_CG_SUPPORT_IH_CG | 939 AMD_CG_SUPPORT_VCN_MGCG | 940 AMD_CG_SUPPORT_JPEG_MGCG; 941 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 942 AMD_PG_SUPPORT_VCN | 943 AMD_PG_SUPPORT_VCN_DPG | 944 AMD_PG_SUPPORT_JPEG; 945 adev->external_rev_id = adev->rev_id + 0x01; 946 break; 947 case IP_VERSION(10, 3, 7): 948 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 949 AMD_CG_SUPPORT_GFX_MGLS | 950 AMD_CG_SUPPORT_GFX_CGCG | 951 AMD_CG_SUPPORT_GFX_CGLS | 952 AMD_CG_SUPPORT_GFX_3D_CGCG | 953 AMD_CG_SUPPORT_GFX_3D_CGLS | 954 AMD_CG_SUPPORT_GFX_RLC_LS | 955 AMD_CG_SUPPORT_GFX_CP_LS | 956 AMD_CG_SUPPORT_GFX_FGCG | 957 AMD_CG_SUPPORT_MC_MGCG | 958 AMD_CG_SUPPORT_MC_LS | 959 AMD_CG_SUPPORT_SDMA_LS | 960 AMD_CG_SUPPORT_HDP_MGCG | 961 AMD_CG_SUPPORT_HDP_LS | 962 AMD_CG_SUPPORT_ATHUB_MGCG | 963 AMD_CG_SUPPORT_ATHUB_LS | 964 AMD_CG_SUPPORT_IH_CG | 965 AMD_CG_SUPPORT_VCN_MGCG | 966 AMD_CG_SUPPORT_JPEG_MGCG; 967 adev->pg_flags = AMD_PG_SUPPORT_VCN | 968 AMD_PG_SUPPORT_VCN_DPG | 969 AMD_PG_SUPPORT_JPEG | 970 AMD_PG_SUPPORT_GFX_PG; 971 adev->external_rev_id = adev->rev_id + 0x01; 972 break; 973 default: 974 /* FIXME: not supported yet */ 975 return -EINVAL; 976 } 977 978 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 979 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 980 AMD_PG_SUPPORT_VCN_DPG | 981 AMD_PG_SUPPORT_JPEG); 982 983 if (amdgpu_sriov_vf(adev)) { 984 amdgpu_virt_init_setting(adev); 985 xgpu_nv_mailbox_set_irq_funcs(adev); 986 } 987 988 return 0; 989 } 990 991 static int nv_common_late_init(void *handle) 992 { 993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 994 995 if (amdgpu_sriov_vf(adev)) { 996 xgpu_nv_mailbox_get_irq(adev); 997 amdgpu_virt_update_sriov_video_codec(adev, 998 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 999 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); 1000 } 1001 1002 return 0; 1003 } 1004 1005 static int nv_common_sw_init(void *handle) 1006 { 1007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1008 1009 if (amdgpu_sriov_vf(adev)) 1010 xgpu_nv_mailbox_add_irq_id(adev); 1011 1012 return 0; 1013 } 1014 1015 static int nv_common_sw_fini(void *handle) 1016 { 1017 return 0; 1018 } 1019 1020 static int nv_common_hw_init(void *handle) 1021 { 1022 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1023 1024 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 1025 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 1026 1027 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1028 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1029 1030 /* enable pcie gen2/3 link */ 1031 nv_pcie_gen3_enable(adev); 1032 /* enable aspm */ 1033 nv_program_aspm(adev); 1034 /* setup nbio registers */ 1035 adev->nbio.funcs->init_registers(adev); 1036 /* remap HDP registers to a hole in mmio space, 1037 * for the purpose of expose those registers 1038 * to process space 1039 */ 1040 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) 1041 adev->nbio.funcs->remap_hdp_registers(adev); 1042 /* enable the doorbell aperture */ 1043 nv_enable_doorbell_aperture(adev, true); 1044 1045 return 0; 1046 } 1047 1048 static int nv_common_hw_fini(void *handle) 1049 { 1050 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1051 1052 /* disable the doorbell aperture */ 1053 nv_enable_doorbell_aperture(adev, false); 1054 1055 return 0; 1056 } 1057 1058 static int nv_common_suspend(void *handle) 1059 { 1060 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1061 1062 return nv_common_hw_fini(adev); 1063 } 1064 1065 static int nv_common_resume(void *handle) 1066 { 1067 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1068 1069 return nv_common_hw_init(adev); 1070 } 1071 1072 static bool nv_common_is_idle(void *handle) 1073 { 1074 return true; 1075 } 1076 1077 static int nv_common_wait_for_idle(void *handle) 1078 { 1079 return 0; 1080 } 1081 1082 static int nv_common_soft_reset(void *handle) 1083 { 1084 return 0; 1085 } 1086 1087 static int nv_common_set_clockgating_state(void *handle, 1088 enum amd_clockgating_state state) 1089 { 1090 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1091 1092 if (amdgpu_sriov_vf(adev)) 1093 return 0; 1094 1095 switch (adev->ip_versions[NBIO_HWIP][0]) { 1096 case IP_VERSION(2, 3, 0): 1097 case IP_VERSION(2, 3, 1): 1098 case IP_VERSION(2, 3, 2): 1099 case IP_VERSION(3, 3, 0): 1100 case IP_VERSION(3, 3, 1): 1101 case IP_VERSION(3, 3, 2): 1102 case IP_VERSION(3, 3, 3): 1103 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1104 state == AMD_CG_STATE_GATE); 1105 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1106 state == AMD_CG_STATE_GATE); 1107 adev->hdp.funcs->update_clock_gating(adev, 1108 state == AMD_CG_STATE_GATE); 1109 adev->smuio.funcs->update_rom_clock_gating(adev, 1110 state == AMD_CG_STATE_GATE); 1111 break; 1112 default: 1113 break; 1114 } 1115 return 0; 1116 } 1117 1118 static int nv_common_set_powergating_state(void *handle, 1119 enum amd_powergating_state state) 1120 { 1121 /* TODO */ 1122 return 0; 1123 } 1124 1125 static void nv_common_get_clockgating_state(void *handle, u64 *flags) 1126 { 1127 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1128 1129 if (amdgpu_sriov_vf(adev)) 1130 *flags = 0; 1131 1132 adev->nbio.funcs->get_clockgating_state(adev, flags); 1133 1134 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1135 1136 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1137 1138 return; 1139 } 1140 1141 static const struct amd_ip_funcs nv_common_ip_funcs = { 1142 .name = "nv_common", 1143 .early_init = nv_common_early_init, 1144 .late_init = nv_common_late_init, 1145 .sw_init = nv_common_sw_init, 1146 .sw_fini = nv_common_sw_fini, 1147 .hw_init = nv_common_hw_init, 1148 .hw_fini = nv_common_hw_fini, 1149 .suspend = nv_common_suspend, 1150 .resume = nv_common_resume, 1151 .is_idle = nv_common_is_idle, 1152 .wait_for_idle = nv_common_wait_for_idle, 1153 .soft_reset = nv_common_soft_reset, 1154 .set_clockgating_state = nv_common_set_clockgating_state, 1155 .set_powergating_state = nv_common_set_powergating_state, 1156 .get_clockgating_state = nv_common_get_clockgating_state, 1157 }; 1158