1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/firmware.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <linux/pci.h> 27 28 #include <drm/amdgpu_drm.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_atombios.h" 32 #include "amdgpu_ih.h" 33 #include "amdgpu_uvd.h" 34 #include "amdgpu_vce.h" 35 #include "amdgpu_ucode.h" 36 #include "amdgpu_psp.h" 37 #include "atom.h" 38 #include "amd_pcie.h" 39 40 #include "gc/gc_10_1_0_offset.h" 41 #include "gc/gc_10_1_0_sh_mask.h" 42 #include "mp/mp_11_0_offset.h" 43 44 #include "soc15.h" 45 #include "soc15_common.h" 46 #include "gmc_v10_0.h" 47 #include "gfxhub_v2_0.h" 48 #include "mmhub_v2_0.h" 49 #include "nbio_v2_3.h" 50 #include "nbio_v7_2.h" 51 #include "hdp_v5_0.h" 52 #include "nv.h" 53 #include "navi10_ih.h" 54 #include "gfx_v10_0.h" 55 #include "sdma_v5_0.h" 56 #include "sdma_v5_2.h" 57 #include "vcn_v2_0.h" 58 #include "jpeg_v2_0.h" 59 #include "vcn_v3_0.h" 60 #include "jpeg_v3_0.h" 61 #include "amdgpu_vkms.h" 62 #include "mes_v10_1.h" 63 #include "mxgpu_nv.h" 64 #include "smuio_v11_0.h" 65 #include "smuio_v11_0_6.h" 66 67 static const struct amd_ip_funcs nv_common_ip_funcs; 68 69 /* Navi */ 70 static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] = 71 { 72 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 74 }; 75 76 static const struct amdgpu_video_codecs nv_video_codecs_encode = 77 { 78 .codec_count = ARRAY_SIZE(nv_video_codecs_encode_array), 79 .codec_array = nv_video_codecs_encode_array, 80 }; 81 82 /* Navi1x */ 83 static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] = 84 { 85 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 86 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 87 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 88 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 89 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 90 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 91 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 92 }; 93 94 static const struct amdgpu_video_codecs nv_video_codecs_decode = 95 { 96 .codec_count = ARRAY_SIZE(nv_video_codecs_decode_array), 97 .codec_array = nv_video_codecs_decode_array, 98 }; 99 100 /* Sienna Cichlid */ 101 static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] = 102 { 103 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 104 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 107 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 108 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 109 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 110 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 111 }; 112 113 static const struct amdgpu_video_codecs sc_video_codecs_decode = 114 { 115 .codec_count = ARRAY_SIZE(sc_video_codecs_decode_array), 116 .codec_array = sc_video_codecs_decode_array, 117 }; 118 119 /* SRIOV Sienna Cichlid, not const since data is controlled by host */ 120 static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] = 121 { 122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)}, 123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)}, 124 }; 125 126 static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] = 127 { 128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)}, 129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)}, 130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)}, 132 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 133 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 134 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 135 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 136 }; 137 138 static struct amdgpu_video_codecs sriov_sc_video_codecs_encode = 139 { 140 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 141 .codec_array = sriov_sc_video_codecs_encode_array, 142 }; 143 144 static struct amdgpu_video_codecs sriov_sc_video_codecs_decode = 145 { 146 .codec_count = ARRAY_SIZE(sriov_sc_video_codecs_decode_array), 147 .codec_array = sriov_sc_video_codecs_decode_array, 148 }; 149 150 /* Beige Goby*/ 151 static const struct amdgpu_video_codec_info bg_video_codecs_decode_array[] = { 152 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 153 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 154 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 155 }; 156 157 static const struct amdgpu_video_codecs bg_video_codecs_decode = { 158 .codec_count = ARRAY_SIZE(bg_video_codecs_decode_array), 159 .codec_array = bg_video_codecs_decode_array, 160 }; 161 162 static const struct amdgpu_video_codecs bg_video_codecs_encode = { 163 .codec_count = 0, 164 .codec_array = NULL, 165 }; 166 167 /* Yellow Carp*/ 168 static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = { 169 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)}, 170 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)}, 171 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)}, 172 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)}, 173 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)}, 174 }; 175 176 static const struct amdgpu_video_codecs yc_video_codecs_decode = { 177 .codec_count = ARRAY_SIZE(yc_video_codecs_decode_array), 178 .codec_array = yc_video_codecs_decode_array, 179 }; 180 181 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 182 const struct amdgpu_video_codecs **codecs) 183 { 184 switch (adev->asic_type) { 185 case CHIP_SIENNA_CICHLID: 186 if (amdgpu_sriov_vf(adev)) { 187 if (encode) 188 *codecs = &sriov_sc_video_codecs_encode; 189 else 190 *codecs = &sriov_sc_video_codecs_decode; 191 } else { 192 if (encode) 193 *codecs = &nv_video_codecs_encode; 194 else 195 *codecs = &sc_video_codecs_decode; 196 } 197 return 0; 198 case CHIP_NAVY_FLOUNDER: 199 case CHIP_DIMGREY_CAVEFISH: 200 case CHIP_VANGOGH: 201 if (encode) 202 *codecs = &nv_video_codecs_encode; 203 else 204 *codecs = &sc_video_codecs_decode; 205 return 0; 206 case CHIP_YELLOW_CARP: 207 if (encode) 208 *codecs = &nv_video_codecs_encode; 209 else 210 *codecs = &yc_video_codecs_decode; 211 return 0; 212 case CHIP_BEIGE_GOBY: 213 if (encode) 214 *codecs = &bg_video_codecs_encode; 215 else 216 *codecs = &bg_video_codecs_decode; 217 return 0; 218 case CHIP_NAVI10: 219 case CHIP_NAVI14: 220 case CHIP_NAVI12: 221 if (encode) 222 *codecs = &nv_video_codecs_encode; 223 else 224 *codecs = &nv_video_codecs_decode; 225 return 0; 226 default: 227 return -EINVAL; 228 } 229 } 230 231 /* 232 * Indirect registers accessor 233 */ 234 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg) 235 { 236 unsigned long address, data; 237 address = adev->nbio.funcs->get_pcie_index_offset(adev); 238 data = adev->nbio.funcs->get_pcie_data_offset(adev); 239 240 return amdgpu_device_indirect_rreg(adev, address, data, reg); 241 } 242 243 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 244 { 245 unsigned long address, data; 246 247 address = adev->nbio.funcs->get_pcie_index_offset(adev); 248 data = adev->nbio.funcs->get_pcie_data_offset(adev); 249 250 amdgpu_device_indirect_wreg(adev, address, data, reg, v); 251 } 252 253 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg) 254 { 255 unsigned long address, data; 256 address = adev->nbio.funcs->get_pcie_index_offset(adev); 257 data = adev->nbio.funcs->get_pcie_data_offset(adev); 258 259 return amdgpu_device_indirect_rreg64(adev, address, data, reg); 260 } 261 262 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) 263 { 264 unsigned long flags, address, data; 265 u32 r; 266 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 267 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 268 269 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 270 WREG32(address, reg * 4); 271 (void)RREG32(address); 272 r = RREG32(data); 273 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 274 return r; 275 } 276 277 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v) 278 { 279 unsigned long address, data; 280 281 address = adev->nbio.funcs->get_pcie_index_offset(adev); 282 data = adev->nbio.funcs->get_pcie_data_offset(adev); 283 284 amdgpu_device_indirect_wreg64(adev, address, data, reg, v); 285 } 286 287 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 288 { 289 unsigned long flags, address, data; 290 291 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 292 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 293 294 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 295 WREG32(address, reg * 4); 296 (void)RREG32(address); 297 WREG32(data, v); 298 (void)RREG32(data); 299 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 300 } 301 302 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg) 303 { 304 unsigned long flags, address, data; 305 u32 r; 306 307 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 308 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 309 310 spin_lock_irqsave(&adev->didt_idx_lock, flags); 311 WREG32(address, (reg)); 312 r = RREG32(data); 313 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 314 return r; 315 } 316 317 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 318 { 319 unsigned long flags, address, data; 320 321 address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX); 322 data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA); 323 324 spin_lock_irqsave(&adev->didt_idx_lock, flags); 325 WREG32(address, (reg)); 326 WREG32(data, (v)); 327 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 328 } 329 330 static u32 nv_get_config_memsize(struct amdgpu_device *adev) 331 { 332 return adev->nbio.funcs->get_memsize(adev); 333 } 334 335 static u32 nv_get_xclk(struct amdgpu_device *adev) 336 { 337 return adev->clock.spll.reference_freq; 338 } 339 340 341 void nv_grbm_select(struct amdgpu_device *adev, 342 u32 me, u32 pipe, u32 queue, u32 vmid) 343 { 344 u32 grbm_gfx_cntl = 0; 345 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe); 346 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me); 347 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid); 348 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue); 349 350 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl); 351 } 352 353 static void nv_vga_set_state(struct amdgpu_device *adev, bool state) 354 { 355 /* todo */ 356 } 357 358 static bool nv_read_disabled_bios(struct amdgpu_device *adev) 359 { 360 /* todo */ 361 return false; 362 } 363 364 static bool nv_read_bios_from_rom(struct amdgpu_device *adev, 365 u8 *bios, u32 length_bytes) 366 { 367 u32 *dw_ptr; 368 u32 i, length_dw; 369 u32 rom_index_offset, rom_data_offset; 370 371 if (bios == NULL) 372 return false; 373 if (length_bytes == 0) 374 return false; 375 /* APU vbios image is part of sbios image */ 376 if (adev->flags & AMD_IS_APU) 377 return false; 378 379 dw_ptr = (u32 *)bios; 380 length_dw = roundup2(length_bytes, 4) / 4; 381 382 rom_index_offset = 383 adev->smuio.funcs->get_rom_index_offset(adev); 384 rom_data_offset = 385 adev->smuio.funcs->get_rom_data_offset(adev); 386 387 /* set rom index to 0 */ 388 WREG32(rom_index_offset, 0); 389 /* read out the rom data */ 390 for (i = 0; i < length_dw; i++) 391 dw_ptr[i] = RREG32(rom_data_offset); 392 393 return true; 394 } 395 396 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = { 397 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)}, 398 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)}, 399 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)}, 400 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)}, 401 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)}, 402 { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)}, 403 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)}, 404 { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)}, 405 { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)}, 406 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)}, 407 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)}, 408 { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)}, 409 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)}, 410 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)}, 411 { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)}, 412 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)}, 413 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)}, 414 { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)}, 415 { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)}, 416 }; 417 418 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num, 419 u32 sh_num, u32 reg_offset) 420 { 421 uint32_t val; 422 423 mutex_lock(&adev->grbm_idx_mutex); 424 if (se_num != 0xffffffff || sh_num != 0xffffffff) 425 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 426 427 val = RREG32(reg_offset); 428 429 if (se_num != 0xffffffff || sh_num != 0xffffffff) 430 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 431 mutex_unlock(&adev->grbm_idx_mutex); 432 return val; 433 } 434 435 static uint32_t nv_get_register_value(struct amdgpu_device *adev, 436 bool indexed, u32 se_num, 437 u32 sh_num, u32 reg_offset) 438 { 439 if (indexed) { 440 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); 441 } else { 442 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) 443 return adev->gfx.config.gb_addr_config; 444 return RREG32(reg_offset); 445 } 446 } 447 448 static int nv_read_register(struct amdgpu_device *adev, u32 se_num, 449 u32 sh_num, u32 reg_offset, u32 *value) 450 { 451 uint32_t i; 452 struct soc15_allowed_register_entry *en; 453 454 *value = 0; 455 for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) { 456 en = &nv_allowed_read_registers[i]; 457 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */ 458 reg_offset != 459 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) 460 continue; 461 462 *value = nv_get_register_value(adev, 463 nv_allowed_read_registers[i].grbm_indexed, 464 se_num, sh_num, reg_offset); 465 return 0; 466 } 467 return -EINVAL; 468 } 469 470 static int nv_asic_mode2_reset(struct amdgpu_device *adev) 471 { 472 u32 i; 473 int ret = 0; 474 475 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 476 477 /* disable BM */ 478 pci_clear_master(adev->pdev); 479 480 amdgpu_device_cache_pci_state(adev->pdev); 481 482 ret = amdgpu_dpm_mode2_reset(adev); 483 if (ret) 484 dev_err(adev->dev, "GPU mode2 reset failed\n"); 485 486 amdgpu_device_load_pci_state(adev->pdev); 487 488 /* wait for asic to come out of reset */ 489 for (i = 0; i < adev->usec_timeout; i++) { 490 u32 memsize = adev->nbio.funcs->get_memsize(adev); 491 492 if (memsize != 0xffffffff) 493 break; 494 udelay(1); 495 } 496 497 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 498 499 return ret; 500 } 501 502 static enum amd_reset_method 503 nv_asic_reset_method(struct amdgpu_device *adev) 504 { 505 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 || 506 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 || 507 amdgpu_reset_method == AMD_RESET_METHOD_BACO || 508 amdgpu_reset_method == AMD_RESET_METHOD_PCI) 509 return amdgpu_reset_method; 510 511 if (amdgpu_reset_method != -1) 512 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", 513 amdgpu_reset_method); 514 515 switch (adev->asic_type) { 516 case CHIP_VANGOGH: 517 case CHIP_YELLOW_CARP: 518 return AMD_RESET_METHOD_MODE2; 519 case CHIP_SIENNA_CICHLID: 520 case CHIP_NAVY_FLOUNDER: 521 case CHIP_DIMGREY_CAVEFISH: 522 case CHIP_BEIGE_GOBY: 523 return AMD_RESET_METHOD_MODE1; 524 default: 525 if (amdgpu_dpm_is_baco_supported(adev)) 526 return AMD_RESET_METHOD_BACO; 527 else 528 return AMD_RESET_METHOD_MODE1; 529 } 530 } 531 532 static int nv_asic_reset(struct amdgpu_device *adev) 533 { 534 int ret = 0; 535 536 switch (nv_asic_reset_method(adev)) { 537 case AMD_RESET_METHOD_PCI: 538 dev_info(adev->dev, "PCI reset\n"); 539 ret = amdgpu_device_pci_reset(adev); 540 break; 541 case AMD_RESET_METHOD_BACO: 542 dev_info(adev->dev, "BACO reset\n"); 543 ret = amdgpu_dpm_baco_reset(adev); 544 break; 545 case AMD_RESET_METHOD_MODE2: 546 dev_info(adev->dev, "MODE2 reset\n"); 547 ret = nv_asic_mode2_reset(adev); 548 break; 549 default: 550 dev_info(adev->dev, "MODE1 reset\n"); 551 ret = amdgpu_device_mode1_reset(adev); 552 break; 553 } 554 555 return ret; 556 } 557 558 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 559 { 560 /* todo */ 561 return 0; 562 } 563 564 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 565 { 566 /* todo */ 567 return 0; 568 } 569 570 static void nv_pcie_gen3_enable(struct amdgpu_device *adev) 571 { 572 if (pci_is_root_bus(adev->pdev->bus)) 573 return; 574 575 if (amdgpu_pcie_gen2 == 0) 576 return; 577 578 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 579 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 580 return; 581 582 /* todo */ 583 } 584 585 static void nv_program_aspm(struct amdgpu_device *adev) 586 { 587 if (!amdgpu_device_should_use_aspm(adev)) 588 return; 589 590 if (!(adev->flags & AMD_IS_APU) && 591 (adev->nbio.funcs->program_aspm)) 592 adev->nbio.funcs->program_aspm(adev); 593 594 } 595 596 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev, 597 bool enable) 598 { 599 adev->nbio.funcs->enable_doorbell_aperture(adev, enable); 600 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); 601 } 602 603 static const struct amdgpu_ip_block_version nv_common_ip_block = 604 { 605 .type = AMD_IP_BLOCK_TYPE_COMMON, 606 .major = 1, 607 .minor = 0, 608 .rev = 0, 609 .funcs = &nv_common_ip_funcs, 610 }; 611 612 static bool nv_is_headless_sku(struct pci_dev *pdev) 613 { 614 if ((pdev->device == 0x731E && 615 (pdev->revision == 0xC6 || pdev->revision == 0xC7)) || 616 (pdev->device == 0x7340 && pdev->revision == 0xC9) || 617 (pdev->device == 0x7360 && pdev->revision == 0xC7)) 618 return true; 619 return false; 620 } 621 622 static int nv_reg_base_init(struct amdgpu_device *adev) 623 { 624 int r; 625 626 if (amdgpu_discovery) { 627 r = amdgpu_discovery_reg_base_init(adev); 628 if (r) { 629 DRM_WARN("failed to init reg base from ip discovery table, " 630 "fallback to legacy init method\n"); 631 goto legacy_init; 632 } 633 634 amdgpu_discovery_harvest_ip(adev); 635 if (nv_is_headless_sku(adev->pdev)) { 636 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 637 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 638 } 639 640 return 0; 641 } 642 643 legacy_init: 644 switch (adev->asic_type) { 645 case CHIP_NAVI10: 646 navi10_reg_base_init(adev); 647 break; 648 case CHIP_NAVI14: 649 navi14_reg_base_init(adev); 650 break; 651 case CHIP_NAVI12: 652 navi12_reg_base_init(adev); 653 break; 654 case CHIP_SIENNA_CICHLID: 655 case CHIP_NAVY_FLOUNDER: 656 sienna_cichlid_reg_base_init(adev); 657 break; 658 case CHIP_VANGOGH: 659 vangogh_reg_base_init(adev); 660 break; 661 case CHIP_DIMGREY_CAVEFISH: 662 dimgrey_cavefish_reg_base_init(adev); 663 break; 664 case CHIP_BEIGE_GOBY: 665 beige_goby_reg_base_init(adev); 666 break; 667 case CHIP_YELLOW_CARP: 668 yellow_carp_reg_base_init(adev); 669 break; 670 case CHIP_CYAN_SKILLFISH: 671 cyan_skillfish_reg_base_init(adev); 672 break; 673 default: 674 return -EINVAL; 675 } 676 677 return 0; 678 } 679 680 void nv_set_virt_ops(struct amdgpu_device *adev) 681 { 682 adev->virt.ops = &xgpu_nv_virt_ops; 683 } 684 685 int nv_set_ip_blocks(struct amdgpu_device *adev) 686 { 687 int r; 688 689 if (adev->asic_type == CHIP_CYAN_SKILLFISH) { 690 adev->nbio.funcs = &nbio_v2_3_funcs; 691 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 692 } else if (adev->flags & AMD_IS_APU) { 693 adev->nbio.funcs = &nbio_v7_2_funcs; 694 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 695 } else { 696 adev->nbio.funcs = &nbio_v2_3_funcs; 697 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 698 } 699 adev->hdp.funcs = &hdp_v5_0_funcs; 700 701 if (adev->asic_type >= CHIP_SIENNA_CICHLID) 702 adev->smuio.funcs = &smuio_v11_0_6_funcs; 703 else 704 adev->smuio.funcs = &smuio_v11_0_funcs; 705 706 if (adev->asic_type == CHIP_SIENNA_CICHLID) 707 adev->gmc.xgmi.supported = true; 708 709 /* Set IP register base before any HW register access */ 710 r = nv_reg_base_init(adev); 711 if (r) 712 return r; 713 714 switch (adev->asic_type) { 715 case CHIP_NAVI10: 716 case CHIP_NAVI14: 717 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 718 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 719 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 720 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 721 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 722 !amdgpu_sriov_vf(adev)) 723 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 724 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 725 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 726 #if defined(CONFIG_DRM_AMD_DC) 727 else if (amdgpu_device_has_dc_support(adev)) 728 amdgpu_device_ip_block_add(adev, &dm_ip_block); 729 #endif 730 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 731 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 732 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 733 !amdgpu_sriov_vf(adev)) 734 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 735 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 736 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 737 if (adev->enable_mes) 738 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 739 break; 740 case CHIP_NAVI12: 741 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 742 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 743 if (!amdgpu_sriov_vf(adev)) { 744 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 745 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 746 } else { 747 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 748 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 749 } 750 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 751 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 752 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 753 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 754 #if defined(CONFIG_DRM_AMD_DC) 755 else if (amdgpu_device_has_dc_support(adev)) 756 amdgpu_device_ip_block_add(adev, &dm_ip_block); 757 #endif 758 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 759 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 760 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 761 !amdgpu_sriov_vf(adev)) 762 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 763 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 764 if (!amdgpu_sriov_vf(adev)) 765 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 766 break; 767 case CHIP_SIENNA_CICHLID: 768 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 769 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 770 if (!amdgpu_sriov_vf(adev)) { 771 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 772 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 773 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 774 } else { 775 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 776 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 777 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 778 } 779 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 780 is_support_sw_smu(adev)) 781 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 782 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 783 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 784 #if defined(CONFIG_DRM_AMD_DC) 785 else if (amdgpu_device_has_dc_support(adev)) 786 amdgpu_device_ip_block_add(adev, &dm_ip_block); 787 #endif 788 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 789 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 790 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 791 if (!amdgpu_sriov_vf(adev)) 792 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 793 if (adev->enable_mes) 794 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block); 795 break; 796 case CHIP_NAVY_FLOUNDER: 797 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 798 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 799 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 800 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 801 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 802 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 803 is_support_sw_smu(adev)) 804 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 805 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 806 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 807 #if defined(CONFIG_DRM_AMD_DC) 808 else if (amdgpu_device_has_dc_support(adev)) 809 amdgpu_device_ip_block_add(adev, &dm_ip_block); 810 #endif 811 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 812 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 813 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 814 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 815 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 816 is_support_sw_smu(adev)) 817 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 818 break; 819 case CHIP_VANGOGH: 820 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 821 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 822 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 823 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 824 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 825 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 826 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 827 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 828 #if defined(CONFIG_DRM_AMD_DC) 829 else if (amdgpu_device_has_dc_support(adev)) 830 amdgpu_device_ip_block_add(adev, &dm_ip_block); 831 #endif 832 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 833 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 834 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 835 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 836 break; 837 case CHIP_DIMGREY_CAVEFISH: 838 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 839 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 840 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 841 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 842 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 843 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 844 is_support_sw_smu(adev)) 845 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 846 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 847 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 848 #if defined(CONFIG_DRM_AMD_DC) 849 else if (amdgpu_device_has_dc_support(adev)) 850 amdgpu_device_ip_block_add(adev, &dm_ip_block); 851 #endif 852 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 853 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 854 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 855 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 856 break; 857 case CHIP_BEIGE_GOBY: 858 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 859 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 860 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 861 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 862 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 863 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 864 is_support_sw_smu(adev)) 865 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 866 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 867 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 868 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 869 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 870 #if defined(CONFIG_DRM_AMD_DC) 871 else if (amdgpu_device_has_dc_support(adev)) 872 amdgpu_device_ip_block_add(adev, &dm_ip_block); 873 #endif 874 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 875 is_support_sw_smu(adev)) 876 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 877 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 878 break; 879 case CHIP_YELLOW_CARP: 880 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 881 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 882 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 883 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 884 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 885 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 886 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 887 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 888 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 889 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 890 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 891 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 892 #if defined(CONFIG_DRM_AMD_DC) 893 else if (amdgpu_device_has_dc_support(adev)) 894 amdgpu_device_ip_block_add(adev, &dm_ip_block); 895 #endif 896 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 897 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 898 break; 899 case CHIP_CYAN_SKILLFISH: 900 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 901 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 902 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 903 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 904 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) 905 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 906 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 907 } 908 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) 909 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 910 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 911 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 912 break; 913 default: 914 return -EINVAL; 915 } 916 917 return 0; 918 } 919 920 static uint32_t nv_get_rev_id(struct amdgpu_device *adev) 921 { 922 return adev->nbio.funcs->get_rev_id(adev); 923 } 924 925 static bool nv_need_full_reset(struct amdgpu_device *adev) 926 { 927 return true; 928 } 929 930 static bool nv_need_reset_on_init(struct amdgpu_device *adev) 931 { 932 u32 sol_reg; 933 934 if (adev->flags & AMD_IS_APU) 935 return false; 936 937 /* Check sOS sign of life register to confirm sys driver and sOS 938 * are already been loaded. 939 */ 940 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 941 if (sol_reg) 942 return true; 943 944 return false; 945 } 946 947 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev) 948 { 949 950 /* TODO 951 * dummy implement for pcie_replay_count sysfs interface 952 * */ 953 954 return 0; 955 } 956 957 static void nv_init_doorbell_index(struct amdgpu_device *adev) 958 { 959 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ; 960 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0; 961 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1; 962 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2; 963 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3; 964 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4; 965 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5; 966 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6; 967 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7; 968 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START; 969 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END; 970 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0; 971 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1; 972 adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING; 973 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0; 974 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1; 975 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2; 976 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3; 977 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH; 978 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1; 979 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3; 980 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5; 981 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7; 982 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP; 983 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP; 984 985 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1; 986 adev->doorbell_index.sdma_doorbell_range = 20; 987 } 988 989 static void nv_pre_asic_init(struct amdgpu_device *adev) 990 { 991 } 992 993 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev, 994 bool enter) 995 { 996 if (enter) 997 amdgpu_gfx_rlc_enter_safe_mode(adev); 998 else 999 amdgpu_gfx_rlc_exit_safe_mode(adev); 1000 1001 if (adev->gfx.funcs->update_perfmon_mgcg) 1002 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter); 1003 1004 if (!(adev->flags & AMD_IS_APU) && 1005 (adev->nbio.funcs->enable_aspm)) 1006 adev->nbio.funcs->enable_aspm(adev, !enter); 1007 1008 return 0; 1009 } 1010 1011 static const struct amdgpu_asic_funcs nv_asic_funcs = 1012 { 1013 .read_disabled_bios = &nv_read_disabled_bios, 1014 .read_bios_from_rom = &nv_read_bios_from_rom, 1015 .read_register = &nv_read_register, 1016 .reset = &nv_asic_reset, 1017 .reset_method = &nv_asic_reset_method, 1018 .set_vga_state = &nv_vga_set_state, 1019 .get_xclk = &nv_get_xclk, 1020 .set_uvd_clocks = &nv_set_uvd_clocks, 1021 .set_vce_clocks = &nv_set_vce_clocks, 1022 .get_config_memsize = &nv_get_config_memsize, 1023 .init_doorbell_index = &nv_init_doorbell_index, 1024 .need_full_reset = &nv_need_full_reset, 1025 .need_reset_on_init = &nv_need_reset_on_init, 1026 .get_pcie_replay_count = &nv_get_pcie_replay_count, 1027 .supports_baco = &amdgpu_dpm_is_baco_supported, 1028 .pre_asic_init = &nv_pre_asic_init, 1029 .update_umd_stable_pstate = &nv_update_umd_stable_pstate, 1030 .query_video_codecs = &nv_query_video_codecs, 1031 }; 1032 1033 static int nv_common_early_init(void *handle) 1034 { 1035 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 1036 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1037 1038 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; 1039 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; 1040 adev->smc_rreg = NULL; 1041 adev->smc_wreg = NULL; 1042 adev->pcie_rreg = &nv_pcie_rreg; 1043 adev->pcie_wreg = &nv_pcie_wreg; 1044 adev->pcie_rreg64 = &nv_pcie_rreg64; 1045 adev->pcie_wreg64 = &nv_pcie_wreg64; 1046 adev->pciep_rreg = &nv_pcie_port_rreg; 1047 adev->pciep_wreg = &nv_pcie_port_wreg; 1048 1049 /* TODO: will add them during VCN v2 implementation */ 1050 adev->uvd_ctx_rreg = NULL; 1051 adev->uvd_ctx_wreg = NULL; 1052 1053 adev->didt_rreg = &nv_didt_rreg; 1054 adev->didt_wreg = &nv_didt_wreg; 1055 1056 adev->asic_funcs = &nv_asic_funcs; 1057 1058 adev->rev_id = nv_get_rev_id(adev); 1059 adev->external_rev_id = 0xff; 1060 switch (adev->asic_type) { 1061 case CHIP_NAVI10: 1062 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1063 AMD_CG_SUPPORT_GFX_CGCG | 1064 AMD_CG_SUPPORT_IH_CG | 1065 AMD_CG_SUPPORT_HDP_MGCG | 1066 AMD_CG_SUPPORT_HDP_LS | 1067 AMD_CG_SUPPORT_SDMA_MGCG | 1068 AMD_CG_SUPPORT_SDMA_LS | 1069 AMD_CG_SUPPORT_MC_MGCG | 1070 AMD_CG_SUPPORT_MC_LS | 1071 AMD_CG_SUPPORT_ATHUB_MGCG | 1072 AMD_CG_SUPPORT_ATHUB_LS | 1073 AMD_CG_SUPPORT_VCN_MGCG | 1074 AMD_CG_SUPPORT_JPEG_MGCG | 1075 AMD_CG_SUPPORT_BIF_MGCG | 1076 AMD_CG_SUPPORT_BIF_LS; 1077 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1078 AMD_PG_SUPPORT_VCN_DPG | 1079 AMD_PG_SUPPORT_JPEG | 1080 AMD_PG_SUPPORT_ATHUB; 1081 adev->external_rev_id = adev->rev_id + 0x1; 1082 break; 1083 case CHIP_NAVI14: 1084 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1085 AMD_CG_SUPPORT_GFX_CGCG | 1086 AMD_CG_SUPPORT_IH_CG | 1087 AMD_CG_SUPPORT_HDP_MGCG | 1088 AMD_CG_SUPPORT_HDP_LS | 1089 AMD_CG_SUPPORT_SDMA_MGCG | 1090 AMD_CG_SUPPORT_SDMA_LS | 1091 AMD_CG_SUPPORT_MC_MGCG | 1092 AMD_CG_SUPPORT_MC_LS | 1093 AMD_CG_SUPPORT_ATHUB_MGCG | 1094 AMD_CG_SUPPORT_ATHUB_LS | 1095 AMD_CG_SUPPORT_VCN_MGCG | 1096 AMD_CG_SUPPORT_JPEG_MGCG | 1097 AMD_CG_SUPPORT_BIF_MGCG | 1098 AMD_CG_SUPPORT_BIF_LS; 1099 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1100 AMD_PG_SUPPORT_JPEG | 1101 AMD_PG_SUPPORT_VCN_DPG; 1102 adev->external_rev_id = adev->rev_id + 20; 1103 break; 1104 case CHIP_NAVI12: 1105 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1106 AMD_CG_SUPPORT_GFX_MGLS | 1107 AMD_CG_SUPPORT_GFX_CGCG | 1108 AMD_CG_SUPPORT_GFX_CP_LS | 1109 AMD_CG_SUPPORT_GFX_RLC_LS | 1110 AMD_CG_SUPPORT_IH_CG | 1111 AMD_CG_SUPPORT_HDP_MGCG | 1112 AMD_CG_SUPPORT_HDP_LS | 1113 AMD_CG_SUPPORT_SDMA_MGCG | 1114 AMD_CG_SUPPORT_SDMA_LS | 1115 AMD_CG_SUPPORT_MC_MGCG | 1116 AMD_CG_SUPPORT_MC_LS | 1117 AMD_CG_SUPPORT_ATHUB_MGCG | 1118 AMD_CG_SUPPORT_ATHUB_LS | 1119 AMD_CG_SUPPORT_VCN_MGCG | 1120 AMD_CG_SUPPORT_JPEG_MGCG; 1121 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1122 AMD_PG_SUPPORT_VCN_DPG | 1123 AMD_PG_SUPPORT_JPEG | 1124 AMD_PG_SUPPORT_ATHUB; 1125 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0, 1126 * as a consequence, the rev_id and external_rev_id are wrong. 1127 * workaround it by hardcoding rev_id to 0 (default value). 1128 */ 1129 if (amdgpu_sriov_vf(adev)) 1130 adev->rev_id = 0; 1131 adev->external_rev_id = adev->rev_id + 0xa; 1132 break; 1133 case CHIP_SIENNA_CICHLID: 1134 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1135 AMD_CG_SUPPORT_GFX_CGCG | 1136 AMD_CG_SUPPORT_GFX_CGLS | 1137 AMD_CG_SUPPORT_GFX_3D_CGCG | 1138 AMD_CG_SUPPORT_MC_MGCG | 1139 AMD_CG_SUPPORT_VCN_MGCG | 1140 AMD_CG_SUPPORT_JPEG_MGCG | 1141 AMD_CG_SUPPORT_HDP_MGCG | 1142 AMD_CG_SUPPORT_HDP_LS | 1143 AMD_CG_SUPPORT_IH_CG | 1144 AMD_CG_SUPPORT_MC_LS; 1145 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1146 AMD_PG_SUPPORT_VCN_DPG | 1147 AMD_PG_SUPPORT_JPEG | 1148 AMD_PG_SUPPORT_ATHUB | 1149 AMD_PG_SUPPORT_MMHUB; 1150 if (amdgpu_sriov_vf(adev)) { 1151 /* hypervisor control CG and PG enablement */ 1152 adev->cg_flags = 0; 1153 adev->pg_flags = 0; 1154 } 1155 adev->external_rev_id = adev->rev_id + 0x28; 1156 break; 1157 case CHIP_NAVY_FLOUNDER: 1158 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1159 AMD_CG_SUPPORT_GFX_CGCG | 1160 AMD_CG_SUPPORT_GFX_CGLS | 1161 AMD_CG_SUPPORT_GFX_3D_CGCG | 1162 AMD_CG_SUPPORT_VCN_MGCG | 1163 AMD_CG_SUPPORT_JPEG_MGCG | 1164 AMD_CG_SUPPORT_MC_MGCG | 1165 AMD_CG_SUPPORT_MC_LS | 1166 AMD_CG_SUPPORT_HDP_MGCG | 1167 AMD_CG_SUPPORT_HDP_LS | 1168 AMD_CG_SUPPORT_IH_CG; 1169 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1170 AMD_PG_SUPPORT_VCN_DPG | 1171 AMD_PG_SUPPORT_JPEG | 1172 AMD_PG_SUPPORT_ATHUB | 1173 AMD_PG_SUPPORT_MMHUB; 1174 adev->external_rev_id = adev->rev_id + 0x32; 1175 break; 1176 1177 case CHIP_VANGOGH: 1178 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1179 AMD_CG_SUPPORT_GFX_MGLS | 1180 AMD_CG_SUPPORT_GFX_CP_LS | 1181 AMD_CG_SUPPORT_GFX_RLC_LS | 1182 AMD_CG_SUPPORT_GFX_CGCG | 1183 AMD_CG_SUPPORT_GFX_CGLS | 1184 AMD_CG_SUPPORT_GFX_3D_CGCG | 1185 AMD_CG_SUPPORT_GFX_3D_CGLS | 1186 AMD_CG_SUPPORT_MC_MGCG | 1187 AMD_CG_SUPPORT_MC_LS | 1188 AMD_CG_SUPPORT_GFX_FGCG | 1189 AMD_CG_SUPPORT_VCN_MGCG | 1190 AMD_CG_SUPPORT_SDMA_MGCG | 1191 AMD_CG_SUPPORT_SDMA_LS | 1192 AMD_CG_SUPPORT_JPEG_MGCG; 1193 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1194 AMD_PG_SUPPORT_VCN | 1195 AMD_PG_SUPPORT_VCN_DPG | 1196 AMD_PG_SUPPORT_JPEG; 1197 if (adev->apu_flags & AMD_APU_IS_VANGOGH) 1198 adev->external_rev_id = adev->rev_id + 0x01; 1199 break; 1200 case CHIP_DIMGREY_CAVEFISH: 1201 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1202 AMD_CG_SUPPORT_GFX_CGCG | 1203 AMD_CG_SUPPORT_GFX_CGLS | 1204 AMD_CG_SUPPORT_GFX_3D_CGCG | 1205 AMD_CG_SUPPORT_VCN_MGCG | 1206 AMD_CG_SUPPORT_JPEG_MGCG | 1207 AMD_CG_SUPPORT_MC_MGCG | 1208 AMD_CG_SUPPORT_MC_LS | 1209 AMD_CG_SUPPORT_HDP_MGCG | 1210 AMD_CG_SUPPORT_HDP_LS | 1211 AMD_CG_SUPPORT_IH_CG; 1212 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1213 AMD_PG_SUPPORT_VCN_DPG | 1214 AMD_PG_SUPPORT_JPEG | 1215 AMD_PG_SUPPORT_ATHUB | 1216 AMD_PG_SUPPORT_MMHUB; 1217 adev->external_rev_id = adev->rev_id + 0x3c; 1218 break; 1219 case CHIP_BEIGE_GOBY: 1220 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1221 AMD_CG_SUPPORT_GFX_CGCG | 1222 AMD_CG_SUPPORT_GFX_CGLS | 1223 AMD_CG_SUPPORT_GFX_3D_CGCG | 1224 AMD_CG_SUPPORT_MC_MGCG | 1225 AMD_CG_SUPPORT_MC_LS | 1226 AMD_CG_SUPPORT_HDP_MGCG | 1227 AMD_CG_SUPPORT_HDP_LS | 1228 AMD_CG_SUPPORT_IH_CG | 1229 AMD_CG_SUPPORT_VCN_MGCG; 1230 adev->pg_flags = AMD_PG_SUPPORT_VCN | 1231 AMD_PG_SUPPORT_VCN_DPG | 1232 AMD_PG_SUPPORT_ATHUB | 1233 AMD_PG_SUPPORT_MMHUB; 1234 adev->external_rev_id = adev->rev_id + 0x46; 1235 break; 1236 case CHIP_YELLOW_CARP: 1237 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | 1238 AMD_CG_SUPPORT_GFX_MGLS | 1239 AMD_CG_SUPPORT_GFX_CGCG | 1240 AMD_CG_SUPPORT_GFX_CGLS | 1241 AMD_CG_SUPPORT_GFX_3D_CGCG | 1242 AMD_CG_SUPPORT_GFX_3D_CGLS | 1243 AMD_CG_SUPPORT_GFX_RLC_LS | 1244 AMD_CG_SUPPORT_GFX_CP_LS | 1245 AMD_CG_SUPPORT_GFX_FGCG | 1246 AMD_CG_SUPPORT_MC_MGCG | 1247 AMD_CG_SUPPORT_MC_LS | 1248 AMD_CG_SUPPORT_SDMA_LS | 1249 AMD_CG_SUPPORT_HDP_MGCG | 1250 AMD_CG_SUPPORT_HDP_LS | 1251 AMD_CG_SUPPORT_ATHUB_MGCG | 1252 AMD_CG_SUPPORT_ATHUB_LS | 1253 AMD_CG_SUPPORT_IH_CG | 1254 AMD_CG_SUPPORT_VCN_MGCG | 1255 AMD_CG_SUPPORT_JPEG_MGCG; 1256 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG | 1257 AMD_PG_SUPPORT_VCN | 1258 AMD_PG_SUPPORT_VCN_DPG | 1259 AMD_PG_SUPPORT_JPEG; 1260 if (adev->pdev->device == 0x1681) 1261 adev->external_rev_id = 0x20; 1262 else 1263 adev->external_rev_id = adev->rev_id + 0x01; 1264 break; 1265 case CHIP_CYAN_SKILLFISH: 1266 adev->cg_flags = 0; 1267 adev->pg_flags = 0; 1268 adev->external_rev_id = adev->rev_id + 0x82; 1269 break; 1270 default: 1271 /* FIXME: not supported yet */ 1272 return -EINVAL; 1273 } 1274 1275 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK) 1276 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN | 1277 AMD_PG_SUPPORT_VCN_DPG | 1278 AMD_PG_SUPPORT_JPEG); 1279 1280 if (amdgpu_sriov_vf(adev)) { 1281 amdgpu_virt_init_setting(adev); 1282 xgpu_nv_mailbox_set_irq_funcs(adev); 1283 } 1284 1285 return 0; 1286 } 1287 1288 static int nv_common_late_init(void *handle) 1289 { 1290 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1291 1292 if (amdgpu_sriov_vf(adev)) { 1293 xgpu_nv_mailbox_get_irq(adev); 1294 amdgpu_virt_update_sriov_video_codec(adev, 1295 sriov_sc_video_codecs_encode_array, ARRAY_SIZE(sriov_sc_video_codecs_encode_array), 1296 sriov_sc_video_codecs_decode_array, ARRAY_SIZE(sriov_sc_video_codecs_decode_array)); 1297 } 1298 1299 return 0; 1300 } 1301 1302 static int nv_common_sw_init(void *handle) 1303 { 1304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1305 1306 if (amdgpu_sriov_vf(adev)) 1307 xgpu_nv_mailbox_add_irq_id(adev); 1308 1309 return 0; 1310 } 1311 1312 static int nv_common_sw_fini(void *handle) 1313 { 1314 return 0; 1315 } 1316 1317 static int nv_common_hw_init(void *handle) 1318 { 1319 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1320 1321 if (adev->nbio.funcs->apply_lc_spc_mode_wa) 1322 adev->nbio.funcs->apply_lc_spc_mode_wa(adev); 1323 1324 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) 1325 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); 1326 1327 /* enable pcie gen2/3 link */ 1328 nv_pcie_gen3_enable(adev); 1329 /* enable aspm */ 1330 nv_program_aspm(adev); 1331 /* setup nbio registers */ 1332 adev->nbio.funcs->init_registers(adev); 1333 /* remap HDP registers to a hole in mmio space, 1334 * for the purpose of expose those registers 1335 * to process space 1336 */ 1337 if (adev->nbio.funcs->remap_hdp_registers) 1338 adev->nbio.funcs->remap_hdp_registers(adev); 1339 /* enable the doorbell aperture */ 1340 nv_enable_doorbell_aperture(adev, true); 1341 1342 return 0; 1343 } 1344 1345 static int nv_common_hw_fini(void *handle) 1346 { 1347 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1348 1349 /* disable the doorbell aperture */ 1350 nv_enable_doorbell_aperture(adev, false); 1351 1352 return 0; 1353 } 1354 1355 static int nv_common_suspend(void *handle) 1356 { 1357 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1358 1359 return nv_common_hw_fini(adev); 1360 } 1361 1362 static int nv_common_resume(void *handle) 1363 { 1364 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1365 1366 return nv_common_hw_init(adev); 1367 } 1368 1369 static bool nv_common_is_idle(void *handle) 1370 { 1371 return true; 1372 } 1373 1374 static int nv_common_wait_for_idle(void *handle) 1375 { 1376 return 0; 1377 } 1378 1379 static int nv_common_soft_reset(void *handle) 1380 { 1381 return 0; 1382 } 1383 1384 static int nv_common_set_clockgating_state(void *handle, 1385 enum amd_clockgating_state state) 1386 { 1387 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1388 1389 if (amdgpu_sriov_vf(adev)) 1390 return 0; 1391 1392 switch (adev->asic_type) { 1393 case CHIP_NAVI10: 1394 case CHIP_NAVI14: 1395 case CHIP_NAVI12: 1396 case CHIP_SIENNA_CICHLID: 1397 case CHIP_NAVY_FLOUNDER: 1398 case CHIP_DIMGREY_CAVEFISH: 1399 case CHIP_BEIGE_GOBY: 1400 adev->nbio.funcs->update_medium_grain_clock_gating(adev, 1401 state == AMD_CG_STATE_GATE); 1402 adev->nbio.funcs->update_medium_grain_light_sleep(adev, 1403 state == AMD_CG_STATE_GATE); 1404 adev->hdp.funcs->update_clock_gating(adev, 1405 state == AMD_CG_STATE_GATE); 1406 adev->smuio.funcs->update_rom_clock_gating(adev, 1407 state == AMD_CG_STATE_GATE); 1408 break; 1409 default: 1410 break; 1411 } 1412 return 0; 1413 } 1414 1415 static int nv_common_set_powergating_state(void *handle, 1416 enum amd_powergating_state state) 1417 { 1418 /* TODO */ 1419 return 0; 1420 } 1421 1422 static void nv_common_get_clockgating_state(void *handle, u32 *flags) 1423 { 1424 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1425 1426 if (amdgpu_sriov_vf(adev)) 1427 *flags = 0; 1428 1429 adev->nbio.funcs->get_clockgating_state(adev, flags); 1430 1431 adev->hdp.funcs->get_clock_gating_state(adev, flags); 1432 1433 adev->smuio.funcs->get_clock_gating_state(adev, flags); 1434 1435 return; 1436 } 1437 1438 static const struct amd_ip_funcs nv_common_ip_funcs = { 1439 .name = "nv_common", 1440 .early_init = nv_common_early_init, 1441 .late_init = nv_common_late_init, 1442 .sw_init = nv_common_sw_init, 1443 .sw_fini = nv_common_sw_fini, 1444 .hw_init = nv_common_hw_init, 1445 .hw_fini = nv_common_hw_fini, 1446 .suspend = nv_common_suspend, 1447 .resume = nv_common_resume, 1448 .is_idle = nv_common_is_idle, 1449 .wait_for_idle = nv_common_wait_for_idle, 1450 .soft_reset = nv_common_soft_reset, 1451 .set_clockgating_state = nv_common_set_clockgating_state, 1452 .set_powergating_state = nv_common_set_powergating_state, 1453 .get_clockgating_state = nv_common_get_clockgating_state, 1454 }; 1455