1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 43 44 static int mes_v11_0_hw_fini(void *handle); 45 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 46 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 47 48 #define MES_EOP_SIZE 2048 49 50 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 51 { 52 struct amdgpu_device *adev = ring->adev; 53 54 if (ring->use_doorbell) { 55 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 56 ring->wptr); 57 WDOORBELL64(ring->doorbell_index, ring->wptr); 58 } else { 59 BUG(); 60 } 61 } 62 63 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 64 { 65 return *ring->rptr_cpu_addr; 66 } 67 68 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 69 { 70 u64 wptr; 71 72 if (ring->use_doorbell) 73 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 74 else 75 BUG(); 76 return wptr; 77 } 78 79 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 80 .type = AMDGPU_RING_TYPE_MES, 81 .align_mask = 1, 82 .nop = 0, 83 .support_64bit_ptrs = true, 84 .get_rptr = mes_v11_0_ring_get_rptr, 85 .get_wptr = mes_v11_0_ring_get_wptr, 86 .set_wptr = mes_v11_0_ring_set_wptr, 87 .insert_nop = amdgpu_ring_insert_nop, 88 }; 89 90 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 91 void *pkt, int size, 92 int api_status_off) 93 { 94 int ndw = size / 4; 95 signed long r; 96 union MESAPI__ADD_QUEUE *x_pkt = pkt; 97 struct MES_API_STATUS *api_status; 98 struct amdgpu_device *adev = mes->adev; 99 struct amdgpu_ring *ring = &mes->ring; 100 unsigned long flags; 101 signed long timeout = adev->usec_timeout; 102 103 if (amdgpu_emu_mode) { 104 timeout *= 100; 105 } else if (amdgpu_sriov_vf(adev)) { 106 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 107 timeout = 15 * 600 * 1000; 108 } 109 BUG_ON(size % 4 != 0); 110 111 spin_lock_irqsave(&mes->ring_lock, flags); 112 if (amdgpu_ring_alloc(ring, ndw)) { 113 spin_unlock_irqrestore(&mes->ring_lock, flags); 114 return -ENOMEM; 115 } 116 117 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 118 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 119 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 120 121 amdgpu_ring_write_multiple(ring, pkt, ndw); 122 amdgpu_ring_commit(ring); 123 spin_unlock_irqrestore(&mes->ring_lock, flags); 124 125 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 126 127 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 128 timeout); 129 if (r < 1) { 130 DRM_ERROR("MES failed to response msg=%d\n", 131 x_pkt->header.opcode); 132 return -ETIMEDOUT; 133 } 134 135 return 0; 136 } 137 138 static int convert_to_mes_queue_type(int queue_type) 139 { 140 if (queue_type == AMDGPU_RING_TYPE_GFX) 141 return MES_QUEUE_TYPE_GFX; 142 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 143 return MES_QUEUE_TYPE_COMPUTE; 144 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 145 return MES_QUEUE_TYPE_SDMA; 146 else 147 BUG(); 148 return -1; 149 } 150 151 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 152 struct mes_add_queue_input *input) 153 { 154 struct amdgpu_device *adev = mes->adev; 155 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 156 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 157 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 158 159 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 160 161 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 162 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 163 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 164 165 mes_add_queue_pkt.process_id = input->process_id; 166 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 167 mes_add_queue_pkt.process_va_start = input->process_va_start; 168 mes_add_queue_pkt.process_va_end = input->process_va_end; 169 mes_add_queue_pkt.process_quantum = input->process_quantum; 170 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 171 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 172 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 173 mes_add_queue_pkt.inprocess_gang_priority = 174 input->inprocess_gang_priority; 175 mes_add_queue_pkt.gang_global_priority_level = 176 input->gang_global_priority_level; 177 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 178 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 179 180 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 181 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 182 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 183 else 184 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 185 186 mes_add_queue_pkt.queue_type = 187 convert_to_mes_queue_type(input->queue_type); 188 mes_add_queue_pkt.paging = input->paging; 189 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 190 mes_add_queue_pkt.gws_base = input->gws_base; 191 mes_add_queue_pkt.gws_size = input->gws_size; 192 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 193 mes_add_queue_pkt.tma_addr = input->tma_addr; 194 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 195 196 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 197 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 198 mes_add_queue_pkt.gds_size = input->queue_size; 199 200 if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 4) && 201 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) && 202 (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3)))) 203 mes_add_queue_pkt.trap_en = 1; 204 205 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 206 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 207 mes_add_queue_pkt.gds_size = input->queue_size; 208 209 return mes_v11_0_submit_pkt_and_poll_completion(mes, 210 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 211 offsetof(union MESAPI__ADD_QUEUE, api_status)); 212 } 213 214 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 215 struct mes_remove_queue_input *input) 216 { 217 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 218 219 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 220 221 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 222 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 223 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 224 225 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 226 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 227 228 return mes_v11_0_submit_pkt_and_poll_completion(mes, 229 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 230 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 231 } 232 233 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 234 struct mes_unmap_legacy_queue_input *input) 235 { 236 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 237 238 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 239 240 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 241 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 242 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 243 244 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 245 mes_remove_queue_pkt.gang_context_addr = 0; 246 247 mes_remove_queue_pkt.pipe_id = input->pipe_id; 248 mes_remove_queue_pkt.queue_id = input->queue_id; 249 250 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 251 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 252 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 253 mes_remove_queue_pkt.tf_data = 254 lower_32_bits(input->trail_fence_data); 255 } else { 256 mes_remove_queue_pkt.unmap_legacy_queue = 1; 257 mes_remove_queue_pkt.queue_type = 258 convert_to_mes_queue_type(input->queue_type); 259 } 260 261 return mes_v11_0_submit_pkt_and_poll_completion(mes, 262 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 263 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 264 } 265 266 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 267 struct mes_suspend_gang_input *input) 268 { 269 return 0; 270 } 271 272 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 273 struct mes_resume_gang_input *input) 274 { 275 return 0; 276 } 277 278 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 279 { 280 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 281 282 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 283 284 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 285 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 286 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 287 288 return mes_v11_0_submit_pkt_and_poll_completion(mes, 289 &mes_status_pkt, sizeof(mes_status_pkt), 290 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 291 } 292 293 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 294 struct mes_misc_op_input *input) 295 { 296 union MESAPI__MISC misc_pkt; 297 298 memset(&misc_pkt, 0, sizeof(misc_pkt)); 299 300 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 301 misc_pkt.header.opcode = MES_SCH_API_MISC; 302 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 303 304 switch (input->op) { 305 case MES_MISC_OP_READ_REG: 306 misc_pkt.opcode = MESAPI_MISC__READ_REG; 307 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 308 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 309 break; 310 case MES_MISC_OP_WRITE_REG: 311 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 312 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 313 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 314 break; 315 case MES_MISC_OP_WRM_REG_WAIT: 316 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 317 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 318 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 319 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 320 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 321 misc_pkt.wait_reg_mem.reg_offset2 = 0; 322 break; 323 case MES_MISC_OP_WRM_REG_WR_WAIT: 324 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 325 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 326 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 327 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 328 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 329 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 330 break; 331 default: 332 DRM_ERROR("unsupported misc op (%d) \n", input->op); 333 return -EINVAL; 334 } 335 336 return mes_v11_0_submit_pkt_and_poll_completion(mes, 337 &misc_pkt, sizeof(misc_pkt), 338 offsetof(union MESAPI__MISC, api_status)); 339 } 340 341 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 342 { 343 int i; 344 struct amdgpu_device *adev = mes->adev; 345 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 346 347 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 348 349 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 350 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 351 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 352 353 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 354 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 355 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 356 mes_set_hw_res_pkt.paging_vmid = 0; 357 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 358 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 359 mes->query_status_fence_gpu_addr; 360 361 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 362 mes_set_hw_res_pkt.compute_hqd_mask[i] = 363 mes->compute_hqd_mask[i]; 364 365 for (i = 0; i < MAX_GFX_PIPES; i++) 366 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 367 368 for (i = 0; i < MAX_SDMA_PIPES; i++) 369 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 370 371 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 372 mes_set_hw_res_pkt.aggregated_doorbells[i] = 373 mes->aggregated_doorbells[i]; 374 375 for (i = 0; i < 5; i++) { 376 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 377 mes_set_hw_res_pkt.mmhub_base[i] = 378 adev->reg_offset[MMHUB_HWIP][0][i]; 379 mes_set_hw_res_pkt.osssys_base[i] = 380 adev->reg_offset[OSSSYS_HWIP][0][i]; 381 } 382 383 mes_set_hw_res_pkt.disable_reset = 1; 384 mes_set_hw_res_pkt.disable_mes_log = 1; 385 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 386 mes_set_hw_res_pkt.oversubscription_timer = 50; 387 388 return mes_v11_0_submit_pkt_and_poll_completion(mes, 389 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 390 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 391 } 392 393 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 394 { 395 struct amdgpu_device *adev = mes->adev; 396 uint32_t data; 397 398 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 399 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 400 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 401 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 402 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 403 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 404 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 405 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 406 407 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 408 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 409 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 410 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 411 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 412 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 413 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 414 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 415 416 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 417 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 418 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 419 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 420 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 421 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 422 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 423 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 424 425 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 426 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 427 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 428 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 429 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 430 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 431 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 432 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 433 434 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 435 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 436 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 437 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 438 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 439 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 440 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 441 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 442 443 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 444 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 445 } 446 447 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 448 .add_hw_queue = mes_v11_0_add_hw_queue, 449 .remove_hw_queue = mes_v11_0_remove_hw_queue, 450 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 451 .suspend_gang = mes_v11_0_suspend_gang, 452 .resume_gang = mes_v11_0_resume_gang, 453 .misc_op = mes_v11_0_misc_op, 454 }; 455 456 static int mes_v11_0_init_microcode(struct amdgpu_device *adev, 457 enum admgpu_mes_pipe pipe) 458 { 459 char fw_name[30]; 460 char ucode_prefix[30]; 461 int err; 462 const struct mes_firmware_header_v1_0 *mes_hdr; 463 struct amdgpu_firmware_info *info; 464 465 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 466 467 if (pipe == AMDGPU_MES_SCHED_PIPE) 468 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes.bin", 469 ucode_prefix); 470 else 471 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mes1.bin", 472 ucode_prefix); 473 474 err = request_firmware(&adev->mes.fw[pipe], fw_name, adev->dev); 475 if (err) 476 return err; 477 478 err = amdgpu_ucode_validate(adev->mes.fw[pipe]); 479 if (err) { 480 release_firmware(adev->mes.fw[pipe]); 481 adev->mes.fw[pipe] = NULL; 482 return err; 483 } 484 485 mes_hdr = (const struct mes_firmware_header_v1_0 *) 486 adev->mes.fw[pipe]->data; 487 adev->mes.ucode_fw_version[pipe] = 488 le32_to_cpu(mes_hdr->mes_ucode_version); 489 adev->mes.ucode_fw_version[pipe] = 490 le32_to_cpu(mes_hdr->mes_ucode_data_version); 491 adev->mes.uc_start_addr[pipe] = 492 le32_to_cpu(mes_hdr->mes_uc_start_addr_lo) | 493 ((uint64_t)(le32_to_cpu(mes_hdr->mes_uc_start_addr_hi)) << 32); 494 adev->mes.data_start_addr[pipe] = 495 le32_to_cpu(mes_hdr->mes_data_start_addr_lo) | 496 ((uint64_t)(le32_to_cpu(mes_hdr->mes_data_start_addr_hi)) << 32); 497 498 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 499 int ucode, ucode_data; 500 501 if (pipe == AMDGPU_MES_SCHED_PIPE) { 502 ucode = AMDGPU_UCODE_ID_CP_MES; 503 ucode_data = AMDGPU_UCODE_ID_CP_MES_DATA; 504 } else { 505 ucode = AMDGPU_UCODE_ID_CP_MES1; 506 ucode_data = AMDGPU_UCODE_ID_CP_MES1_DATA; 507 } 508 509 info = &adev->firmware.ucode[ucode]; 510 info->ucode_id = ucode; 511 info->fw = adev->mes.fw[pipe]; 512 adev->firmware.fw_size += 513 roundup2(le32_to_cpu(mes_hdr->mes_ucode_size_bytes), 514 PAGE_SIZE); 515 516 info = &adev->firmware.ucode[ucode_data]; 517 info->ucode_id = ucode_data; 518 info->fw = adev->mes.fw[pipe]; 519 adev->firmware.fw_size += 520 roundup2(le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes), 521 PAGE_SIZE); 522 } 523 524 return 0; 525 } 526 527 static void mes_v11_0_free_microcode(struct amdgpu_device *adev, 528 enum admgpu_mes_pipe pipe) 529 { 530 release_firmware(adev->mes.fw[pipe]); 531 adev->mes.fw[pipe] = NULL; 532 } 533 534 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 535 enum admgpu_mes_pipe pipe) 536 { 537 int r; 538 const struct mes_firmware_header_v1_0 *mes_hdr; 539 const __le32 *fw_data; 540 unsigned fw_size; 541 542 mes_hdr = (const struct mes_firmware_header_v1_0 *) 543 adev->mes.fw[pipe]->data; 544 545 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 546 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 547 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 548 549 r = amdgpu_bo_create_reserved(adev, fw_size, 550 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 551 &adev->mes.ucode_fw_obj[pipe], 552 &adev->mes.ucode_fw_gpu_addr[pipe], 553 (void **)&adev->mes.ucode_fw_ptr[pipe]); 554 if (r) { 555 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 556 return r; 557 } 558 559 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 560 561 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 562 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 563 564 return 0; 565 } 566 567 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 568 enum admgpu_mes_pipe pipe) 569 { 570 int r; 571 const struct mes_firmware_header_v1_0 *mes_hdr; 572 const __le32 *fw_data; 573 unsigned fw_size; 574 575 mes_hdr = (const struct mes_firmware_header_v1_0 *) 576 adev->mes.fw[pipe]->data; 577 578 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 579 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 580 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 581 582 r = amdgpu_bo_create_reserved(adev, fw_size, 583 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 584 &adev->mes.data_fw_obj[pipe], 585 &adev->mes.data_fw_gpu_addr[pipe], 586 (void **)&adev->mes.data_fw_ptr[pipe]); 587 if (r) { 588 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 589 return r; 590 } 591 592 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 593 594 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 595 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 596 597 return 0; 598 } 599 600 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 601 enum admgpu_mes_pipe pipe) 602 { 603 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 604 &adev->mes.data_fw_gpu_addr[pipe], 605 (void **)&adev->mes.data_fw_ptr[pipe]); 606 607 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 608 &adev->mes.ucode_fw_gpu_addr[pipe], 609 (void **)&adev->mes.ucode_fw_ptr[pipe]); 610 } 611 612 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 613 { 614 uint64_t ucode_addr; 615 uint32_t pipe, data = 0; 616 617 if (enable) { 618 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 619 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 620 data = REG_SET_FIELD(data, CP_MES_CNTL, 621 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 622 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 623 624 mutex_lock(&adev->srbm_mutex); 625 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 626 if (!adev->enable_mes_kiq && 627 pipe == AMDGPU_MES_KIQ_PIPE) 628 continue; 629 630 soc21_grbm_select(adev, 3, pipe, 0, 0); 631 632 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 633 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 634 lower_32_bits(ucode_addr)); 635 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 636 upper_32_bits(ucode_addr)); 637 } 638 soc21_grbm_select(adev, 0, 0, 0, 0); 639 mutex_unlock(&adev->srbm_mutex); 640 641 /* unhalt MES and activate pipe0 */ 642 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 643 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 644 adev->enable_mes_kiq ? 1 : 0); 645 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 646 647 if (amdgpu_emu_mode) 648 drm_msleep(100); 649 else 650 udelay(50); 651 } else { 652 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 653 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 654 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 655 data = REG_SET_FIELD(data, CP_MES_CNTL, 656 MES_INVALIDATE_ICACHE, 1); 657 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 658 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 659 adev->enable_mes_kiq ? 1 : 0); 660 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 661 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 662 } 663 } 664 665 /* This function is for backdoor MES firmware */ 666 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 667 enum admgpu_mes_pipe pipe, bool prime_icache) 668 { 669 int r; 670 uint32_t data; 671 uint64_t ucode_addr; 672 673 mes_v11_0_enable(adev, false); 674 675 if (!adev->mes.fw[pipe]) 676 return -EINVAL; 677 678 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 679 if (r) 680 return r; 681 682 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 683 if (r) { 684 mes_v11_0_free_ucode_buffers(adev, pipe); 685 return r; 686 } 687 688 mutex_lock(&adev->srbm_mutex); 689 /* me=3, pipe=0, queue=0 */ 690 soc21_grbm_select(adev, 3, pipe, 0, 0); 691 692 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 693 694 /* set ucode start address */ 695 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 696 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 697 lower_32_bits(ucode_addr)); 698 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 699 upper_32_bits(ucode_addr)); 700 701 /* set ucode fimrware address */ 702 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 703 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 704 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 705 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 706 707 /* set ucode instruction cache boundary to 2M-1 */ 708 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 709 710 /* set ucode data firmware address */ 711 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 712 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 713 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 714 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 715 716 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 717 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 718 719 if (prime_icache) { 720 /* invalidate ICACHE */ 721 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 722 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 723 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 724 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 725 726 /* prime the ICACHE. */ 727 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 728 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 729 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 730 } 731 732 soc21_grbm_select(adev, 0, 0, 0, 0); 733 mutex_unlock(&adev->srbm_mutex); 734 735 return 0; 736 } 737 738 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 739 enum admgpu_mes_pipe pipe) 740 { 741 int r; 742 u32 *eop; 743 744 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 745 AMDGPU_GEM_DOMAIN_GTT, 746 &adev->mes.eop_gpu_obj[pipe], 747 &adev->mes.eop_gpu_addr[pipe], 748 (void **)&eop); 749 if (r) { 750 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 751 return r; 752 } 753 754 memset(eop, 0, 755 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 756 757 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 758 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 759 760 return 0; 761 } 762 763 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 764 { 765 struct v11_compute_mqd *mqd = ring->mqd_ptr; 766 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 767 uint32_t tmp; 768 769 mqd->header = 0xC0310800; 770 mqd->compute_pipelinestat_enable = 0x00000001; 771 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 772 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 773 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 774 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 775 mqd->compute_misc_reserved = 0x00000007; 776 777 eop_base_addr = ring->eop_gpu_addr >> 8; 778 779 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 780 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 781 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 782 (order_base_2(MES_EOP_SIZE / 4) - 1)); 783 784 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 785 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 786 mqd->cp_hqd_eop_control = tmp; 787 788 /* disable the queue if it's active */ 789 ring->wptr = 0; 790 mqd->cp_hqd_pq_rptr = 0; 791 mqd->cp_hqd_pq_wptr_lo = 0; 792 mqd->cp_hqd_pq_wptr_hi = 0; 793 794 /* set the pointer to the MQD */ 795 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 796 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 797 798 /* set MQD vmid to 0 */ 799 tmp = regCP_MQD_CONTROL_DEFAULT; 800 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 801 mqd->cp_mqd_control = tmp; 802 803 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 804 hqd_gpu_addr = ring->gpu_addr >> 8; 805 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 806 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 807 808 /* set the wb address whether it's enabled or not */ 809 wb_gpu_addr = ring->rptr_gpu_addr; 810 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 811 mqd->cp_hqd_pq_rptr_report_addr_hi = 812 upper_32_bits(wb_gpu_addr) & 0xffff; 813 814 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 815 wb_gpu_addr = ring->wptr_gpu_addr; 816 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 817 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 818 819 /* set up the HQD, this is similar to CP_RB0_CNTL */ 820 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 821 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 822 (order_base_2(ring->ring_size / 4) - 1)); 823 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 824 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 825 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 826 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 827 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 828 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 829 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 830 mqd->cp_hqd_pq_control = tmp; 831 832 /* enable doorbell */ 833 tmp = 0; 834 if (ring->use_doorbell) { 835 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 836 DOORBELL_OFFSET, ring->doorbell_index); 837 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 838 DOORBELL_EN, 1); 839 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 840 DOORBELL_SOURCE, 0); 841 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 842 DOORBELL_HIT, 0); 843 } 844 else 845 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 846 DOORBELL_EN, 0); 847 mqd->cp_hqd_pq_doorbell_control = tmp; 848 849 mqd->cp_hqd_vmid = 0; 850 /* activate the queue */ 851 mqd->cp_hqd_active = 1; 852 853 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 854 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 855 PRELOAD_SIZE, 0x55); 856 mqd->cp_hqd_persistent_state = tmp; 857 858 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 859 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 860 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 861 862 return 0; 863 } 864 865 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 866 { 867 struct v11_compute_mqd *mqd = ring->mqd_ptr; 868 struct amdgpu_device *adev = ring->adev; 869 uint32_t data = 0; 870 871 mutex_lock(&adev->srbm_mutex); 872 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 873 874 /* set CP_HQD_VMID.VMID = 0. */ 875 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 876 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 877 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 878 879 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 880 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 881 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 882 DOORBELL_EN, 0); 883 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 884 885 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 886 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 887 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 888 889 /* set CP_MQD_CONTROL.VMID=0 */ 890 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 891 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 892 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 893 894 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 895 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 896 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 897 898 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 899 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 900 mqd->cp_hqd_pq_rptr_report_addr_lo); 901 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 902 mqd->cp_hqd_pq_rptr_report_addr_hi); 903 904 /* set CP_HQD_PQ_CONTROL */ 905 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 906 907 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 908 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 909 mqd->cp_hqd_pq_wptr_poll_addr_lo); 910 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 911 mqd->cp_hqd_pq_wptr_poll_addr_hi); 912 913 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 914 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 915 mqd->cp_hqd_pq_doorbell_control); 916 917 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 918 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 919 920 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 921 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 922 923 soc21_grbm_select(adev, 0, 0, 0, 0); 924 mutex_unlock(&adev->srbm_mutex); 925 } 926 927 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 928 { 929 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 930 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 931 int r; 932 933 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 934 return -EINVAL; 935 936 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 937 if (r) { 938 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 939 return r; 940 } 941 942 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 943 944 r = amdgpu_ring_test_ring(kiq_ring); 945 if (r) { 946 DRM_ERROR("kfq enable failed\n"); 947 kiq_ring->sched.ready = false; 948 } 949 return r; 950 } 951 952 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 953 enum admgpu_mes_pipe pipe) 954 { 955 struct amdgpu_ring *ring; 956 int r; 957 958 if (pipe == AMDGPU_MES_KIQ_PIPE) 959 ring = &adev->gfx.kiq.ring; 960 else if (pipe == AMDGPU_MES_SCHED_PIPE) 961 ring = &adev->mes.ring; 962 else 963 BUG(); 964 965 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 966 (amdgpu_in_reset(adev) || adev->in_suspend)) { 967 *(ring->wptr_cpu_addr) = 0; 968 *(ring->rptr_cpu_addr) = 0; 969 amdgpu_ring_clear_ring(ring); 970 } 971 972 r = mes_v11_0_mqd_init(ring); 973 if (r) 974 return r; 975 976 if (pipe == AMDGPU_MES_SCHED_PIPE) { 977 r = mes_v11_0_kiq_enable_queue(adev); 978 if (r) 979 return r; 980 } else { 981 mes_v11_0_queue_init_register(ring); 982 } 983 984 /* get MES scheduler/KIQ versions */ 985 mutex_lock(&adev->srbm_mutex); 986 soc21_grbm_select(adev, 3, pipe, 0, 0); 987 988 if (pipe == AMDGPU_MES_SCHED_PIPE) 989 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 990 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 991 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 992 993 soc21_grbm_select(adev, 0, 0, 0, 0); 994 mutex_unlock(&adev->srbm_mutex); 995 996 return 0; 997 } 998 999 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 1000 { 1001 struct amdgpu_ring *ring; 1002 1003 ring = &adev->mes.ring; 1004 1005 ring->funcs = &mes_v11_0_ring_funcs; 1006 1007 ring->me = 3; 1008 ring->pipe = 0; 1009 ring->queue = 0; 1010 1011 ring->ring_obj = NULL; 1012 ring->use_doorbell = true; 1013 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 1014 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 1015 ring->no_scheduler = true; 1016 snprintf(ring->name, sizeof(ring->name), "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1017 1018 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1019 AMDGPU_RING_PRIO_DEFAULT, NULL); 1020 } 1021 1022 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 1023 { 1024 struct amdgpu_ring *ring; 1025 1026 mtx_init(&adev->gfx.kiq.ring_lock, IPL_TTY); 1027 1028 ring = &adev->gfx.kiq.ring; 1029 1030 ring->me = 3; 1031 ring->pipe = 1; 1032 ring->queue = 0; 1033 1034 ring->adev = NULL; 1035 ring->ring_obj = NULL; 1036 ring->use_doorbell = true; 1037 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 1038 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 1039 ring->no_scheduler = true; 1040 snprintf(ring->name, sizeof(ring->name), "mes_kiq_%d.%d.%d", 1041 ring->me, ring->pipe, ring->queue); 1042 1043 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 1044 AMDGPU_RING_PRIO_DEFAULT, NULL); 1045 } 1046 1047 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 1048 enum admgpu_mes_pipe pipe) 1049 { 1050 int r, mqd_size = sizeof(struct v11_compute_mqd); 1051 struct amdgpu_ring *ring; 1052 1053 if (pipe == AMDGPU_MES_KIQ_PIPE) 1054 ring = &adev->gfx.kiq.ring; 1055 else if (pipe == AMDGPU_MES_SCHED_PIPE) 1056 ring = &adev->mes.ring; 1057 else 1058 BUG(); 1059 1060 if (ring->mqd_obj) 1061 return 0; 1062 1063 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 1064 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 1065 &ring->mqd_gpu_addr, &ring->mqd_ptr); 1066 if (r) { 1067 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 1068 return r; 1069 } 1070 1071 memset(ring->mqd_ptr, 0, mqd_size); 1072 1073 /* prepare MQD backup */ 1074 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 1075 if (!adev->mes.mqd_backup[pipe]) 1076 dev_warn(adev->dev, 1077 "no memory to create MQD backup for ring %s\n", 1078 ring->name); 1079 1080 return 0; 1081 } 1082 1083 static int mes_v11_0_sw_init(void *handle) 1084 { 1085 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1086 int pipe, r; 1087 1088 adev->mes.adev = adev; 1089 adev->mes.funcs = &mes_v11_0_funcs; 1090 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1091 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1092 1093 r = amdgpu_mes_init(adev); 1094 if (r) 1095 return r; 1096 1097 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1098 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1099 continue; 1100 1101 r = mes_v11_0_init_microcode(adev, pipe); 1102 if (r) 1103 return r; 1104 1105 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1106 if (r) 1107 return r; 1108 1109 r = mes_v11_0_mqd_sw_init(adev, pipe); 1110 if (r) 1111 return r; 1112 } 1113 1114 if (adev->enable_mes_kiq) { 1115 r = mes_v11_0_kiq_ring_init(adev); 1116 if (r) 1117 return r; 1118 } 1119 1120 r = mes_v11_0_ring_init(adev); 1121 if (r) 1122 return r; 1123 1124 return 0; 1125 } 1126 1127 static int mes_v11_0_sw_fini(void *handle) 1128 { 1129 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1130 int pipe; 1131 1132 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1133 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1134 1135 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1136 kfree(adev->mes.mqd_backup[pipe]); 1137 1138 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1139 &adev->mes.eop_gpu_addr[pipe], 1140 NULL); 1141 1142 mes_v11_0_free_microcode(adev, pipe); 1143 } 1144 1145 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1146 &adev->gfx.kiq.ring.mqd_gpu_addr, 1147 &adev->gfx.kiq.ring.mqd_ptr); 1148 1149 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1150 &adev->mes.ring.mqd_gpu_addr, 1151 &adev->mes.ring.mqd_ptr); 1152 1153 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1154 amdgpu_ring_fini(&adev->mes.ring); 1155 1156 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1157 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1158 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1159 } 1160 1161 amdgpu_mes_fini(adev); 1162 return 0; 1163 } 1164 1165 static void mes_v11_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1166 { 1167 uint32_t data; 1168 int i; 1169 1170 mutex_lock(&adev->srbm_mutex); 1171 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1172 1173 /* disable the queue if it's active */ 1174 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1175 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1176 for (i = 0; i < adev->usec_timeout; i++) { 1177 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1178 break; 1179 udelay(1); 1180 } 1181 } 1182 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1183 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1184 DOORBELL_EN, 0); 1185 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1186 DOORBELL_HIT, 1); 1187 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1188 1189 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1190 1191 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1192 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1193 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1194 1195 soc21_grbm_select(adev, 0, 0, 0, 0); 1196 mutex_unlock(&adev->srbm_mutex); 1197 1198 adev->mes.ring.sched.ready = false; 1199 } 1200 1201 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1202 { 1203 uint32_t tmp; 1204 struct amdgpu_device *adev = ring->adev; 1205 1206 /* tell RLC which is KIQ queue */ 1207 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1208 tmp &= 0xffffff00; 1209 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1210 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1211 tmp |= 0x80; 1212 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1213 } 1214 1215 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1216 { 1217 int r = 0; 1218 1219 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1220 1221 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1222 if (r) { 1223 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1224 return r; 1225 } 1226 1227 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1228 if (r) { 1229 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1230 return r; 1231 } 1232 1233 } 1234 1235 mes_v11_0_enable(adev, true); 1236 1237 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1238 1239 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1240 if (r) 1241 goto failure; 1242 1243 return r; 1244 1245 failure: 1246 mes_v11_0_hw_fini(adev); 1247 return r; 1248 } 1249 1250 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1251 { 1252 if (adev->mes.ring.sched.ready) 1253 mes_v11_0_kiq_dequeue_sched(adev); 1254 1255 mes_v11_0_enable(adev, false); 1256 return 0; 1257 } 1258 1259 static int mes_v11_0_hw_init(void *handle) 1260 { 1261 int r; 1262 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1263 1264 if (!adev->enable_mes_kiq) { 1265 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1266 r = mes_v11_0_load_microcode(adev, 1267 AMDGPU_MES_SCHED_PIPE, true); 1268 if (r) { 1269 DRM_ERROR("failed to MES fw, r=%d\n", r); 1270 return r; 1271 } 1272 } 1273 1274 mes_v11_0_enable(adev, true); 1275 } 1276 1277 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1278 if (r) 1279 goto failure; 1280 1281 r = mes_v11_0_set_hw_resources(&adev->mes); 1282 if (r) 1283 goto failure; 1284 1285 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1286 1287 r = mes_v11_0_query_sched_status(&adev->mes); 1288 if (r) { 1289 DRM_ERROR("MES is busy\n"); 1290 goto failure; 1291 } 1292 1293 /* 1294 * Disable KIQ ring usage from the driver once MES is enabled. 1295 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1296 * with MES enabled. 1297 */ 1298 adev->gfx.kiq.ring.sched.ready = false; 1299 adev->mes.ring.sched.ready = true; 1300 1301 return 0; 1302 1303 failure: 1304 mes_v11_0_hw_fini(adev); 1305 return r; 1306 } 1307 1308 static int mes_v11_0_hw_fini(void *handle) 1309 { 1310 return 0; 1311 } 1312 1313 static int mes_v11_0_suspend(void *handle) 1314 { 1315 int r; 1316 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1317 1318 r = amdgpu_mes_suspend(adev); 1319 if (r) 1320 return r; 1321 1322 return mes_v11_0_hw_fini(adev); 1323 } 1324 1325 static int mes_v11_0_resume(void *handle) 1326 { 1327 int r; 1328 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1329 1330 r = mes_v11_0_hw_init(adev); 1331 if (r) 1332 return r; 1333 1334 return amdgpu_mes_resume(adev); 1335 } 1336 1337 static int mes_v11_0_late_init(void *handle) 1338 { 1339 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1340 1341 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1342 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1343 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))) 1344 amdgpu_mes_self_test(adev); 1345 1346 return 0; 1347 } 1348 1349 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1350 .name = "mes_v11_0", 1351 .late_init = mes_v11_0_late_init, 1352 .sw_init = mes_v11_0_sw_init, 1353 .sw_fini = mes_v11_0_sw_fini, 1354 .hw_init = mes_v11_0_hw_init, 1355 .hw_fini = mes_v11_0_hw_fini, 1356 .suspend = mes_v11_0_suspend, 1357 .resume = mes_v11_0_resume, 1358 }; 1359 1360 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1361 .type = AMD_IP_BLOCK_TYPE_MES, 1362 .major = 11, 1363 .minor = 0, 1364 .rev = 0, 1365 .funcs = &mes_v11_0_ip_funcs, 1366 }; 1367