1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "soc21.h" 29 #include "gc/gc_11_0_0_offset.h" 30 #include "gc/gc_11_0_0_sh_mask.h" 31 #include "gc/gc_11_0_0_default.h" 32 #include "v11_structs.h" 33 #include "mes_v11_api_def.h" 34 35 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); 36 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes1.bin"); 37 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes.bin"); 38 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mes1.bin"); 39 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes.bin"); 40 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mes1.bin"); 41 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mes1.bin"); 43 44 static int mes_v11_0_hw_fini(void *handle); 45 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); 46 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); 47 48 #define MES_EOP_SIZE 2048 49 50 static void mes_v11_0_ring_set_wptr(struct amdgpu_ring *ring) 51 { 52 struct amdgpu_device *adev = ring->adev; 53 54 if (ring->use_doorbell) { 55 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 56 ring->wptr); 57 WDOORBELL64(ring->doorbell_index, ring->wptr); 58 } else { 59 BUG(); 60 } 61 } 62 63 static u64 mes_v11_0_ring_get_rptr(struct amdgpu_ring *ring) 64 { 65 return *ring->rptr_cpu_addr; 66 } 67 68 static u64 mes_v11_0_ring_get_wptr(struct amdgpu_ring *ring) 69 { 70 u64 wptr; 71 72 if (ring->use_doorbell) 73 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 74 else 75 BUG(); 76 return wptr; 77 } 78 79 static const struct amdgpu_ring_funcs mes_v11_0_ring_funcs = { 80 .type = AMDGPU_RING_TYPE_MES, 81 .align_mask = 1, 82 .nop = 0, 83 .support_64bit_ptrs = true, 84 .get_rptr = mes_v11_0_ring_get_rptr, 85 .get_wptr = mes_v11_0_ring_get_wptr, 86 .set_wptr = mes_v11_0_ring_set_wptr, 87 .insert_nop = amdgpu_ring_insert_nop, 88 }; 89 90 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 91 void *pkt, int size, 92 int api_status_off) 93 { 94 int ndw = size / 4; 95 signed long r; 96 union MESAPI__ADD_QUEUE *x_pkt = pkt; 97 struct MES_API_STATUS *api_status; 98 struct amdgpu_device *adev = mes->adev; 99 struct amdgpu_ring *ring = &mes->ring; 100 unsigned long flags; 101 signed long timeout = adev->usec_timeout; 102 103 if (amdgpu_emu_mode) { 104 timeout *= 100; 105 } else if (amdgpu_sriov_vf(adev)) { 106 /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */ 107 timeout = 15 * 600 * 1000; 108 } 109 BUG_ON(size % 4 != 0); 110 111 spin_lock_irqsave(&mes->ring_lock, flags); 112 if (amdgpu_ring_alloc(ring, ndw)) { 113 spin_unlock_irqrestore(&mes->ring_lock, flags); 114 return -ENOMEM; 115 } 116 117 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 118 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 119 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 120 121 amdgpu_ring_write_multiple(ring, pkt, ndw); 122 amdgpu_ring_commit(ring); 123 spin_unlock_irqrestore(&mes->ring_lock, flags); 124 125 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 126 127 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 128 timeout); 129 if (r < 1) { 130 DRM_ERROR("MES failed to response msg=%d\n", 131 x_pkt->header.opcode); 132 return -ETIMEDOUT; 133 } 134 135 return 0; 136 } 137 138 static int convert_to_mes_queue_type(int queue_type) 139 { 140 if (queue_type == AMDGPU_RING_TYPE_GFX) 141 return MES_QUEUE_TYPE_GFX; 142 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 143 return MES_QUEUE_TYPE_COMPUTE; 144 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 145 return MES_QUEUE_TYPE_SDMA; 146 else 147 BUG(); 148 return -1; 149 } 150 151 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, 152 struct mes_add_queue_input *input) 153 { 154 struct amdgpu_device *adev = mes->adev; 155 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 156 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 157 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 158 159 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 160 161 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 162 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 163 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 164 165 mes_add_queue_pkt.process_id = input->process_id; 166 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 167 mes_add_queue_pkt.process_va_start = input->process_va_start; 168 mes_add_queue_pkt.process_va_end = input->process_va_end; 169 mes_add_queue_pkt.process_quantum = input->process_quantum; 170 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 171 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 172 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 173 mes_add_queue_pkt.inprocess_gang_priority = 174 input->inprocess_gang_priority; 175 mes_add_queue_pkt.gang_global_priority_level = 176 input->gang_global_priority_level; 177 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 178 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 179 180 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> 181 AMDGPU_MES_API_VERSION_SHIFT) >= 2) 182 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; 183 else 184 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 185 186 mes_add_queue_pkt.queue_type = 187 convert_to_mes_queue_type(input->queue_type); 188 mes_add_queue_pkt.paging = input->paging; 189 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 190 mes_add_queue_pkt.gws_base = input->gws_base; 191 mes_add_queue_pkt.gws_size = input->gws_size; 192 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 193 mes_add_queue_pkt.tma_addr = input->tma_addr; 194 mes_add_queue_pkt.is_kfd_process = input->is_kfd_process; 195 196 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 197 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 198 mes_add_queue_pkt.gds_size = input->queue_size; 199 200 if (!(((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 4) && 201 (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) && 202 (adev->ip_versions[GC_HWIP][0] <= IP_VERSION(11, 0, 3)))) 203 mes_add_queue_pkt.trap_en = 1; 204 205 /* For KFD, gds_size is re-used for queue size (needed in MES for AQL queues) */ 206 mes_add_queue_pkt.is_aql_queue = input->is_aql_queue; 207 mes_add_queue_pkt.gds_size = input->queue_size; 208 209 return mes_v11_0_submit_pkt_and_poll_completion(mes, 210 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 211 offsetof(union MESAPI__ADD_QUEUE, api_status)); 212 } 213 214 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, 215 struct mes_remove_queue_input *input) 216 { 217 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 218 219 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 220 221 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 222 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 223 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 224 225 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 226 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 227 228 return mes_v11_0_submit_pkt_and_poll_completion(mes, 229 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 230 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 231 } 232 233 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, 234 struct mes_unmap_legacy_queue_input *input) 235 { 236 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 237 238 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 239 240 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 241 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 242 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 243 244 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 245 mes_remove_queue_pkt.gang_context_addr = 0; 246 247 mes_remove_queue_pkt.pipe_id = input->pipe_id; 248 mes_remove_queue_pkt.queue_id = input->queue_id; 249 250 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 251 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 252 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 253 mes_remove_queue_pkt.tf_data = 254 lower_32_bits(input->trail_fence_data); 255 } else { 256 mes_remove_queue_pkt.unmap_legacy_queue = 1; 257 mes_remove_queue_pkt.queue_type = 258 convert_to_mes_queue_type(input->queue_type); 259 } 260 261 return mes_v11_0_submit_pkt_and_poll_completion(mes, 262 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 263 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 264 } 265 266 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, 267 struct mes_suspend_gang_input *input) 268 { 269 return 0; 270 } 271 272 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, 273 struct mes_resume_gang_input *input) 274 { 275 return 0; 276 } 277 278 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) 279 { 280 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 281 282 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 283 284 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 285 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 286 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 287 288 return mes_v11_0_submit_pkt_and_poll_completion(mes, 289 &mes_status_pkt, sizeof(mes_status_pkt), 290 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 291 } 292 293 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, 294 struct mes_misc_op_input *input) 295 { 296 union MESAPI__MISC misc_pkt; 297 298 memset(&misc_pkt, 0, sizeof(misc_pkt)); 299 300 misc_pkt.header.type = MES_API_TYPE_SCHEDULER; 301 misc_pkt.header.opcode = MES_SCH_API_MISC; 302 misc_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 303 304 switch (input->op) { 305 case MES_MISC_OP_READ_REG: 306 misc_pkt.opcode = MESAPI_MISC__READ_REG; 307 misc_pkt.read_reg.reg_offset = input->read_reg.reg_offset; 308 misc_pkt.read_reg.buffer_addr = input->read_reg.buffer_addr; 309 break; 310 case MES_MISC_OP_WRITE_REG: 311 misc_pkt.opcode = MESAPI_MISC__WRITE_REG; 312 misc_pkt.write_reg.reg_offset = input->write_reg.reg_offset; 313 misc_pkt.write_reg.reg_value = input->write_reg.reg_value; 314 break; 315 case MES_MISC_OP_WRM_REG_WAIT: 316 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 317 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WAIT_REG_MEM; 318 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 319 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 320 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 321 misc_pkt.wait_reg_mem.reg_offset2 = 0; 322 break; 323 case MES_MISC_OP_WRM_REG_WR_WAIT: 324 misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; 325 misc_pkt.wait_reg_mem.op = WRM_OPERATION__WR_WAIT_WR_REG; 326 misc_pkt.wait_reg_mem.reference = input->wrm_reg.ref; 327 misc_pkt.wait_reg_mem.mask = input->wrm_reg.mask; 328 misc_pkt.wait_reg_mem.reg_offset1 = input->wrm_reg.reg0; 329 misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; 330 break; 331 default: 332 DRM_ERROR("unsupported misc op (%d) \n", input->op); 333 return -EINVAL; 334 } 335 336 return mes_v11_0_submit_pkt_and_poll_completion(mes, 337 &misc_pkt, sizeof(misc_pkt), 338 offsetof(union MESAPI__MISC, api_status)); 339 } 340 341 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) 342 { 343 int i; 344 struct amdgpu_device *adev = mes->adev; 345 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 346 347 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 348 349 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 350 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 351 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 352 353 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 354 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 355 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 356 mes_set_hw_res_pkt.paging_vmid = 0; 357 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 358 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 359 mes->query_status_fence_gpu_addr; 360 361 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 362 mes_set_hw_res_pkt.compute_hqd_mask[i] = 363 mes->compute_hqd_mask[i]; 364 365 for (i = 0; i < MAX_GFX_PIPES; i++) 366 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 367 368 for (i = 0; i < MAX_SDMA_PIPES; i++) 369 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 370 371 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 372 mes_set_hw_res_pkt.aggregated_doorbells[i] = 373 mes->aggregated_doorbells[i]; 374 375 for (i = 0; i < 5; i++) { 376 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 377 mes_set_hw_res_pkt.mmhub_base[i] = 378 adev->reg_offset[MMHUB_HWIP][0][i]; 379 mes_set_hw_res_pkt.osssys_base[i] = 380 adev->reg_offset[OSSSYS_HWIP][0][i]; 381 } 382 383 mes_set_hw_res_pkt.disable_reset = 1; 384 mes_set_hw_res_pkt.disable_mes_log = 1; 385 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 386 mes_set_hw_res_pkt.oversubscription_timer = 50; 387 388 return mes_v11_0_submit_pkt_and_poll_completion(mes, 389 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 390 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 391 } 392 393 static void mes_v11_0_init_aggregated_doorbell(struct amdgpu_mes *mes) 394 { 395 struct amdgpu_device *adev = mes->adev; 396 uint32_t data; 397 398 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1); 399 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 400 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 401 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 402 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 403 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 404 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 405 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL1, data); 406 407 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2); 408 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 409 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 410 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 411 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 412 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 413 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 414 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL2, data); 415 416 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3); 417 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 418 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 419 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 420 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 421 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 422 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 423 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL3, data); 424 425 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4); 426 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 427 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 428 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 429 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 430 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 431 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 432 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL4, data); 433 434 data = RREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5); 435 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 436 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 437 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 438 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 439 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 440 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 441 WREG32_SOC15(GC, 0, regCP_MES_DOORBELL_CONTROL5, data); 442 443 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 444 WREG32_SOC15(GC, 0, regCP_HQD_GFX_CONTROL, data); 445 } 446 447 static const struct amdgpu_mes_funcs mes_v11_0_funcs = { 448 .add_hw_queue = mes_v11_0_add_hw_queue, 449 .remove_hw_queue = mes_v11_0_remove_hw_queue, 450 .unmap_legacy_queue = mes_v11_0_unmap_legacy_queue, 451 .suspend_gang = mes_v11_0_suspend_gang, 452 .resume_gang = mes_v11_0_resume_gang, 453 .misc_op = mes_v11_0_misc_op, 454 }; 455 456 static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, 457 enum admgpu_mes_pipe pipe) 458 { 459 int r; 460 const struct mes_firmware_header_v1_0 *mes_hdr; 461 const __le32 *fw_data; 462 unsigned fw_size; 463 464 mes_hdr = (const struct mes_firmware_header_v1_0 *) 465 adev->mes.fw[pipe]->data; 466 467 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 468 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 469 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 470 471 r = amdgpu_bo_create_reserved(adev, fw_size, 472 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 473 &adev->mes.ucode_fw_obj[pipe], 474 &adev->mes.ucode_fw_gpu_addr[pipe], 475 (void **)&adev->mes.ucode_fw_ptr[pipe]); 476 if (r) { 477 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 478 return r; 479 } 480 481 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 482 483 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 484 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 485 486 return 0; 487 } 488 489 static int mes_v11_0_allocate_ucode_data_buffer(struct amdgpu_device *adev, 490 enum admgpu_mes_pipe pipe) 491 { 492 int r; 493 const struct mes_firmware_header_v1_0 *mes_hdr; 494 const __le32 *fw_data; 495 unsigned fw_size; 496 497 mes_hdr = (const struct mes_firmware_header_v1_0 *) 498 adev->mes.fw[pipe]->data; 499 500 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 501 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 502 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 503 504 r = amdgpu_bo_create_reserved(adev, fw_size, 505 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 506 &adev->mes.data_fw_obj[pipe], 507 &adev->mes.data_fw_gpu_addr[pipe], 508 (void **)&adev->mes.data_fw_ptr[pipe]); 509 if (r) { 510 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 511 return r; 512 } 513 514 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 515 516 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 517 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 518 519 return 0; 520 } 521 522 static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, 523 enum admgpu_mes_pipe pipe) 524 { 525 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 526 &adev->mes.data_fw_gpu_addr[pipe], 527 (void **)&adev->mes.data_fw_ptr[pipe]); 528 529 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 530 &adev->mes.ucode_fw_gpu_addr[pipe], 531 (void **)&adev->mes.ucode_fw_ptr[pipe]); 532 } 533 534 static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) 535 { 536 uint64_t ucode_addr; 537 uint32_t pipe, data = 0; 538 539 if (enable) { 540 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 541 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 542 data = REG_SET_FIELD(data, CP_MES_CNTL, 543 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 544 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 545 546 mutex_lock(&adev->srbm_mutex); 547 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 548 if (!adev->enable_mes_kiq && 549 pipe == AMDGPU_MES_KIQ_PIPE) 550 continue; 551 552 soc21_grbm_select(adev, 3, pipe, 0, 0); 553 554 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 555 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 556 lower_32_bits(ucode_addr)); 557 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 558 upper_32_bits(ucode_addr)); 559 } 560 soc21_grbm_select(adev, 0, 0, 0, 0); 561 mutex_unlock(&adev->srbm_mutex); 562 563 /* unhalt MES and activate pipe0 */ 564 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 565 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 566 adev->enable_mes_kiq ? 1 : 0); 567 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 568 569 if (amdgpu_emu_mode) 570 drm_msleep(100); 571 else 572 udelay(50); 573 } else { 574 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); 575 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 576 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 577 data = REG_SET_FIELD(data, CP_MES_CNTL, 578 MES_INVALIDATE_ICACHE, 1); 579 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 580 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 581 adev->enable_mes_kiq ? 1 : 0); 582 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 583 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); 584 } 585 } 586 587 /* This function is for backdoor MES firmware */ 588 static int mes_v11_0_load_microcode(struct amdgpu_device *adev, 589 enum admgpu_mes_pipe pipe, bool prime_icache) 590 { 591 int r; 592 uint32_t data; 593 uint64_t ucode_addr; 594 595 mes_v11_0_enable(adev, false); 596 597 if (!adev->mes.fw[pipe]) 598 return -EINVAL; 599 600 r = mes_v11_0_allocate_ucode_buffer(adev, pipe); 601 if (r) 602 return r; 603 604 r = mes_v11_0_allocate_ucode_data_buffer(adev, pipe); 605 if (r) { 606 mes_v11_0_free_ucode_buffers(adev, pipe); 607 return r; 608 } 609 610 mutex_lock(&adev->srbm_mutex); 611 /* me=3, pipe=0, queue=0 */ 612 soc21_grbm_select(adev, 3, pipe, 0, 0); 613 614 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); 615 616 /* set ucode start address */ 617 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; 618 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, 619 lower_32_bits(ucode_addr)); 620 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, 621 upper_32_bits(ucode_addr)); 622 623 /* set ucode fimrware address */ 624 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, 625 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 626 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, 627 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 628 629 /* set ucode instruction cache boundary to 2M-1 */ 630 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); 631 632 /* set ucode data firmware address */ 633 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, 634 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 635 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, 636 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 637 638 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 639 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x3FFFF); 640 641 if (prime_icache) { 642 /* invalidate ICACHE */ 643 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 644 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 645 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 646 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 647 648 /* prime the ICACHE. */ 649 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); 650 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 651 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); 652 } 653 654 soc21_grbm_select(adev, 0, 0, 0, 0); 655 mutex_unlock(&adev->srbm_mutex); 656 657 return 0; 658 } 659 660 static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, 661 enum admgpu_mes_pipe pipe) 662 { 663 int r; 664 u32 *eop; 665 666 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 667 AMDGPU_GEM_DOMAIN_GTT, 668 &adev->mes.eop_gpu_obj[pipe], 669 &adev->mes.eop_gpu_addr[pipe], 670 (void **)&eop); 671 if (r) { 672 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 673 return r; 674 } 675 676 memset(eop, 0, 677 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 678 679 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 680 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 681 682 return 0; 683 } 684 685 static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) 686 { 687 struct v11_compute_mqd *mqd = ring->mqd_ptr; 688 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 689 uint32_t tmp; 690 691 mqd->header = 0xC0310800; 692 mqd->compute_pipelinestat_enable = 0x00000001; 693 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 694 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 695 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 696 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 697 mqd->compute_misc_reserved = 0x00000007; 698 699 eop_base_addr = ring->eop_gpu_addr >> 8; 700 701 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 702 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 703 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 704 (order_base_2(MES_EOP_SIZE / 4) - 1)); 705 706 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 707 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 708 mqd->cp_hqd_eop_control = tmp; 709 710 /* disable the queue if it's active */ 711 ring->wptr = 0; 712 mqd->cp_hqd_pq_rptr = 0; 713 mqd->cp_hqd_pq_wptr_lo = 0; 714 mqd->cp_hqd_pq_wptr_hi = 0; 715 716 /* set the pointer to the MQD */ 717 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 718 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 719 720 /* set MQD vmid to 0 */ 721 tmp = regCP_MQD_CONTROL_DEFAULT; 722 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 723 mqd->cp_mqd_control = tmp; 724 725 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 726 hqd_gpu_addr = ring->gpu_addr >> 8; 727 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 728 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 729 730 /* set the wb address whether it's enabled or not */ 731 wb_gpu_addr = ring->rptr_gpu_addr; 732 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 733 mqd->cp_hqd_pq_rptr_report_addr_hi = 734 upper_32_bits(wb_gpu_addr) & 0xffff; 735 736 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 737 wb_gpu_addr = ring->wptr_gpu_addr; 738 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 739 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 740 741 /* set up the HQD, this is similar to CP_RB0_CNTL */ 742 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 743 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 744 (order_base_2(ring->ring_size / 4) - 1)); 745 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 746 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 747 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 748 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 749 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 750 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 751 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 752 mqd->cp_hqd_pq_control = tmp; 753 754 /* enable doorbell */ 755 tmp = 0; 756 if (ring->use_doorbell) { 757 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 758 DOORBELL_OFFSET, ring->doorbell_index); 759 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 760 DOORBELL_EN, 1); 761 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 762 DOORBELL_SOURCE, 0); 763 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 764 DOORBELL_HIT, 0); 765 } 766 else 767 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 768 DOORBELL_EN, 0); 769 mqd->cp_hqd_pq_doorbell_control = tmp; 770 771 mqd->cp_hqd_vmid = 0; 772 /* activate the queue */ 773 mqd->cp_hqd_active = 1; 774 775 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 776 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, 777 PRELOAD_SIZE, 0x55); 778 mqd->cp_hqd_persistent_state = tmp; 779 780 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; 781 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; 782 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; 783 784 return 0; 785 } 786 787 static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) 788 { 789 struct v11_compute_mqd *mqd = ring->mqd_ptr; 790 struct amdgpu_device *adev = ring->adev; 791 uint32_t data = 0; 792 793 mutex_lock(&adev->srbm_mutex); 794 soc21_grbm_select(adev, 3, ring->pipe, 0, 0); 795 796 /* set CP_HQD_VMID.VMID = 0. */ 797 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); 798 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 799 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); 800 801 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 802 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 803 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 804 DOORBELL_EN, 0); 805 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 806 807 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 808 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 809 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 810 811 /* set CP_MQD_CONTROL.VMID=0 */ 812 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); 813 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 814 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); 815 816 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 817 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 818 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 819 820 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 821 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, 822 mqd->cp_hqd_pq_rptr_report_addr_lo); 823 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 824 mqd->cp_hqd_pq_rptr_report_addr_hi); 825 826 /* set CP_HQD_PQ_CONTROL */ 827 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 828 829 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 830 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, 831 mqd->cp_hqd_pq_wptr_poll_addr_lo); 832 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, 833 mqd->cp_hqd_pq_wptr_poll_addr_hi); 834 835 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 836 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 837 mqd->cp_hqd_pq_doorbell_control); 838 839 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 840 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 841 842 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 843 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); 844 845 soc21_grbm_select(adev, 0, 0, 0, 0); 846 mutex_unlock(&adev->srbm_mutex); 847 } 848 849 static int mes_v11_0_kiq_enable_queue(struct amdgpu_device *adev) 850 { 851 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 852 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 853 int r; 854 855 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 856 return -EINVAL; 857 858 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 859 if (r) { 860 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 861 return r; 862 } 863 864 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 865 866 r = amdgpu_ring_test_ring(kiq_ring); 867 if (r) { 868 DRM_ERROR("kfq enable failed\n"); 869 kiq_ring->sched.ready = false; 870 } 871 return r; 872 } 873 874 static int mes_v11_0_queue_init(struct amdgpu_device *adev, 875 enum admgpu_mes_pipe pipe) 876 { 877 struct amdgpu_ring *ring; 878 int r; 879 880 if (pipe == AMDGPU_MES_KIQ_PIPE) 881 ring = &adev->gfx.kiq.ring; 882 else if (pipe == AMDGPU_MES_SCHED_PIPE) 883 ring = &adev->mes.ring; 884 else 885 BUG(); 886 887 if ((pipe == AMDGPU_MES_SCHED_PIPE) && 888 (amdgpu_in_reset(adev) || adev->in_suspend)) { 889 *(ring->wptr_cpu_addr) = 0; 890 *(ring->rptr_cpu_addr) = 0; 891 amdgpu_ring_clear_ring(ring); 892 } 893 894 r = mes_v11_0_mqd_init(ring); 895 if (r) 896 return r; 897 898 if (pipe == AMDGPU_MES_SCHED_PIPE) { 899 r = mes_v11_0_kiq_enable_queue(adev); 900 if (r) 901 return r; 902 } else { 903 mes_v11_0_queue_init_register(ring); 904 } 905 906 /* get MES scheduler/KIQ versions */ 907 mutex_lock(&adev->srbm_mutex); 908 soc21_grbm_select(adev, 3, pipe, 0, 0); 909 910 if (pipe == AMDGPU_MES_SCHED_PIPE) 911 adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 912 else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) 913 adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); 914 915 soc21_grbm_select(adev, 0, 0, 0, 0); 916 mutex_unlock(&adev->srbm_mutex); 917 918 return 0; 919 } 920 921 static int mes_v11_0_ring_init(struct amdgpu_device *adev) 922 { 923 struct amdgpu_ring *ring; 924 925 ring = &adev->mes.ring; 926 927 ring->funcs = &mes_v11_0_ring_funcs; 928 929 ring->me = 3; 930 ring->pipe = 0; 931 ring->queue = 0; 932 933 ring->ring_obj = NULL; 934 ring->use_doorbell = true; 935 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 936 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 937 ring->no_scheduler = true; 938 snprintf(ring->name, sizeof(ring->name), "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 939 940 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 941 AMDGPU_RING_PRIO_DEFAULT, NULL); 942 } 943 944 static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) 945 { 946 struct amdgpu_ring *ring; 947 948 mtx_init(&adev->gfx.kiq.ring_lock, IPL_TTY); 949 950 ring = &adev->gfx.kiq.ring; 951 952 ring->me = 3; 953 ring->pipe = 1; 954 ring->queue = 0; 955 956 ring->adev = NULL; 957 ring->ring_obj = NULL; 958 ring->use_doorbell = true; 959 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 960 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 961 ring->no_scheduler = true; 962 snprintf(ring->name, sizeof(ring->name), "mes_kiq_%d.%d.%d", 963 ring->me, ring->pipe, ring->queue); 964 965 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 966 AMDGPU_RING_PRIO_DEFAULT, NULL); 967 } 968 969 static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, 970 enum admgpu_mes_pipe pipe) 971 { 972 int r, mqd_size = sizeof(struct v11_compute_mqd); 973 struct amdgpu_ring *ring; 974 975 if (pipe == AMDGPU_MES_KIQ_PIPE) 976 ring = &adev->gfx.kiq.ring; 977 else if (pipe == AMDGPU_MES_SCHED_PIPE) 978 ring = &adev->mes.ring; 979 else 980 BUG(); 981 982 if (ring->mqd_obj) 983 return 0; 984 985 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 986 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 987 &ring->mqd_gpu_addr, &ring->mqd_ptr); 988 if (r) { 989 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 990 return r; 991 } 992 993 memset(ring->mqd_ptr, 0, mqd_size); 994 995 /* prepare MQD backup */ 996 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 997 if (!adev->mes.mqd_backup[pipe]) 998 dev_warn(adev->dev, 999 "no memory to create MQD backup for ring %s\n", 1000 ring->name); 1001 1002 return 0; 1003 } 1004 1005 static int mes_v11_0_sw_init(void *handle) 1006 { 1007 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1008 int pipe, r; 1009 1010 adev->mes.adev = adev; 1011 adev->mes.funcs = &mes_v11_0_funcs; 1012 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; 1013 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; 1014 1015 r = amdgpu_mes_init(adev); 1016 if (r) 1017 return r; 1018 1019 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1020 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1021 continue; 1022 1023 r = mes_v11_0_allocate_eop_buf(adev, pipe); 1024 if (r) 1025 return r; 1026 1027 r = mes_v11_0_mqd_sw_init(adev, pipe); 1028 if (r) 1029 return r; 1030 } 1031 1032 if (adev->enable_mes_kiq) { 1033 r = mes_v11_0_kiq_ring_init(adev); 1034 if (r) 1035 return r; 1036 } 1037 1038 r = mes_v11_0_ring_init(adev); 1039 if (r) 1040 return r; 1041 1042 return 0; 1043 } 1044 1045 static int mes_v11_0_sw_fini(void *handle) 1046 { 1047 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1048 int pipe; 1049 1050 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 1051 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 1052 1053 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1054 kfree(adev->mes.mqd_backup[pipe]); 1055 1056 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 1057 &adev->mes.eop_gpu_addr[pipe], 1058 NULL); 1059 amdgpu_ucode_release(&adev->mes.fw[pipe]); 1060 } 1061 1062 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 1063 &adev->gfx.kiq.ring.mqd_gpu_addr, 1064 &adev->gfx.kiq.ring.mqd_ptr); 1065 1066 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 1067 &adev->mes.ring.mqd_gpu_addr, 1068 &adev->mes.ring.mqd_ptr); 1069 1070 amdgpu_ring_fini(&adev->gfx.kiq.ring); 1071 amdgpu_ring_fini(&adev->mes.ring); 1072 1073 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1074 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1075 mes_v11_0_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1076 } 1077 1078 amdgpu_mes_fini(adev); 1079 return 0; 1080 } 1081 1082 static void mes_v11_0_kiq_dequeue_sched(struct amdgpu_device *adev) 1083 { 1084 uint32_t data; 1085 int i; 1086 1087 mutex_lock(&adev->srbm_mutex); 1088 soc21_grbm_select(adev, 3, AMDGPU_MES_SCHED_PIPE, 0, 0); 1089 1090 /* disable the queue if it's active */ 1091 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { 1092 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); 1093 for (i = 0; i < adev->usec_timeout; i++) { 1094 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) 1095 break; 1096 udelay(1); 1097 } 1098 } 1099 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); 1100 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1101 DOORBELL_EN, 0); 1102 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 1103 DOORBELL_HIT, 1); 1104 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); 1105 1106 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); 1107 1108 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); 1109 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); 1110 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); 1111 1112 soc21_grbm_select(adev, 0, 0, 0, 0); 1113 mutex_unlock(&adev->srbm_mutex); 1114 1115 adev->mes.ring.sched.ready = false; 1116 } 1117 1118 static void mes_v11_0_kiq_setting(struct amdgpu_ring *ring) 1119 { 1120 uint32_t tmp; 1121 struct amdgpu_device *adev = ring->adev; 1122 1123 /* tell RLC which is KIQ queue */ 1124 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); 1125 tmp &= 0xffffff00; 1126 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1127 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1128 tmp |= 0x80; 1129 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); 1130 } 1131 1132 static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) 1133 { 1134 int r = 0; 1135 1136 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1137 1138 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_SCHED_PIPE, false); 1139 if (r) { 1140 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1141 return r; 1142 } 1143 1144 r = mes_v11_0_load_microcode(adev, AMDGPU_MES_KIQ_PIPE, true); 1145 if (r) { 1146 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1147 return r; 1148 } 1149 1150 } 1151 1152 mes_v11_0_enable(adev, true); 1153 1154 mes_v11_0_kiq_setting(&adev->gfx.kiq.ring); 1155 1156 r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); 1157 if (r) 1158 goto failure; 1159 1160 return r; 1161 1162 failure: 1163 mes_v11_0_hw_fini(adev); 1164 return r; 1165 } 1166 1167 static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) 1168 { 1169 if (adev->mes.ring.sched.ready) 1170 mes_v11_0_kiq_dequeue_sched(adev); 1171 1172 mes_v11_0_enable(adev, false); 1173 return 0; 1174 } 1175 1176 static int mes_v11_0_hw_init(void *handle) 1177 { 1178 int r; 1179 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1180 1181 if (!adev->enable_mes_kiq) { 1182 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1183 r = mes_v11_0_load_microcode(adev, 1184 AMDGPU_MES_SCHED_PIPE, true); 1185 if (r) { 1186 DRM_ERROR("failed to MES fw, r=%d\n", r); 1187 return r; 1188 } 1189 } 1190 1191 mes_v11_0_enable(adev, true); 1192 } 1193 1194 r = mes_v11_0_queue_init(adev, AMDGPU_MES_SCHED_PIPE); 1195 if (r) 1196 goto failure; 1197 1198 r = mes_v11_0_set_hw_resources(&adev->mes); 1199 if (r) 1200 goto failure; 1201 1202 mes_v11_0_init_aggregated_doorbell(&adev->mes); 1203 1204 r = mes_v11_0_query_sched_status(&adev->mes); 1205 if (r) { 1206 DRM_ERROR("MES is busy\n"); 1207 goto failure; 1208 } 1209 1210 /* 1211 * Disable KIQ ring usage from the driver once MES is enabled. 1212 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1213 * with MES enabled. 1214 */ 1215 adev->gfx.kiq.ring.sched.ready = false; 1216 adev->mes.ring.sched.ready = true; 1217 1218 return 0; 1219 1220 failure: 1221 mes_v11_0_hw_fini(adev); 1222 return r; 1223 } 1224 1225 static int mes_v11_0_hw_fini(void *handle) 1226 { 1227 return 0; 1228 } 1229 1230 static int mes_v11_0_suspend(void *handle) 1231 { 1232 int r; 1233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1234 1235 r = amdgpu_mes_suspend(adev); 1236 if (r) 1237 return r; 1238 1239 return mes_v11_0_hw_fini(adev); 1240 } 1241 1242 static int mes_v11_0_resume(void *handle) 1243 { 1244 int r; 1245 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1246 1247 r = mes_v11_0_hw_init(adev); 1248 if (r) 1249 return r; 1250 1251 return amdgpu_mes_resume(adev); 1252 } 1253 1254 static int mes_v11_0_early_init(void *handle) 1255 { 1256 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1257 int pipe, r; 1258 1259 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1260 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1261 continue; 1262 r = amdgpu_mes_init_microcode(adev, pipe); 1263 if (r) 1264 return r; 1265 } 1266 1267 return 0; 1268 } 1269 1270 static int mes_v11_0_late_init(void *handle) 1271 { 1272 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1273 1274 /* it's only intended for use in mes_self_test case, not for s0ix and reset */ 1275 if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && 1276 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(11, 0, 3))) 1277 amdgpu_mes_self_test(adev); 1278 1279 return 0; 1280 } 1281 1282 static const struct amd_ip_funcs mes_v11_0_ip_funcs = { 1283 .name = "mes_v11_0", 1284 .early_init = mes_v11_0_early_init, 1285 .late_init = mes_v11_0_late_init, 1286 .sw_init = mes_v11_0_sw_init, 1287 .sw_fini = mes_v11_0_sw_fini, 1288 .hw_init = mes_v11_0_hw_init, 1289 .hw_fini = mes_v11_0_hw_fini, 1290 .suspend = mes_v11_0_suspend, 1291 .resume = mes_v11_0_resume, 1292 }; 1293 1294 const struct amdgpu_ip_block_version mes_v11_0_ip_block = { 1295 .type = AMD_IP_BLOCK_TYPE_MES, 1296 .major = 11, 1297 .minor = 0, 1298 .rev = 0, 1299 .funcs = &mes_v11_0_ip_funcs, 1300 }; 1301