1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/module.h> 26 #include "amdgpu.h" 27 #include "soc15_common.h" 28 #include "nv.h" 29 #include "gc/gc_10_1_0_offset.h" 30 #include "gc/gc_10_1_0_sh_mask.h" 31 #include "gc/gc_10_1_0_default.h" 32 #include "v10_structs.h" 33 #include "mes_api_def.h" 34 35 #define mmCP_MES_IC_OP_CNTL_Sienna_Cichlid 0x2820 36 #define mmCP_MES_IC_OP_CNTL_Sienna_Cichlid_BASE_IDX 1 37 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 38 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 39 40 MODULE_FIRMWARE("amdgpu/navi10_mes.bin"); 41 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes.bin"); 42 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mes1.bin"); 43 44 static int mes_v10_1_hw_fini(void *handle); 45 static int mes_v10_1_kiq_hw_init(struct amdgpu_device *adev); 46 47 #define MES_EOP_SIZE 2048 48 49 static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring) 50 { 51 struct amdgpu_device *adev = ring->adev; 52 53 if (ring->use_doorbell) { 54 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 55 ring->wptr); 56 WDOORBELL64(ring->doorbell_index, ring->wptr); 57 } else { 58 BUG(); 59 } 60 } 61 62 static u64 mes_v10_1_ring_get_rptr(struct amdgpu_ring *ring) 63 { 64 return *ring->rptr_cpu_addr; 65 } 66 67 static u64 mes_v10_1_ring_get_wptr(struct amdgpu_ring *ring) 68 { 69 u64 wptr; 70 71 if (ring->use_doorbell) 72 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 73 else 74 BUG(); 75 return wptr; 76 } 77 78 static const struct amdgpu_ring_funcs mes_v10_1_ring_funcs = { 79 .type = AMDGPU_RING_TYPE_MES, 80 .align_mask = 1, 81 .nop = 0, 82 .support_64bit_ptrs = true, 83 .get_rptr = mes_v10_1_ring_get_rptr, 84 .get_wptr = mes_v10_1_ring_get_wptr, 85 .set_wptr = mes_v10_1_ring_set_wptr, 86 .insert_nop = amdgpu_ring_insert_nop, 87 }; 88 89 static int mes_v10_1_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, 90 void *pkt, int size, 91 int api_status_off) 92 { 93 int ndw = size / 4; 94 signed long r; 95 union MESAPI__ADD_QUEUE *x_pkt = pkt; 96 struct MES_API_STATUS *api_status; 97 struct amdgpu_device *adev = mes->adev; 98 struct amdgpu_ring *ring = &mes->ring; 99 unsigned long flags; 100 101 BUG_ON(size % 4 != 0); 102 103 spin_lock_irqsave(&mes->ring_lock, flags); 104 if (amdgpu_ring_alloc(ring, ndw)) { 105 spin_unlock_irqrestore(&mes->ring_lock, flags); 106 return -ENOMEM; 107 } 108 109 api_status = (struct MES_API_STATUS *)((char *)pkt + api_status_off); 110 api_status->api_completion_fence_addr = mes->ring.fence_drv.gpu_addr; 111 api_status->api_completion_fence_value = ++mes->ring.fence_drv.sync_seq; 112 113 amdgpu_ring_write_multiple(ring, pkt, ndw); 114 amdgpu_ring_commit(ring); 115 spin_unlock_irqrestore(&mes->ring_lock, flags); 116 117 DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode); 118 119 r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq, 120 adev->usec_timeout); 121 if (r < 1) { 122 DRM_ERROR("MES failed to response msg=%d\n", 123 x_pkt->header.opcode); 124 return -ETIMEDOUT; 125 } 126 127 return 0; 128 } 129 130 static int convert_to_mes_queue_type(int queue_type) 131 { 132 if (queue_type == AMDGPU_RING_TYPE_GFX) 133 return MES_QUEUE_TYPE_GFX; 134 else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) 135 return MES_QUEUE_TYPE_COMPUTE; 136 else if (queue_type == AMDGPU_RING_TYPE_SDMA) 137 return MES_QUEUE_TYPE_SDMA; 138 else 139 BUG(); 140 return -1; 141 } 142 143 static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes, 144 struct mes_add_queue_input *input) 145 { 146 struct amdgpu_device *adev = mes->adev; 147 union MESAPI__ADD_QUEUE mes_add_queue_pkt; 148 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; 149 uint32_t vm_cntx_cntl = hub->vm_cntx_cntl; 150 151 memset(&mes_add_queue_pkt, 0, sizeof(mes_add_queue_pkt)); 152 153 mes_add_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 154 mes_add_queue_pkt.header.opcode = MES_SCH_API_ADD_QUEUE; 155 mes_add_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 156 157 mes_add_queue_pkt.process_id = input->process_id; 158 mes_add_queue_pkt.page_table_base_addr = input->page_table_base_addr; 159 mes_add_queue_pkt.process_va_start = input->process_va_start; 160 mes_add_queue_pkt.process_va_end = input->process_va_end; 161 mes_add_queue_pkt.process_quantum = input->process_quantum; 162 mes_add_queue_pkt.process_context_addr = input->process_context_addr; 163 mes_add_queue_pkt.gang_quantum = input->gang_quantum; 164 mes_add_queue_pkt.gang_context_addr = input->gang_context_addr; 165 mes_add_queue_pkt.inprocess_gang_priority = 166 input->inprocess_gang_priority; 167 mes_add_queue_pkt.gang_global_priority_level = 168 input->gang_global_priority_level; 169 mes_add_queue_pkt.doorbell_offset = input->doorbell_offset; 170 mes_add_queue_pkt.mqd_addr = input->mqd_addr; 171 mes_add_queue_pkt.wptr_addr = input->wptr_addr; 172 mes_add_queue_pkt.queue_type = 173 convert_to_mes_queue_type(input->queue_type); 174 mes_add_queue_pkt.paging = input->paging; 175 mes_add_queue_pkt.vm_context_cntl = vm_cntx_cntl; 176 mes_add_queue_pkt.gws_base = input->gws_base; 177 mes_add_queue_pkt.gws_size = input->gws_size; 178 mes_add_queue_pkt.trap_handler_addr = input->tba_addr; 179 180 return mes_v10_1_submit_pkt_and_poll_completion(mes, 181 &mes_add_queue_pkt, sizeof(mes_add_queue_pkt), 182 offsetof(union MESAPI__ADD_QUEUE, api_status)); 183 } 184 185 static int mes_v10_1_remove_hw_queue(struct amdgpu_mes *mes, 186 struct mes_remove_queue_input *input) 187 { 188 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 189 190 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 191 192 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 193 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 194 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 195 196 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 197 mes_remove_queue_pkt.gang_context_addr = input->gang_context_addr; 198 199 return mes_v10_1_submit_pkt_and_poll_completion(mes, 200 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 201 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 202 } 203 204 static int mes_v10_1_unmap_legacy_queue(struct amdgpu_mes *mes, 205 struct mes_unmap_legacy_queue_input *input) 206 { 207 union MESAPI__REMOVE_QUEUE mes_remove_queue_pkt; 208 209 memset(&mes_remove_queue_pkt, 0, sizeof(mes_remove_queue_pkt)); 210 211 mes_remove_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; 212 mes_remove_queue_pkt.header.opcode = MES_SCH_API_REMOVE_QUEUE; 213 mes_remove_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 214 215 mes_remove_queue_pkt.doorbell_offset = input->doorbell_offset; 216 mes_remove_queue_pkt.gang_context_addr = 0; 217 218 mes_remove_queue_pkt.pipe_id = input->pipe_id; 219 mes_remove_queue_pkt.queue_id = input->queue_id; 220 221 if (input->action == PREEMPT_QUEUES_NO_UNMAP) { 222 mes_remove_queue_pkt.preempt_legacy_gfx_queue = 1; 223 mes_remove_queue_pkt.tf_addr = input->trail_fence_addr; 224 mes_remove_queue_pkt.tf_data = 225 lower_32_bits(input->trail_fence_data); 226 } else { 227 if (input->queue_type == AMDGPU_RING_TYPE_GFX) 228 mes_remove_queue_pkt.unmap_legacy_gfx_queue = 1; 229 else 230 mes_remove_queue_pkt.unmap_kiq_utility_queue = 1; 231 } 232 233 return mes_v10_1_submit_pkt_and_poll_completion(mes, 234 &mes_remove_queue_pkt, sizeof(mes_remove_queue_pkt), 235 offsetof(union MESAPI__REMOVE_QUEUE, api_status)); 236 } 237 238 static int mes_v10_1_suspend_gang(struct amdgpu_mes *mes, 239 struct mes_suspend_gang_input *input) 240 { 241 return 0; 242 } 243 244 static int mes_v10_1_resume_gang(struct amdgpu_mes *mes, 245 struct mes_resume_gang_input *input) 246 { 247 return 0; 248 } 249 250 static int mes_v10_1_query_sched_status(struct amdgpu_mes *mes) 251 { 252 union MESAPI__QUERY_MES_STATUS mes_status_pkt; 253 254 memset(&mes_status_pkt, 0, sizeof(mes_status_pkt)); 255 256 mes_status_pkt.header.type = MES_API_TYPE_SCHEDULER; 257 mes_status_pkt.header.opcode = MES_SCH_API_QUERY_SCHEDULER_STATUS; 258 mes_status_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 259 260 return mes_v10_1_submit_pkt_and_poll_completion(mes, 261 &mes_status_pkt, sizeof(mes_status_pkt), 262 offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); 263 } 264 265 static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) 266 { 267 int i; 268 struct amdgpu_device *adev = mes->adev; 269 union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt; 270 271 memset(&mes_set_hw_res_pkt, 0, sizeof(mes_set_hw_res_pkt)); 272 273 mes_set_hw_res_pkt.header.type = MES_API_TYPE_SCHEDULER; 274 mes_set_hw_res_pkt.header.opcode = MES_SCH_API_SET_HW_RSRC; 275 mes_set_hw_res_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; 276 277 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; 278 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; 279 mes_set_hw_res_pkt.gds_size = adev->gds.gds_size; 280 mes_set_hw_res_pkt.paging_vmid = 0; 281 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr; 282 mes_set_hw_res_pkt.query_status_fence_gpu_mc_ptr = 283 mes->query_status_fence_gpu_addr; 284 285 for (i = 0; i < MAX_COMPUTE_PIPES; i++) 286 mes_set_hw_res_pkt.compute_hqd_mask[i] = 287 mes->compute_hqd_mask[i]; 288 289 for (i = 0; i < MAX_GFX_PIPES; i++) 290 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; 291 292 for (i = 0; i < MAX_SDMA_PIPES; i++) 293 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; 294 295 for (i = 0; i < AMD_PRIORITY_NUM_LEVELS; i++) 296 mes_set_hw_res_pkt.aggregated_doorbells[i] = 297 mes->aggregated_doorbells[i]; 298 299 for (i = 0; i < 5; i++) { 300 mes_set_hw_res_pkt.gc_base[i] = adev->reg_offset[GC_HWIP][0][i]; 301 mes_set_hw_res_pkt.mmhub_base[i] = 302 adev->reg_offset[MMHUB_HWIP][0][i]; 303 mes_set_hw_res_pkt.osssys_base[i] = 304 adev->reg_offset[OSSSYS_HWIP][0][i]; 305 } 306 307 mes_set_hw_res_pkt.disable_reset = 1; 308 mes_set_hw_res_pkt.disable_mes_log = 1; 309 mes_set_hw_res_pkt.use_different_vmid_compute = 1; 310 311 return mes_v10_1_submit_pkt_and_poll_completion(mes, 312 &mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt), 313 offsetof(union MESAPI_SET_HW_RESOURCES, api_status)); 314 } 315 316 static void mes_v10_1_init_aggregated_doorbell(struct amdgpu_mes *mes) 317 { 318 struct amdgpu_device *adev = mes->adev; 319 uint32_t data; 320 321 data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL1); 322 data &= ~(CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK | 323 CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK | 324 CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK); 325 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_LOW] << 326 CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT; 327 data |= 1 << CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT; 328 WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL1, data); 329 330 data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL2); 331 data &= ~(CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK | 332 CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK | 333 CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK); 334 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_NORMAL] << 335 CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT; 336 data |= 1 << CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT; 337 WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL2, data); 338 339 data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL3); 340 data &= ~(CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK | 341 CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK | 342 CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK); 343 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_MEDIUM] << 344 CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT; 345 data |= 1 << CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT; 346 WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL3, data); 347 348 data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL4); 349 data &= ~(CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK | 350 CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK | 351 CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK); 352 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_HIGH] << 353 CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT; 354 data |= 1 << CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT; 355 WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL4, data); 356 357 data = RREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL5); 358 data &= ~(CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK | 359 CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK | 360 CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK); 361 data |= mes->aggregated_doorbells[AMDGPU_MES_PRIORITY_LEVEL_REALTIME] << 362 CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT; 363 data |= 1 << CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT; 364 WREG32_SOC15(GC, 0, mmCP_MES_DOORBELL_CONTROL5, data); 365 366 data = 1 << CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT; 367 WREG32_SOC15(GC, 0, mmCP_HQD_GFX_CONTROL, data); 368 } 369 370 static const struct amdgpu_mes_funcs mes_v10_1_funcs = { 371 .add_hw_queue = mes_v10_1_add_hw_queue, 372 .remove_hw_queue = mes_v10_1_remove_hw_queue, 373 .unmap_legacy_queue = mes_v10_1_unmap_legacy_queue, 374 .suspend_gang = mes_v10_1_suspend_gang, 375 .resume_gang = mes_v10_1_resume_gang, 376 }; 377 378 static int mes_v10_1_allocate_ucode_buffer(struct amdgpu_device *adev, 379 enum admgpu_mes_pipe pipe) 380 { 381 int r; 382 const struct mes_firmware_header_v1_0 *mes_hdr; 383 const __le32 *fw_data; 384 unsigned fw_size; 385 386 mes_hdr = (const struct mes_firmware_header_v1_0 *) 387 adev->mes.fw[pipe]->data; 388 389 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 390 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 391 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 392 393 r = amdgpu_bo_create_reserved(adev, fw_size, 394 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 395 &adev->mes.ucode_fw_obj[pipe], 396 &adev->mes.ucode_fw_gpu_addr[pipe], 397 (void **)&adev->mes.ucode_fw_ptr[pipe]); 398 if (r) { 399 dev_err(adev->dev, "(%d) failed to create mes fw bo\n", r); 400 return r; 401 } 402 403 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); 404 405 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); 406 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); 407 408 return 0; 409 } 410 411 static int mes_v10_1_allocate_ucode_data_buffer(struct amdgpu_device *adev, 412 enum admgpu_mes_pipe pipe) 413 { 414 int r; 415 const struct mes_firmware_header_v1_0 *mes_hdr; 416 const __le32 *fw_data; 417 unsigned fw_size; 418 419 mes_hdr = (const struct mes_firmware_header_v1_0 *) 420 adev->mes.fw[pipe]->data; 421 422 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 423 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 424 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 425 426 r = amdgpu_bo_create_reserved(adev, fw_size, 427 64 * 1024, AMDGPU_GEM_DOMAIN_GTT, 428 &adev->mes.data_fw_obj[pipe], 429 &adev->mes.data_fw_gpu_addr[pipe], 430 (void **)&adev->mes.data_fw_ptr[pipe]); 431 if (r) { 432 dev_err(adev->dev, "(%d) failed to create mes data fw bo\n", r); 433 return r; 434 } 435 436 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); 437 438 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); 439 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); 440 441 return 0; 442 } 443 444 static void mes_v10_1_free_ucode_buffers(struct amdgpu_device *adev, 445 enum admgpu_mes_pipe pipe) 446 { 447 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], 448 &adev->mes.data_fw_gpu_addr[pipe], 449 (void **)&adev->mes.data_fw_ptr[pipe]); 450 451 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], 452 &adev->mes.ucode_fw_gpu_addr[pipe], 453 (void **)&adev->mes.ucode_fw_ptr[pipe]); 454 } 455 456 static void mes_v10_1_enable(struct amdgpu_device *adev, bool enable) 457 { 458 uint32_t pipe, data = 0; 459 460 if (enable) { 461 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); 462 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 463 data = REG_SET_FIELD(data, CP_MES_CNTL, 464 MES_PIPE1_RESET, adev->enable_mes_kiq ? 1 : 0); 465 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); 466 467 mutex_lock(&adev->srbm_mutex); 468 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 469 if (!adev->enable_mes_kiq && 470 pipe == AMDGPU_MES_KIQ_PIPE) 471 continue; 472 473 nv_grbm_select(adev, 3, pipe, 0, 0); 474 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, 475 (uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2); 476 } 477 nv_grbm_select(adev, 0, 0, 0, 0); 478 mutex_unlock(&adev->srbm_mutex); 479 480 /* clear BYPASS_UNCACHED to avoid hangs after interrupt. */ 481 data = RREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL); 482 data = REG_SET_FIELD(data, CP_MES_DC_OP_CNTL, 483 BYPASS_UNCACHED, 0); 484 WREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL, data); 485 486 /* unhalt MES and activate pipe0 */ 487 data = REG_SET_FIELD(0, CP_MES_CNTL, MES_PIPE0_ACTIVE, 1); 488 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 489 adev->enable_mes_kiq ? 1 : 0); 490 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); 491 udelay(100); 492 } else { 493 data = RREG32_SOC15(GC, 0, mmCP_MES_CNTL); 494 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_ACTIVE, 0); 495 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_ACTIVE, 0); 496 data = REG_SET_FIELD(data, CP_MES_CNTL, 497 MES_INVALIDATE_ICACHE, 1); 498 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE0_RESET, 1); 499 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_PIPE1_RESET, 500 adev->enable_mes_kiq ? 1 : 0); 501 data = REG_SET_FIELD(data, CP_MES_CNTL, MES_HALT, 1); 502 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); 503 } 504 } 505 506 /* This function is for backdoor MES firmware */ 507 static int mes_v10_1_load_microcode(struct amdgpu_device *adev, 508 enum admgpu_mes_pipe pipe) 509 { 510 int r; 511 uint32_t data; 512 513 mes_v10_1_enable(adev, false); 514 515 if (!adev->mes.fw[pipe]) 516 return -EINVAL; 517 518 r = mes_v10_1_allocate_ucode_buffer(adev, pipe); 519 if (r) 520 return r; 521 522 r = mes_v10_1_allocate_ucode_data_buffer(adev, pipe); 523 if (r) { 524 mes_v10_1_free_ucode_buffers(adev, pipe); 525 return r; 526 } 527 528 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0); 529 530 mutex_lock(&adev->srbm_mutex); 531 /* me=3, pipe=0, queue=0 */ 532 nv_grbm_select(adev, 3, pipe, 0, 0); 533 534 /* set ucode start address */ 535 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, 536 (uint32_t)(adev->mes.uc_start_addr[pipe]) >> 2); 537 538 /* set ucode fimrware address */ 539 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_LO, 540 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 541 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_HI, 542 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); 543 544 /* set ucode instruction cache boundary to 2M-1 */ 545 WREG32_SOC15(GC, 0, mmCP_MES_MIBOUND_LO, 0x1FFFFF); 546 547 /* set ucode data firmware address */ 548 WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_LO, 549 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 550 WREG32_SOC15(GC, 0, mmCP_MES_MDBASE_HI, 551 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); 552 553 /* Set 0x3FFFF (256K-1) to CP_MES_MDBOUND_LO */ 554 WREG32_SOC15(GC, 0, mmCP_MES_MDBOUND_LO, 0x3FFFF); 555 556 /* invalidate ICACHE */ 557 switch (adev->ip_versions[GC_HWIP][0]) { 558 case IP_VERSION(10, 3, 0): 559 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid); 560 break; 561 default: 562 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL); 563 break; 564 } 565 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 0); 566 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1); 567 switch (adev->ip_versions[GC_HWIP][0]) { 568 case IP_VERSION(10, 3, 0): 569 WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data); 570 break; 571 default: 572 WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data); 573 break; 574 } 575 576 /* prime the ICACHE. */ 577 switch (adev->ip_versions[GC_HWIP][0]) { 578 case IP_VERSION(10, 3, 0): 579 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid); 580 break; 581 default: 582 data = RREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL); 583 break; 584 } 585 data = REG_SET_FIELD(data, CP_MES_IC_OP_CNTL, PRIME_ICACHE, 1); 586 switch (adev->ip_versions[GC_HWIP][0]) { 587 case IP_VERSION(10, 3, 0): 588 WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL_Sienna_Cichlid, data); 589 break; 590 default: 591 WREG32_SOC15(GC, 0, mmCP_MES_IC_OP_CNTL, data); 592 break; 593 } 594 595 nv_grbm_select(adev, 0, 0, 0, 0); 596 mutex_unlock(&adev->srbm_mutex); 597 598 return 0; 599 } 600 601 static int mes_v10_1_allocate_eop_buf(struct amdgpu_device *adev, 602 enum admgpu_mes_pipe pipe) 603 { 604 int r; 605 u32 *eop; 606 607 r = amdgpu_bo_create_reserved(adev, MES_EOP_SIZE, PAGE_SIZE, 608 AMDGPU_GEM_DOMAIN_GTT, 609 &adev->mes.eop_gpu_obj[pipe], 610 &adev->mes.eop_gpu_addr[pipe], 611 (void **)&eop); 612 if (r) { 613 dev_warn(adev->dev, "(%d) create EOP bo failed\n", r); 614 return r; 615 } 616 617 memset(eop, 0, adev->mes.eop_gpu_obj[pipe]->tbo.base.size); 618 619 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); 620 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); 621 622 return 0; 623 } 624 625 static int mes_v10_1_mqd_init(struct amdgpu_ring *ring) 626 { 627 struct v10_compute_mqd *mqd = ring->mqd_ptr; 628 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 629 uint32_t tmp; 630 631 mqd->header = 0xC0310800; 632 mqd->compute_pipelinestat_enable = 0x00000001; 633 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 634 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 635 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 636 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 637 mqd->compute_misc_reserved = 0x00000003; 638 639 eop_base_addr = ring->eop_gpu_addr >> 8; 640 641 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 642 tmp = mmCP_HQD_EOP_CONTROL_DEFAULT; 643 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 644 (order_base_2(MES_EOP_SIZE / 4) - 1)); 645 646 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); 647 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 648 mqd->cp_hqd_eop_control = tmp; 649 650 /* disable the queue if it's active */ 651 ring->wptr = 0; 652 mqd->cp_hqd_pq_rptr = 0; 653 mqd->cp_hqd_pq_wptr_lo = 0; 654 mqd->cp_hqd_pq_wptr_hi = 0; 655 656 /* set the pointer to the MQD */ 657 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 658 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 659 660 /* set MQD vmid to 0 */ 661 tmp = mmCP_MQD_CONTROL_DEFAULT; 662 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 663 mqd->cp_mqd_control = tmp; 664 665 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 666 hqd_gpu_addr = ring->gpu_addr >> 8; 667 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); 668 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 669 670 /* set the wb address whether it's enabled or not */ 671 wb_gpu_addr = ring->rptr_gpu_addr; 672 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 673 mqd->cp_hqd_pq_rptr_report_addr_hi = 674 upper_32_bits(wb_gpu_addr) & 0xffff; 675 676 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 677 wb_gpu_addr = ring->wptr_gpu_addr; 678 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; 679 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 680 681 /* set up the HQD, this is similar to CP_RB0_CNTL */ 682 tmp = mmCP_HQD_PQ_CONTROL_DEFAULT; 683 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 684 (order_base_2(ring->ring_size / 4) - 1)); 685 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 686 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 687 #ifdef __BIG_ENDIAN 688 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 689 #endif 690 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); 691 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 692 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 693 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 694 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, NO_UPDATE_RPTR, 1); 695 mqd->cp_hqd_pq_control = tmp; 696 697 /* enable doorbell? */ 698 tmp = 0; 699 if (ring->use_doorbell) { 700 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 701 DOORBELL_OFFSET, ring->doorbell_index); 702 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 703 DOORBELL_EN, 1); 704 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 705 DOORBELL_SOURCE, 0); 706 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 707 DOORBELL_HIT, 0); 708 } 709 else 710 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 711 DOORBELL_EN, 0); 712 mqd->cp_hqd_pq_doorbell_control = tmp; 713 714 mqd->cp_hqd_vmid = 0; 715 /* activate the queue */ 716 mqd->cp_hqd_active = 1; 717 mqd->cp_hqd_persistent_state = mmCP_HQD_PERSISTENT_STATE_DEFAULT; 718 mqd->cp_hqd_ib_control = mmCP_HQD_IB_CONTROL_DEFAULT; 719 mqd->cp_hqd_iq_timer = mmCP_HQD_IQ_TIMER_DEFAULT; 720 mqd->cp_hqd_quantum = mmCP_HQD_QUANTUM_DEFAULT; 721 722 tmp = mmCP_HQD_GFX_CONTROL_DEFAULT; 723 tmp = REG_SET_FIELD(tmp, CP_HQD_GFX_CONTROL, DB_UPDATED_MSG_EN, 1); 724 /* offset: 184 - this is used for CP_HQD_GFX_CONTROL */ 725 mqd->cp_hqd_suspend_cntl_stack_offset = tmp; 726 727 return 0; 728 } 729 730 #if 0 731 static void mes_v10_1_queue_init_register(struct amdgpu_ring *ring) 732 { 733 struct v10_compute_mqd *mqd = ring->mqd_ptr; 734 struct amdgpu_device *adev = ring->adev; 735 uint32_t data = 0; 736 737 mutex_lock(&adev->srbm_mutex); 738 nv_grbm_select(adev, 3, ring->pipe, 0, 0); 739 740 /* set CP_HQD_VMID.VMID = 0. */ 741 data = RREG32_SOC15(GC, 0, mmCP_HQD_VMID); 742 data = REG_SET_FIELD(data, CP_HQD_VMID, VMID, 0); 743 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, data); 744 745 /* set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_EN=0 */ 746 data = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 747 data = REG_SET_FIELD(data, CP_HQD_PQ_DOORBELL_CONTROL, 748 DOORBELL_EN, 0); 749 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data); 750 751 /* set CP_MQD_BASE_ADDR/HI with the MQD base address */ 752 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); 753 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 754 755 /* set CP_MQD_CONTROL.VMID=0 */ 756 data = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 757 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); 758 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 0); 759 760 /* set CP_HQD_PQ_BASE/HI with the ring buffer base address */ 761 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); 762 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); 763 764 /* set CP_HQD_PQ_RPTR_REPORT_ADDR/HI */ 765 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 766 mqd->cp_hqd_pq_rptr_report_addr_lo); 767 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 768 mqd->cp_hqd_pq_rptr_report_addr_hi); 769 770 /* set CP_HQD_PQ_CONTROL */ 771 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); 772 773 /* set CP_HQD_PQ_WPTR_POLL_ADDR/HI */ 774 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 775 mqd->cp_hqd_pq_wptr_poll_addr_lo); 776 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 777 mqd->cp_hqd_pq_wptr_poll_addr_hi); 778 779 /* set CP_HQD_PQ_DOORBELL_CONTROL */ 780 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 781 mqd->cp_hqd_pq_doorbell_control); 782 783 /* set CP_HQD_PERSISTENT_STATE.PRELOAD_SIZE=0x53 */ 784 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); 785 786 /* set CP_HQD_ACTIVE.ACTIVE=1 */ 787 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, mqd->cp_hqd_active); 788 789 nv_grbm_select(adev, 0, 0, 0, 0); 790 mutex_unlock(&adev->srbm_mutex); 791 } 792 #endif 793 794 static int mes_v10_1_kiq_enable_queue(struct amdgpu_device *adev) 795 { 796 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 797 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 798 int r; 799 800 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 801 return -EINVAL; 802 803 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); 804 if (r) { 805 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 806 return r; 807 } 808 809 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring); 810 811 r = amdgpu_ring_test_ring(kiq_ring); 812 if (r) { 813 DRM_ERROR("kfq enable failed\n"); 814 kiq_ring->sched.ready = false; 815 } 816 817 return r; 818 } 819 820 static int mes_v10_1_queue_init(struct amdgpu_device *adev) 821 { 822 int r; 823 824 r = mes_v10_1_mqd_init(&adev->mes.ring); 825 if (r) 826 return r; 827 828 r = mes_v10_1_kiq_enable_queue(adev); 829 if (r) 830 return r; 831 832 return 0; 833 } 834 835 static int mes_v10_1_ring_init(struct amdgpu_device *adev) 836 { 837 struct amdgpu_ring *ring; 838 839 ring = &adev->mes.ring; 840 841 ring->funcs = &mes_v10_1_ring_funcs; 842 843 ring->me = 3; 844 ring->pipe = 0; 845 ring->queue = 0; 846 847 ring->ring_obj = NULL; 848 ring->use_doorbell = true; 849 ring->doorbell_index = adev->doorbell_index.mes_ring0 << 1; 850 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; 851 ring->no_scheduler = true; 852 snprintf(ring->name, sizeof(ring->name), "mes_%d.%d.%d", ring->me, ring->pipe, ring->queue); 853 854 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 855 AMDGPU_RING_PRIO_DEFAULT, NULL); 856 } 857 858 static int mes_v10_1_kiq_ring_init(struct amdgpu_device *adev) 859 { 860 struct amdgpu_ring *ring; 861 862 mtx_init(&adev->gfx.kiq.ring_lock, IPL_TTY); 863 864 ring = &adev->gfx.kiq.ring; 865 866 ring->me = 3; 867 ring->pipe = 1; 868 ring->queue = 0; 869 870 ring->adev = NULL; 871 ring->ring_obj = NULL; 872 ring->use_doorbell = true; 873 ring->doorbell_index = adev->doorbell_index.mes_ring1 << 1; 874 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; 875 ring->no_scheduler = true; 876 snprintf(ring->name, sizeof(ring->name), "mes_kiq_%d.%d.%d", 877 ring->me, ring->pipe, ring->queue); 878 879 return amdgpu_ring_init(adev, ring, 1024, NULL, 0, 880 AMDGPU_RING_PRIO_DEFAULT, NULL); 881 } 882 883 static int mes_v10_1_mqd_sw_init(struct amdgpu_device *adev, 884 enum admgpu_mes_pipe pipe) 885 { 886 int r, mqd_size = sizeof(struct v10_compute_mqd); 887 struct amdgpu_ring *ring; 888 889 if (pipe == AMDGPU_MES_KIQ_PIPE) 890 ring = &adev->gfx.kiq.ring; 891 else if (pipe == AMDGPU_MES_SCHED_PIPE) 892 ring = &adev->mes.ring; 893 else 894 BUG(); 895 896 if (ring->mqd_obj) 897 return 0; 898 899 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 900 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 901 &ring->mqd_gpu_addr, &ring->mqd_ptr); 902 if (r) { 903 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 904 return r; 905 } 906 memset(ring->mqd_ptr, 0, mqd_size); 907 908 /* prepare MQD backup */ 909 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); 910 if (!adev->mes.mqd_backup[pipe]) 911 dev_warn(adev->dev, 912 "no memory to create MQD backup for ring %s\n", 913 ring->name); 914 915 return 0; 916 } 917 918 static int mes_v10_1_sw_init(void *handle) 919 { 920 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 921 int pipe, r; 922 923 adev->mes.adev = adev; 924 adev->mes.funcs = &mes_v10_1_funcs; 925 adev->mes.kiq_hw_init = &mes_v10_1_kiq_hw_init; 926 927 r = amdgpu_mes_init(adev); 928 if (r) 929 return r; 930 931 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 932 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 933 continue; 934 935 r = mes_v10_1_allocate_eop_buf(adev, pipe); 936 if (r) 937 return r; 938 939 r = mes_v10_1_mqd_sw_init(adev, pipe); 940 if (r) 941 return r; 942 } 943 944 if (adev->enable_mes_kiq) { 945 r = mes_v10_1_kiq_ring_init(adev); 946 if (r) 947 return r; 948 } 949 950 r = mes_v10_1_ring_init(adev); 951 if (r) 952 return r; 953 954 return 0; 955 } 956 957 static int mes_v10_1_sw_fini(void *handle) 958 { 959 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 960 int pipe; 961 962 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs); 963 amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs); 964 965 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 966 kfree(adev->mes.mqd_backup[pipe]); 967 968 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], 969 &adev->mes.eop_gpu_addr[pipe], 970 NULL); 971 amdgpu_ucode_release(&adev->mes.fw[pipe]); 972 } 973 974 amdgpu_bo_free_kernel(&adev->gfx.kiq.ring.mqd_obj, 975 &adev->gfx.kiq.ring.mqd_gpu_addr, 976 &adev->gfx.kiq.ring.mqd_ptr); 977 978 amdgpu_bo_free_kernel(&adev->mes.ring.mqd_obj, 979 &adev->mes.ring.mqd_gpu_addr, 980 &adev->mes.ring.mqd_ptr); 981 982 amdgpu_ring_fini(&adev->gfx.kiq.ring); 983 amdgpu_ring_fini(&adev->mes.ring); 984 985 amdgpu_mes_fini(adev); 986 return 0; 987 } 988 989 static void mes_v10_1_kiq_setting(struct amdgpu_ring *ring) 990 { 991 uint32_t tmp; 992 struct amdgpu_device *adev = ring->adev; 993 994 /* tell RLC which is KIQ queue */ 995 switch (adev->ip_versions[GC_HWIP][0]) { 996 case IP_VERSION(10, 3, 0): 997 case IP_VERSION(10, 3, 2): 998 case IP_VERSION(10, 3, 1): 999 case IP_VERSION(10, 3, 4): 1000 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 1001 tmp &= 0xffffff00; 1002 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1003 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 1004 tmp |= 0x80; 1005 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 1006 break; 1007 default: 1008 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 1009 tmp &= 0xffffff00; 1010 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 1011 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 1012 tmp |= 0x80; 1013 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 1014 break; 1015 } 1016 } 1017 1018 static int mes_v10_1_kiq_hw_init(struct amdgpu_device *adev) 1019 { 1020 int r = 0; 1021 1022 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1023 r = mes_v10_1_load_microcode(adev, AMDGPU_MES_KIQ_PIPE); 1024 if (r) { 1025 DRM_ERROR("failed to load MES kiq fw, r=%d\n", r); 1026 return r; 1027 } 1028 1029 r = mes_v10_1_load_microcode(adev, AMDGPU_MES_SCHED_PIPE); 1030 if (r) { 1031 DRM_ERROR("failed to load MES fw, r=%d\n", r); 1032 return r; 1033 } 1034 } 1035 1036 mes_v10_1_enable(adev, true); 1037 1038 mes_v10_1_kiq_setting(&adev->gfx.kiq.ring); 1039 1040 r = mes_v10_1_queue_init(adev); 1041 if (r) 1042 goto failure; 1043 1044 return r; 1045 1046 failure: 1047 mes_v10_1_hw_fini(adev); 1048 return r; 1049 } 1050 1051 static int mes_v10_1_hw_init(void *handle) 1052 { 1053 int r; 1054 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1055 1056 if (!adev->enable_mes_kiq) { 1057 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1058 r = mes_v10_1_load_microcode(adev, 1059 AMDGPU_MES_SCHED_PIPE); 1060 if (r) { 1061 DRM_ERROR("failed to MES fw, r=%d\n", r); 1062 return r; 1063 } 1064 } 1065 1066 mes_v10_1_enable(adev, true); 1067 } 1068 1069 r = mes_v10_1_queue_init(adev); 1070 if (r) 1071 goto failure; 1072 1073 r = mes_v10_1_set_hw_resources(&adev->mes); 1074 if (r) 1075 goto failure; 1076 1077 mes_v10_1_init_aggregated_doorbell(&adev->mes); 1078 1079 r = mes_v10_1_query_sched_status(&adev->mes); 1080 if (r) { 1081 DRM_ERROR("MES is busy\n"); 1082 goto failure; 1083 } 1084 1085 /* 1086 * Disable KIQ ring usage from the driver once MES is enabled. 1087 * MES uses KIQ ring exclusively so driver cannot access KIQ ring 1088 * with MES enabled. 1089 */ 1090 adev->gfx.kiq.ring.sched.ready = false; 1091 adev->mes.ring.sched.ready = true; 1092 1093 return 0; 1094 1095 failure: 1096 mes_v10_1_hw_fini(adev); 1097 return r; 1098 } 1099 1100 static int mes_v10_1_hw_fini(void *handle) 1101 { 1102 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1103 1104 adev->mes.ring.sched.ready = false; 1105 1106 mes_v10_1_enable(adev, false); 1107 1108 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1109 mes_v10_1_free_ucode_buffers(adev, AMDGPU_MES_KIQ_PIPE); 1110 mes_v10_1_free_ucode_buffers(adev, AMDGPU_MES_SCHED_PIPE); 1111 } 1112 1113 return 0; 1114 } 1115 1116 static int mes_v10_1_suspend(void *handle) 1117 { 1118 int r; 1119 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1120 1121 r = amdgpu_mes_suspend(adev); 1122 if (r) 1123 return r; 1124 1125 return mes_v10_1_hw_fini(adev); 1126 } 1127 1128 static int mes_v10_1_resume(void *handle) 1129 { 1130 int r; 1131 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1132 1133 r = mes_v10_1_hw_init(adev); 1134 if (r) 1135 return r; 1136 1137 return amdgpu_mes_resume(adev); 1138 } 1139 1140 static int mes_v10_0_early_init(void *handle) 1141 { 1142 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1143 int pipe, r; 1144 1145 for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { 1146 if (!adev->enable_mes_kiq && pipe == AMDGPU_MES_KIQ_PIPE) 1147 continue; 1148 r = amdgpu_mes_init_microcode(adev, pipe); 1149 if (r) 1150 return r; 1151 } 1152 1153 return 0; 1154 } 1155 1156 static int mes_v10_0_late_init(void *handle) 1157 { 1158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1159 1160 if (!amdgpu_in_reset(adev)) 1161 amdgpu_mes_self_test(adev); 1162 1163 return 0; 1164 } 1165 1166 static const struct amd_ip_funcs mes_v10_1_ip_funcs = { 1167 .name = "mes_v10_1", 1168 .early_init = mes_v10_0_early_init, 1169 .late_init = mes_v10_0_late_init, 1170 .sw_init = mes_v10_1_sw_init, 1171 .sw_fini = mes_v10_1_sw_fini, 1172 .hw_init = mes_v10_1_hw_init, 1173 .hw_fini = mes_v10_1_hw_fini, 1174 .suspend = mes_v10_1_suspend, 1175 .resume = mes_v10_1_resume, 1176 }; 1177 1178 const struct amdgpu_ip_block_version mes_v10_1_ip_block = { 1179 .type = AMD_IP_BLOCK_TYPE_MES, 1180 .major = 10, 1181 .minor = 1, 1182 .rev = 0, 1183 .funcs = &mes_v10_1_ip_funcs, 1184 }; 1185