1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/kernel.h> 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_gfx.h" 28 #include "soc15.h" 29 #include "soc15d.h" 30 #include "amdgpu_atomfirmware.h" 31 32 #include "gc/gc_9_0_offset.h" 33 #include "gc/gc_9_0_sh_mask.h" 34 #include "vega10_enum.h" 35 #include "hdp/hdp_4_0_offset.h" 36 37 #include "soc15_common.h" 38 #include "clearstate_gfx9.h" 39 #include "v9_structs.h" 40 41 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 42 43 #define GFX9_NUM_GFX_RINGS 1 44 #define GFX9_MEC_HPD_SIZE 2048 45 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 46 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 47 48 #define mmPWR_MISC_CNTL_STATUS 0x0183 49 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0 50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 52 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L 53 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L 54 55 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 56 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 57 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 58 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 59 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 60 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 61 62 MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); 63 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); 64 MODULE_FIRMWARE("amdgpu/vega12_me.bin"); 65 MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); 66 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); 67 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); 68 69 MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); 70 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); 71 MODULE_FIRMWARE("amdgpu/vega20_me.bin"); 72 MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); 73 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); 74 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); 75 76 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 77 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 78 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 79 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 80 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 81 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 82 83 MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); 84 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); 85 MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 86 MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); 87 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); 88 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); 89 90 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 91 { 92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 109 }; 110 111 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 112 { 113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), 120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), 122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 131 }; 132 133 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = 134 { 135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), 136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), 139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), 140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), 141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), 142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), 143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), 144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) 146 }; 147 148 static const struct soc15_reg_golden golden_settings_gc_9_1[] = 149 { 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 171 }; 172 173 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = 174 { 175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), 177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), 178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), 179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), 180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) 182 }; 183 184 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = 185 { 186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) 188 }; 189 190 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = 191 { 192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 208 }; 209 210 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = 211 { 212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), 213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), 216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), 217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), 219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), 221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000) 222 }; 223 224 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = 225 { 226 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 227 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 228 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 229 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 230 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 231 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 232 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 233 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 234 }; 235 236 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = 237 { 238 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, 239 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, 240 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, 241 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, 242 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, 243 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, 244 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, 245 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, 246 }; 247 248 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 249 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 250 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 251 252 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 253 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 254 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 255 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 256 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 257 struct amdgpu_cu_info *cu_info); 258 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 259 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 260 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); 261 262 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 263 { 264 switch (adev->asic_type) { 265 case CHIP_VEGA10: 266 soc15_program_register_sequence(adev, 267 golden_settings_gc_9_0, 268 ARRAY_SIZE(golden_settings_gc_9_0)); 269 soc15_program_register_sequence(adev, 270 golden_settings_gc_9_0_vg10, 271 ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 272 break; 273 case CHIP_VEGA12: 274 soc15_program_register_sequence(adev, 275 golden_settings_gc_9_2_1, 276 ARRAY_SIZE(golden_settings_gc_9_2_1)); 277 soc15_program_register_sequence(adev, 278 golden_settings_gc_9_2_1_vg12, 279 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); 280 break; 281 case CHIP_VEGA20: 282 soc15_program_register_sequence(adev, 283 golden_settings_gc_9_0, 284 ARRAY_SIZE(golden_settings_gc_9_0)); 285 soc15_program_register_sequence(adev, 286 golden_settings_gc_9_0_vg20, 287 ARRAY_SIZE(golden_settings_gc_9_0_vg20)); 288 break; 289 case CHIP_RAVEN: 290 soc15_program_register_sequence(adev, 291 golden_settings_gc_9_1, 292 ARRAY_SIZE(golden_settings_gc_9_1)); 293 soc15_program_register_sequence(adev, 294 golden_settings_gc_9_1_rv1, 295 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 296 break; 297 default: 298 break; 299 } 300 301 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, 302 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 303 } 304 305 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) 306 { 307 adev->gfx.scratch.num_reg = 8; 308 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 309 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 310 } 311 312 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 313 bool wc, uint32_t reg, uint32_t val) 314 { 315 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 316 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 317 WRITE_DATA_DST_SEL(0) | 318 (wc ? WR_CONFIRM : 0)); 319 amdgpu_ring_write(ring, reg); 320 amdgpu_ring_write(ring, 0); 321 amdgpu_ring_write(ring, val); 322 } 323 324 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 325 int mem_space, int opt, uint32_t addr0, 326 uint32_t addr1, uint32_t ref, uint32_t mask, 327 uint32_t inv) 328 { 329 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 330 amdgpu_ring_write(ring, 331 /* memory (1) or register (0) */ 332 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 333 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 334 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 335 WAIT_REG_MEM_ENGINE(eng_sel))); 336 337 if (mem_space) 338 BUG_ON(addr0 & 0x3); /* Dword align */ 339 amdgpu_ring_write(ring, addr0); 340 amdgpu_ring_write(ring, addr1); 341 amdgpu_ring_write(ring, ref); 342 amdgpu_ring_write(ring, mask); 343 amdgpu_ring_write(ring, inv); /* poll interval */ 344 } 345 346 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 347 { 348 struct amdgpu_device *adev = ring->adev; 349 uint32_t scratch; 350 uint32_t tmp = 0; 351 unsigned i; 352 int r; 353 354 r = amdgpu_gfx_scratch_get(adev, &scratch); 355 if (r) { 356 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 357 return r; 358 } 359 WREG32(scratch, 0xCAFEDEAD); 360 r = amdgpu_ring_alloc(ring, 3); 361 if (r) { 362 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 363 ring->idx, r); 364 amdgpu_gfx_scratch_free(adev, scratch); 365 return r; 366 } 367 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 368 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 369 amdgpu_ring_write(ring, 0xDEADBEEF); 370 amdgpu_ring_commit(ring); 371 372 for (i = 0; i < adev->usec_timeout; i++) { 373 tmp = RREG32(scratch); 374 if (tmp == 0xDEADBEEF) 375 break; 376 DRM_UDELAY(1); 377 } 378 if (i < adev->usec_timeout) { 379 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", 380 ring->idx, i); 381 } else { 382 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 383 ring->idx, scratch, tmp); 384 r = -EINVAL; 385 } 386 amdgpu_gfx_scratch_free(adev, scratch); 387 return r; 388 } 389 390 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 391 { 392 struct amdgpu_device *adev = ring->adev; 393 struct amdgpu_ib ib; 394 struct dma_fence *f = NULL; 395 396 unsigned index; 397 uint64_t gpu_addr; 398 uint32_t tmp; 399 long r; 400 401 r = amdgpu_device_wb_get(adev, &index); 402 if (r) { 403 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 404 return r; 405 } 406 407 gpu_addr = adev->wb.gpu_addr + (index * 4); 408 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 409 memset(&ib, 0, sizeof(ib)); 410 r = amdgpu_ib_get(adev, NULL, 16, &ib); 411 if (r) { 412 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 413 goto err1; 414 } 415 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 416 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 417 ib.ptr[2] = lower_32_bits(gpu_addr); 418 ib.ptr[3] = upper_32_bits(gpu_addr); 419 ib.ptr[4] = 0xDEADBEEF; 420 ib.length_dw = 5; 421 422 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 423 if (r) 424 goto err2; 425 426 r = dma_fence_wait_timeout(f, false, timeout); 427 if (r == 0) { 428 DRM_ERROR("amdgpu: IB test timed out.\n"); 429 r = -ETIMEDOUT; 430 goto err2; 431 } else if (r < 0) { 432 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 433 goto err2; 434 } 435 436 tmp = adev->wb.wb[index]; 437 if (tmp == 0xDEADBEEF) { 438 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); 439 r = 0; 440 } else { 441 DRM_ERROR("ib test on ring %d failed\n", ring->idx); 442 r = -EINVAL; 443 } 444 445 err2: 446 amdgpu_ib_free(adev, &ib, NULL); 447 dma_fence_put(f); 448 err1: 449 amdgpu_device_wb_free(adev, index); 450 return r; 451 } 452 453 454 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 455 { 456 release_firmware(adev->gfx.pfp_fw); 457 adev->gfx.pfp_fw = NULL; 458 release_firmware(adev->gfx.me_fw); 459 adev->gfx.me_fw = NULL; 460 release_firmware(adev->gfx.ce_fw); 461 adev->gfx.ce_fw = NULL; 462 release_firmware(adev->gfx.rlc_fw); 463 adev->gfx.rlc_fw = NULL; 464 release_firmware(adev->gfx.mec_fw); 465 adev->gfx.mec_fw = NULL; 466 release_firmware(adev->gfx.mec2_fw); 467 adev->gfx.mec2_fw = NULL; 468 469 kfree(adev->gfx.rlc.register_list_format); 470 } 471 472 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 473 { 474 const struct rlc_firmware_header_v2_1 *rlc_hdr; 475 476 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 477 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 478 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 479 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 480 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 481 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 482 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 483 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 484 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 485 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 486 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 487 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 488 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 489 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 490 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 491 } 492 493 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 494 { 495 const char *chip_name; 496 char fw_name[30]; 497 int err; 498 struct amdgpu_firmware_info *info = NULL; 499 const struct common_firmware_header *header = NULL; 500 const struct gfx_firmware_header_v1_0 *cp_hdr; 501 const struct rlc_firmware_header_v2_0 *rlc_hdr; 502 unsigned int *tmp = NULL; 503 unsigned int i = 0; 504 uint16_t version_major; 505 uint16_t version_minor; 506 507 DRM_DEBUG("\n"); 508 509 switch (adev->asic_type) { 510 case CHIP_VEGA10: 511 chip_name = "vega10"; 512 break; 513 case CHIP_VEGA12: 514 chip_name = "vega12"; 515 break; 516 case CHIP_VEGA20: 517 chip_name = "vega20"; 518 break; 519 case CHIP_RAVEN: 520 if (adev->pdev->device == 0x15d8) 521 chip_name = "picasso"; 522 else 523 chip_name = "raven"; 524 break; 525 default: 526 BUG(); 527 } 528 529 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 530 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 531 if (err) 532 goto out; 533 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 534 if (err) 535 goto out; 536 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 537 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 538 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 539 540 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 541 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 542 if (err) 543 goto out; 544 err = amdgpu_ucode_validate(adev->gfx.me_fw); 545 if (err) 546 goto out; 547 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 548 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 549 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 550 551 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 552 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 553 if (err) 554 goto out; 555 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 556 if (err) 557 goto out; 558 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 559 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 560 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 561 562 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 563 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 564 if (err) 565 goto out; 566 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 567 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 568 569 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 570 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 571 if (version_major == 2 && version_minor == 1) 572 adev->gfx.rlc.is_rlc_v2_1 = true; 573 574 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 575 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 576 adev->gfx.rlc.save_and_restore_offset = 577 le32_to_cpu(rlc_hdr->save_and_restore_offset); 578 adev->gfx.rlc.clear_state_descriptor_offset = 579 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 580 adev->gfx.rlc.avail_scratch_ram_locations = 581 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 582 adev->gfx.rlc.reg_restore_list_size = 583 le32_to_cpu(rlc_hdr->reg_restore_list_size); 584 adev->gfx.rlc.reg_list_format_start = 585 le32_to_cpu(rlc_hdr->reg_list_format_start); 586 adev->gfx.rlc.reg_list_format_separate_start = 587 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 588 adev->gfx.rlc.starting_offsets_start = 589 le32_to_cpu(rlc_hdr->starting_offsets_start); 590 adev->gfx.rlc.reg_list_format_size_bytes = 591 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 592 adev->gfx.rlc.reg_list_size_bytes = 593 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 594 adev->gfx.rlc.register_list_format = 595 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 596 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 597 if (!adev->gfx.rlc.register_list_format) { 598 err = -ENOMEM; 599 goto out; 600 } 601 602 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 603 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 604 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 605 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 606 607 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 608 609 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 610 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 611 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 612 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 613 614 if (adev->gfx.rlc.is_rlc_v2_1) 615 gfx_v9_0_init_rlc_ext_microcode(adev); 616 617 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 618 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 619 if (err) 620 goto out; 621 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 622 if (err) 623 goto out; 624 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 625 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 626 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 627 628 629 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 630 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 631 if (!err) { 632 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 633 if (err) 634 goto out; 635 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 636 adev->gfx.mec2_fw->data; 637 adev->gfx.mec2_fw_version = 638 le32_to_cpu(cp_hdr->header.ucode_version); 639 adev->gfx.mec2_feature_version = 640 le32_to_cpu(cp_hdr->ucode_feature_version); 641 } else { 642 err = 0; 643 adev->gfx.mec2_fw = NULL; 644 } 645 646 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 647 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 648 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 649 info->fw = adev->gfx.pfp_fw; 650 header = (const struct common_firmware_header *)info->fw->data; 651 adev->firmware.fw_size += 652 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 653 654 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 655 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 656 info->fw = adev->gfx.me_fw; 657 header = (const struct common_firmware_header *)info->fw->data; 658 adev->firmware.fw_size += 659 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 660 661 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 662 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 663 info->fw = adev->gfx.ce_fw; 664 header = (const struct common_firmware_header *)info->fw->data; 665 adev->firmware.fw_size += 666 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 667 668 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 669 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 670 info->fw = adev->gfx.rlc_fw; 671 header = (const struct common_firmware_header *)info->fw->data; 672 adev->firmware.fw_size += 673 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 674 675 if (adev->gfx.rlc.is_rlc_v2_1 && 676 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 677 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 678 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 679 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 680 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 681 info->fw = adev->gfx.rlc_fw; 682 adev->firmware.fw_size += 683 roundup2(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 684 685 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 686 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 687 info->fw = adev->gfx.rlc_fw; 688 adev->firmware.fw_size += 689 roundup2(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 690 691 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 692 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 693 info->fw = adev->gfx.rlc_fw; 694 adev->firmware.fw_size += 695 roundup2(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 696 } 697 698 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 699 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 700 info->fw = adev->gfx.mec_fw; 701 header = (const struct common_firmware_header *)info->fw->data; 702 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 703 adev->firmware.fw_size += 704 roundup2(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 705 706 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 707 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 708 info->fw = adev->gfx.mec_fw; 709 adev->firmware.fw_size += 710 roundup2(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 711 712 if (adev->gfx.mec2_fw) { 713 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 714 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 715 info->fw = adev->gfx.mec2_fw; 716 header = (const struct common_firmware_header *)info->fw->data; 717 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 718 adev->firmware.fw_size += 719 roundup2(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 720 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 721 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 722 info->fw = adev->gfx.mec2_fw; 723 adev->firmware.fw_size += 724 roundup2(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 725 } 726 727 } 728 729 out: 730 if (err) { 731 dev_err(adev->dev, 732 "gfx9: Failed to load firmware \"%s\"\n", 733 fw_name); 734 release_firmware(adev->gfx.pfp_fw); 735 adev->gfx.pfp_fw = NULL; 736 release_firmware(adev->gfx.me_fw); 737 adev->gfx.me_fw = NULL; 738 release_firmware(adev->gfx.ce_fw); 739 adev->gfx.ce_fw = NULL; 740 release_firmware(adev->gfx.rlc_fw); 741 adev->gfx.rlc_fw = NULL; 742 release_firmware(adev->gfx.mec_fw); 743 adev->gfx.mec_fw = NULL; 744 release_firmware(adev->gfx.mec2_fw); 745 adev->gfx.mec2_fw = NULL; 746 } 747 return err; 748 } 749 750 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 751 { 752 u32 count = 0; 753 const struct cs_section_def *sect = NULL; 754 const struct cs_extent_def *ext = NULL; 755 756 /* begin clear state */ 757 count += 2; 758 /* context control state */ 759 count += 3; 760 761 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 762 for (ext = sect->section; ext->extent != NULL; ++ext) { 763 if (sect->id == SECT_CONTEXT) 764 count += 2 + ext->reg_count; 765 else 766 return 0; 767 } 768 } 769 770 /* end clear state */ 771 count += 2; 772 /* clear state */ 773 count += 2; 774 775 return count; 776 } 777 778 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 779 volatile u32 *buffer) 780 { 781 u32 count = 0, i; 782 const struct cs_section_def *sect = NULL; 783 const struct cs_extent_def *ext = NULL; 784 785 if (adev->gfx.rlc.cs_data == NULL) 786 return; 787 if (buffer == NULL) 788 return; 789 790 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 791 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 792 793 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 794 buffer[count++] = cpu_to_le32(0x80000000); 795 buffer[count++] = cpu_to_le32(0x80000000); 796 797 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 798 for (ext = sect->section; ext->extent != NULL; ++ext) { 799 if (sect->id == SECT_CONTEXT) { 800 buffer[count++] = 801 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 802 buffer[count++] = cpu_to_le32(ext->reg_index - 803 PACKET3_SET_CONTEXT_REG_START); 804 for (i = 0; i < ext->reg_count; i++) 805 buffer[count++] = cpu_to_le32(ext->extent[i]); 806 } else { 807 return; 808 } 809 } 810 } 811 812 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 813 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 814 815 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 816 buffer[count++] = cpu_to_le32(0); 817 } 818 819 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 820 { 821 uint32_t data; 822 823 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 824 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 825 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 826 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 827 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 828 829 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 830 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 831 832 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 833 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 834 835 mutex_lock(&adev->grbm_idx_mutex); 836 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 837 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 838 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 839 840 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 841 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 842 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 843 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 844 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 845 846 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 847 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 848 data &= 0x0000FFFF; 849 data |= 0x00C00000; 850 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 851 852 /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */ 853 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF); 854 855 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 856 * but used for RLC_LB_CNTL configuration */ 857 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 858 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 859 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 860 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 861 mutex_unlock(&adev->grbm_idx_mutex); 862 } 863 864 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 865 { 866 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 867 } 868 869 static void rv_init_cp_jump_table(struct amdgpu_device *adev) 870 { 871 const __le32 *fw_data; 872 volatile u32 *dst_ptr; 873 int me, i, max_me = 5; 874 u32 bo_offset = 0; 875 u32 table_offset, table_size; 876 877 /* write the cp table buffer */ 878 dst_ptr = adev->gfx.rlc.cp_table_ptr; 879 for (me = 0; me < max_me; me++) { 880 if (me == 0) { 881 const struct gfx_firmware_header_v1_0 *hdr = 882 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 883 fw_data = (const __le32 *) 884 (adev->gfx.ce_fw->data + 885 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 886 table_offset = le32_to_cpu(hdr->jt_offset); 887 table_size = le32_to_cpu(hdr->jt_size); 888 } else if (me == 1) { 889 const struct gfx_firmware_header_v1_0 *hdr = 890 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 891 fw_data = (const __le32 *) 892 (adev->gfx.pfp_fw->data + 893 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 894 table_offset = le32_to_cpu(hdr->jt_offset); 895 table_size = le32_to_cpu(hdr->jt_size); 896 } else if (me == 2) { 897 const struct gfx_firmware_header_v1_0 *hdr = 898 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 899 fw_data = (const __le32 *) 900 (adev->gfx.me_fw->data + 901 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 902 table_offset = le32_to_cpu(hdr->jt_offset); 903 table_size = le32_to_cpu(hdr->jt_size); 904 } else if (me == 3) { 905 const struct gfx_firmware_header_v1_0 *hdr = 906 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 907 fw_data = (const __le32 *) 908 (adev->gfx.mec_fw->data + 909 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 910 table_offset = le32_to_cpu(hdr->jt_offset); 911 table_size = le32_to_cpu(hdr->jt_size); 912 } else if (me == 4) { 913 const struct gfx_firmware_header_v1_0 *hdr = 914 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; 915 fw_data = (const __le32 *) 916 (adev->gfx.mec2_fw->data + 917 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 918 table_offset = le32_to_cpu(hdr->jt_offset); 919 table_size = le32_to_cpu(hdr->jt_size); 920 } 921 922 for (i = 0; i < table_size; i ++) { 923 dst_ptr[bo_offset + i] = 924 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i])); 925 } 926 927 bo_offset += table_size; 928 } 929 } 930 931 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev) 932 { 933 /* clear state block */ 934 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 935 &adev->gfx.rlc.clear_state_gpu_addr, 936 (void **)&adev->gfx.rlc.cs_ptr); 937 938 /* jump table block */ 939 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 940 &adev->gfx.rlc.cp_table_gpu_addr, 941 (void **)&adev->gfx.rlc.cp_table_ptr); 942 } 943 944 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 945 { 946 volatile u32 *dst_ptr; 947 u32 dws; 948 const struct cs_section_def *cs_data; 949 int r; 950 951 adev->gfx.rlc.cs_data = gfx9_cs_data; 952 953 cs_data = adev->gfx.rlc.cs_data; 954 955 if (cs_data) { 956 /* clear state block */ 957 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev); 958 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE, 959 AMDGPU_GEM_DOMAIN_VRAM, 960 &adev->gfx.rlc.clear_state_obj, 961 &adev->gfx.rlc.clear_state_gpu_addr, 962 (void **)&adev->gfx.rlc.cs_ptr); 963 if (r) { 964 dev_err(adev->dev, "(%d) failed to create rlc csb bo\n", 965 r); 966 gfx_v9_0_rlc_fini(adev); 967 return r; 968 } 969 /* set up the cs buffer */ 970 dst_ptr = adev->gfx.rlc.cs_ptr; 971 gfx_v9_0_get_csb_buffer(adev, dst_ptr); 972 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); 973 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 974 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 975 } 976 977 if (adev->asic_type == CHIP_RAVEN) { 978 /* TODO: double check the cp_table_size for RV */ 979 adev->gfx.rlc.cp_table_size = roundup2(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 980 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, 981 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 982 &adev->gfx.rlc.cp_table_obj, 983 &adev->gfx.rlc.cp_table_gpu_addr, 984 (void **)&adev->gfx.rlc.cp_table_ptr); 985 if (r) { 986 dev_err(adev->dev, 987 "(%d) failed to create cp table bo\n", r); 988 gfx_v9_0_rlc_fini(adev); 989 return r; 990 } 991 992 rv_init_cp_jump_table(adev); 993 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); 994 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); 995 996 gfx_v9_0_init_lbpw(adev); 997 } 998 999 return 0; 1000 } 1001 1002 static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev) 1003 { 1004 int r; 1005 1006 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 1007 if (unlikely(r != 0)) 1008 return r; 1009 1010 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, 1011 AMDGPU_GEM_DOMAIN_VRAM); 1012 if (!r) 1013 adev->gfx.rlc.clear_state_gpu_addr = 1014 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); 1015 1016 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1017 1018 return r; 1019 } 1020 1021 static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev) 1022 { 1023 int r; 1024 1025 if (!adev->gfx.rlc.clear_state_obj) 1026 return; 1027 1028 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); 1029 if (likely(r == 0)) { 1030 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 1031 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 1032 } 1033 } 1034 1035 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 1036 { 1037 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1038 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1039 } 1040 1041 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 1042 { 1043 int r; 1044 u32 *hpd; 1045 const __le32 *fw_data; 1046 unsigned fw_size; 1047 u32 *fw; 1048 size_t mec_hpd_size; 1049 1050 const struct gfx_firmware_header_v1_0 *mec_hdr; 1051 1052 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1053 1054 /* take ownership of the relevant compute queues */ 1055 amdgpu_gfx_compute_queue_acquire(adev); 1056 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 1057 1058 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1059 AMDGPU_GEM_DOMAIN_GTT, 1060 &adev->gfx.mec.hpd_eop_obj, 1061 &adev->gfx.mec.hpd_eop_gpu_addr, 1062 (void **)&hpd); 1063 if (r) { 1064 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1065 gfx_v9_0_mec_fini(adev); 1066 return r; 1067 } 1068 1069 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 1070 1071 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1072 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1073 1074 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1075 1076 fw_data = (const __le32 *) 1077 (adev->gfx.mec_fw->data + 1078 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1079 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 1080 1081 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1082 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1083 &adev->gfx.mec.mec_fw_obj, 1084 &adev->gfx.mec.mec_fw_gpu_addr, 1085 (void **)&fw); 1086 if (r) { 1087 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 1088 gfx_v9_0_mec_fini(adev); 1089 return r; 1090 } 1091 1092 memcpy(fw, fw_data, fw_size); 1093 1094 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1095 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1096 1097 return 0; 1098 } 1099 1100 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 1101 { 1102 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1103 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1104 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1105 (address << SQ_IND_INDEX__INDEX__SHIFT) | 1106 (SQ_IND_INDEX__FORCE_READ_MASK)); 1107 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1108 } 1109 1110 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 1111 uint32_t wave, uint32_t thread, 1112 uint32_t regno, uint32_t num, uint32_t *out) 1113 { 1114 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1115 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1116 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 1117 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1118 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 1119 (SQ_IND_INDEX__FORCE_READ_MASK) | 1120 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1121 while (num--) 1122 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1123 } 1124 1125 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1126 { 1127 /* type 1 wave data */ 1128 dst[(*no_fields)++] = 1; 1129 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 1130 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 1131 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 1132 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 1133 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 1134 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 1135 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 1136 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 1137 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 1138 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 1139 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 1140 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 1141 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 1142 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 1143 } 1144 1145 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1146 uint32_t wave, uint32_t start, 1147 uint32_t size, uint32_t *dst) 1148 { 1149 wave_read_regs( 1150 adev, simd, wave, 0, 1151 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 1152 } 1153 1154 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1155 uint32_t wave, uint32_t thread, 1156 uint32_t start, uint32_t size, 1157 uint32_t *dst) 1158 { 1159 wave_read_regs( 1160 adev, simd, wave, thread, 1161 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1162 } 1163 1164 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 1165 u32 me, u32 pipe, u32 q) 1166 { 1167 soc15_grbm_select(adev, me, pipe, q, 0); 1168 } 1169 1170 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 1171 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 1172 .select_se_sh = &gfx_v9_0_select_se_sh, 1173 .read_wave_data = &gfx_v9_0_read_wave_data, 1174 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 1175 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 1176 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q 1177 }; 1178 1179 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 1180 { 1181 u32 gb_addr_config; 1182 int err; 1183 1184 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 1185 1186 switch (adev->asic_type) { 1187 case CHIP_VEGA10: 1188 adev->gfx.config.max_hw_contexts = 8; 1189 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1190 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1191 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1192 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1193 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 1194 break; 1195 case CHIP_VEGA12: 1196 adev->gfx.config.max_hw_contexts = 8; 1197 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1198 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1199 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1200 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1201 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; 1202 DRM_INFO("fix gfx.config for vega12\n"); 1203 break; 1204 case CHIP_VEGA20: 1205 adev->gfx.config.max_hw_contexts = 8; 1206 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1207 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1208 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1209 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1210 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1211 gb_addr_config &= ~0xf3e777ff; 1212 gb_addr_config |= 0x22014042; 1213 /* check vbios table if gpu info is not available */ 1214 err = amdgpu_atomfirmware_get_gfx_info(adev); 1215 if (err) 1216 return err; 1217 break; 1218 case CHIP_RAVEN: 1219 adev->gfx.config.max_hw_contexts = 8; 1220 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1221 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1222 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 1223 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1224 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 1225 break; 1226 default: 1227 BUG(); 1228 break; 1229 } 1230 1231 adev->gfx.config.gb_addr_config = gb_addr_config; 1232 1233 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1234 REG_GET_FIELD( 1235 adev->gfx.config.gb_addr_config, 1236 GB_ADDR_CONFIG, 1237 NUM_PIPES); 1238 1239 adev->gfx.config.max_tile_pipes = 1240 adev->gfx.config.gb_addr_config_fields.num_pipes; 1241 1242 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 1243 REG_GET_FIELD( 1244 adev->gfx.config.gb_addr_config, 1245 GB_ADDR_CONFIG, 1246 NUM_BANKS); 1247 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1248 REG_GET_FIELD( 1249 adev->gfx.config.gb_addr_config, 1250 GB_ADDR_CONFIG, 1251 MAX_COMPRESSED_FRAGS); 1252 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1253 REG_GET_FIELD( 1254 adev->gfx.config.gb_addr_config, 1255 GB_ADDR_CONFIG, 1256 NUM_RB_PER_SE); 1257 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1258 REG_GET_FIELD( 1259 adev->gfx.config.gb_addr_config, 1260 GB_ADDR_CONFIG, 1261 NUM_SHADER_ENGINES); 1262 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1263 REG_GET_FIELD( 1264 adev->gfx.config.gb_addr_config, 1265 GB_ADDR_CONFIG, 1266 PIPE_INTERLEAVE_SIZE)); 1267 1268 return 0; 1269 } 1270 1271 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev, 1272 struct amdgpu_ngg_buf *ngg_buf, 1273 int size_se, 1274 int default_size_se) 1275 { 1276 int r; 1277 1278 if (size_se < 0) { 1279 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se); 1280 return -EINVAL; 1281 } 1282 size_se = size_se ? size_se : default_size_se; 1283 1284 ngg_buf->size = size_se * adev->gfx.config.max_shader_engines; 1285 r = amdgpu_bo_create_kernel(adev, ngg_buf->size, 1286 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1287 &ngg_buf->bo, 1288 &ngg_buf->gpu_addr, 1289 NULL); 1290 if (r) { 1291 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r); 1292 return r; 1293 } 1294 ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo); 1295 1296 return r; 1297 } 1298 1299 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev) 1300 { 1301 int i; 1302 1303 for (i = 0; i < NGG_BUF_MAX; i++) 1304 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo, 1305 &adev->gfx.ngg.buf[i].gpu_addr, 1306 NULL); 1307 1308 memset(&adev->gfx.ngg.buf[0], 0, 1309 sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX); 1310 1311 adev->gfx.ngg.init = false; 1312 1313 return 0; 1314 } 1315 1316 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) 1317 { 1318 int r; 1319 1320 if (!amdgpu_ngg || adev->gfx.ngg.init == true) 1321 return 0; 1322 1323 /* GDS reserve memory: 64 bytes alignment */ 1324 adev->gfx.ngg.gds_reserve_size = roundup2(5 * 4, 0x40); 1325 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; 1326 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; 1327 adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); 1328 adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); 1329 1330 /* Primitive Buffer */ 1331 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], 1332 amdgpu_prim_buf_per_se, 1333 64 * 1024); 1334 if (r) { 1335 dev_err(adev->dev, "Failed to create Primitive Buffer\n"); 1336 goto err; 1337 } 1338 1339 /* Position Buffer */ 1340 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS], 1341 amdgpu_pos_buf_per_se, 1342 256 * 1024); 1343 if (r) { 1344 dev_err(adev->dev, "Failed to create Position Buffer\n"); 1345 goto err; 1346 } 1347 1348 /* Control Sideband */ 1349 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL], 1350 amdgpu_cntl_sb_buf_per_se, 1351 256); 1352 if (r) { 1353 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n"); 1354 goto err; 1355 } 1356 1357 /* Parameter Cache, not created by default */ 1358 if (amdgpu_param_buf_per_se <= 0) 1359 goto out; 1360 1361 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM], 1362 amdgpu_param_buf_per_se, 1363 512 * 1024); 1364 if (r) { 1365 dev_err(adev->dev, "Failed to create Parameter Cache\n"); 1366 goto err; 1367 } 1368 1369 out: 1370 adev->gfx.ngg.init = true; 1371 return 0; 1372 err: 1373 gfx_v9_0_ngg_fini(adev); 1374 return r; 1375 } 1376 1377 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) 1378 { 1379 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 1380 int r; 1381 u32 data, base; 1382 1383 if (!amdgpu_ngg) 1384 return 0; 1385 1386 /* Program buffer size */ 1387 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, 1388 adev->gfx.ngg.buf[NGG_PRIM].size >> 8); 1389 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, 1390 adev->gfx.ngg.buf[NGG_POS].size >> 8); 1391 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data); 1392 1393 data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, 1394 adev->gfx.ngg.buf[NGG_CNTL].size >> 8); 1395 data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, 1396 adev->gfx.ngg.buf[NGG_PARAM].size >> 10); 1397 WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data); 1398 1399 /* Program buffer base address */ 1400 base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); 1401 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base); 1402 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data); 1403 1404 base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr); 1405 data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base); 1406 WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data); 1407 1408 base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); 1409 data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base); 1410 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data); 1411 1412 base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr); 1413 data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base); 1414 WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data); 1415 1416 base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); 1417 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base); 1418 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data); 1419 1420 base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr); 1421 data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base); 1422 WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data); 1423 1424 /* Clear GDS reserved memory */ 1425 r = amdgpu_ring_alloc(ring, 17); 1426 if (r) { 1427 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n", 1428 ring->idx, r); 1429 return r; 1430 } 1431 1432 gfx_v9_0_write_data_to_reg(ring, 0, false, 1433 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 1434 (adev->gds.mem.total_size + 1435 adev->gfx.ngg.gds_reserve_size) >> 1436 AMDGPU_GDS_SHIFT); 1437 1438 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 1439 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 1440 PACKET3_DMA_DATA_DST_SEL(1) | 1441 PACKET3_DMA_DATA_SRC_SEL(2))); 1442 amdgpu_ring_write(ring, 0); 1443 amdgpu_ring_write(ring, 0); 1444 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); 1445 amdgpu_ring_write(ring, 0); 1446 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 1447 adev->gfx.ngg.gds_reserve_size); 1448 1449 gfx_v9_0_write_data_to_reg(ring, 0, false, 1450 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); 1451 1452 amdgpu_ring_commit(ring); 1453 1454 return 0; 1455 } 1456 1457 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1458 int mec, int pipe, int queue) 1459 { 1460 int r; 1461 unsigned irq_type; 1462 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1463 1464 ring = &adev->gfx.compute_ring[ring_id]; 1465 1466 /* mec0 is me1 */ 1467 ring->me = mec + 1; 1468 ring->pipe = pipe; 1469 ring->queue = queue; 1470 1471 ring->ring_obj = NULL; 1472 ring->use_doorbell = true; 1473 ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1; 1474 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1475 + (ring_id * GFX9_MEC_HPD_SIZE); 1476 snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1477 1478 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1479 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1480 + ring->pipe; 1481 1482 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1483 r = amdgpu_ring_init(adev, ring, 1024, 1484 &adev->gfx.eop_irq, irq_type); 1485 if (r) 1486 return r; 1487 1488 1489 return 0; 1490 } 1491 1492 static int gfx_v9_0_sw_init(void *handle) 1493 { 1494 int i, j, k, r, ring_id; 1495 struct amdgpu_ring *ring; 1496 struct amdgpu_kiq *kiq; 1497 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1498 1499 switch (adev->asic_type) { 1500 case CHIP_VEGA10: 1501 case CHIP_VEGA12: 1502 case CHIP_VEGA20: 1503 case CHIP_RAVEN: 1504 adev->gfx.mec.num_mec = 2; 1505 break; 1506 default: 1507 adev->gfx.mec.num_mec = 1; 1508 break; 1509 } 1510 1511 adev->gfx.mec.num_pipe_per_mec = 4; 1512 adev->gfx.mec.num_queue_per_pipe = 8; 1513 1514 /* KIQ event */ 1515 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_IB2_INTERRUPT_PKT, &adev->gfx.kiq.irq); 1516 if (r) 1517 return r; 1518 1519 /* EOP Event */ 1520 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 1521 if (r) 1522 return r; 1523 1524 /* Privileged reg */ 1525 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 1526 &adev->gfx.priv_reg_irq); 1527 if (r) 1528 return r; 1529 1530 /* Privileged inst */ 1531 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 1532 &adev->gfx.priv_inst_irq); 1533 if (r) 1534 return r; 1535 1536 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1537 1538 gfx_v9_0_scratch_init(adev); 1539 1540 r = gfx_v9_0_init_microcode(adev); 1541 if (r) { 1542 DRM_ERROR("Failed to load gfx firmware!\n"); 1543 return r; 1544 } 1545 1546 r = gfx_v9_0_rlc_init(adev); 1547 if (r) { 1548 DRM_ERROR("Failed to init rlc BOs!\n"); 1549 return r; 1550 } 1551 1552 r = gfx_v9_0_mec_init(adev); 1553 if (r) { 1554 DRM_ERROR("Failed to init MEC BOs!\n"); 1555 return r; 1556 } 1557 1558 /* set up the gfx ring */ 1559 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 1560 ring = &adev->gfx.gfx_ring[i]; 1561 ring->ring_obj = NULL; 1562 if (!i) 1563 snprintf(ring->name, sizeof(ring->name), "gfx"); 1564 else 1565 snprintf(ring->name, sizeof(ring->name), "gfx_%d", i); 1566 ring->use_doorbell = true; 1567 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1; 1568 r = amdgpu_ring_init(adev, ring, 1024, 1569 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); 1570 if (r) 1571 return r; 1572 } 1573 1574 /* set up the compute queues - allocate horizontally across pipes */ 1575 ring_id = 0; 1576 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1577 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1578 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1579 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 1580 continue; 1581 1582 r = gfx_v9_0_compute_ring_init(adev, 1583 ring_id, 1584 i, k, j); 1585 if (r) 1586 return r; 1587 1588 ring_id++; 1589 } 1590 } 1591 } 1592 1593 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 1594 if (r) { 1595 DRM_ERROR("Failed to init KIQ BOs!\n"); 1596 return r; 1597 } 1598 1599 kiq = &adev->gfx.kiq; 1600 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1601 if (r) 1602 return r; 1603 1604 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 1605 r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 1606 if (r) 1607 return r; 1608 1609 /* reserve GDS, GWS and OA resource for gfx */ 1610 r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, 1611 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, 1612 &adev->gds.gds_gfx_bo, NULL, NULL); 1613 if (r) 1614 return r; 1615 1616 r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, 1617 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, 1618 &adev->gds.gws_gfx_bo, NULL, NULL); 1619 if (r) 1620 return r; 1621 1622 r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, 1623 PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, 1624 &adev->gds.oa_gfx_bo, NULL, NULL); 1625 if (r) 1626 return r; 1627 1628 adev->gfx.ce_ram_size = 0x8000; 1629 1630 r = gfx_v9_0_gpu_early_init(adev); 1631 if (r) 1632 return r; 1633 1634 r = gfx_v9_0_ngg_init(adev); 1635 if (r) 1636 return r; 1637 1638 return 0; 1639 } 1640 1641 1642 static int gfx_v9_0_sw_fini(void *handle) 1643 { 1644 int i; 1645 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1646 1647 amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL); 1648 amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL); 1649 amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL); 1650 1651 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1652 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1653 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1654 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1655 1656 amdgpu_gfx_compute_mqd_sw_fini(adev); 1657 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); 1658 amdgpu_gfx_kiq_fini(adev); 1659 1660 gfx_v9_0_mec_fini(adev); 1661 gfx_v9_0_ngg_fini(adev); 1662 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 1663 &adev->gfx.rlc.clear_state_gpu_addr, 1664 (void **)&adev->gfx.rlc.cs_ptr); 1665 if (adev->asic_type == CHIP_RAVEN) { 1666 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 1667 &adev->gfx.rlc.cp_table_gpu_addr, 1668 (void **)&adev->gfx.rlc.cp_table_ptr); 1669 } 1670 gfx_v9_0_free_microcode(adev); 1671 1672 return 0; 1673 } 1674 1675 1676 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 1677 { 1678 /* TODO */ 1679 } 1680 1681 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) 1682 { 1683 u32 data; 1684 1685 if (instance == 0xffffffff) 1686 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 1687 else 1688 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 1689 1690 if (se_num == 0xffffffff) 1691 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 1692 else 1693 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1694 1695 if (sh_num == 0xffffffff) 1696 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 1697 else 1698 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 1699 1700 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1701 } 1702 1703 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1704 { 1705 u32 data, mask; 1706 1707 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1708 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1709 1710 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1711 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1712 1713 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1714 adev->gfx.config.max_sh_per_se); 1715 1716 return (~data) & mask; 1717 } 1718 1719 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 1720 { 1721 int i, j; 1722 u32 data; 1723 u32 active_rbs = 0; 1724 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1725 adev->gfx.config.max_sh_per_se; 1726 1727 mutex_lock(&adev->grbm_idx_mutex); 1728 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1729 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1730 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1731 data = gfx_v9_0_get_rb_active_bitmap(adev); 1732 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1733 rb_bitmap_width_per_sh); 1734 } 1735 } 1736 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1737 mutex_unlock(&adev->grbm_idx_mutex); 1738 1739 adev->gfx.config.backend_enable_mask = active_rbs; 1740 adev->gfx.config.num_rbs = hweight32(active_rbs); 1741 } 1742 1743 #define DEFAULT_SH_MEM_BASES (0x6000) 1744 #define FIRST_COMPUTE_VMID (8) 1745 #define LAST_COMPUTE_VMID (16) 1746 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 1747 { 1748 int i; 1749 uint32_t sh_mem_config; 1750 uint32_t sh_mem_bases; 1751 1752 /* 1753 * Configure apertures: 1754 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1755 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1756 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1757 */ 1758 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1759 1760 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 1761 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 1762 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 1763 1764 mutex_lock(&adev->srbm_mutex); 1765 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1766 soc15_grbm_select(adev, 0, 0, 0, i); 1767 /* CP and shaders */ 1768 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 1769 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1770 } 1771 soc15_grbm_select(adev, 0, 0, 0, 0); 1772 mutex_unlock(&adev->srbm_mutex); 1773 } 1774 1775 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) 1776 { 1777 u32 tmp; 1778 int i; 1779 1780 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1781 1782 gfx_v9_0_tiling_mode_table_init(adev); 1783 1784 gfx_v9_0_setup_rb(adev); 1785 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 1786 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); 1787 1788 /* XXX SH_MEM regs */ 1789 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1790 mutex_lock(&adev->srbm_mutex); 1791 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) { 1792 soc15_grbm_select(adev, 0, 0, 0, i); 1793 /* CP and shaders */ 1794 if (i == 0) { 1795 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1796 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1797 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); 1798 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0); 1799 } else { 1800 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 1801 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 1802 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); 1803 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1804 (adev->gmc.private_aperture_start >> 48)); 1805 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1806 (adev->gmc.shared_aperture_start >> 48)); 1807 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 1808 } 1809 } 1810 soc15_grbm_select(adev, 0, 0, 0, 0); 1811 1812 mutex_unlock(&adev->srbm_mutex); 1813 1814 gfx_v9_0_init_compute_vmid(adev); 1815 } 1816 1817 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 1818 { 1819 u32 i, j, k; 1820 u32 mask; 1821 1822 mutex_lock(&adev->grbm_idx_mutex); 1823 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1824 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1825 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1826 for (k = 0; k < adev->usec_timeout; k++) { 1827 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 1828 break; 1829 udelay(1); 1830 } 1831 if (k == adev->usec_timeout) { 1832 gfx_v9_0_select_se_sh(adev, 0xffffffff, 1833 0xffffffff, 0xffffffff); 1834 mutex_unlock(&adev->grbm_idx_mutex); 1835 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1836 i, j); 1837 return; 1838 } 1839 } 1840 } 1841 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1842 mutex_unlock(&adev->grbm_idx_mutex); 1843 1844 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 1845 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 1846 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 1847 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 1848 for (k = 0; k < adev->usec_timeout; k++) { 1849 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 1850 break; 1851 udelay(1); 1852 } 1853 } 1854 1855 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1856 bool enable) 1857 { 1858 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 1859 1860 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 1861 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 1862 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 1863 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 1864 1865 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 1866 } 1867 1868 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 1869 { 1870 /* csib */ 1871 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 1872 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1873 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 1874 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1875 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 1876 adev->gfx.rlc.clear_state_size); 1877 } 1878 1879 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, 1880 int indirect_offset, 1881 int list_size, 1882 int *unique_indirect_regs, 1883 int unique_indirect_reg_count, 1884 int *indirect_start_offsets, 1885 int *indirect_start_offsets_count, 1886 int max_start_offsets_count) 1887 { 1888 int idx; 1889 1890 for (; indirect_offset < list_size; indirect_offset++) { 1891 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); 1892 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 1893 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 1894 1895 while (register_list_format[indirect_offset] != 0xFFFFFFFF) { 1896 indirect_offset += 2; 1897 1898 /* look for the matching indice */ 1899 for (idx = 0; idx < unique_indirect_reg_count; idx++) { 1900 if (unique_indirect_regs[idx] == 1901 register_list_format[indirect_offset] || 1902 !unique_indirect_regs[idx]) 1903 break; 1904 } 1905 1906 BUG_ON(idx >= unique_indirect_reg_count); 1907 1908 if (!unique_indirect_regs[idx]) 1909 unique_indirect_regs[idx] = register_list_format[indirect_offset]; 1910 1911 indirect_offset++; 1912 } 1913 } 1914 } 1915 1916 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) 1917 { 1918 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 1919 int unique_indirect_reg_count = 0; 1920 1921 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 1922 int indirect_start_offsets_count = 0; 1923 1924 int list_size = 0; 1925 int i = 0, j = 0; 1926 u32 tmp = 0; 1927 1928 u32 *register_list_format = 1929 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 1930 if (!register_list_format) 1931 return -ENOMEM; 1932 memcpy(register_list_format, adev->gfx.rlc.register_list_format, 1933 adev->gfx.rlc.reg_list_format_size_bytes); 1934 1935 /* setup unique_indirect_regs array and indirect_start_offsets array */ 1936 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); 1937 gfx_v9_1_parse_ind_reg_list(register_list_format, 1938 adev->gfx.rlc.reg_list_format_direct_reg_list_length, 1939 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 1940 unique_indirect_regs, 1941 unique_indirect_reg_count, 1942 indirect_start_offsets, 1943 &indirect_start_offsets_count, 1944 ARRAY_SIZE(indirect_start_offsets)); 1945 1946 /* enable auto inc in case it is disabled */ 1947 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 1948 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1949 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 1950 1951 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 1952 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 1953 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 1954 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 1955 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 1956 adev->gfx.rlc.register_restore[i]); 1957 1958 /* load indirect register */ 1959 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 1960 adev->gfx.rlc.reg_list_format_start); 1961 1962 /* direct register portion */ 1963 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) 1964 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 1965 register_list_format[i]); 1966 1967 /* indirect register portion */ 1968 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { 1969 if (register_list_format[i] == 0xFFFFFFFF) { 1970 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 1971 continue; 1972 } 1973 1974 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 1975 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 1976 1977 for (j = 0; j < unique_indirect_reg_count; j++) { 1978 if (register_list_format[i] == unique_indirect_regs[j]) { 1979 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); 1980 break; 1981 } 1982 } 1983 1984 BUG_ON(j >= unique_indirect_reg_count); 1985 1986 i++; 1987 } 1988 1989 /* set save/restore list size */ 1990 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 1991 list_size = list_size >> 1; 1992 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 1993 adev->gfx.rlc.reg_restore_list_size); 1994 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 1995 1996 /* write the starting offsets to RLC scratch ram */ 1997 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 1998 adev->gfx.rlc.starting_offsets_start); 1999 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 2000 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2001 indirect_start_offsets[i]); 2002 2003 /* load unique indirect regs*/ 2004 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 2005 if (unique_indirect_regs[i] != 0) { 2006 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) 2007 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], 2008 unique_indirect_regs[i] & 0x3FFFF); 2009 2010 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) 2011 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], 2012 unique_indirect_regs[i] >> 20); 2013 } 2014 } 2015 2016 kfree(register_list_format); 2017 return 0; 2018 } 2019 2020 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 2021 { 2022 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 2023 } 2024 2025 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 2026 bool enable) 2027 { 2028 uint32_t data = 0; 2029 uint32_t default_data = 0; 2030 2031 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 2032 if (enable == true) { 2033 /* enable GFXIP control over CGPG */ 2034 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2035 if(default_data != data) 2036 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2037 2038 /* update status */ 2039 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 2040 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 2041 if(default_data != data) 2042 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2043 } else { 2044 /* restore GFXIP control over GCPG */ 2045 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2046 if(default_data != data) 2047 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2048 } 2049 } 2050 2051 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 2052 { 2053 uint32_t data = 0; 2054 2055 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2056 AMD_PG_SUPPORT_GFX_SMG | 2057 AMD_PG_SUPPORT_GFX_DMG)) { 2058 /* init IDLE_POLL_COUNT = 60 */ 2059 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2060 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 2061 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2062 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2063 2064 /* init RLC PG Delay */ 2065 data = 0; 2066 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 2067 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 2068 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 2069 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 2070 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 2071 2072 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 2073 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 2074 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 2075 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 2076 2077 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 2078 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 2079 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 2080 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 2081 2082 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 2083 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2084 2085 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 2086 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2087 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 2088 2089 pwr_10_0_gfxip_control_over_cgpg(adev, true); 2090 } 2091 } 2092 2093 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 2094 bool enable) 2095 { 2096 uint32_t data = 0; 2097 uint32_t default_data = 0; 2098 2099 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2100 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2101 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 2102 enable ? 1 : 0); 2103 if (default_data != data) 2104 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2105 } 2106 2107 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 2108 bool enable) 2109 { 2110 uint32_t data = 0; 2111 uint32_t default_data = 0; 2112 2113 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2114 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2115 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 2116 enable ? 1 : 0); 2117 if(default_data != data) 2118 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2119 } 2120 2121 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 2122 bool enable) 2123 { 2124 uint32_t data = 0; 2125 uint32_t default_data = 0; 2126 2127 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2128 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2129 CP_PG_DISABLE, 2130 enable ? 0 : 1); 2131 if(default_data != data) 2132 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2133 } 2134 2135 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 2136 bool enable) 2137 { 2138 uint32_t data, default_data; 2139 2140 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2141 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2142 GFX_POWER_GATING_ENABLE, 2143 enable ? 1 : 0); 2144 if(default_data != data) 2145 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2146 } 2147 2148 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 2149 bool enable) 2150 { 2151 uint32_t data, default_data; 2152 2153 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2154 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2155 GFX_PIPELINE_PG_ENABLE, 2156 enable ? 1 : 0); 2157 if(default_data != data) 2158 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2159 2160 if (!enable) 2161 /* read any GFX register to wake up GFX */ 2162 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 2163 } 2164 2165 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 2166 bool enable) 2167 { 2168 uint32_t data, default_data; 2169 2170 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2171 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2172 STATIC_PER_CU_PG_ENABLE, 2173 enable ? 1 : 0); 2174 if(default_data != data) 2175 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2176 } 2177 2178 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2179 bool enable) 2180 { 2181 uint32_t data, default_data; 2182 2183 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2184 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2185 DYN_PER_CU_PG_ENABLE, 2186 enable ? 1 : 0); 2187 if(default_data != data) 2188 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2189 } 2190 2191 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2192 { 2193 gfx_v9_0_init_csb(adev); 2194 2195 /* 2196 * Rlc save restore list is workable since v2_1. 2197 * And it's needed by gfxoff feature. 2198 */ 2199 if (adev->gfx.rlc.is_rlc_v2_1) { 2200 if (adev->asic_type == CHIP_VEGA12) 2201 gfx_v9_1_init_rlc_save_restore_list(adev); 2202 gfx_v9_0_enable_save_restore_machine(adev); 2203 } 2204 2205 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2206 AMD_PG_SUPPORT_GFX_SMG | 2207 AMD_PG_SUPPORT_GFX_DMG | 2208 AMD_PG_SUPPORT_CP | 2209 AMD_PG_SUPPORT_GDS | 2210 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2211 WREG32(mmRLC_JUMP_TABLE_RESTORE, 2212 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2213 gfx_v9_0_init_gfx_power_gating(adev); 2214 } 2215 } 2216 2217 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 2218 { 2219 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 2220 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 2221 gfx_v9_0_wait_for_rlc_serdes(adev); 2222 } 2223 2224 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 2225 { 2226 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 2227 udelay(50); 2228 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 2229 udelay(50); 2230 } 2231 2232 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 2233 { 2234 #ifdef AMDGPU_RLC_DEBUG_RETRY 2235 u32 rlc_ucode_ver; 2236 #endif 2237 2238 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 2239 udelay(50); 2240 2241 /* carrizo do enable cp interrupt after cp inited */ 2242 if (!(adev->flags & AMD_IS_APU)) { 2243 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 2244 udelay(50); 2245 } 2246 2247 #ifdef AMDGPU_RLC_DEBUG_RETRY 2248 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 2249 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 2250 if(rlc_ucode_ver == 0x108) { 2251 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 2252 rlc_ucode_ver, adev->gfx.rlc_fw_version); 2253 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 2254 * default is 0x9C4 to create a 100us interval */ 2255 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 2256 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 2257 * to disable the page fault retry interrupts, default is 2258 * 0x100 (256) */ 2259 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 2260 } 2261 #endif 2262 } 2263 2264 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 2265 { 2266 const struct rlc_firmware_header_v2_0 *hdr; 2267 const __le32 *fw_data; 2268 unsigned i, fw_size; 2269 2270 if (!adev->gfx.rlc_fw) 2271 return -EINVAL; 2272 2273 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 2274 amdgpu_ucode_print_rlc_hdr(&hdr->header); 2275 2276 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2277 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 2278 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 2279 2280 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 2281 RLCG_UCODE_LOADING_START_ADDRESS); 2282 for (i = 0; i < fw_size; i++) 2283 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 2284 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 2285 2286 return 0; 2287 } 2288 2289 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 2290 { 2291 int r; 2292 2293 if (amdgpu_sriov_vf(adev)) { 2294 gfx_v9_0_init_csb(adev); 2295 return 0; 2296 } 2297 2298 gfx_v9_0_rlc_stop(adev); 2299 2300 /* disable CG */ 2301 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 2302 2303 gfx_v9_0_rlc_reset(adev); 2304 2305 gfx_v9_0_init_pg(adev); 2306 2307 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 2308 /* legacy rlc firmware loading */ 2309 r = gfx_v9_0_rlc_load_microcode(adev); 2310 if (r) 2311 return r; 2312 } 2313 2314 if (adev->asic_type == CHIP_RAVEN) { 2315 if (amdgpu_lbpw != 0) 2316 gfx_v9_0_enable_lbpw(adev, true); 2317 else 2318 gfx_v9_0_enable_lbpw(adev, false); 2319 } 2320 2321 gfx_v9_0_rlc_start(adev); 2322 2323 return 0; 2324 } 2325 2326 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2327 { 2328 int i; 2329 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2330 2331 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2332 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2333 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2334 if (!enable) { 2335 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2336 adev->gfx.gfx_ring[i].ready = false; 2337 } 2338 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 2339 udelay(50); 2340 } 2341 2342 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2343 { 2344 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2345 const struct gfx_firmware_header_v1_0 *ce_hdr; 2346 const struct gfx_firmware_header_v1_0 *me_hdr; 2347 const __le32 *fw_data; 2348 unsigned i, fw_size; 2349 2350 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2351 return -EINVAL; 2352 2353 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2354 adev->gfx.pfp_fw->data; 2355 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2356 adev->gfx.ce_fw->data; 2357 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2358 adev->gfx.me_fw->data; 2359 2360 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2361 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2362 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2363 2364 gfx_v9_0_cp_gfx_enable(adev, false); 2365 2366 /* PFP */ 2367 fw_data = (const __le32 *) 2368 (adev->gfx.pfp_fw->data + 2369 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2370 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 2371 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 2372 for (i = 0; i < fw_size; i++) 2373 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 2374 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 2375 2376 /* CE */ 2377 fw_data = (const __le32 *) 2378 (adev->gfx.ce_fw->data + 2379 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2380 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 2381 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 2382 for (i = 0; i < fw_size; i++) 2383 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 2384 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 2385 2386 /* ME */ 2387 fw_data = (const __le32 *) 2388 (adev->gfx.me_fw->data + 2389 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2390 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 2391 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 2392 for (i = 0; i < fw_size; i++) 2393 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 2394 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 2395 2396 return 0; 2397 } 2398 2399 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 2400 { 2401 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 2402 const struct cs_section_def *sect = NULL; 2403 const struct cs_extent_def *ext = NULL; 2404 int r, i, tmp; 2405 2406 /* init the CP */ 2407 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 2408 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2409 2410 gfx_v9_0_cp_gfx_enable(adev, true); 2411 2412 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 2413 if (r) { 2414 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2415 return r; 2416 } 2417 2418 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2419 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2420 2421 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2422 amdgpu_ring_write(ring, 0x80000000); 2423 amdgpu_ring_write(ring, 0x80000000); 2424 2425 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 2426 for (ext = sect->section; ext->extent != NULL; ++ext) { 2427 if (sect->id == SECT_CONTEXT) { 2428 amdgpu_ring_write(ring, 2429 PACKET3(PACKET3_SET_CONTEXT_REG, 2430 ext->reg_count)); 2431 amdgpu_ring_write(ring, 2432 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 2433 for (i = 0; i < ext->reg_count; i++) 2434 amdgpu_ring_write(ring, ext->extent[i]); 2435 } 2436 } 2437 } 2438 2439 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2440 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2441 2442 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2443 amdgpu_ring_write(ring, 0); 2444 2445 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2446 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2447 amdgpu_ring_write(ring, 0x8000); 2448 amdgpu_ring_write(ring, 0x8000); 2449 2450 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 2451 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 2452 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 2453 amdgpu_ring_write(ring, tmp); 2454 amdgpu_ring_write(ring, 0); 2455 2456 amdgpu_ring_commit(ring); 2457 2458 return 0; 2459 } 2460 2461 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 2462 { 2463 struct amdgpu_ring *ring; 2464 u32 tmp; 2465 u32 rb_bufsz; 2466 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2467 2468 /* Set the write pointer delay */ 2469 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2470 2471 /* set the RB to use vmid 0 */ 2472 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2473 2474 /* Set ring buffer size */ 2475 ring = &adev->gfx.gfx_ring[0]; 2476 rb_bufsz = order_base_2(ring->ring_size / 8); 2477 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2478 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2479 #ifdef __BIG_ENDIAN 2480 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2481 #endif 2482 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2483 2484 /* Initialize the ring buffer's write pointers */ 2485 ring->wptr = 0; 2486 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2487 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2488 2489 /* set the wb address wether it's enabled or not */ 2490 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2491 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2492 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2493 2494 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2495 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 2496 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 2497 2498 mdelay(1); 2499 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2500 2501 rb_addr = ring->gpu_addr >> 8; 2502 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2503 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2504 2505 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2506 if (ring->use_doorbell) { 2507 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2508 DOORBELL_OFFSET, ring->doorbell_index); 2509 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2510 DOORBELL_EN, 1); 2511 } else { 2512 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 2513 } 2514 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2515 2516 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2517 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2518 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2519 2520 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2521 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2522 2523 2524 /* start the ring */ 2525 gfx_v9_0_cp_gfx_start(adev); 2526 ring->ready = true; 2527 2528 return 0; 2529 } 2530 2531 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2532 { 2533 int i; 2534 2535 if (enable) { 2536 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2537 } else { 2538 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2539 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2540 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2541 adev->gfx.compute_ring[i].ready = false; 2542 adev->gfx.kiq.ring.ready = false; 2543 } 2544 udelay(50); 2545 } 2546 2547 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2548 { 2549 const struct gfx_firmware_header_v1_0 *mec_hdr; 2550 const __le32 *fw_data; 2551 unsigned i; 2552 u32 tmp; 2553 2554 if (!adev->gfx.mec_fw) 2555 return -EINVAL; 2556 2557 gfx_v9_0_cp_compute_enable(adev, false); 2558 2559 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2560 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2561 2562 fw_data = (const __le32 *) 2563 (adev->gfx.mec_fw->data + 2564 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2565 tmp = 0; 2566 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2567 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2568 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2569 2570 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2571 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 2572 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2573 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2574 2575 /* MEC1 */ 2576 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 2577 mec_hdr->jt_offset); 2578 for (i = 0; i < mec_hdr->jt_size; i++) 2579 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 2580 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 2581 2582 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 2583 adev->gfx.mec_fw_version); 2584 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 2585 2586 return 0; 2587 } 2588 2589 /* KIQ functions */ 2590 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 2591 { 2592 uint32_t tmp; 2593 struct amdgpu_device *adev = ring->adev; 2594 2595 /* tell RLC which is KIQ queue */ 2596 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 2597 tmp &= 0xffffff00; 2598 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2599 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2600 tmp |= 0x80; 2601 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2602 } 2603 2604 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev) 2605 { 2606 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 2607 uint32_t scratch, tmp = 0; 2608 uint64_t queue_mask = 0; 2609 int r, i; 2610 2611 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { 2612 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) 2613 continue; 2614 2615 /* This situation may be hit in the future if a new HW 2616 * generation exposes more than 64 queues. If so, the 2617 * definition of queue_mask needs updating */ 2618 if (WARN_ON(i >= (sizeof(queue_mask)*8))) { 2619 DRM_ERROR("Invalid KCQ enabled: %d\n", i); 2620 break; 2621 } 2622 2623 queue_mask |= (1ull << i); 2624 } 2625 2626 r = amdgpu_gfx_scratch_get(adev, &scratch); 2627 if (r) { 2628 DRM_ERROR("Failed to get scratch reg (%d).\n", r); 2629 return r; 2630 } 2631 WREG32(scratch, 0xCAFEDEAD); 2632 2633 r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11); 2634 if (r) { 2635 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 2636 amdgpu_gfx_scratch_free(adev, scratch); 2637 return r; 2638 } 2639 2640 /* set resources */ 2641 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 2642 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 2643 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 2644 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 2645 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 2646 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 2647 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 2648 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 2649 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 2650 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2651 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; 2652 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 2653 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2654 2655 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 2656 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 2657 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 2658 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 2659 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 2660 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 2661 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 2662 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 2663 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 2664 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 2665 PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */ 2666 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 2667 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 2668 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 2669 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 2670 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 2671 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 2672 } 2673 /* write to scratch for completion */ 2674 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 2675 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 2676 amdgpu_ring_write(kiq_ring, 0xDEADBEEF); 2677 amdgpu_ring_commit(kiq_ring); 2678 2679 for (i = 0; i < adev->usec_timeout; i++) { 2680 tmp = RREG32(scratch); 2681 if (tmp == 0xDEADBEEF) 2682 break; 2683 DRM_UDELAY(1); 2684 } 2685 if (i >= adev->usec_timeout) { 2686 DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n", 2687 scratch, tmp); 2688 r = -EINVAL; 2689 } 2690 amdgpu_gfx_scratch_free(adev, scratch); 2691 2692 return r; 2693 } 2694 2695 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 2696 { 2697 struct amdgpu_device *adev = ring->adev; 2698 struct v9_mqd *mqd = ring->mqd_ptr; 2699 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 2700 uint32_t tmp; 2701 2702 mqd->header = 0xC0310800; 2703 mqd->compute_pipelinestat_enable = 0x00000001; 2704 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2705 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2706 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2707 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2708 mqd->compute_misc_reserved = 0x00000003; 2709 2710 mqd->dynamic_cu_mask_addr_lo = 2711 lower_32_bits(ring->mqd_gpu_addr 2712 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 2713 mqd->dynamic_cu_mask_addr_hi = 2714 upper_32_bits(ring->mqd_gpu_addr 2715 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 2716 2717 eop_base_addr = ring->eop_gpu_addr >> 8; 2718 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 2719 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 2720 2721 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2722 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 2723 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2724 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 2725 2726 mqd->cp_hqd_eop_control = tmp; 2727 2728 /* enable doorbell? */ 2729 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 2730 2731 if (ring->use_doorbell) { 2732 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2733 DOORBELL_OFFSET, ring->doorbell_index); 2734 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2735 DOORBELL_EN, 1); 2736 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2737 DOORBELL_SOURCE, 0); 2738 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2739 DOORBELL_HIT, 0); 2740 } else { 2741 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2742 DOORBELL_EN, 0); 2743 } 2744 2745 mqd->cp_hqd_pq_doorbell_control = tmp; 2746 2747 /* disable the queue if it's active */ 2748 ring->wptr = 0; 2749 mqd->cp_hqd_dequeue_request = 0; 2750 mqd->cp_hqd_pq_rptr = 0; 2751 mqd->cp_hqd_pq_wptr_lo = 0; 2752 mqd->cp_hqd_pq_wptr_hi = 0; 2753 2754 /* set the pointer to the MQD */ 2755 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 2756 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 2757 2758 /* set MQD vmid to 0 */ 2759 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 2760 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 2761 mqd->cp_mqd_control = tmp; 2762 2763 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2764 hqd_gpu_addr = ring->gpu_addr >> 8; 2765 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2766 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2767 2768 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2769 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 2770 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 2771 (order_base_2(ring->ring_size / 4) - 1)); 2772 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 2773 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 2774 #ifdef __BIG_ENDIAN 2775 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 2776 #endif 2777 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 2778 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 2779 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 2780 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 2781 mqd->cp_hqd_pq_control = tmp; 2782 2783 /* set the wb address whether it's enabled or not */ 2784 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2785 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2786 mqd->cp_hqd_pq_rptr_report_addr_hi = 2787 upper_32_bits(wb_gpu_addr) & 0xffff; 2788 2789 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2790 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2791 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2792 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2793 2794 tmp = 0; 2795 /* enable the doorbell if requested */ 2796 if (ring->use_doorbell) { 2797 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 2798 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2799 DOORBELL_OFFSET, ring->doorbell_index); 2800 2801 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2802 DOORBELL_EN, 1); 2803 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2804 DOORBELL_SOURCE, 0); 2805 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2806 DOORBELL_HIT, 0); 2807 } 2808 2809 mqd->cp_hqd_pq_doorbell_control = tmp; 2810 2811 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2812 ring->wptr = 0; 2813 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 2814 2815 /* set the vmid for the queue */ 2816 mqd->cp_hqd_vmid = 0; 2817 2818 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 2819 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 2820 mqd->cp_hqd_persistent_state = tmp; 2821 2822 /* set MIN_IB_AVAIL_SIZE */ 2823 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 2824 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 2825 mqd->cp_hqd_ib_control = tmp; 2826 2827 /* activate the queue */ 2828 mqd->cp_hqd_active = 1; 2829 2830 return 0; 2831 } 2832 2833 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 2834 { 2835 struct amdgpu_device *adev = ring->adev; 2836 struct v9_mqd *mqd = ring->mqd_ptr; 2837 int j; 2838 2839 /* disable wptr polling */ 2840 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 2841 2842 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 2843 mqd->cp_hqd_eop_base_addr_lo); 2844 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 2845 mqd->cp_hqd_eop_base_addr_hi); 2846 2847 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2848 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 2849 mqd->cp_hqd_eop_control); 2850 2851 /* enable doorbell? */ 2852 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 2853 mqd->cp_hqd_pq_doorbell_control); 2854 2855 /* disable the queue if it's active */ 2856 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 2857 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 2858 for (j = 0; j < adev->usec_timeout; j++) { 2859 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 2860 break; 2861 udelay(1); 2862 } 2863 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 2864 mqd->cp_hqd_dequeue_request); 2865 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 2866 mqd->cp_hqd_pq_rptr); 2867 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 2868 mqd->cp_hqd_pq_wptr_lo); 2869 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 2870 mqd->cp_hqd_pq_wptr_hi); 2871 } 2872 2873 /* set the pointer to the MQD */ 2874 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 2875 mqd->cp_mqd_base_addr_lo); 2876 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 2877 mqd->cp_mqd_base_addr_hi); 2878 2879 /* set MQD vmid to 0 */ 2880 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 2881 mqd->cp_mqd_control); 2882 2883 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2884 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 2885 mqd->cp_hqd_pq_base_lo); 2886 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 2887 mqd->cp_hqd_pq_base_hi); 2888 2889 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2890 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 2891 mqd->cp_hqd_pq_control); 2892 2893 /* set the wb address whether it's enabled or not */ 2894 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 2895 mqd->cp_hqd_pq_rptr_report_addr_lo); 2896 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 2897 mqd->cp_hqd_pq_rptr_report_addr_hi); 2898 2899 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2900 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 2901 mqd->cp_hqd_pq_wptr_poll_addr_lo); 2902 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 2903 mqd->cp_hqd_pq_wptr_poll_addr_hi); 2904 2905 /* enable the doorbell if requested */ 2906 if (ring->use_doorbell) { 2907 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 2908 (AMDGPU_DOORBELL64_KIQ *2) << 2); 2909 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 2910 (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2); 2911 } 2912 2913 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 2914 mqd->cp_hqd_pq_doorbell_control); 2915 2916 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2917 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 2918 mqd->cp_hqd_pq_wptr_lo); 2919 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 2920 mqd->cp_hqd_pq_wptr_hi); 2921 2922 /* set the vmid for the queue */ 2923 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 2924 2925 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 2926 mqd->cp_hqd_persistent_state); 2927 2928 /* activate the queue */ 2929 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 2930 mqd->cp_hqd_active); 2931 2932 if (ring->use_doorbell) 2933 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 2934 2935 return 0; 2936 } 2937 2938 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) 2939 { 2940 struct amdgpu_device *adev = ring->adev; 2941 int j; 2942 2943 /* disable the queue if it's active */ 2944 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 2945 2946 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 2947 2948 for (j = 0; j < adev->usec_timeout; j++) { 2949 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 2950 break; 2951 udelay(1); 2952 } 2953 2954 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 2955 DRM_DEBUG("KIQ dequeue request failed.\n"); 2956 2957 /* Manual disable if dequeue request times out */ 2958 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 2959 } 2960 2961 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 2962 0); 2963 } 2964 2965 WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0); 2966 WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0); 2967 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); 2968 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 2969 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 2970 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0); 2971 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); 2972 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); 2973 2974 return 0; 2975 } 2976 2977 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 2978 { 2979 struct amdgpu_device *adev = ring->adev; 2980 struct v9_mqd *mqd = ring->mqd_ptr; 2981 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 2982 2983 gfx_v9_0_kiq_setting(ring); 2984 2985 if (adev->in_gpu_reset) { /* for GPU_RESET case */ 2986 /* reset MQD to a clean status */ 2987 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2988 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 2989 2990 /* reset ring buffer */ 2991 ring->wptr = 0; 2992 amdgpu_ring_clear_ring(ring); 2993 2994 mutex_lock(&adev->srbm_mutex); 2995 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2996 gfx_v9_0_kiq_init_register(ring); 2997 soc15_grbm_select(adev, 0, 0, 0, 0); 2998 mutex_unlock(&adev->srbm_mutex); 2999 } else { 3000 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3001 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3002 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3003 mutex_lock(&adev->srbm_mutex); 3004 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3005 gfx_v9_0_mqd_init(ring); 3006 gfx_v9_0_kiq_init_register(ring); 3007 soc15_grbm_select(adev, 0, 0, 0, 0); 3008 mutex_unlock(&adev->srbm_mutex); 3009 3010 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3011 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3012 } 3013 3014 return 0; 3015 } 3016 3017 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 3018 { 3019 struct amdgpu_device *adev = ring->adev; 3020 struct v9_mqd *mqd = ring->mqd_ptr; 3021 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3022 3023 if (!adev->in_gpu_reset && !adev->gfx.in_suspend) { 3024 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3025 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3026 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3027 mutex_lock(&adev->srbm_mutex); 3028 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3029 gfx_v9_0_mqd_init(ring); 3030 soc15_grbm_select(adev, 0, 0, 0, 0); 3031 mutex_unlock(&adev->srbm_mutex); 3032 3033 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3034 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3035 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3036 /* reset MQD to a clean status */ 3037 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3038 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3039 3040 /* reset ring buffer */ 3041 ring->wptr = 0; 3042 amdgpu_ring_clear_ring(ring); 3043 } else { 3044 amdgpu_ring_clear_ring(ring); 3045 } 3046 3047 return 0; 3048 } 3049 3050 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3051 { 3052 struct amdgpu_ring *ring = NULL; 3053 int r = 0, i; 3054 3055 gfx_v9_0_cp_compute_enable(adev, true); 3056 3057 ring = &adev->gfx.kiq.ring; 3058 3059 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3060 if (unlikely(r != 0)) 3061 goto done; 3062 3063 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3064 if (!r) { 3065 r = gfx_v9_0_kiq_init_queue(ring); 3066 amdgpu_bo_kunmap(ring->mqd_obj); 3067 ring->mqd_ptr = NULL; 3068 } 3069 amdgpu_bo_unreserve(ring->mqd_obj); 3070 if (r) 3071 goto done; 3072 3073 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3074 ring = &adev->gfx.compute_ring[i]; 3075 3076 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3077 if (unlikely(r != 0)) 3078 goto done; 3079 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3080 if (!r) { 3081 r = gfx_v9_0_kcq_init_queue(ring); 3082 amdgpu_bo_kunmap(ring->mqd_obj); 3083 ring->mqd_ptr = NULL; 3084 } 3085 amdgpu_bo_unreserve(ring->mqd_obj); 3086 if (r) 3087 goto done; 3088 } 3089 3090 r = gfx_v9_0_kiq_kcq_enable(adev); 3091 done: 3092 return r; 3093 } 3094 3095 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 3096 { 3097 int r, i; 3098 struct amdgpu_ring *ring; 3099 3100 if (!(adev->flags & AMD_IS_APU)) 3101 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3102 3103 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3104 /* legacy firmware loading */ 3105 r = gfx_v9_0_cp_gfx_load_microcode(adev); 3106 if (r) 3107 return r; 3108 3109 r = gfx_v9_0_cp_compute_load_microcode(adev); 3110 if (r) 3111 return r; 3112 } 3113 3114 r = gfx_v9_0_cp_gfx_resume(adev); 3115 if (r) 3116 return r; 3117 3118 r = gfx_v9_0_kiq_resume(adev); 3119 if (r) 3120 return r; 3121 3122 ring = &adev->gfx.gfx_ring[0]; 3123 r = amdgpu_ring_test_ring(ring); 3124 if (r) { 3125 ring->ready = false; 3126 return r; 3127 } 3128 3129 ring = &adev->gfx.kiq.ring; 3130 ring->ready = true; 3131 r = amdgpu_ring_test_ring(ring); 3132 if (r) 3133 ring->ready = false; 3134 3135 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3136 ring = &adev->gfx.compute_ring[i]; 3137 3138 ring->ready = true; 3139 r = amdgpu_ring_test_ring(ring); 3140 if (r) 3141 ring->ready = false; 3142 } 3143 3144 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3145 3146 return 0; 3147 } 3148 3149 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 3150 { 3151 gfx_v9_0_cp_gfx_enable(adev, enable); 3152 gfx_v9_0_cp_compute_enable(adev, enable); 3153 } 3154 3155 static int gfx_v9_0_hw_init(void *handle) 3156 { 3157 int r; 3158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3159 3160 gfx_v9_0_init_golden_registers(adev); 3161 3162 gfx_v9_0_gpu_init(adev); 3163 3164 r = gfx_v9_0_csb_vram_pin(adev); 3165 if (r) 3166 return r; 3167 3168 r = gfx_v9_0_rlc_resume(adev); 3169 if (r) 3170 return r; 3171 3172 r = gfx_v9_0_cp_resume(adev); 3173 if (r) 3174 return r; 3175 3176 r = gfx_v9_0_ngg_en(adev); 3177 if (r) 3178 return r; 3179 3180 return r; 3181 } 3182 3183 static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring *ring) 3184 { 3185 struct amdgpu_device *adev = kiq_ring->adev; 3186 uint32_t scratch, tmp = 0; 3187 int r, i; 3188 3189 r = amdgpu_gfx_scratch_get(adev, &scratch); 3190 if (r) { 3191 DRM_ERROR("Failed to get scratch reg (%d).\n", r); 3192 return r; 3193 } 3194 WREG32(scratch, 0xCAFEDEAD); 3195 3196 r = amdgpu_ring_alloc(kiq_ring, 10); 3197 if (r) { 3198 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3199 amdgpu_gfx_scratch_free(adev, scratch); 3200 return r; 3201 } 3202 3203 /* unmap queues */ 3204 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3205 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3206 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */ 3207 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3208 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) | 3209 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3210 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3211 amdgpu_ring_write(kiq_ring, 0); 3212 amdgpu_ring_write(kiq_ring, 0); 3213 amdgpu_ring_write(kiq_ring, 0); 3214 /* write to scratch for completion */ 3215 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3216 amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 3217 amdgpu_ring_write(kiq_ring, 0xDEADBEEF); 3218 amdgpu_ring_commit(kiq_ring); 3219 3220 for (i = 0; i < adev->usec_timeout; i++) { 3221 tmp = RREG32(scratch); 3222 if (tmp == 0xDEADBEEF) 3223 break; 3224 DRM_UDELAY(1); 3225 } 3226 if (i >= adev->usec_timeout) { 3227 DRM_ERROR("KCQ disabled failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp); 3228 r = -EINVAL; 3229 } 3230 amdgpu_gfx_scratch_free(adev, scratch); 3231 return r; 3232 } 3233 3234 static int gfx_v9_0_hw_fini(void *handle) 3235 { 3236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3237 int i; 3238 3239 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX, 3240 AMD_PG_STATE_UNGATE); 3241 3242 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3243 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3244 3245 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3246 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3247 gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]); 3248 3249 if (amdgpu_sriov_vf(adev)) { 3250 gfx_v9_0_cp_gfx_enable(adev, false); 3251 /* must disable polling for SRIOV when hw finished, otherwise 3252 * CPC engine may still keep fetching WB address which is already 3253 * invalid after sw finished and trigger DMAR reading error in 3254 * hypervisor side. 3255 */ 3256 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3257 return 0; 3258 } 3259 3260 /* Use deinitialize sequence from CAIL when unbinding device from driver, 3261 * otherwise KIQ is hanging when binding back 3262 */ 3263 if (!adev->in_gpu_reset && !adev->gfx.in_suspend) { 3264 mutex_lock(&adev->srbm_mutex); 3265 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, 3266 adev->gfx.kiq.ring.pipe, 3267 adev->gfx.kiq.ring.queue, 0); 3268 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); 3269 soc15_grbm_select(adev, 0, 0, 0, 0); 3270 mutex_unlock(&adev->srbm_mutex); 3271 } 3272 3273 gfx_v9_0_cp_enable(adev, false); 3274 gfx_v9_0_rlc_stop(adev); 3275 3276 gfx_v9_0_csb_vram_unpin(adev); 3277 3278 return 0; 3279 } 3280 3281 static int gfx_v9_0_suspend(void *handle) 3282 { 3283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3284 3285 adev->gfx.in_suspend = true; 3286 return gfx_v9_0_hw_fini(adev); 3287 } 3288 3289 static int gfx_v9_0_resume(void *handle) 3290 { 3291 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3292 int r; 3293 3294 r = gfx_v9_0_hw_init(adev); 3295 adev->gfx.in_suspend = false; 3296 return r; 3297 } 3298 3299 static bool gfx_v9_0_is_idle(void *handle) 3300 { 3301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3302 3303 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3304 GRBM_STATUS, GUI_ACTIVE)) 3305 return false; 3306 else 3307 return true; 3308 } 3309 3310 static int gfx_v9_0_wait_for_idle(void *handle) 3311 { 3312 unsigned i; 3313 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3314 3315 for (i = 0; i < adev->usec_timeout; i++) { 3316 if (gfx_v9_0_is_idle(handle)) 3317 return 0; 3318 udelay(1); 3319 } 3320 return -ETIMEDOUT; 3321 } 3322 3323 static int gfx_v9_0_soft_reset(void *handle) 3324 { 3325 u32 grbm_soft_reset = 0; 3326 u32 tmp; 3327 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3328 3329 /* GRBM_STATUS */ 3330 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3331 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3332 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3333 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 3334 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 3335 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 3336 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 3337 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3338 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3339 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3340 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 3341 } 3342 3343 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3344 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3345 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 3346 } 3347 3348 /* GRBM_STATUS2 */ 3349 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3350 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3351 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3352 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3353 3354 3355 if (grbm_soft_reset) { 3356 /* stop the rlc */ 3357 gfx_v9_0_rlc_stop(adev); 3358 3359 /* Disable GFX parsing/prefetching */ 3360 gfx_v9_0_cp_gfx_enable(adev, false); 3361 3362 /* Disable MEC parsing/prefetching */ 3363 gfx_v9_0_cp_compute_enable(adev, false); 3364 3365 if (grbm_soft_reset) { 3366 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3367 tmp |= grbm_soft_reset; 3368 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3369 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3370 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3371 3372 udelay(50); 3373 3374 tmp &= ~grbm_soft_reset; 3375 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3376 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3377 } 3378 3379 /* Wait a little for things to settle down */ 3380 udelay(50); 3381 } 3382 return 0; 3383 } 3384 3385 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3386 { 3387 uint64_t clock; 3388 3389 mutex_lock(&adev->gfx.gpu_clock_mutex); 3390 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3391 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 3392 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3393 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3394 return clock; 3395 } 3396 3397 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3398 uint32_t vmid, 3399 uint32_t gds_base, uint32_t gds_size, 3400 uint32_t gws_base, uint32_t gws_size, 3401 uint32_t oa_base, uint32_t oa_size) 3402 { 3403 struct amdgpu_device *adev = ring->adev; 3404 3405 gds_base = gds_base >> AMDGPU_GDS_SHIFT; 3406 gds_size = gds_size >> AMDGPU_GDS_SHIFT; 3407 3408 gws_base = gws_base >> AMDGPU_GWS_SHIFT; 3409 gws_size = gws_size >> AMDGPU_GWS_SHIFT; 3410 3411 oa_base = oa_base >> AMDGPU_OA_SHIFT; 3412 oa_size = oa_size >> AMDGPU_OA_SHIFT; 3413 3414 /* GDS Base */ 3415 gfx_v9_0_write_data_to_reg(ring, 0, false, 3416 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 3417 gds_base); 3418 3419 /* GDS Size */ 3420 gfx_v9_0_write_data_to_reg(ring, 0, false, 3421 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 3422 gds_size); 3423 3424 /* GWS */ 3425 gfx_v9_0_write_data_to_reg(ring, 0, false, 3426 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 3427 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3428 3429 /* OA */ 3430 gfx_v9_0_write_data_to_reg(ring, 0, false, 3431 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 3432 (1 << (oa_size + oa_base)) - (1 << oa_base)); 3433 } 3434 3435 static int gfx_v9_0_early_init(void *handle) 3436 { 3437 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3438 3439 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 3440 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 3441 gfx_v9_0_set_ring_funcs(adev); 3442 gfx_v9_0_set_irq_funcs(adev); 3443 gfx_v9_0_set_gds_init(adev); 3444 gfx_v9_0_set_rlc_funcs(adev); 3445 3446 return 0; 3447 } 3448 3449 static int gfx_v9_0_late_init(void *handle) 3450 { 3451 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3452 int r; 3453 3454 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3455 if (r) 3456 return r; 3457 3458 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3459 if (r) 3460 return r; 3461 3462 return 0; 3463 } 3464 3465 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev) 3466 { 3467 uint32_t rlc_setting, data; 3468 unsigned i; 3469 3470 if (adev->gfx.rlc.in_safe_mode) 3471 return; 3472 3473 /* if RLC is not enabled, do nothing */ 3474 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3475 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 3476 return; 3477 3478 if (adev->cg_flags & 3479 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG | 3480 AMD_CG_SUPPORT_GFX_3D_CGCG)) { 3481 data = RLC_SAFE_MODE__CMD_MASK; 3482 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3483 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3484 3485 /* wait for RLC_SAFE_MODE */ 3486 for (i = 0; i < adev->usec_timeout; i++) { 3487 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 3488 break; 3489 udelay(1); 3490 } 3491 adev->gfx.rlc.in_safe_mode = true; 3492 } 3493 } 3494 3495 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev) 3496 { 3497 uint32_t rlc_setting, data; 3498 3499 if (!adev->gfx.rlc.in_safe_mode) 3500 return; 3501 3502 /* if RLC is not enabled, do nothing */ 3503 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3504 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 3505 return; 3506 3507 if (adev->cg_flags & 3508 (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) { 3509 /* 3510 * Try to exit safe mode only if it is already in safe 3511 * mode. 3512 */ 3513 data = RLC_SAFE_MODE__CMD_MASK; 3514 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3515 adev->gfx.rlc.in_safe_mode = false; 3516 } 3517 } 3518 3519 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 3520 bool enable) 3521 { 3522 gfx_v9_0_enter_rlc_safe_mode(adev); 3523 3524 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 3525 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 3526 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 3527 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 3528 } else { 3529 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 3530 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 3531 } 3532 3533 gfx_v9_0_exit_rlc_safe_mode(adev); 3534 } 3535 3536 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 3537 bool enable) 3538 { 3539 /* TODO: double check if we need to perform under safe mode */ 3540 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 3541 3542 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 3543 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 3544 else 3545 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 3546 3547 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 3548 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 3549 else 3550 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 3551 3552 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 3553 } 3554 3555 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3556 bool enable) 3557 { 3558 uint32_t data, def; 3559 3560 /* It is disabled by HW by default */ 3561 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3562 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3563 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3564 3565 if (adev->asic_type != CHIP_VEGA12) 3566 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 3567 3568 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3569 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3570 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3571 3572 /* only for Vega10 & Raven1 */ 3573 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 3574 3575 if (def != data) 3576 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3577 3578 /* MGLS is a global flag to control all MGLS in GFX */ 3579 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3580 /* 2 - RLC memory Light sleep */ 3581 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 3582 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3583 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3584 if (def != data) 3585 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3586 } 3587 /* 3 - CP memory Light sleep */ 3588 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3589 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3590 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3591 if (def != data) 3592 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3593 } 3594 } 3595 } else { 3596 /* 1 - MGCG_OVERRIDE */ 3597 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3598 3599 if (adev->asic_type != CHIP_VEGA12) 3600 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 3601 3602 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3603 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3604 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3605 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3606 3607 if (def != data) 3608 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3609 3610 /* 2 - disable MGLS in RLC */ 3611 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3612 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3613 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3614 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3615 } 3616 3617 /* 3 - disable MGLS in CP */ 3618 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3619 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3620 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3621 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3622 } 3623 } 3624 } 3625 3626 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 3627 bool enable) 3628 { 3629 uint32_t data, def; 3630 3631 adev->gfx.rlc.funcs->enter_safe_mode(adev); 3632 3633 /* Enable 3D CGCG/CGLS */ 3634 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 3635 /* write cmd to clear cgcg/cgls ov */ 3636 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3637 /* unset CGCG override */ 3638 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3639 /* update CGCG and CGLS override bits */ 3640 if (def != data) 3641 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3642 3643 /* enable 3Dcgcg FSM(0x0000363f) */ 3644 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3645 3646 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3647 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 3648 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3649 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3650 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 3651 if (def != data) 3652 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3653 3654 /* set IDLE_POLL_COUNT(0x00900100) */ 3655 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3656 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3657 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3658 if (def != data) 3659 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3660 } else { 3661 /* Disable CGCG/CGLS */ 3662 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3663 /* disable cgcg, cgls should be disabled */ 3664 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 3665 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 3666 /* disable cgcg and cgls in FSM */ 3667 if (def != data) 3668 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 3669 } 3670 3671 adev->gfx.rlc.funcs->exit_safe_mode(adev); 3672 } 3673 3674 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 3675 bool enable) 3676 { 3677 uint32_t def, data; 3678 3679 adev->gfx.rlc.funcs->enter_safe_mode(adev); 3680 3681 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 3682 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3683 /* unset CGCG override */ 3684 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3685 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3686 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3687 else 3688 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3689 /* update CGCG and CGLS override bits */ 3690 if (def != data) 3691 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3692 3693 /* enable cgcg FSM(0x0000363F) */ 3694 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3695 3696 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3697 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3698 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3699 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3700 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3701 if (def != data) 3702 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 3703 3704 /* set IDLE_POLL_COUNT(0x00900100) */ 3705 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 3706 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3707 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3708 if (def != data) 3709 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 3710 } else { 3711 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3712 /* reset CGCG/CGLS bits */ 3713 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 3714 /* disable cgcg and cgls in FSM */ 3715 if (def != data) 3716 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 3717 } 3718 3719 adev->gfx.rlc.funcs->exit_safe_mode(adev); 3720 } 3721 3722 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 3723 bool enable) 3724 { 3725 if (enable) { 3726 /* CGCG/CGLS should be enabled after MGCG/MGLS 3727 * === MGCG + MGLS === 3728 */ 3729 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 3730 /* === CGCG /CGLS for GFX 3D Only === */ 3731 gfx_v9_0_update_3d_clock_gating(adev, enable); 3732 /* === CGCG + CGLS === */ 3733 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 3734 } else { 3735 /* CGCG/CGLS should be disabled before MGCG/MGLS 3736 * === CGCG + CGLS === 3737 */ 3738 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 3739 /* === CGCG /CGLS for GFX 3D Only === */ 3740 gfx_v9_0_update_3d_clock_gating(adev, enable); 3741 /* === MGCG + MGLS === */ 3742 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 3743 } 3744 return 0; 3745 } 3746 3747 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 3748 .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode, 3749 .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode 3750 }; 3751 3752 static int gfx_v9_0_set_powergating_state(void *handle, 3753 enum amd_powergating_state state) 3754 { 3755 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3756 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 3757 3758 switch (adev->asic_type) { 3759 case CHIP_RAVEN: 3760 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 3761 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 3762 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 3763 } else { 3764 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 3765 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 3766 } 3767 3768 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 3769 gfx_v9_0_enable_cp_power_gating(adev, true); 3770 else 3771 gfx_v9_0_enable_cp_power_gating(adev, false); 3772 3773 /* update gfx cgpg state */ 3774 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 3775 3776 /* update mgcg state */ 3777 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 3778 3779 /* set gfx off through smu */ 3780 if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu) 3781 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true); 3782 break; 3783 case CHIP_VEGA12: 3784 /* set gfx off through smu */ 3785 if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu) 3786 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true); 3787 break; 3788 default: 3789 break; 3790 } 3791 3792 return 0; 3793 } 3794 3795 static int gfx_v9_0_set_clockgating_state(void *handle, 3796 enum amd_clockgating_state state) 3797 { 3798 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3799 3800 if (amdgpu_sriov_vf(adev)) 3801 return 0; 3802 3803 switch (adev->asic_type) { 3804 case CHIP_VEGA10: 3805 case CHIP_VEGA12: 3806 case CHIP_VEGA20: 3807 case CHIP_RAVEN: 3808 gfx_v9_0_update_gfx_clock_gating(adev, 3809 state == AMD_CG_STATE_GATE ? true : false); 3810 break; 3811 default: 3812 break; 3813 } 3814 return 0; 3815 } 3816 3817 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 3818 { 3819 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3820 int data; 3821 3822 if (amdgpu_sriov_vf(adev)) 3823 *flags = 0; 3824 3825 /* AMD_CG_SUPPORT_GFX_MGCG */ 3826 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3827 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 3828 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 3829 3830 /* AMD_CG_SUPPORT_GFX_CGCG */ 3831 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 3832 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 3833 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 3834 3835 /* AMD_CG_SUPPORT_GFX_CGLS */ 3836 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 3837 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 3838 3839 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 3840 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3841 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 3842 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 3843 3844 /* AMD_CG_SUPPORT_GFX_CP_LS */ 3845 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3846 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 3847 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 3848 3849 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 3850 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 3851 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 3852 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 3853 3854 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 3855 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 3856 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 3857 } 3858 3859 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 3860 { 3861 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/ 3862 } 3863 3864 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 3865 { 3866 struct amdgpu_device *adev = ring->adev; 3867 u64 wptr; 3868 3869 /* XXX check if swapping is necessary on BE */ 3870 if (ring->use_doorbell) { 3871 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 3872 } else { 3873 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 3874 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 3875 } 3876 3877 return wptr; 3878 } 3879 3880 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 3881 { 3882 struct amdgpu_device *adev = ring->adev; 3883 3884 if (ring->use_doorbell) { 3885 /* XXX check if swapping is necessary on BE */ 3886 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 3887 WDOORBELL64(ring->doorbell_index, ring->wptr); 3888 } else { 3889 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3890 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3891 } 3892 } 3893 3894 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 3895 { 3896 struct amdgpu_device *adev = ring->adev; 3897 u32 ref_and_mask, reg_mem_engine; 3898 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 3899 3900 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3901 switch (ring->me) { 3902 case 1: 3903 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 3904 break; 3905 case 2: 3906 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 3907 break; 3908 default: 3909 return; 3910 } 3911 reg_mem_engine = 0; 3912 } else { 3913 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 3914 reg_mem_engine = 1; /* pfp */ 3915 } 3916 3917 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 3918 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 3919 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 3920 ref_and_mask, ref_and_mask, 0x20); 3921 } 3922 3923 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 3924 struct amdgpu_ib *ib, 3925 unsigned vmid, bool ctx_switch) 3926 { 3927 u32 header, control = 0; 3928 3929 if (ib->flags & AMDGPU_IB_FLAG_CE) 3930 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 3931 else 3932 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 3933 3934 control |= ib->length_dw | (vmid << 24); 3935 3936 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 3937 control |= INDIRECT_BUFFER_PRE_ENB(1); 3938 3939 if (!(ib->flags & AMDGPU_IB_FLAG_CE)) 3940 gfx_v9_0_ring_emit_de_meta(ring); 3941 } 3942 3943 amdgpu_ring_write(ring, header); 3944 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3945 amdgpu_ring_write(ring, 3946 #ifdef __BIG_ENDIAN 3947 (2 << 0) | 3948 #endif 3949 lower_32_bits(ib->gpu_addr)); 3950 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3951 amdgpu_ring_write(ring, control); 3952 } 3953 3954 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 3955 struct amdgpu_ib *ib, 3956 unsigned vmid, bool ctx_switch) 3957 { 3958 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 3959 3960 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3961 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 3962 amdgpu_ring_write(ring, 3963 #ifdef __BIG_ENDIAN 3964 (2 << 0) | 3965 #endif 3966 lower_32_bits(ib->gpu_addr)); 3967 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3968 amdgpu_ring_write(ring, control); 3969 } 3970 3971 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 3972 u64 seq, unsigned flags) 3973 { 3974 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 3975 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 3976 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 3977 3978 /* RELEASE_MEM - flush caches, send int */ 3979 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 3980 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 3981 EOP_TC_NC_ACTION_EN) : 3982 (EOP_TCL1_ACTION_EN | 3983 EOP_TC_ACTION_EN | 3984 EOP_TC_WB_ACTION_EN | 3985 EOP_TC_MD_ACTION_EN)) | 3986 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3987 EVENT_INDEX(5))); 3988 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 3989 3990 /* 3991 * the address should be Qword aligned if 64bit write, Dword 3992 * aligned if only send 32bit data low (discard data high) 3993 */ 3994 if (write64bit) 3995 BUG_ON(addr & 0x7); 3996 else 3997 BUG_ON(addr & 0x3); 3998 amdgpu_ring_write(ring, lower_32_bits(addr)); 3999 amdgpu_ring_write(ring, upper_32_bits(addr)); 4000 amdgpu_ring_write(ring, lower_32_bits(seq)); 4001 amdgpu_ring_write(ring, upper_32_bits(seq)); 4002 amdgpu_ring_write(ring, 0); 4003 } 4004 4005 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4006 { 4007 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4008 uint32_t seq = ring->fence_drv.sync_seq; 4009 uint64_t addr = ring->fence_drv.gpu_addr; 4010 4011 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 4012 lower_32_bits(addr), upper_32_bits(addr), 4013 seq, 0xffffffff, 4); 4014 } 4015 4016 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4017 unsigned vmid, uint64_t pd_addr) 4018 { 4019 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4020 4021 /* compute doesn't have PFP */ 4022 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4023 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4024 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4025 amdgpu_ring_write(ring, 0x0); 4026 } 4027 } 4028 4029 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4030 { 4031 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 4032 } 4033 4034 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4035 { 4036 u64 wptr; 4037 4038 /* XXX check if swapping is necessary on BE */ 4039 if (ring->use_doorbell) 4040 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 4041 else 4042 BUG(); 4043 return wptr; 4044 } 4045 4046 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring, 4047 bool acquire) 4048 { 4049 struct amdgpu_device *adev = ring->adev; 4050 int pipe_num, tmp, reg; 4051 int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1; 4052 4053 pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe; 4054 4055 /* first me only has 2 entries, GFX and HP3D */ 4056 if (ring->me > 0) 4057 pipe_num -= 2; 4058 4059 reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num; 4060 tmp = RREG32(reg); 4061 tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent); 4062 WREG32(reg, tmp); 4063 } 4064 4065 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev, 4066 struct amdgpu_ring *ring, 4067 bool acquire) 4068 { 4069 int i, pipe; 4070 bool reserve; 4071 struct amdgpu_ring *iring; 4072 4073 mutex_lock(&adev->gfx.pipe_reserve_mutex); 4074 pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0); 4075 if (acquire) 4076 set_bit(pipe, adev->gfx.pipe_reserve_bitmap); 4077 else 4078 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap); 4079 4080 if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) { 4081 /* Clear all reservations - everyone reacquires all resources */ 4082 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) 4083 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i], 4084 true); 4085 4086 for (i = 0; i < adev->gfx.num_compute_rings; ++i) 4087 gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i], 4088 true); 4089 } else { 4090 /* Lower all pipes without a current reservation */ 4091 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) { 4092 iring = &adev->gfx.gfx_ring[i]; 4093 pipe = amdgpu_gfx_queue_to_bit(adev, 4094 iring->me, 4095 iring->pipe, 4096 0); 4097 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); 4098 gfx_v9_0_ring_set_pipe_percent(iring, reserve); 4099 } 4100 4101 for (i = 0; i < adev->gfx.num_compute_rings; ++i) { 4102 iring = &adev->gfx.compute_ring[i]; 4103 pipe = amdgpu_gfx_queue_to_bit(adev, 4104 iring->me, 4105 iring->pipe, 4106 0); 4107 reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap); 4108 gfx_v9_0_ring_set_pipe_percent(iring, reserve); 4109 } 4110 } 4111 4112 mutex_unlock(&adev->gfx.pipe_reserve_mutex); 4113 } 4114 4115 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev, 4116 struct amdgpu_ring *ring, 4117 bool acquire) 4118 { 4119 uint32_t pipe_priority = acquire ? 0x2 : 0x0; 4120 uint32_t queue_priority = acquire ? 0xf : 0x0; 4121 4122 mutex_lock(&adev->srbm_mutex); 4123 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 4124 4125 WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority); 4126 WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority); 4127 4128 soc15_grbm_select(adev, 0, 0, 0, 0); 4129 mutex_unlock(&adev->srbm_mutex); 4130 } 4131 4132 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring, 4133 enum drm_sched_priority priority) 4134 { 4135 struct amdgpu_device *adev = ring->adev; 4136 bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW; 4137 4138 if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) 4139 return; 4140 4141 gfx_v9_0_hqd_set_priority(adev, ring, acquire); 4142 gfx_v9_0_pipe_reserve_resources(adev, ring, acquire); 4143 } 4144 4145 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4146 { 4147 struct amdgpu_device *adev = ring->adev; 4148 4149 /* XXX check if swapping is necessary on BE */ 4150 if (ring->use_doorbell) { 4151 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4152 WDOORBELL64(ring->doorbell_index, ring->wptr); 4153 } else{ 4154 BUG(); /* only DOORBELL method supported on gfx9 now */ 4155 } 4156 } 4157 4158 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4159 u64 seq, unsigned int flags) 4160 { 4161 struct amdgpu_device *adev = ring->adev; 4162 4163 /* we only allocate 32bit for each seq wb address */ 4164 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4165 4166 /* write fence seq to the "addr" */ 4167 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4168 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4169 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4170 amdgpu_ring_write(ring, lower_32_bits(addr)); 4171 amdgpu_ring_write(ring, upper_32_bits(addr)); 4172 amdgpu_ring_write(ring, lower_32_bits(seq)); 4173 4174 if (flags & AMDGPU_FENCE_FLAG_INT) { 4175 /* set register to trigger INT */ 4176 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4177 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4178 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4179 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 4180 amdgpu_ring_write(ring, 0); 4181 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4182 } 4183 } 4184 4185 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 4186 { 4187 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4188 amdgpu_ring_write(ring, 0); 4189 } 4190 4191 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 4192 { 4193 struct v9_ce_ib_state ce_payload = {0}; 4194 uint64_t csa_addr; 4195 int cnt; 4196 4197 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 4198 csa_addr = amdgpu_csa_vaddr(ring->adev); 4199 4200 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4201 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 4202 WRITE_DATA_DST_SEL(8) | 4203 WR_CONFIRM) | 4204 WRITE_DATA_CACHE_POLICY(0)); 4205 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 4206 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 4207 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2); 4208 } 4209 4210 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) 4211 { 4212 struct v9_de_ib_state de_payload = {0}; 4213 uint64_t csa_addr, gds_addr; 4214 int cnt; 4215 4216 csa_addr = amdgpu_csa_vaddr(ring->adev); 4217 gds_addr = csa_addr + 4096; 4218 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 4219 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 4220 4221 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 4222 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4223 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 4224 WRITE_DATA_DST_SEL(8) | 4225 WR_CONFIRM) | 4226 WRITE_DATA_CACHE_POLICY(0)); 4227 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 4228 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 4229 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); 4230 } 4231 4232 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 4233 { 4234 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4235 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 4236 } 4237 4238 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 4239 { 4240 uint32_t dw2 = 0; 4241 4242 if (amdgpu_sriov_vf(ring->adev)) 4243 gfx_v9_0_ring_emit_ce_meta(ring); 4244 4245 gfx_v9_0_ring_emit_tmz(ring, true); 4246 4247 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4248 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4249 /* set load_global_config & load_global_uconfig */ 4250 dw2 |= 0x8001; 4251 /* set load_cs_sh_regs */ 4252 dw2 |= 0x01000000; 4253 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4254 dw2 |= 0x10002; 4255 4256 /* set load_ce_ram if preamble presented */ 4257 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 4258 dw2 |= 0x10000000; 4259 } else { 4260 /* still load_ce_ram if this is the first time preamble presented 4261 * although there is no context switch happens. 4262 */ 4263 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 4264 dw2 |= 0x10000000; 4265 } 4266 4267 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4268 amdgpu_ring_write(ring, dw2); 4269 amdgpu_ring_write(ring, 0); 4270 } 4271 4272 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 4273 { 4274 unsigned ret; 4275 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4276 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 4277 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 4278 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 4279 ret = ring->wptr & ring->buf_mask; 4280 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 4281 return ret; 4282 } 4283 4284 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 4285 { 4286 unsigned cur; 4287 BUG_ON(offset > ring->buf_mask); 4288 BUG_ON(ring->ring[offset] != 0x55aa55aa); 4289 4290 cur = (ring->wptr & ring->buf_mask) - 1; 4291 if (likely(cur > offset)) 4292 ring->ring[offset] = cur - offset; 4293 else 4294 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 4295 } 4296 4297 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 4298 { 4299 struct amdgpu_device *adev = ring->adev; 4300 4301 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4302 amdgpu_ring_write(ring, 0 | /* src: register*/ 4303 (5 << 8) | /* dst: memory */ 4304 (1 << 20)); /* write confirm */ 4305 amdgpu_ring_write(ring, reg); 4306 amdgpu_ring_write(ring, 0); 4307 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4308 adev->virt.reg_val_offs * 4)); 4309 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4310 adev->virt.reg_val_offs * 4)); 4311 } 4312 4313 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 4314 uint32_t val) 4315 { 4316 uint32_t cmd = 0; 4317 4318 switch (ring->funcs->type) { 4319 case AMDGPU_RING_TYPE_GFX: 4320 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4321 break; 4322 case AMDGPU_RING_TYPE_KIQ: 4323 cmd = (1 << 16); /* no inc addr */ 4324 break; 4325 default: 4326 cmd = WR_CONFIRM; 4327 break; 4328 } 4329 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4330 amdgpu_ring_write(ring, cmd); 4331 amdgpu_ring_write(ring, reg); 4332 amdgpu_ring_write(ring, 0); 4333 amdgpu_ring_write(ring, val); 4334 } 4335 4336 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4337 uint32_t val, uint32_t mask) 4338 { 4339 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4340 } 4341 4342 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4343 uint32_t reg0, uint32_t reg1, 4344 uint32_t ref, uint32_t mask) 4345 { 4346 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4347 4348 if (amdgpu_sriov_vf(ring->adev)) 4349 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4350 ref, mask, 0x20); 4351 else 4352 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 4353 ref, mask); 4354 } 4355 4356 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4357 enum amdgpu_interrupt_state state) 4358 { 4359 switch (state) { 4360 case AMDGPU_IRQ_STATE_DISABLE: 4361 case AMDGPU_IRQ_STATE_ENABLE: 4362 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4363 TIME_STAMP_INT_ENABLE, 4364 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4365 break; 4366 default: 4367 break; 4368 } 4369 } 4370 4371 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4372 int me, int pipe, 4373 enum amdgpu_interrupt_state state) 4374 { 4375 u32 mec_int_cntl, mec_int_cntl_reg; 4376 4377 /* 4378 * amdgpu controls only the first MEC. That's why this function only 4379 * handles the setting of interrupts for this specific MEC. All other 4380 * pipes' interrupts are set by amdkfd. 4381 */ 4382 4383 if (me == 1) { 4384 switch (pipe) { 4385 case 0: 4386 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4387 break; 4388 case 1: 4389 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 4390 break; 4391 case 2: 4392 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 4393 break; 4394 case 3: 4395 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 4396 break; 4397 default: 4398 DRM_DEBUG("invalid pipe %d\n", pipe); 4399 return; 4400 } 4401 } else { 4402 DRM_DEBUG("invalid me %d\n", me); 4403 return; 4404 } 4405 4406 switch (state) { 4407 case AMDGPU_IRQ_STATE_DISABLE: 4408 mec_int_cntl = RREG32(mec_int_cntl_reg); 4409 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4410 TIME_STAMP_INT_ENABLE, 0); 4411 WREG32(mec_int_cntl_reg, mec_int_cntl); 4412 break; 4413 case AMDGPU_IRQ_STATE_ENABLE: 4414 mec_int_cntl = RREG32(mec_int_cntl_reg); 4415 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4416 TIME_STAMP_INT_ENABLE, 1); 4417 WREG32(mec_int_cntl_reg, mec_int_cntl); 4418 break; 4419 default: 4420 break; 4421 } 4422 } 4423 4424 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4425 struct amdgpu_irq_src *source, 4426 unsigned type, 4427 enum amdgpu_interrupt_state state) 4428 { 4429 switch (state) { 4430 case AMDGPU_IRQ_STATE_DISABLE: 4431 case AMDGPU_IRQ_STATE_ENABLE: 4432 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4433 PRIV_REG_INT_ENABLE, 4434 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4435 break; 4436 default: 4437 break; 4438 } 4439 4440 return 0; 4441 } 4442 4443 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4444 struct amdgpu_irq_src *source, 4445 unsigned type, 4446 enum amdgpu_interrupt_state state) 4447 { 4448 switch (state) { 4449 case AMDGPU_IRQ_STATE_DISABLE: 4450 case AMDGPU_IRQ_STATE_ENABLE: 4451 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4452 PRIV_INSTR_INT_ENABLE, 4453 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4454 default: 4455 break; 4456 } 4457 4458 return 0; 4459 } 4460 4461 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4462 struct amdgpu_irq_src *src, 4463 unsigned type, 4464 enum amdgpu_interrupt_state state) 4465 { 4466 switch (type) { 4467 case AMDGPU_CP_IRQ_GFX_EOP: 4468 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 4469 break; 4470 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4471 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4472 break; 4473 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4474 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4475 break; 4476 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4477 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4478 break; 4479 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4480 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4481 break; 4482 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4483 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4484 break; 4485 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4486 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4487 break; 4488 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4489 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4490 break; 4491 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4492 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4493 break; 4494 default: 4495 break; 4496 } 4497 return 0; 4498 } 4499 4500 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 4501 struct amdgpu_irq_src *source, 4502 struct amdgpu_iv_entry *entry) 4503 { 4504 int i; 4505 u8 me_id, pipe_id, queue_id; 4506 struct amdgpu_ring *ring; 4507 4508 DRM_DEBUG("IH: CP EOP\n"); 4509 me_id = (entry->ring_id & 0x0c) >> 2; 4510 pipe_id = (entry->ring_id & 0x03) >> 0; 4511 queue_id = (entry->ring_id & 0x70) >> 4; 4512 4513 switch (me_id) { 4514 case 0: 4515 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4516 break; 4517 case 1: 4518 case 2: 4519 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4520 ring = &adev->gfx.compute_ring[i]; 4521 /* Per-queue interrupt is supported for MEC starting from VI. 4522 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4523 */ 4524 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4525 amdgpu_fence_process(ring); 4526 } 4527 break; 4528 } 4529 return 0; 4530 } 4531 4532 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 4533 struct amdgpu_irq_src *source, 4534 struct amdgpu_iv_entry *entry) 4535 { 4536 DRM_ERROR("Illegal register access in command stream\n"); 4537 schedule_work(&adev->reset_work); 4538 return 0; 4539 } 4540 4541 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 4542 struct amdgpu_irq_src *source, 4543 struct amdgpu_iv_entry *entry) 4544 { 4545 DRM_ERROR("Illegal instruction in command stream\n"); 4546 schedule_work(&adev->reset_work); 4547 return 0; 4548 } 4549 4550 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 4551 struct amdgpu_irq_src *src, 4552 unsigned int type, 4553 enum amdgpu_interrupt_state state) 4554 { 4555 uint32_t tmp, target; 4556 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 4557 4558 if (ring->me == 1) 4559 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4560 else 4561 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 4562 target += ring->pipe; 4563 4564 switch (type) { 4565 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 4566 if (state == AMDGPU_IRQ_STATE_DISABLE) { 4567 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 4568 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 4569 GENERIC2_INT_ENABLE, 0); 4570 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 4571 4572 tmp = RREG32(target); 4573 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 4574 GENERIC2_INT_ENABLE, 0); 4575 WREG32(target, tmp); 4576 } else { 4577 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 4578 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 4579 GENERIC2_INT_ENABLE, 1); 4580 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 4581 4582 tmp = RREG32(target); 4583 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 4584 GENERIC2_INT_ENABLE, 1); 4585 WREG32(target, tmp); 4586 } 4587 break; 4588 default: 4589 BUG(); /* kiq only support GENERIC2_INT now */ 4590 break; 4591 } 4592 return 0; 4593 } 4594 4595 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev, 4596 struct amdgpu_irq_src *source, 4597 struct amdgpu_iv_entry *entry) 4598 { 4599 u8 me_id, pipe_id, queue_id; 4600 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 4601 4602 me_id = (entry->ring_id & 0x0c) >> 2; 4603 pipe_id = (entry->ring_id & 0x03) >> 0; 4604 queue_id = (entry->ring_id & 0x70) >> 4; 4605 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 4606 me_id, pipe_id, queue_id); 4607 4608 amdgpu_fence_process(ring); 4609 return 0; 4610 } 4611 4612 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 4613 .name = "gfx_v9_0", 4614 .early_init = gfx_v9_0_early_init, 4615 .late_init = gfx_v9_0_late_init, 4616 .sw_init = gfx_v9_0_sw_init, 4617 .sw_fini = gfx_v9_0_sw_fini, 4618 .hw_init = gfx_v9_0_hw_init, 4619 .hw_fini = gfx_v9_0_hw_fini, 4620 .suspend = gfx_v9_0_suspend, 4621 .resume = gfx_v9_0_resume, 4622 .is_idle = gfx_v9_0_is_idle, 4623 .wait_for_idle = gfx_v9_0_wait_for_idle, 4624 .soft_reset = gfx_v9_0_soft_reset, 4625 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 4626 .set_powergating_state = gfx_v9_0_set_powergating_state, 4627 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 4628 }; 4629 4630 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 4631 .type = AMDGPU_RING_TYPE_GFX, 4632 .align_mask = 0xff, 4633 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4634 .support_64bit_ptrs = true, 4635 .vmhub = AMDGPU_GFXHUB, 4636 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 4637 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 4638 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 4639 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 4640 5 + /* COND_EXEC */ 4641 7 + /* PIPELINE_SYNC */ 4642 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4643 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4644 2 + /* VM_FLUSH */ 4645 8 + /* FENCE for VM_FLUSH */ 4646 20 + /* GDS switch */ 4647 4 + /* double SWITCH_BUFFER, 4648 the first COND_EXEC jump to the place just 4649 prior to this double SWITCH_BUFFER */ 4650 5 + /* COND_EXEC */ 4651 7 + /* HDP_flush */ 4652 4 + /* VGT_flush */ 4653 14 + /* CE_META */ 4654 31 + /* DE_META */ 4655 3 + /* CNTX_CTRL */ 4656 5 + /* HDP_INVL */ 4657 8 + 8 + /* FENCE x2 */ 4658 2, /* SWITCH_BUFFER */ 4659 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 4660 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 4661 .emit_fence = gfx_v9_0_ring_emit_fence, 4662 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 4663 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 4664 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 4665 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 4666 .test_ring = gfx_v9_0_ring_test_ring, 4667 .test_ib = gfx_v9_0_ring_test_ib, 4668 .insert_nop = amdgpu_ring_insert_nop, 4669 .pad_ib = amdgpu_ring_generic_pad_ib, 4670 .emit_switch_buffer = gfx_v9_ring_emit_sb, 4671 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 4672 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 4673 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 4674 .emit_tmz = gfx_v9_0_ring_emit_tmz, 4675 .emit_wreg = gfx_v9_0_ring_emit_wreg, 4676 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 4677 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 4678 }; 4679 4680 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 4681 .type = AMDGPU_RING_TYPE_COMPUTE, 4682 .align_mask = 0xff, 4683 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4684 .support_64bit_ptrs = true, 4685 .vmhub = AMDGPU_GFXHUB, 4686 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 4687 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 4688 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 4689 .emit_frame_size = 4690 20 + /* gfx_v9_0_ring_emit_gds_switch */ 4691 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 4692 5 + /* hdp invalidate */ 4693 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 4694 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4695 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4696 2 + /* gfx_v9_0_ring_emit_vm_flush */ 4697 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 4698 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ 4699 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 4700 .emit_fence = gfx_v9_0_ring_emit_fence, 4701 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 4702 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 4703 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 4704 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 4705 .test_ring = gfx_v9_0_ring_test_ring, 4706 .test_ib = gfx_v9_0_ring_test_ib, 4707 .insert_nop = amdgpu_ring_insert_nop, 4708 .pad_ib = amdgpu_ring_generic_pad_ib, 4709 .set_priority = gfx_v9_0_ring_set_priority_compute, 4710 .emit_wreg = gfx_v9_0_ring_emit_wreg, 4711 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 4712 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 4713 }; 4714 4715 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 4716 .type = AMDGPU_RING_TYPE_KIQ, 4717 .align_mask = 0xff, 4718 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 4719 .support_64bit_ptrs = true, 4720 .vmhub = AMDGPU_GFXHUB, 4721 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 4722 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 4723 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 4724 .emit_frame_size = 4725 20 + /* gfx_v9_0_ring_emit_gds_switch */ 4726 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 4727 5 + /* hdp invalidate */ 4728 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 4729 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 4730 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 4731 2 + /* gfx_v9_0_ring_emit_vm_flush */ 4732 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 4733 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */ 4734 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 4735 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 4736 .test_ring = gfx_v9_0_ring_test_ring, 4737 .test_ib = gfx_v9_0_ring_test_ib, 4738 .insert_nop = amdgpu_ring_insert_nop, 4739 .pad_ib = amdgpu_ring_generic_pad_ib, 4740 .emit_rreg = gfx_v9_0_ring_emit_rreg, 4741 .emit_wreg = gfx_v9_0_ring_emit_wreg, 4742 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 4743 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 4744 }; 4745 4746 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 4747 { 4748 int i; 4749 4750 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 4751 4752 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4753 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 4754 4755 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4756 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 4757 } 4758 4759 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = { 4760 .set = gfx_v9_0_kiq_set_interrupt_state, 4761 .process = gfx_v9_0_kiq_irq, 4762 }; 4763 4764 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 4765 .set = gfx_v9_0_set_eop_interrupt_state, 4766 .process = gfx_v9_0_eop_irq, 4767 }; 4768 4769 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 4770 .set = gfx_v9_0_set_priv_reg_fault_state, 4771 .process = gfx_v9_0_priv_reg_irq, 4772 }; 4773 4774 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 4775 .set = gfx_v9_0_set_priv_inst_fault_state, 4776 .process = gfx_v9_0_priv_inst_irq, 4777 }; 4778 4779 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 4780 { 4781 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 4782 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 4783 4784 adev->gfx.priv_reg_irq.num_types = 1; 4785 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 4786 4787 adev->gfx.priv_inst_irq.num_types = 1; 4788 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 4789 4790 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 4791 adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs; 4792 } 4793 4794 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 4795 { 4796 switch (adev->asic_type) { 4797 case CHIP_VEGA10: 4798 case CHIP_VEGA12: 4799 case CHIP_VEGA20: 4800 case CHIP_RAVEN: 4801 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 4802 break; 4803 default: 4804 break; 4805 } 4806 } 4807 4808 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 4809 { 4810 /* init asci gds info */ 4811 adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); 4812 adev->gds.gws.total_size = 64; 4813 adev->gds.oa.total_size = 16; 4814 4815 if (adev->gds.mem.total_size == 64 * 1024) { 4816 adev->gds.mem.gfx_partition_size = 4096; 4817 adev->gds.mem.cs_partition_size = 4096; 4818 4819 adev->gds.gws.gfx_partition_size = 4; 4820 adev->gds.gws.cs_partition_size = 4; 4821 4822 adev->gds.oa.gfx_partition_size = 4; 4823 adev->gds.oa.cs_partition_size = 1; 4824 } else { 4825 adev->gds.mem.gfx_partition_size = 1024; 4826 adev->gds.mem.cs_partition_size = 1024; 4827 4828 adev->gds.gws.gfx_partition_size = 16; 4829 adev->gds.gws.cs_partition_size = 16; 4830 4831 adev->gds.oa.gfx_partition_size = 4; 4832 adev->gds.oa.cs_partition_size = 4; 4833 } 4834 } 4835 4836 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 4837 u32 bitmap) 4838 { 4839 u32 data; 4840 4841 if (!bitmap) 4842 return; 4843 4844 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4845 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4846 4847 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 4848 } 4849 4850 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 4851 { 4852 u32 data, mask; 4853 4854 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 4855 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 4856 4857 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 4858 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 4859 4860 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 4861 4862 return (~data) & mask; 4863 } 4864 4865 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 4866 struct amdgpu_cu_info *cu_info) 4867 { 4868 int i, j, k, counter, active_cu_number = 0; 4869 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 4870 unsigned disable_masks[4 * 2]; 4871 4872 if (!adev || !cu_info) 4873 return -EINVAL; 4874 4875 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 4876 4877 mutex_lock(&adev->grbm_idx_mutex); 4878 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4879 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4880 mask = 1; 4881 ao_bitmap = 0; 4882 counter = 0; 4883 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 4884 if (i < 4 && j < 2) 4885 gfx_v9_0_set_user_cu_inactive_bitmap( 4886 adev, disable_masks[i * 2 + j]); 4887 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 4888 cu_info->bitmap[i][j] = bitmap; 4889 4890 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 4891 if (bitmap & mask) { 4892 if (counter < adev->gfx.config.max_cu_per_sh) 4893 ao_bitmap |= mask; 4894 counter ++; 4895 } 4896 mask <<= 1; 4897 } 4898 active_cu_number += counter; 4899 if (i < 2 && j < 2) 4900 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 4901 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 4902 } 4903 } 4904 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4905 mutex_unlock(&adev->grbm_idx_mutex); 4906 4907 cu_info->number = active_cu_number; 4908 cu_info->ao_cu_mask = ao_cu_mask; 4909 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 4910 4911 return 0; 4912 } 4913 4914 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 4915 { 4916 .type = AMD_IP_BLOCK_TYPE_GFX, 4917 .major = 9, 4918 .minor = 0, 4919 .rev = 0, 4920 .funcs = &gfx_v9_0_ip_funcs, 4921 }; 4922