1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 30 #include "amdgpu.h" 31 #include "amdgpu_gfx.h" 32 #include "soc15.h" 33 #include "soc15d.h" 34 #include "amdgpu_atomfirmware.h" 35 #include "amdgpu_pm.h" 36 37 #include "gc/gc_9_0_offset.h" 38 #include "gc/gc_9_0_sh_mask.h" 39 40 #include "vega10_enum.h" 41 #include "hdp/hdp_4_0_offset.h" 42 43 #include "soc15_common.h" 44 #include "clearstate_gfx9.h" 45 #include "v9_structs.h" 46 47 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" 48 49 #include "amdgpu_ras.h" 50 51 #include "gfx_v9_4.h" 52 53 #define GFX9_NUM_GFX_RINGS 1 54 #define GFX9_MEC_HPD_SIZE 4096 55 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 56 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L 57 58 #define mmPWR_MISC_CNTL_STATUS 0x0183 59 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0 60 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 61 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 62 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L 63 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L 64 65 #define mmGCEA_PROBE_MAP 0x070c 66 #define mmGCEA_PROBE_MAP_BASE_IDX 0 67 68 MODULE_FIRMWARE("amdgpu/vega10_ce.bin"); 69 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin"); 70 MODULE_FIRMWARE("amdgpu/vega10_me.bin"); 71 MODULE_FIRMWARE("amdgpu/vega10_mec.bin"); 72 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin"); 73 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin"); 74 75 MODULE_FIRMWARE("amdgpu/vega12_ce.bin"); 76 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin"); 77 MODULE_FIRMWARE("amdgpu/vega12_me.bin"); 78 MODULE_FIRMWARE("amdgpu/vega12_mec.bin"); 79 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin"); 80 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin"); 81 82 MODULE_FIRMWARE("amdgpu/vega20_ce.bin"); 83 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin"); 84 MODULE_FIRMWARE("amdgpu/vega20_me.bin"); 85 MODULE_FIRMWARE("amdgpu/vega20_mec.bin"); 86 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin"); 87 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin"); 88 89 MODULE_FIRMWARE("amdgpu/raven_ce.bin"); 90 MODULE_FIRMWARE("amdgpu/raven_pfp.bin"); 91 MODULE_FIRMWARE("amdgpu/raven_me.bin"); 92 MODULE_FIRMWARE("amdgpu/raven_mec.bin"); 93 MODULE_FIRMWARE("amdgpu/raven_mec2.bin"); 94 MODULE_FIRMWARE("amdgpu/raven_rlc.bin"); 95 96 MODULE_FIRMWARE("amdgpu/picasso_ce.bin"); 97 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin"); 98 MODULE_FIRMWARE("amdgpu/picasso_me.bin"); 99 MODULE_FIRMWARE("amdgpu/picasso_mec.bin"); 100 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin"); 101 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin"); 102 MODULE_FIRMWARE("amdgpu/picasso_rlc_am4.bin"); 103 104 MODULE_FIRMWARE("amdgpu/raven2_ce.bin"); 105 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin"); 106 MODULE_FIRMWARE("amdgpu/raven2_me.bin"); 107 MODULE_FIRMWARE("amdgpu/raven2_mec.bin"); 108 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin"); 109 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin"); 110 MODULE_FIRMWARE("amdgpu/raven_kicker_rlc.bin"); 111 112 MODULE_FIRMWARE("amdgpu/arcturus_mec.bin"); 113 MODULE_FIRMWARE("amdgpu/arcturus_mec2.bin"); 114 MODULE_FIRMWARE("amdgpu/arcturus_rlc.bin"); 115 116 MODULE_FIRMWARE("amdgpu/renoir_ce.bin"); 117 MODULE_FIRMWARE("amdgpu/renoir_pfp.bin"); 118 MODULE_FIRMWARE("amdgpu/renoir_me.bin"); 119 MODULE_FIRMWARE("amdgpu/renoir_mec.bin"); 120 MODULE_FIRMWARE("amdgpu/renoir_mec2.bin"); 121 MODULE_FIRMWARE("amdgpu/renoir_rlc.bin"); 122 123 #define mmTCP_CHAN_STEER_0_ARCT 0x0b03 124 #define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0 125 #define mmTCP_CHAN_STEER_1_ARCT 0x0b04 126 #define mmTCP_CHAN_STEER_1_ARCT_BASE_IDX 0 127 #define mmTCP_CHAN_STEER_2_ARCT 0x0b09 128 #define mmTCP_CHAN_STEER_2_ARCT_BASE_IDX 0 129 #define mmTCP_CHAN_STEER_3_ARCT 0x0b0a 130 #define mmTCP_CHAN_STEER_3_ARCT_BASE_IDX 0 131 #define mmTCP_CHAN_STEER_4_ARCT 0x0b0b 132 #define mmTCP_CHAN_STEER_4_ARCT_BASE_IDX 0 133 #define mmTCP_CHAN_STEER_5_ARCT 0x0b0c 134 #define mmTCP_CHAN_STEER_5_ARCT_BASE_IDX 0 135 136 enum ta_ras_gfx_subblock { 137 /*CPC*/ 138 TA_RAS_BLOCK__GFX_CPC_INDEX_START = 0, 139 TA_RAS_BLOCK__GFX_CPC_SCRATCH = TA_RAS_BLOCK__GFX_CPC_INDEX_START, 140 TA_RAS_BLOCK__GFX_CPC_UCODE, 141 TA_RAS_BLOCK__GFX_DC_STATE_ME1, 142 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1, 143 TA_RAS_BLOCK__GFX_DC_RESTORE_ME1, 144 TA_RAS_BLOCK__GFX_DC_STATE_ME2, 145 TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2, 146 TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 147 TA_RAS_BLOCK__GFX_CPC_INDEX_END = TA_RAS_BLOCK__GFX_DC_RESTORE_ME2, 148 /* CPF*/ 149 TA_RAS_BLOCK__GFX_CPF_INDEX_START, 150 TA_RAS_BLOCK__GFX_CPF_ROQ_ME2 = TA_RAS_BLOCK__GFX_CPF_INDEX_START, 151 TA_RAS_BLOCK__GFX_CPF_ROQ_ME1, 152 TA_RAS_BLOCK__GFX_CPF_TAG, 153 TA_RAS_BLOCK__GFX_CPF_INDEX_END = TA_RAS_BLOCK__GFX_CPF_TAG, 154 /* CPG*/ 155 TA_RAS_BLOCK__GFX_CPG_INDEX_START, 156 TA_RAS_BLOCK__GFX_CPG_DMA_ROQ = TA_RAS_BLOCK__GFX_CPG_INDEX_START, 157 TA_RAS_BLOCK__GFX_CPG_DMA_TAG, 158 TA_RAS_BLOCK__GFX_CPG_TAG, 159 TA_RAS_BLOCK__GFX_CPG_INDEX_END = TA_RAS_BLOCK__GFX_CPG_TAG, 160 /* GDS*/ 161 TA_RAS_BLOCK__GFX_GDS_INDEX_START, 162 TA_RAS_BLOCK__GFX_GDS_MEM = TA_RAS_BLOCK__GFX_GDS_INDEX_START, 163 TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, 164 TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, 165 TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, 166 TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 167 TA_RAS_BLOCK__GFX_GDS_INDEX_END = TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, 168 /* SPI*/ 169 TA_RAS_BLOCK__GFX_SPI_SR_MEM, 170 /* SQ*/ 171 TA_RAS_BLOCK__GFX_SQ_INDEX_START, 172 TA_RAS_BLOCK__GFX_SQ_SGPR = TA_RAS_BLOCK__GFX_SQ_INDEX_START, 173 TA_RAS_BLOCK__GFX_SQ_LDS_D, 174 TA_RAS_BLOCK__GFX_SQ_LDS_I, 175 TA_RAS_BLOCK__GFX_SQ_VGPR, /* VGPR = SP*/ 176 TA_RAS_BLOCK__GFX_SQ_INDEX_END = TA_RAS_BLOCK__GFX_SQ_VGPR, 177 /* SQC (3 ranges)*/ 178 TA_RAS_BLOCK__GFX_SQC_INDEX_START, 179 /* SQC range 0*/ 180 TA_RAS_BLOCK__GFX_SQC_INDEX0_START = TA_RAS_BLOCK__GFX_SQC_INDEX_START, 181 TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = 182 TA_RAS_BLOCK__GFX_SQC_INDEX0_START, 183 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 184 TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, 185 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 186 TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, 187 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 188 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 189 TA_RAS_BLOCK__GFX_SQC_INDEX0_END = 190 TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, 191 /* SQC range 1*/ 192 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 193 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = 194 TA_RAS_BLOCK__GFX_SQC_INDEX1_START, 195 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 196 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, 197 TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, 198 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, 199 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, 200 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, 201 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 202 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 203 TA_RAS_BLOCK__GFX_SQC_INDEX1_END = 204 TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, 205 /* SQC range 2*/ 206 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 207 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = 208 TA_RAS_BLOCK__GFX_SQC_INDEX2_START, 209 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 210 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, 211 TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, 212 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, 213 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, 214 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, 215 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 216 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 217 TA_RAS_BLOCK__GFX_SQC_INDEX2_END = 218 TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, 219 TA_RAS_BLOCK__GFX_SQC_INDEX_END = TA_RAS_BLOCK__GFX_SQC_INDEX2_END, 220 /* TA*/ 221 TA_RAS_BLOCK__GFX_TA_INDEX_START, 222 TA_RAS_BLOCK__GFX_TA_FS_DFIFO = TA_RAS_BLOCK__GFX_TA_INDEX_START, 223 TA_RAS_BLOCK__GFX_TA_FS_AFIFO, 224 TA_RAS_BLOCK__GFX_TA_FL_LFIFO, 225 TA_RAS_BLOCK__GFX_TA_FX_LFIFO, 226 TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 227 TA_RAS_BLOCK__GFX_TA_INDEX_END = TA_RAS_BLOCK__GFX_TA_FS_CFIFO, 228 /* TCA*/ 229 TA_RAS_BLOCK__GFX_TCA_INDEX_START, 230 TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO = TA_RAS_BLOCK__GFX_TCA_INDEX_START, 231 TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 232 TA_RAS_BLOCK__GFX_TCA_INDEX_END = TA_RAS_BLOCK__GFX_TCA_REQ_FIFO, 233 /* TCC (5 sub-ranges)*/ 234 TA_RAS_BLOCK__GFX_TCC_INDEX_START, 235 /* TCC range 0*/ 236 TA_RAS_BLOCK__GFX_TCC_INDEX0_START = TA_RAS_BLOCK__GFX_TCC_INDEX_START, 237 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX0_START, 238 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, 239 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, 240 TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, 241 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, 242 TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, 243 TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, 244 TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 245 TA_RAS_BLOCK__GFX_TCC_INDEX0_END = TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, 246 /* TCC range 1*/ 247 TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 248 TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC = TA_RAS_BLOCK__GFX_TCC_INDEX1_START, 249 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 250 TA_RAS_BLOCK__GFX_TCC_INDEX1_END = 251 TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, 252 /* TCC range 2*/ 253 TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 254 TA_RAS_BLOCK__GFX_TCC_RETURN_DATA = TA_RAS_BLOCK__GFX_TCC_INDEX2_START, 255 TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, 256 TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, 257 TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN, 258 TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, 259 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO, 260 TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, 261 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 262 TA_RAS_BLOCK__GFX_TCC_INDEX2_END = 263 TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, 264 /* TCC range 3*/ 265 TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 266 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = TA_RAS_BLOCK__GFX_TCC_INDEX3_START, 267 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 268 TA_RAS_BLOCK__GFX_TCC_INDEX3_END = 269 TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, 270 /* TCC range 4*/ 271 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 272 TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = 273 TA_RAS_BLOCK__GFX_TCC_INDEX4_START, 274 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 275 TA_RAS_BLOCK__GFX_TCC_INDEX4_END = 276 TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, 277 TA_RAS_BLOCK__GFX_TCC_INDEX_END = TA_RAS_BLOCK__GFX_TCC_INDEX4_END, 278 /* TCI*/ 279 TA_RAS_BLOCK__GFX_TCI_WRITE_RAM, 280 /* TCP*/ 281 TA_RAS_BLOCK__GFX_TCP_INDEX_START, 282 TA_RAS_BLOCK__GFX_TCP_CACHE_RAM = TA_RAS_BLOCK__GFX_TCP_INDEX_START, 283 TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM, 284 TA_RAS_BLOCK__GFX_TCP_CMD_FIFO, 285 TA_RAS_BLOCK__GFX_TCP_VM_FIFO, 286 TA_RAS_BLOCK__GFX_TCP_DB_RAM, 287 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, 288 TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 289 TA_RAS_BLOCK__GFX_TCP_INDEX_END = TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, 290 /* TD*/ 291 TA_RAS_BLOCK__GFX_TD_INDEX_START, 292 TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO = TA_RAS_BLOCK__GFX_TD_INDEX_START, 293 TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI, 294 TA_RAS_BLOCK__GFX_TD_CS_FIFO, 295 TA_RAS_BLOCK__GFX_TD_INDEX_END = TA_RAS_BLOCK__GFX_TD_CS_FIFO, 296 /* EA (3 sub-ranges)*/ 297 TA_RAS_BLOCK__GFX_EA_INDEX_START, 298 /* EA range 0*/ 299 TA_RAS_BLOCK__GFX_EA_INDEX0_START = TA_RAS_BLOCK__GFX_EA_INDEX_START, 300 TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = TA_RAS_BLOCK__GFX_EA_INDEX0_START, 301 TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, 302 TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, 303 TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM, 304 TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM, 305 TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, 306 TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, 307 TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 308 TA_RAS_BLOCK__GFX_EA_INDEX0_END = TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, 309 /* EA range 1*/ 310 TA_RAS_BLOCK__GFX_EA_INDEX1_START, 311 TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = TA_RAS_BLOCK__GFX_EA_INDEX1_START, 312 TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, 313 TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM, 314 TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, 315 TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, 316 TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, 317 TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 318 TA_RAS_BLOCK__GFX_EA_INDEX1_END = TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, 319 /* EA range 2*/ 320 TA_RAS_BLOCK__GFX_EA_INDEX2_START, 321 TA_RAS_BLOCK__GFX_EA_MAM_D0MEM = TA_RAS_BLOCK__GFX_EA_INDEX2_START, 322 TA_RAS_BLOCK__GFX_EA_MAM_D1MEM, 323 TA_RAS_BLOCK__GFX_EA_MAM_D2MEM, 324 TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 325 TA_RAS_BLOCK__GFX_EA_INDEX2_END = TA_RAS_BLOCK__GFX_EA_MAM_D3MEM, 326 TA_RAS_BLOCK__GFX_EA_INDEX_END = TA_RAS_BLOCK__GFX_EA_INDEX2_END, 327 /* UTC VM L2 bank*/ 328 TA_RAS_BLOCK__UTC_VML2_BANK_CACHE, 329 /* UTC VM walker*/ 330 TA_RAS_BLOCK__UTC_VML2_WALKER, 331 /* UTC ATC L2 2MB cache*/ 332 TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, 333 /* UTC ATC L2 4KB cache*/ 334 TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, 335 TA_RAS_BLOCK__GFX_MAX 336 }; 337 338 struct ras_gfx_subblock { 339 unsigned char *name; 340 int ta_subblock; 341 int hw_supported_error_type; 342 int sw_supported_error_type; 343 }; 344 345 #define AMDGPU_RAS_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \ 346 [AMDGPU_RAS_BLOCK__##subblock] = { \ 347 #subblock, \ 348 TA_RAS_BLOCK__##subblock, \ 349 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \ 350 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \ 351 } 352 353 static const struct ras_gfx_subblock ras_gfx_subblocks[] = { 354 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1), 355 AMDGPU_RAS_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1), 356 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 357 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 358 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0), 359 AMDGPU_RAS_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 360 AMDGPU_RAS_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 361 AMDGPU_RAS_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 362 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0), 363 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0), 364 AMDGPU_RAS_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1), 365 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0), 366 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1), 367 AMDGPU_RAS_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1), 368 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 369 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0), 370 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0, 371 0), 372 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0, 373 0), 374 AMDGPU_RAS_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0), 375 AMDGPU_RAS_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0), 376 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0), 377 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1), 378 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0), 379 AMDGPU_RAS_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0), 380 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1), 381 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 382 0, 0), 383 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 384 0), 385 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 386 0, 0), 387 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0, 388 0), 389 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0, 390 0, 0), 391 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 392 0), 393 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 394 1), 395 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 396 0, 0, 0), 397 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 398 0), 399 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 400 0), 401 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 402 0), 403 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 404 0), 405 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 406 0), 407 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 408 0, 0), 409 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 410 0), 411 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0, 412 0), 413 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0, 414 0, 0, 0), 415 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 416 0), 417 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 418 0), 419 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0, 420 0), 421 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0, 422 0), 423 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0, 424 0), 425 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0, 426 0, 0), 427 AMDGPU_RAS_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0, 428 0), 429 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1), 430 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 431 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 432 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 433 AMDGPU_RAS_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0), 434 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0), 435 AMDGPU_RAS_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 436 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1), 437 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0, 438 1), 439 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0, 440 1), 441 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0, 442 1), 443 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0, 444 0), 445 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0, 446 0), 447 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 448 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0), 449 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0), 450 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0), 451 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0), 452 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0), 453 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 454 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0), 455 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0), 456 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 457 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0), 458 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0, 459 0), 460 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 461 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0, 462 0), 463 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0, 464 0, 0), 465 AMDGPU_RAS_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0, 466 0), 467 AMDGPU_RAS_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 468 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1), 469 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0), 470 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 471 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0), 472 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0), 473 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0), 474 AMDGPU_RAS_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0), 475 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1), 476 AMDGPU_RAS_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0), 477 AMDGPU_RAS_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0), 478 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1), 479 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 480 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 481 AMDGPU_RAS_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 482 AMDGPU_RAS_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0), 483 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 484 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0), 485 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0), 486 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 487 AMDGPU_RAS_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 488 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 489 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0), 490 AMDGPU_RAS_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0), 491 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 492 AMDGPU_RAS_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0), 493 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0), 494 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0), 495 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0), 496 AMDGPU_RAS_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0), 497 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0), 498 AMDGPU_RAS_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0), 499 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0), 500 AMDGPU_RAS_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0), 501 }; 502 503 static const struct soc15_reg_golden golden_settings_gc_9_0[] = 504 { 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x80000000, 0x80000000), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 525 }; 526 527 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = 528 { 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) 547 }; 548 549 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = 550 { 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) 562 }; 563 564 static const struct soc15_reg_golden golden_settings_gc_9_1[] = 565 { 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 590 }; 591 592 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] = 593 { 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800) 601 }; 602 603 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] = 604 { 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080), 624 }; 625 626 static const struct soc15_reg_golden golden_settings_gc_9_1_rn[] = 627 { 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x24000042), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x24000042), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_PROBE_MAP, 0xffffffff, 0x0000cccc), 640 }; 641 642 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] = 643 { 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0xffffffff, 0x000001ff), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382) 647 }; 648 649 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] = 650 { 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff) 667 }; 668 669 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] = 670 { 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC1_F32_INT_DIS, 0x00000800, 0x00000800), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_MEC2_F32_INT_DIS, 0x00000800, 0x00000800), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_DEBUG, 0x00008000, 0x00008000) 684 }; 685 686 static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] = 687 { 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x10b0000), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_0_ARCT, 0x3fffffff, 0x346f0a4e), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_1_ARCT, 0x3fffffff, 0x1c642ca), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_2_ARCT, 0x3fffffff, 0x26f45098), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_3_ARCT, 0x3fffffff, 0x2ebd9fe3), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_4_ARCT, 0x3fffffff, 0xb90f5b1), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00), 698 }; 699 700 static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = { 701 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)}, 702 {SOC15_REG_ENTRY(GC, 0, mmSQ_IND_INDEX)}, 703 }; 704 705 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] = 706 { 707 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 708 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 709 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 710 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 711 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 712 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 713 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 714 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0, 715 }; 716 717 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = 718 { 719 mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0, 720 mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0, 721 mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0, 722 mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0, 723 mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0, 724 mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0, 725 mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0, 726 mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0, 727 }; 728 729 void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) 730 { 731 #ifdef __linux__ 732 static void *scratch_reg0; 733 static void *scratch_reg1; 734 static void *scratch_reg2; 735 static void *scratch_reg3; 736 static void *spare_int; 737 #endif 738 static uint32_t grbm_cntl; 739 static uint32_t grbm_idx; 740 741 #ifdef __linux__ 742 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4; 743 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; 744 scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4; 745 scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4; 746 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4; 747 #endif 748 749 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; 750 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; 751 752 if (amdgpu_sriov_runtime(adev)) { 753 pr_err("shouldn't call rlcg write register during runtime\n"); 754 return; 755 } 756 757 if (offset == grbm_cntl || offset == grbm_idx) { 758 if (offset == grbm_cntl) 759 bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh, 760 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4, v); 761 else if (offset == grbm_idx) 762 bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh, 763 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4, v); 764 765 bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh, 766 offset * 4, v); 767 768 } else { 769 uint32_t i = 0; 770 uint32_t retries = 50000; 771 772 bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh, 773 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4, v); 774 bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh, 775 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4, 776 offset | 0x80000000); 777 bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh, 778 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4, 779 1); 780 for (i = 0; i < retries; i++) { 781 u32 tmp; 782 783 tmp = bus_space_read_4(adev->rmmio_bst, adev->rmmio_bsh, 784 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4); 785 if (!(tmp & 0x80000000)) 786 break; 787 788 udelay(10); 789 } 790 if (i >= retries) 791 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 792 } 793 794 } 795 796 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 797 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 798 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 799 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 800 801 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); 802 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev); 803 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev); 804 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev); 805 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 806 struct amdgpu_cu_info *cu_info); 807 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev); 808 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 809 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring); 810 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring); 811 static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 812 void *ras_error_status); 813 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 814 void *inject_if); 815 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev); 816 817 static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, 818 uint64_t queue_mask) 819 { 820 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 821 amdgpu_ring_write(kiq_ring, 822 PACKET3_SET_RESOURCES_VMID_MASK(0) | 823 /* vmid_mask:0* queue_type:0 (KIQ) */ 824 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); 825 amdgpu_ring_write(kiq_ring, 826 lower_32_bits(queue_mask)); /* queue mask lo */ 827 amdgpu_ring_write(kiq_ring, 828 upper_32_bits(queue_mask)); /* queue mask hi */ 829 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 830 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 831 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 832 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 833 } 834 835 static void gfx_v9_0_kiq_map_queues(struct amdgpu_ring *kiq_ring, 836 struct amdgpu_ring *ring) 837 { 838 struct amdgpu_device *adev = kiq_ring->adev; 839 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 840 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 841 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 842 843 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 844 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 845 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 846 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 847 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 848 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 849 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 850 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 851 /*queue_type: normal compute queue */ 852 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | 853 /* alloc format: all_on_one_pipe */ 854 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | 855 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 856 /* num_queues: must be 1 */ 857 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); 858 amdgpu_ring_write(kiq_ring, 859 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 860 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 861 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 862 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 863 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 864 } 865 866 static void gfx_v9_0_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 867 struct amdgpu_ring *ring, 868 enum amdgpu_unmap_queues_action action, 869 u64 gpu_addr, u64 seq) 870 { 871 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 872 873 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 874 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 875 PACKET3_UNMAP_QUEUES_ACTION(action) | 876 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 877 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 878 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 879 amdgpu_ring_write(kiq_ring, 880 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 881 882 if (action == PREEMPT_QUEUES_NO_UNMAP) { 883 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 884 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 885 amdgpu_ring_write(kiq_ring, seq); 886 } else { 887 amdgpu_ring_write(kiq_ring, 0); 888 amdgpu_ring_write(kiq_ring, 0); 889 amdgpu_ring_write(kiq_ring, 0); 890 } 891 } 892 893 static void gfx_v9_0_kiq_query_status(struct amdgpu_ring *kiq_ring, 894 struct amdgpu_ring *ring, 895 u64 addr, 896 u64 seq) 897 { 898 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 899 900 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 901 amdgpu_ring_write(kiq_ring, 902 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 903 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 904 PACKET3_QUERY_STATUS_COMMAND(2)); 905 /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 906 amdgpu_ring_write(kiq_ring, 907 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 908 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 909 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 910 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 911 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 912 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 913 } 914 915 static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 916 uint16_t pasid, uint32_t flush_type, 917 bool all_hub) 918 { 919 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 920 amdgpu_ring_write(kiq_ring, 921 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 922 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 923 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 924 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 925 } 926 927 static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { 928 .kiq_set_resources = gfx_v9_0_kiq_set_resources, 929 .kiq_map_queues = gfx_v9_0_kiq_map_queues, 930 .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues, 931 .kiq_query_status = gfx_v9_0_kiq_query_status, 932 .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs, 933 .set_resources_size = 8, 934 .map_queues_size = 7, 935 .unmap_queues_size = 6, 936 .query_status_size = 7, 937 .invalidate_tlbs_size = 2, 938 }; 939 940 static void gfx_v9_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 941 { 942 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; 943 } 944 945 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) 946 { 947 switch (adev->asic_type) { 948 case CHIP_VEGA10: 949 soc15_program_register_sequence(adev, 950 golden_settings_gc_9_0, 951 ARRAY_SIZE(golden_settings_gc_9_0)); 952 soc15_program_register_sequence(adev, 953 golden_settings_gc_9_0_vg10, 954 ARRAY_SIZE(golden_settings_gc_9_0_vg10)); 955 break; 956 case CHIP_VEGA12: 957 soc15_program_register_sequence(adev, 958 golden_settings_gc_9_2_1, 959 ARRAY_SIZE(golden_settings_gc_9_2_1)); 960 soc15_program_register_sequence(adev, 961 golden_settings_gc_9_2_1_vg12, 962 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); 963 break; 964 case CHIP_VEGA20: 965 soc15_program_register_sequence(adev, 966 golden_settings_gc_9_0, 967 ARRAY_SIZE(golden_settings_gc_9_0)); 968 soc15_program_register_sequence(adev, 969 golden_settings_gc_9_0_vg20, 970 ARRAY_SIZE(golden_settings_gc_9_0_vg20)); 971 break; 972 case CHIP_ARCTURUS: 973 soc15_program_register_sequence(adev, 974 golden_settings_gc_9_4_1_arct, 975 ARRAY_SIZE(golden_settings_gc_9_4_1_arct)); 976 break; 977 case CHIP_RAVEN: 978 soc15_program_register_sequence(adev, golden_settings_gc_9_1, 979 ARRAY_SIZE(golden_settings_gc_9_1)); 980 if (adev->rev_id >= 8) 981 soc15_program_register_sequence(adev, 982 golden_settings_gc_9_1_rv2, 983 ARRAY_SIZE(golden_settings_gc_9_1_rv2)); 984 else 985 soc15_program_register_sequence(adev, 986 golden_settings_gc_9_1_rv1, 987 ARRAY_SIZE(golden_settings_gc_9_1_rv1)); 988 break; 989 case CHIP_RENOIR: 990 soc15_program_register_sequence(adev, 991 golden_settings_gc_9_1_rn, 992 ARRAY_SIZE(golden_settings_gc_9_1_rn)); 993 return; /* for renoir, don't need common goldensetting */ 994 default: 995 break; 996 } 997 998 if (adev->asic_type != CHIP_ARCTURUS) 999 soc15_program_register_sequence(adev, golden_settings_gc_9_x_common, 1000 (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); 1001 } 1002 1003 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) 1004 { 1005 adev->gfx.scratch.num_reg = 8; 1006 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 1007 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 1008 } 1009 1010 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 1011 bool wc, uint32_t reg, uint32_t val) 1012 { 1013 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1014 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 1015 WRITE_DATA_DST_SEL(0) | 1016 (wc ? WR_CONFIRM : 0)); 1017 amdgpu_ring_write(ring, reg); 1018 amdgpu_ring_write(ring, 0); 1019 amdgpu_ring_write(ring, val); 1020 } 1021 1022 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 1023 int mem_space, int opt, uint32_t addr0, 1024 uint32_t addr1, uint32_t ref, uint32_t mask, 1025 uint32_t inv) 1026 { 1027 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 1028 amdgpu_ring_write(ring, 1029 /* memory (1) or register (0) */ 1030 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 1031 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 1032 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 1033 WAIT_REG_MEM_ENGINE(eng_sel))); 1034 1035 if (mem_space) 1036 BUG_ON(addr0 & 0x3); /* Dword align */ 1037 amdgpu_ring_write(ring, addr0); 1038 amdgpu_ring_write(ring, addr1); 1039 amdgpu_ring_write(ring, ref); 1040 amdgpu_ring_write(ring, mask); 1041 amdgpu_ring_write(ring, inv); /* poll interval */ 1042 } 1043 1044 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring) 1045 { 1046 struct amdgpu_device *adev = ring->adev; 1047 uint32_t scratch; 1048 uint32_t tmp = 0; 1049 unsigned i; 1050 int r; 1051 1052 r = amdgpu_gfx_scratch_get(adev, &scratch); 1053 if (r) 1054 return r; 1055 1056 WREG32(scratch, 0xCAFEDEAD); 1057 r = amdgpu_ring_alloc(ring, 3); 1058 if (r) 1059 goto error_free_scratch; 1060 1061 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 1062 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 1063 amdgpu_ring_write(ring, 0xDEADBEEF); 1064 amdgpu_ring_commit(ring); 1065 1066 for (i = 0; i < adev->usec_timeout; i++) { 1067 tmp = RREG32(scratch); 1068 if (tmp == 0xDEADBEEF) 1069 break; 1070 udelay(1); 1071 } 1072 1073 if (i >= adev->usec_timeout) 1074 r = -ETIMEDOUT; 1075 1076 error_free_scratch: 1077 amdgpu_gfx_scratch_free(adev, scratch); 1078 return r; 1079 } 1080 1081 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1082 { 1083 struct amdgpu_device *adev = ring->adev; 1084 struct amdgpu_ib ib; 1085 struct dma_fence *f = NULL; 1086 1087 unsigned index; 1088 uint64_t gpu_addr; 1089 uint32_t tmp; 1090 long r; 1091 1092 r = amdgpu_device_wb_get(adev, &index); 1093 if (r) 1094 return r; 1095 1096 gpu_addr = adev->wb.gpu_addr + (index * 4); 1097 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 1098 memset(&ib, 0, sizeof(ib)); 1099 r = amdgpu_ib_get(adev, NULL, 16, &ib); 1100 if (r) 1101 goto err1; 1102 1103 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 1104 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 1105 ib.ptr[2] = lower_32_bits(gpu_addr); 1106 ib.ptr[3] = upper_32_bits(gpu_addr); 1107 ib.ptr[4] = 0xDEADBEEF; 1108 ib.length_dw = 5; 1109 1110 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 1111 if (r) 1112 goto err2; 1113 1114 r = dma_fence_wait_timeout(f, false, timeout); 1115 if (r == 0) { 1116 r = -ETIMEDOUT; 1117 goto err2; 1118 } else if (r < 0) { 1119 goto err2; 1120 } 1121 1122 tmp = adev->wb.wb[index]; 1123 if (tmp == 0xDEADBEEF) 1124 r = 0; 1125 else 1126 r = -EINVAL; 1127 1128 err2: 1129 amdgpu_ib_free(adev, &ib, NULL); 1130 dma_fence_put(f); 1131 err1: 1132 amdgpu_device_wb_free(adev, index); 1133 return r; 1134 } 1135 1136 1137 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev) 1138 { 1139 release_firmware(adev->gfx.pfp_fw); 1140 adev->gfx.pfp_fw = NULL; 1141 release_firmware(adev->gfx.me_fw); 1142 adev->gfx.me_fw = NULL; 1143 release_firmware(adev->gfx.ce_fw); 1144 adev->gfx.ce_fw = NULL; 1145 release_firmware(adev->gfx.rlc_fw); 1146 adev->gfx.rlc_fw = NULL; 1147 release_firmware(adev->gfx.mec_fw); 1148 adev->gfx.mec_fw = NULL; 1149 release_firmware(adev->gfx.mec2_fw); 1150 adev->gfx.mec2_fw = NULL; 1151 1152 kfree(adev->gfx.rlc.register_list_format); 1153 } 1154 1155 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 1156 { 1157 const struct rlc_firmware_header_v2_1 *rlc_hdr; 1158 1159 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1160 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 1161 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 1162 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 1163 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 1164 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 1165 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 1166 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 1167 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 1168 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 1169 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 1170 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 1171 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 1172 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 1173 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 1174 } 1175 1176 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev) 1177 { 1178 adev->gfx.me_fw_write_wait = false; 1179 adev->gfx.mec_fw_write_wait = false; 1180 1181 if ((adev->asic_type != CHIP_ARCTURUS) && 1182 ((adev->gfx.mec_fw_version < 0x000001a5) || 1183 (adev->gfx.mec_feature_version < 46) || 1184 (adev->gfx.pfp_fw_version < 0x000000b7) || 1185 (adev->gfx.pfp_feature_version < 46))) 1186 DRM_WARN_ONCE("CP firmware version too old, please update!"); 1187 1188 switch (adev->asic_type) { 1189 case CHIP_VEGA10: 1190 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1191 (adev->gfx.me_feature_version >= 42) && 1192 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1193 (adev->gfx.pfp_feature_version >= 42)) 1194 adev->gfx.me_fw_write_wait = true; 1195 1196 if ((adev->gfx.mec_fw_version >= 0x00000193) && 1197 (adev->gfx.mec_feature_version >= 42)) 1198 adev->gfx.mec_fw_write_wait = true; 1199 break; 1200 case CHIP_VEGA12: 1201 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1202 (adev->gfx.me_feature_version >= 44) && 1203 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1204 (adev->gfx.pfp_feature_version >= 44)) 1205 adev->gfx.me_fw_write_wait = true; 1206 1207 if ((adev->gfx.mec_fw_version >= 0x00000196) && 1208 (adev->gfx.mec_feature_version >= 44)) 1209 adev->gfx.mec_fw_write_wait = true; 1210 break; 1211 case CHIP_VEGA20: 1212 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1213 (adev->gfx.me_feature_version >= 44) && 1214 (adev->gfx.pfp_fw_version >= 0x000000b2) && 1215 (adev->gfx.pfp_feature_version >= 44)) 1216 adev->gfx.me_fw_write_wait = true; 1217 1218 if ((adev->gfx.mec_fw_version >= 0x00000197) && 1219 (adev->gfx.mec_feature_version >= 44)) 1220 adev->gfx.mec_fw_write_wait = true; 1221 break; 1222 case CHIP_RAVEN: 1223 if ((adev->gfx.me_fw_version >= 0x0000009c) && 1224 (adev->gfx.me_feature_version >= 42) && 1225 (adev->gfx.pfp_fw_version >= 0x000000b1) && 1226 (adev->gfx.pfp_feature_version >= 42)) 1227 adev->gfx.me_fw_write_wait = true; 1228 1229 if ((adev->gfx.mec_fw_version >= 0x00000192) && 1230 (adev->gfx.mec_feature_version >= 42)) 1231 adev->gfx.mec_fw_write_wait = true; 1232 break; 1233 default: 1234 adev->gfx.me_fw_write_wait = true; 1235 adev->gfx.mec_fw_write_wait = true; 1236 break; 1237 } 1238 } 1239 1240 struct amdgpu_gfxoff_quirk { 1241 u16 chip_vendor; 1242 u16 chip_device; 1243 u16 subsys_vendor; 1244 u16 subsys_device; 1245 u8 revision; 1246 }; 1247 1248 static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { 1249 /* https://bugzilla.kernel.org/show_bug.cgi?id=204689 */ 1250 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 }, 1251 /* https://bugzilla.kernel.org/show_bug.cgi?id=207171 */ 1252 { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, 1253 /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ 1254 { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, 1255 { 0, 0, 0, 0, 0 }, 1256 }; 1257 1258 static bool gfx_v9_0_should_disable_gfxoff(struct pci_dev *pdev) 1259 { 1260 const struct amdgpu_gfxoff_quirk *p = amdgpu_gfxoff_quirk_list; 1261 1262 while (p && p->chip_device != 0) { 1263 if (pdev->vendor == p->chip_vendor && 1264 pdev->device == p->chip_device && 1265 pdev->subsystem_vendor == p->subsys_vendor && 1266 pdev->subsystem_device == p->subsys_device && 1267 pdev->revision == p->revision) { 1268 return true; 1269 } 1270 ++p; 1271 } 1272 return false; 1273 } 1274 1275 static bool is_raven_kicker(struct amdgpu_device *adev) 1276 { 1277 if (adev->pm.fw_version >= 0x41e2b) 1278 return true; 1279 else 1280 return false; 1281 } 1282 1283 static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev) 1284 { 1285 if (gfx_v9_0_should_disable_gfxoff(adev->pdev)) 1286 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1287 1288 switch (adev->asic_type) { 1289 case CHIP_VEGA10: 1290 case CHIP_VEGA12: 1291 case CHIP_VEGA20: 1292 break; 1293 case CHIP_RAVEN: 1294 if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) && 1295 ((!is_raven_kicker(adev) && 1296 adev->gfx.rlc_fw_version < 531) || 1297 (adev->gfx.rlc_feature_version < 1) || 1298 !adev->gfx.rlc.is_rlc_v2_1)) 1299 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 1300 1301 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1302 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1303 AMD_PG_SUPPORT_CP | 1304 AMD_PG_SUPPORT_RLC_SMU_HS; 1305 break; 1306 case CHIP_RENOIR: 1307 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 1308 adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | 1309 AMD_PG_SUPPORT_CP | 1310 AMD_PG_SUPPORT_RLC_SMU_HS; 1311 break; 1312 default: 1313 break; 1314 } 1315 } 1316 1317 static int gfx_v9_0_init_cp_gfx_microcode(struct amdgpu_device *adev, 1318 const char *chip_name) 1319 { 1320 char fw_name[30]; 1321 int err; 1322 struct amdgpu_firmware_info *info = NULL; 1323 const struct common_firmware_header *header = NULL; 1324 const struct gfx_firmware_header_v1_0 *cp_hdr; 1325 1326 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 1327 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 1328 if (err) 1329 goto out; 1330 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 1331 if (err) 1332 goto out; 1333 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 1334 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1335 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1336 1337 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 1338 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 1339 if (err) 1340 goto out; 1341 err = amdgpu_ucode_validate(adev->gfx.me_fw); 1342 if (err) 1343 goto out; 1344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 1345 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1346 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1347 1348 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 1349 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 1350 if (err) 1351 goto out; 1352 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 1353 if (err) 1354 goto out; 1355 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 1356 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1357 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1358 1359 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1360 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 1361 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 1362 info->fw = adev->gfx.pfp_fw; 1363 header = (const struct common_firmware_header *)info->fw->data; 1364 adev->firmware.fw_size += 1365 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1366 1367 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 1368 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 1369 info->fw = adev->gfx.me_fw; 1370 header = (const struct common_firmware_header *)info->fw->data; 1371 adev->firmware.fw_size += 1372 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1373 1374 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 1375 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 1376 info->fw = adev->gfx.ce_fw; 1377 header = (const struct common_firmware_header *)info->fw->data; 1378 adev->firmware.fw_size += 1379 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1380 } 1381 1382 out: 1383 if (err) { 1384 dev_err(adev->dev, 1385 "gfx9: Failed to load firmware \"%s\"\n", 1386 fw_name); 1387 release_firmware(adev->gfx.pfp_fw); 1388 adev->gfx.pfp_fw = NULL; 1389 release_firmware(adev->gfx.me_fw); 1390 adev->gfx.me_fw = NULL; 1391 release_firmware(adev->gfx.ce_fw); 1392 adev->gfx.ce_fw = NULL; 1393 } 1394 return err; 1395 } 1396 1397 static int gfx_v9_0_init_rlc_microcode(struct amdgpu_device *adev, 1398 const char *chip_name) 1399 { 1400 char fw_name[30]; 1401 int err; 1402 struct amdgpu_firmware_info *info = NULL; 1403 const struct common_firmware_header *header = NULL; 1404 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1405 unsigned int *tmp = NULL; 1406 unsigned int i = 0; 1407 uint16_t version_major; 1408 uint16_t version_minor; 1409 uint32_t smu_version; 1410 1411 /* 1412 * For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin 1413 * instead of picasso_rlc.bin. 1414 * Judgment method: 1415 * PCO AM4: revision >= 0xC8 && revision <= 0xCF 1416 * or revision >= 0xD8 && revision <= 0xDF 1417 * otherwise is PCO FP5 1418 */ 1419 if (!strcmp(chip_name, "picasso") && 1420 (((adev->pdev->revision >= 0xC8) && (adev->pdev->revision <= 0xCF)) || 1421 ((adev->pdev->revision >= 0xD8) && (adev->pdev->revision <= 0xDF)))) 1422 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc_am4.bin", chip_name); 1423 else if (!strcmp(chip_name, "raven") && (amdgpu_pm_load_smu_firmware(adev, &smu_version) == 0) && 1424 (smu_version >= 0x41e2b)) 1425 /** 1426 *SMC is loaded by SBIOS on APU and it's able to get the SMU version directly. 1427 */ 1428 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_kicker_rlc.bin", chip_name); 1429 else 1430 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 1431 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 1432 if (err) 1433 goto out; 1434 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 1435 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1436 1437 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1438 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1439 if (version_major == 2 && version_minor == 1) 1440 adev->gfx.rlc.is_rlc_v2_1 = true; 1441 1442 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 1443 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 1444 adev->gfx.rlc.save_and_restore_offset = 1445 le32_to_cpu(rlc_hdr->save_and_restore_offset); 1446 adev->gfx.rlc.clear_state_descriptor_offset = 1447 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 1448 adev->gfx.rlc.avail_scratch_ram_locations = 1449 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 1450 adev->gfx.rlc.reg_restore_list_size = 1451 le32_to_cpu(rlc_hdr->reg_restore_list_size); 1452 adev->gfx.rlc.reg_list_format_start = 1453 le32_to_cpu(rlc_hdr->reg_list_format_start); 1454 adev->gfx.rlc.reg_list_format_separate_start = 1455 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 1456 adev->gfx.rlc.starting_offsets_start = 1457 le32_to_cpu(rlc_hdr->starting_offsets_start); 1458 adev->gfx.rlc.reg_list_format_size_bytes = 1459 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 1460 adev->gfx.rlc.reg_list_size_bytes = 1461 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 1462 adev->gfx.rlc.register_list_format = 1463 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 1464 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 1465 if (!adev->gfx.rlc.register_list_format) { 1466 err = -ENOMEM; 1467 goto out; 1468 } 1469 1470 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 1471 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 1472 for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) 1473 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 1474 1475 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 1476 1477 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 1478 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 1479 for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) 1480 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 1481 1482 if (adev->gfx.rlc.is_rlc_v2_1) 1483 gfx_v9_0_init_rlc_ext_microcode(adev); 1484 1485 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1486 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 1487 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 1488 info->fw = adev->gfx.rlc_fw; 1489 header = (const struct common_firmware_header *)info->fw->data; 1490 adev->firmware.fw_size += 1491 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 1492 1493 if (adev->gfx.rlc.is_rlc_v2_1 && 1494 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 1495 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 1496 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 1497 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 1498 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 1499 info->fw = adev->gfx.rlc_fw; 1500 adev->firmware.fw_size += 1501 roundup2(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 1502 1503 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 1504 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 1505 info->fw = adev->gfx.rlc_fw; 1506 adev->firmware.fw_size += 1507 roundup2(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 1508 1509 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 1510 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 1511 info->fw = adev->gfx.rlc_fw; 1512 adev->firmware.fw_size += 1513 roundup2(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 1514 } 1515 } 1516 1517 out: 1518 if (err) { 1519 dev_err(adev->dev, 1520 "gfx9: Failed to load firmware \"%s\"\n", 1521 fw_name); 1522 release_firmware(adev->gfx.rlc_fw); 1523 adev->gfx.rlc_fw = NULL; 1524 } 1525 return err; 1526 } 1527 1528 static int gfx_v9_0_init_cp_compute_microcode(struct amdgpu_device *adev, 1529 const char *chip_name) 1530 { 1531 char fw_name[30]; 1532 int err; 1533 struct amdgpu_firmware_info *info = NULL; 1534 const struct common_firmware_header *header = NULL; 1535 const struct gfx_firmware_header_v1_0 *cp_hdr; 1536 1537 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 1538 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 1539 if (err) 1540 goto out; 1541 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 1542 if (err) 1543 goto out; 1544 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1545 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 1546 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 1547 1548 1549 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 1550 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 1551 if (!err) { 1552 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 1553 if (err) 1554 goto out; 1555 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1556 adev->gfx.mec2_fw->data; 1557 adev->gfx.mec2_fw_version = 1558 le32_to_cpu(cp_hdr->header.ucode_version); 1559 adev->gfx.mec2_feature_version = 1560 le32_to_cpu(cp_hdr->ucode_feature_version); 1561 } else { 1562 err = 0; 1563 adev->gfx.mec2_fw = NULL; 1564 } 1565 1566 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1567 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 1568 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 1569 info->fw = adev->gfx.mec_fw; 1570 header = (const struct common_firmware_header *)info->fw->data; 1571 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 1572 adev->firmware.fw_size += 1573 roundup2(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 1574 1575 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 1576 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 1577 info->fw = adev->gfx.mec_fw; 1578 adev->firmware.fw_size += 1579 roundup2(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 1580 1581 if (adev->gfx.mec2_fw) { 1582 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 1583 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 1584 info->fw = adev->gfx.mec2_fw; 1585 header = (const struct common_firmware_header *)info->fw->data; 1586 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 1587 adev->firmware.fw_size += 1588 roundup2(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 1589 1590 /* TODO: Determine if MEC2 JT FW loading can be removed 1591 for all GFX V9 asic and above */ 1592 if (adev->asic_type != CHIP_ARCTURUS && 1593 adev->asic_type != CHIP_RENOIR) { 1594 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 1595 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 1596 info->fw = adev->gfx.mec2_fw; 1597 adev->firmware.fw_size += 1598 roundup2(le32_to_cpu(cp_hdr->jt_size) * 4, 1599 PAGE_SIZE); 1600 } 1601 } 1602 } 1603 1604 out: 1605 gfx_v9_0_check_if_need_gfxoff(adev); 1606 gfx_v9_0_check_fw_write_wait(adev); 1607 if (err) { 1608 dev_err(adev->dev, 1609 "gfx9: Failed to load firmware \"%s\"\n", 1610 fw_name); 1611 release_firmware(adev->gfx.mec_fw); 1612 adev->gfx.mec_fw = NULL; 1613 release_firmware(adev->gfx.mec2_fw); 1614 adev->gfx.mec2_fw = NULL; 1615 } 1616 return err; 1617 } 1618 1619 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) 1620 { 1621 const char *chip_name; 1622 int r; 1623 1624 DRM_DEBUG("\n"); 1625 1626 switch (adev->asic_type) { 1627 case CHIP_VEGA10: 1628 chip_name = "vega10"; 1629 break; 1630 case CHIP_VEGA12: 1631 chip_name = "vega12"; 1632 break; 1633 case CHIP_VEGA20: 1634 chip_name = "vega20"; 1635 break; 1636 case CHIP_RAVEN: 1637 if (adev->rev_id >= 8) 1638 chip_name = "raven2"; 1639 else if (adev->pdev->device == 0x15d8) 1640 chip_name = "picasso"; 1641 else 1642 chip_name = "raven"; 1643 break; 1644 case CHIP_ARCTURUS: 1645 chip_name = "arcturus"; 1646 break; 1647 case CHIP_RENOIR: 1648 chip_name = "renoir"; 1649 break; 1650 default: 1651 BUG(); 1652 } 1653 1654 /* No CPG in Arcturus */ 1655 if (adev->asic_type != CHIP_ARCTURUS) { 1656 r = gfx_v9_0_init_cp_gfx_microcode(adev, chip_name); 1657 if (r) 1658 return r; 1659 } 1660 1661 r = gfx_v9_0_init_rlc_microcode(adev, chip_name); 1662 if (r) 1663 return r; 1664 1665 r = gfx_v9_0_init_cp_compute_microcode(adev, chip_name); 1666 if (r) 1667 return r; 1668 1669 return r; 1670 } 1671 1672 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev) 1673 { 1674 u32 count = 0; 1675 const struct cs_section_def *sect = NULL; 1676 const struct cs_extent_def *ext = NULL; 1677 1678 /* begin clear state */ 1679 count += 2; 1680 /* context control state */ 1681 count += 3; 1682 1683 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 1684 for (ext = sect->section; ext->extent != NULL; ++ext) { 1685 if (sect->id == SECT_CONTEXT) 1686 count += 2 + ext->reg_count; 1687 else 1688 return 0; 1689 } 1690 } 1691 1692 /* end clear state */ 1693 count += 2; 1694 /* clear state */ 1695 count += 2; 1696 1697 return count; 1698 } 1699 1700 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev, 1701 volatile u32 *buffer) 1702 { 1703 u32 count = 0, i; 1704 const struct cs_section_def *sect = NULL; 1705 const struct cs_extent_def *ext = NULL; 1706 1707 if (adev->gfx.rlc.cs_data == NULL) 1708 return; 1709 if (buffer == NULL) 1710 return; 1711 1712 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1713 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1714 1715 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1716 buffer[count++] = cpu_to_le32(0x80000000); 1717 buffer[count++] = cpu_to_le32(0x80000000); 1718 1719 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1720 for (ext = sect->section; ext->extent != NULL; ++ext) { 1721 if (sect->id == SECT_CONTEXT) { 1722 buffer[count++] = 1723 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1724 buffer[count++] = cpu_to_le32(ext->reg_index - 1725 PACKET3_SET_CONTEXT_REG_START); 1726 for (i = 0; i < ext->reg_count; i++) 1727 buffer[count++] = cpu_to_le32(ext->extent[i]); 1728 } else { 1729 return; 1730 } 1731 } 1732 } 1733 1734 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1735 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 1736 1737 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1738 buffer[count++] = cpu_to_le32(0); 1739 } 1740 1741 static void gfx_v9_0_init_always_on_cu_mask(struct amdgpu_device *adev) 1742 { 1743 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info; 1744 uint32_t pg_always_on_cu_num = 2; 1745 uint32_t always_on_cu_num; 1746 uint32_t i, j, k; 1747 uint32_t mask, cu_bitmap, counter; 1748 1749 if (adev->flags & AMD_IS_APU) 1750 always_on_cu_num = 4; 1751 else if (adev->asic_type == CHIP_VEGA12) 1752 always_on_cu_num = 8; 1753 else 1754 always_on_cu_num = 12; 1755 1756 mutex_lock(&adev->grbm_idx_mutex); 1757 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1758 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1759 mask = 1; 1760 cu_bitmap = 0; 1761 counter = 0; 1762 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 1763 1764 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 1765 if (cu_info->bitmap[i][j] & mask) { 1766 if (counter == pg_always_on_cu_num) 1767 WREG32_SOC15(GC, 0, mmRLC_PG_ALWAYS_ON_CU_MASK, cu_bitmap); 1768 if (counter < always_on_cu_num) 1769 cu_bitmap |= mask; 1770 else 1771 break; 1772 counter++; 1773 } 1774 mask <<= 1; 1775 } 1776 1777 WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, cu_bitmap); 1778 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; 1779 } 1780 } 1781 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1782 mutex_unlock(&adev->grbm_idx_mutex); 1783 } 1784 1785 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev) 1786 { 1787 uint32_t data; 1788 1789 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1790 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1791 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7); 1792 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1793 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16)); 1794 1795 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1796 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1797 1798 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1799 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500); 1800 1801 mutex_lock(&adev->grbm_idx_mutex); 1802 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1803 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1804 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1805 1806 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1807 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1808 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1809 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1810 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1811 1812 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1813 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1814 data &= 0x0000FFFF; 1815 data |= 0x00C00000; 1816 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1817 1818 /* 1819 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xF (4 CUs AON for Raven), 1820 * programmed in gfx_v9_0_init_always_on_cu_mask() 1821 */ 1822 1823 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1824 * but used for RLC_LB_CNTL configuration */ 1825 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1826 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1827 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1828 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1829 mutex_unlock(&adev->grbm_idx_mutex); 1830 1831 gfx_v9_0_init_always_on_cu_mask(adev); 1832 } 1833 1834 static void gfx_v9_4_init_lbpw(struct amdgpu_device *adev) 1835 { 1836 uint32_t data; 1837 1838 /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */ 1839 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F); 1840 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x033388F8); 1841 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077); 1842 WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x10 | 0x27 << 8 | 0x02FA << 16)); 1843 1844 /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */ 1845 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000); 1846 1847 /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */ 1848 WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000800); 1849 1850 mutex_lock(&adev->grbm_idx_mutex); 1851 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1852 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1853 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1854 1855 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ 1856 data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003); 1857 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010); 1858 data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F); 1859 WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data); 1860 1861 /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */ 1862 data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7); 1863 data &= 0x0000FFFF; 1864 data |= 0x00C00000; 1865 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data); 1866 1867 /* 1868 * RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF (12 CUs AON), 1869 * programmed in gfx_v9_0_init_always_on_cu_mask() 1870 */ 1871 1872 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, 1873 * but used for RLC_LB_CNTL configuration */ 1874 data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK; 1875 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); 1876 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); 1877 WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data); 1878 mutex_unlock(&adev->grbm_idx_mutex); 1879 1880 gfx_v9_0_init_always_on_cu_mask(adev); 1881 } 1882 1883 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable) 1884 { 1885 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 1886 } 1887 1888 static int gfx_v9_0_cp_jump_table_num(struct amdgpu_device *adev) 1889 { 1890 return 5; 1891 } 1892 1893 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) 1894 { 1895 const struct cs_section_def *cs_data; 1896 int r; 1897 1898 adev->gfx.rlc.cs_data = gfx9_cs_data; 1899 1900 cs_data = adev->gfx.rlc.cs_data; 1901 1902 if (cs_data) { 1903 /* init clear state block */ 1904 r = amdgpu_gfx_rlc_init_csb(adev); 1905 if (r) 1906 return r; 1907 } 1908 1909 if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) { 1910 /* TODO: double check the cp_table_size for RV */ 1911 adev->gfx.rlc.cp_table_size = roundup2(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ 1912 r = amdgpu_gfx_rlc_init_cpt(adev); 1913 if (r) 1914 return r; 1915 } 1916 1917 switch (adev->asic_type) { 1918 case CHIP_RAVEN: 1919 gfx_v9_0_init_lbpw(adev); 1920 break; 1921 case CHIP_VEGA20: 1922 gfx_v9_4_init_lbpw(adev); 1923 break; 1924 default: 1925 break; 1926 } 1927 1928 /* init spm vmid with 0xf */ 1929 if (adev->gfx.rlc.funcs->update_spm_vmid) 1930 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1931 1932 return 0; 1933 } 1934 1935 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev) 1936 { 1937 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1938 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1939 } 1940 1941 static int gfx_v9_0_mec_init(struct amdgpu_device *adev) 1942 { 1943 int r; 1944 u32 *hpd; 1945 const __le32 *fw_data; 1946 unsigned fw_size; 1947 u32 *fw; 1948 size_t mec_hpd_size; 1949 1950 const struct gfx_firmware_header_v1_0 *mec_hdr; 1951 1952 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1953 1954 /* take ownership of the relevant compute queues */ 1955 amdgpu_gfx_compute_queue_acquire(adev); 1956 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; 1957 1958 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1959 AMDGPU_GEM_DOMAIN_VRAM, 1960 &adev->gfx.mec.hpd_eop_obj, 1961 &adev->gfx.mec.hpd_eop_gpu_addr, 1962 (void **)&hpd); 1963 if (r) { 1964 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1965 gfx_v9_0_mec_fini(adev); 1966 return r; 1967 } 1968 1969 memset(hpd, 0, mec_hpd_size); 1970 1971 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1972 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1973 1974 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1975 1976 fw_data = (const __le32 *) 1977 (adev->gfx.mec_fw->data + 1978 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1979 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4; 1980 1981 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1982 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1983 &adev->gfx.mec.mec_fw_obj, 1984 &adev->gfx.mec.mec_fw_gpu_addr, 1985 (void **)&fw); 1986 if (r) { 1987 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r); 1988 gfx_v9_0_mec_fini(adev); 1989 return r; 1990 } 1991 1992 memcpy(fw, fw_data, fw_size); 1993 1994 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1995 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1996 1997 return 0; 1998 } 1999 2000 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) 2001 { 2002 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 2003 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2004 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2005 (address << SQ_IND_INDEX__INDEX__SHIFT) | 2006 (SQ_IND_INDEX__FORCE_READ_MASK)); 2007 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 2008 } 2009 2010 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, 2011 uint32_t wave, uint32_t thread, 2012 uint32_t regno, uint32_t num, uint32_t *out) 2013 { 2014 WREG32_SOC15_RLC(GC, 0, mmSQ_IND_INDEX, 2015 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 2016 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | 2017 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 2018 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) | 2019 (SQ_IND_INDEX__FORCE_READ_MASK) | 2020 (SQ_IND_INDEX__AUTO_INCR_MASK)); 2021 while (num--) 2022 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 2023 } 2024 2025 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 2026 { 2027 /* type 1 wave data */ 2028 dst[(*no_fields)++] = 1; 2029 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); 2030 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); 2031 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); 2032 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); 2033 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); 2034 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID); 2035 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0); 2036 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1); 2037 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC); 2038 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC); 2039 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS); 2040 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS); 2041 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0); 2042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0); 2043 } 2044 2045 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 2046 uint32_t wave, uint32_t start, 2047 uint32_t size, uint32_t *dst) 2048 { 2049 wave_read_regs( 2050 adev, simd, wave, 0, 2051 start + SQIND_WAVE_SGPRS_OFFSET, size, dst); 2052 } 2053 2054 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 2055 uint32_t wave, uint32_t thread, 2056 uint32_t start, uint32_t size, 2057 uint32_t *dst) 2058 { 2059 wave_read_regs( 2060 adev, simd, wave, thread, 2061 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 2062 } 2063 2064 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev, 2065 u32 me, u32 pipe, u32 q, u32 vm) 2066 { 2067 soc15_grbm_select(adev, me, pipe, q, vm); 2068 } 2069 2070 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { 2071 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 2072 .select_se_sh = &gfx_v9_0_select_se_sh, 2073 .read_wave_data = &gfx_v9_0_read_wave_data, 2074 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 2075 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 2076 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, 2077 .ras_error_inject = &gfx_v9_0_ras_error_inject, 2078 .query_ras_error_count = &gfx_v9_0_query_ras_error_count, 2079 .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count, 2080 }; 2081 2082 static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs = { 2083 .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, 2084 .select_se_sh = &gfx_v9_0_select_se_sh, 2085 .read_wave_data = &gfx_v9_0_read_wave_data, 2086 .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, 2087 .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, 2088 .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, 2089 .ras_error_inject = &gfx_v9_4_ras_error_inject, 2090 .query_ras_error_count = &gfx_v9_4_query_ras_error_count, 2091 .reset_ras_error_count = &gfx_v9_4_reset_ras_error_count, 2092 }; 2093 2094 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) 2095 { 2096 u32 gb_addr_config; 2097 int err; 2098 2099 adev->gfx.funcs = &gfx_v9_0_gfx_funcs; 2100 2101 switch (adev->asic_type) { 2102 case CHIP_VEGA10: 2103 adev->gfx.config.max_hw_contexts = 8; 2104 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2105 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2106 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2107 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2108 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN; 2109 break; 2110 case CHIP_VEGA12: 2111 adev->gfx.config.max_hw_contexts = 8; 2112 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2113 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2114 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2115 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2116 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; 2117 DRM_INFO("fix gfx.config for vega12\n"); 2118 break; 2119 case CHIP_VEGA20: 2120 adev->gfx.config.max_hw_contexts = 8; 2121 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2122 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2123 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2124 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2125 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2126 gb_addr_config &= ~0xf3e777ff; 2127 gb_addr_config |= 0x22014042; 2128 /* check vbios table if gpu info is not available */ 2129 err = amdgpu_atomfirmware_get_gfx_info(adev); 2130 if (err) 2131 return err; 2132 break; 2133 case CHIP_RAVEN: 2134 adev->gfx.config.max_hw_contexts = 8; 2135 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2136 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2137 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2138 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2139 if (adev->rev_id >= 8) 2140 gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN; 2141 else 2142 gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; 2143 break; 2144 case CHIP_ARCTURUS: 2145 adev->gfx.funcs = &gfx_v9_4_gfx_funcs; 2146 adev->gfx.config.max_hw_contexts = 8; 2147 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2148 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2149 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 2150 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2151 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2152 gb_addr_config &= ~0xf3e777ff; 2153 gb_addr_config |= 0x22014042; 2154 break; 2155 case CHIP_RENOIR: 2156 adev->gfx.config.max_hw_contexts = 8; 2157 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 2158 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 2159 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80; 2160 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 2161 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 2162 gb_addr_config &= ~0xf3e777ff; 2163 gb_addr_config |= 0x22010042; 2164 break; 2165 default: 2166 BUG(); 2167 break; 2168 } 2169 2170 adev->gfx.config.gb_addr_config = gb_addr_config; 2171 2172 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 2173 REG_GET_FIELD( 2174 adev->gfx.config.gb_addr_config, 2175 GB_ADDR_CONFIG, 2176 NUM_PIPES); 2177 2178 adev->gfx.config.max_tile_pipes = 2179 adev->gfx.config.gb_addr_config_fields.num_pipes; 2180 2181 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << 2182 REG_GET_FIELD( 2183 adev->gfx.config.gb_addr_config, 2184 GB_ADDR_CONFIG, 2185 NUM_BANKS); 2186 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 2187 REG_GET_FIELD( 2188 adev->gfx.config.gb_addr_config, 2189 GB_ADDR_CONFIG, 2190 MAX_COMPRESSED_FRAGS); 2191 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 2192 REG_GET_FIELD( 2193 adev->gfx.config.gb_addr_config, 2194 GB_ADDR_CONFIG, 2195 NUM_RB_PER_SE); 2196 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 2197 REG_GET_FIELD( 2198 adev->gfx.config.gb_addr_config, 2199 GB_ADDR_CONFIG, 2200 NUM_SHADER_ENGINES); 2201 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 2202 REG_GET_FIELD( 2203 adev->gfx.config.gb_addr_config, 2204 GB_ADDR_CONFIG, 2205 PIPE_INTERLEAVE_SIZE)); 2206 2207 return 0; 2208 } 2209 2210 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 2211 int mec, int pipe, int queue) 2212 { 2213 int r; 2214 unsigned irq_type; 2215 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 2216 2217 ring = &adev->gfx.compute_ring[ring_id]; 2218 2219 /* mec0 is me1 */ 2220 ring->me = mec + 1; 2221 ring->pipe = pipe; 2222 ring->queue = queue; 2223 2224 ring->ring_obj = NULL; 2225 ring->use_doorbell = true; 2226 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 2227 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 2228 + (ring_id * GFX9_MEC_HPD_SIZE); 2229 snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 2230 2231 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2232 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 2233 + ring->pipe; 2234 2235 /* type-2 packets are deprecated on MEC, use type-3 instead */ 2236 r = amdgpu_ring_init(adev, ring, 1024, 2237 &adev->gfx.eop_irq, irq_type); 2238 if (r) 2239 return r; 2240 2241 2242 return 0; 2243 } 2244 2245 static int gfx_v9_0_sw_init(void *handle) 2246 { 2247 int i, j, k, r, ring_id; 2248 struct amdgpu_ring *ring; 2249 struct amdgpu_kiq *kiq; 2250 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2251 2252 switch (adev->asic_type) { 2253 case CHIP_VEGA10: 2254 case CHIP_VEGA12: 2255 case CHIP_VEGA20: 2256 case CHIP_RAVEN: 2257 case CHIP_ARCTURUS: 2258 case CHIP_RENOIR: 2259 adev->gfx.mec.num_mec = 2; 2260 break; 2261 default: 2262 adev->gfx.mec.num_mec = 1; 2263 break; 2264 } 2265 2266 adev->gfx.mec.num_pipe_per_mec = 4; 2267 adev->gfx.mec.num_queue_per_pipe = 8; 2268 2269 /* EOP Event */ 2270 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); 2271 if (r) 2272 return r; 2273 2274 /* Privileged reg */ 2275 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT, 2276 &adev->gfx.priv_reg_irq); 2277 if (r) 2278 return r; 2279 2280 /* Privileged inst */ 2281 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT, 2282 &adev->gfx.priv_inst_irq); 2283 if (r) 2284 return r; 2285 2286 /* ECC error */ 2287 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_ECC_ERROR, 2288 &adev->gfx.cp_ecc_error_irq); 2289 if (r) 2290 return r; 2291 2292 /* FUE error */ 2293 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_FUE_ERROR, 2294 &adev->gfx.cp_ecc_error_irq); 2295 if (r) 2296 return r; 2297 2298 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 2299 2300 gfx_v9_0_scratch_init(adev); 2301 2302 r = gfx_v9_0_init_microcode(adev); 2303 if (r) { 2304 DRM_ERROR("Failed to load gfx firmware!\n"); 2305 return r; 2306 } 2307 2308 r = adev->gfx.rlc.funcs->init(adev); 2309 if (r) { 2310 DRM_ERROR("Failed to init rlc BOs!\n"); 2311 return r; 2312 } 2313 2314 r = gfx_v9_0_mec_init(adev); 2315 if (r) { 2316 DRM_ERROR("Failed to init MEC BOs!\n"); 2317 return r; 2318 } 2319 2320 /* set up the gfx ring */ 2321 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2322 ring = &adev->gfx.gfx_ring[i]; 2323 ring->ring_obj = NULL; 2324 if (!i) 2325 snprintf(ring->name, sizeof(ring->name), "gfx"); 2326 else 2327 snprintf(ring->name, sizeof(ring->name), "gfx_%d", i); 2328 ring->use_doorbell = true; 2329 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 2330 r = amdgpu_ring_init(adev, ring, 1024, 2331 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP); 2332 if (r) 2333 return r; 2334 } 2335 2336 /* set up the compute queues - allocate horizontally across pipes */ 2337 ring_id = 0; 2338 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 2339 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 2340 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 2341 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) 2342 continue; 2343 2344 r = gfx_v9_0_compute_ring_init(adev, 2345 ring_id, 2346 i, k, j); 2347 if (r) 2348 return r; 2349 2350 ring_id++; 2351 } 2352 } 2353 } 2354 2355 r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE); 2356 if (r) { 2357 DRM_ERROR("Failed to init KIQ BOs!\n"); 2358 return r; 2359 } 2360 2361 kiq = &adev->gfx.kiq; 2362 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 2363 if (r) 2364 return r; 2365 2366 /* create MQD for all compute queues as wel as KIQ for SRIOV case */ 2367 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation)); 2368 if (r) 2369 return r; 2370 2371 adev->gfx.ce_ram_size = 0x8000; 2372 2373 r = gfx_v9_0_gpu_early_init(adev); 2374 if (r) 2375 return r; 2376 2377 return 0; 2378 } 2379 2380 2381 static int gfx_v9_0_sw_fini(void *handle) 2382 { 2383 int i; 2384 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2385 2386 amdgpu_gfx_ras_fini(adev); 2387 2388 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2389 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 2390 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2391 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 2392 2393 amdgpu_gfx_mqd_sw_fini(adev); 2394 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 2395 amdgpu_gfx_kiq_fini(adev); 2396 2397 gfx_v9_0_mec_fini(adev); 2398 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); 2399 if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RENOIR) { 2400 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 2401 &adev->gfx.rlc.cp_table_gpu_addr, 2402 (void **)&adev->gfx.rlc.cp_table_ptr); 2403 } 2404 gfx_v9_0_free_microcode(adev); 2405 2406 return 0; 2407 } 2408 2409 2410 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev) 2411 { 2412 /* TODO */ 2413 } 2414 2415 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance) 2416 { 2417 u32 data; 2418 2419 if (instance == 0xffffffff) 2420 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1); 2421 else 2422 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance); 2423 2424 if (se_num == 0xffffffff) 2425 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); 2426 else 2427 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 2428 2429 if (sh_num == 0xffffffff) 2430 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1); 2431 else 2432 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 2433 2434 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); 2435 } 2436 2437 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev) 2438 { 2439 u32 data, mask; 2440 2441 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 2442 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 2443 2444 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 2445 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 2446 2447 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 2448 adev->gfx.config.max_sh_per_se); 2449 2450 return (~data) & mask; 2451 } 2452 2453 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev) 2454 { 2455 int i, j; 2456 u32 data; 2457 u32 active_rbs = 0; 2458 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 2459 adev->gfx.config.max_sh_per_se; 2460 2461 mutex_lock(&adev->grbm_idx_mutex); 2462 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2463 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2464 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 2465 data = gfx_v9_0_get_rb_active_bitmap(adev); 2466 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 2467 rb_bitmap_width_per_sh); 2468 } 2469 } 2470 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2471 mutex_unlock(&adev->grbm_idx_mutex); 2472 2473 adev->gfx.config.backend_enable_mask = active_rbs; 2474 adev->gfx.config.num_rbs = hweight32(active_rbs); 2475 } 2476 2477 #define DEFAULT_SH_MEM_BASES (0x6000) 2478 #define FIRST_COMPUTE_VMID (8) 2479 #define LAST_COMPUTE_VMID (16) 2480 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev) 2481 { 2482 int i; 2483 uint32_t sh_mem_config; 2484 uint32_t sh_mem_bases; 2485 2486 /* 2487 * Configure apertures: 2488 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 2489 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 2490 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 2491 */ 2492 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 2493 2494 sh_mem_config = SH_MEM_ADDRESS_MODE_64 | 2495 SH_MEM_ALIGNMENT_MODE_UNALIGNED << 2496 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 2497 2498 mutex_lock(&adev->srbm_mutex); 2499 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 2500 soc15_grbm_select(adev, 0, 0, 0, i); 2501 /* CP and shaders */ 2502 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 2503 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 2504 } 2505 soc15_grbm_select(adev, 0, 0, 0, 0); 2506 mutex_unlock(&adev->srbm_mutex); 2507 2508 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 2509 acccess. These should be enabled by FW for target VMIDs. */ 2510 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 2511 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 2512 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 2513 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 2514 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 2515 } 2516 } 2517 2518 static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev) 2519 { 2520 int vmid; 2521 2522 /* 2523 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 2524 * access. Compute VMIDs should be enabled by FW for target VMIDs, 2525 * the driver can enable them for graphics. VMID0 should maintain 2526 * access so that HWS firmware can save/restore entries. 2527 */ 2528 for (vmid = 1; vmid < 16; vmid++) { 2529 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 2530 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 2531 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 2532 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 2533 } 2534 } 2535 2536 static void gfx_v9_0_init_sq_config(struct amdgpu_device *adev) 2537 { 2538 uint32_t tmp; 2539 2540 switch (adev->asic_type) { 2541 case CHIP_ARCTURUS: 2542 tmp = RREG32_SOC15(GC, 0, mmSQ_CONFIG); 2543 tmp = REG_SET_FIELD(tmp, SQ_CONFIG, 2544 DISABLE_BARRIER_WAITCNT, 1); 2545 WREG32_SOC15(GC, 0, mmSQ_CONFIG, tmp); 2546 break; 2547 default: 2548 break; 2549 }; 2550 } 2551 2552 static void gfx_v9_0_constants_init(struct amdgpu_device *adev) 2553 { 2554 u32 tmp; 2555 int i; 2556 2557 WREG32_FIELD15_RLC(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 2558 2559 gfx_v9_0_tiling_mode_table_init(adev); 2560 2561 gfx_v9_0_setup_rb(adev); 2562 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info); 2563 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2); 2564 2565 /* XXX SH_MEM regs */ 2566 /* where to put LDS, scratch, GPUVM in FSA64 space */ 2567 mutex_lock(&adev->srbm_mutex); 2568 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 2569 soc15_grbm_select(adev, 0, 0, 0, i); 2570 /* CP and shaders */ 2571 if (i == 0) { 2572 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2573 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2574 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2575 !!amdgpu_noretry); 2576 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2577 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, 0); 2578 } else { 2579 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, 2580 SH_MEM_ALIGNMENT_MODE_UNALIGNED); 2581 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, RETRY_DISABLE, 2582 !!amdgpu_noretry); 2583 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, tmp); 2584 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 2585 (adev->gmc.private_aperture_start >> 48)); 2586 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 2587 (adev->gmc.shared_aperture_start >> 48)); 2588 WREG32_SOC15_RLC(GC, 0, mmSH_MEM_BASES, tmp); 2589 } 2590 } 2591 soc15_grbm_select(adev, 0, 0, 0, 0); 2592 2593 mutex_unlock(&adev->srbm_mutex); 2594 2595 gfx_v9_0_init_compute_vmid(adev); 2596 gfx_v9_0_init_gds_vmid(adev); 2597 gfx_v9_0_init_sq_config(adev); 2598 } 2599 2600 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev) 2601 { 2602 u32 i, j, k; 2603 u32 mask; 2604 2605 mutex_lock(&adev->grbm_idx_mutex); 2606 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2607 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2608 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 2609 for (k = 0; k < adev->usec_timeout; k++) { 2610 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 2611 break; 2612 udelay(1); 2613 } 2614 if (k == adev->usec_timeout) { 2615 gfx_v9_0_select_se_sh(adev, 0xffffffff, 2616 0xffffffff, 0xffffffff); 2617 mutex_unlock(&adev->grbm_idx_mutex); 2618 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 2619 i, j); 2620 return; 2621 } 2622 } 2623 } 2624 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2625 mutex_unlock(&adev->grbm_idx_mutex); 2626 2627 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | 2628 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK | 2629 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK | 2630 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK; 2631 for (k = 0; k < adev->usec_timeout; k++) { 2632 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) 2633 break; 2634 udelay(1); 2635 } 2636 } 2637 2638 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 2639 bool enable) 2640 { 2641 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 2642 2643 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); 2644 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); 2645 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); 2646 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); 2647 2648 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 2649 } 2650 2651 static void gfx_v9_0_init_csb(struct amdgpu_device *adev) 2652 { 2653 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 2654 /* csib */ 2655 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI), 2656 adev->gfx.rlc.clear_state_gpu_addr >> 32); 2657 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO), 2658 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 2659 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH), 2660 adev->gfx.rlc.clear_state_size); 2661 } 2662 2663 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format, 2664 int indirect_offset, 2665 int list_size, 2666 int *unique_indirect_regs, 2667 int unique_indirect_reg_count, 2668 int *indirect_start_offsets, 2669 int *indirect_start_offsets_count, 2670 int max_start_offsets_count) 2671 { 2672 int idx; 2673 2674 for (; indirect_offset < list_size; indirect_offset++) { 2675 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count); 2676 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset; 2677 *indirect_start_offsets_count = *indirect_start_offsets_count + 1; 2678 2679 while (register_list_format[indirect_offset] != 0xFFFFFFFF) { 2680 indirect_offset += 2; 2681 2682 /* look for the matching indice */ 2683 for (idx = 0; idx < unique_indirect_reg_count; idx++) { 2684 if (unique_indirect_regs[idx] == 2685 register_list_format[indirect_offset] || 2686 !unique_indirect_regs[idx]) 2687 break; 2688 } 2689 2690 BUG_ON(idx >= unique_indirect_reg_count); 2691 2692 if (!unique_indirect_regs[idx]) 2693 unique_indirect_regs[idx] = register_list_format[indirect_offset]; 2694 2695 indirect_offset++; 2696 } 2697 } 2698 } 2699 2700 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev) 2701 { 2702 int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2703 int unique_indirect_reg_count = 0; 2704 2705 int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; 2706 int indirect_start_offsets_count = 0; 2707 2708 int list_size = 0; 2709 int i = 0, j = 0; 2710 u32 tmp = 0; 2711 2712 u32 *register_list_format = 2713 kmemdup(adev->gfx.rlc.register_list_format, 2714 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL); 2715 if (!register_list_format) 2716 return -ENOMEM; 2717 2718 /* setup unique_indirect_regs array and indirect_start_offsets array */ 2719 unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs); 2720 gfx_v9_1_parse_ind_reg_list(register_list_format, 2721 adev->gfx.rlc.reg_list_format_direct_reg_list_length, 2722 adev->gfx.rlc.reg_list_format_size_bytes >> 2, 2723 unique_indirect_regs, 2724 unique_indirect_reg_count, 2725 indirect_start_offsets, 2726 &indirect_start_offsets_count, 2727 ARRAY_SIZE(indirect_start_offsets)); 2728 2729 /* enable auto inc in case it is disabled */ 2730 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 2731 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 2732 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 2733 2734 /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */ 2735 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 2736 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET); 2737 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) 2738 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), 2739 adev->gfx.rlc.register_restore[i]); 2740 2741 /* load indirect register */ 2742 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2743 adev->gfx.rlc.reg_list_format_start); 2744 2745 /* direct register portion */ 2746 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++) 2747 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2748 register_list_format[i]); 2749 2750 /* indirect register portion */ 2751 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) { 2752 if (register_list_format[i] == 0xFFFFFFFF) { 2753 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2754 continue; 2755 } 2756 2757 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2758 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]); 2759 2760 for (j = 0; j < unique_indirect_reg_count; j++) { 2761 if (register_list_format[i] == unique_indirect_regs[j]) { 2762 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j); 2763 break; 2764 } 2765 } 2766 2767 BUG_ON(j >= unique_indirect_reg_count); 2768 2769 i++; 2770 } 2771 2772 /* set save/restore list size */ 2773 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; 2774 list_size = list_size >> 1; 2775 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2776 adev->gfx.rlc.reg_restore_list_size); 2777 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size); 2778 2779 /* write the starting offsets to RLC scratch ram */ 2780 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), 2781 adev->gfx.rlc.starting_offsets_start); 2782 for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++) 2783 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), 2784 indirect_start_offsets[i]); 2785 2786 /* load unique indirect regs*/ 2787 for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) { 2788 if (unique_indirect_regs[i] != 0) { 2789 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) 2790 + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i], 2791 unique_indirect_regs[i] & 0x3FFFF); 2792 2793 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) 2794 + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i], 2795 unique_indirect_regs[i] >> 20); 2796 } 2797 } 2798 2799 kfree(register_list_format); 2800 return 0; 2801 } 2802 2803 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev) 2804 { 2805 WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1); 2806 } 2807 2808 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev, 2809 bool enable) 2810 { 2811 uint32_t data = 0; 2812 uint32_t default_data = 0; 2813 2814 default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS)); 2815 if (enable == true) { 2816 /* enable GFXIP control over CGPG */ 2817 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2818 if(default_data != data) 2819 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2820 2821 /* update status */ 2822 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK; 2823 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT); 2824 if(default_data != data) 2825 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2826 } else { 2827 /* restore GFXIP control over GCPG */ 2828 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK; 2829 if(default_data != data) 2830 WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data); 2831 } 2832 } 2833 2834 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev) 2835 { 2836 uint32_t data = 0; 2837 2838 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2839 AMD_PG_SUPPORT_GFX_SMG | 2840 AMD_PG_SUPPORT_GFX_DMG)) { 2841 /* init IDLE_POLL_COUNT = 60 */ 2842 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); 2843 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 2844 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 2845 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); 2846 2847 /* init RLC PG Delay */ 2848 data = 0; 2849 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT); 2850 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT); 2851 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT); 2852 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT); 2853 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data); 2854 2855 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2)); 2856 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK; 2857 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT); 2858 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data); 2859 2860 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3)); 2861 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK; 2862 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT); 2863 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data); 2864 2865 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL)); 2866 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK; 2867 2868 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */ 2869 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT); 2870 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data); 2871 2872 pwr_10_0_gfxip_control_over_cgpg(adev, true); 2873 } 2874 } 2875 2876 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, 2877 bool enable) 2878 { 2879 uint32_t data = 0; 2880 uint32_t default_data = 0; 2881 2882 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2883 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2884 SMU_CLK_SLOWDOWN_ON_PU_ENABLE, 2885 enable ? 1 : 0); 2886 if (default_data != data) 2887 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2888 } 2889 2890 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, 2891 bool enable) 2892 { 2893 uint32_t data = 0; 2894 uint32_t default_data = 0; 2895 2896 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2897 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2898 SMU_CLK_SLOWDOWN_ON_PD_ENABLE, 2899 enable ? 1 : 0); 2900 if(default_data != data) 2901 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2902 } 2903 2904 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev, 2905 bool enable) 2906 { 2907 uint32_t data = 0; 2908 uint32_t default_data = 0; 2909 2910 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2911 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2912 CP_PG_DISABLE, 2913 enable ? 0 : 1); 2914 if(default_data != data) 2915 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2916 } 2917 2918 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev, 2919 bool enable) 2920 { 2921 uint32_t data, default_data; 2922 2923 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2924 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2925 GFX_POWER_GATING_ENABLE, 2926 enable ? 1 : 0); 2927 if(default_data != data) 2928 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2929 } 2930 2931 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev, 2932 bool enable) 2933 { 2934 uint32_t data, default_data; 2935 2936 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2937 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2938 GFX_PIPELINE_PG_ENABLE, 2939 enable ? 1 : 0); 2940 if(default_data != data) 2941 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2942 2943 if (!enable) 2944 /* read any GFX register to wake up GFX */ 2945 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL)); 2946 } 2947 2948 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, 2949 bool enable) 2950 { 2951 uint32_t data, default_data; 2952 2953 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2954 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2955 STATIC_PER_CU_PG_ENABLE, 2956 enable ? 1 : 0); 2957 if(default_data != data) 2958 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2959 } 2960 2961 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, 2962 bool enable) 2963 { 2964 uint32_t data, default_data; 2965 2966 default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL)); 2967 data = REG_SET_FIELD(data, RLC_PG_CNTL, 2968 DYN_PER_CU_PG_ENABLE, 2969 enable ? 1 : 0); 2970 if(default_data != data) 2971 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data); 2972 } 2973 2974 static void gfx_v9_0_init_pg(struct amdgpu_device *adev) 2975 { 2976 gfx_v9_0_init_csb(adev); 2977 2978 /* 2979 * Rlc save restore list is workable since v2_1. 2980 * And it's needed by gfxoff feature. 2981 */ 2982 if (adev->gfx.rlc.is_rlc_v2_1) { 2983 if (adev->asic_type == CHIP_VEGA12 || 2984 (adev->asic_type == CHIP_RAVEN && 2985 adev->rev_id >= 8)) 2986 gfx_v9_1_init_rlc_save_restore_list(adev); 2987 gfx_v9_0_enable_save_restore_machine(adev); 2988 } 2989 2990 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG | 2991 AMD_PG_SUPPORT_GFX_SMG | 2992 AMD_PG_SUPPORT_GFX_DMG | 2993 AMD_PG_SUPPORT_CP | 2994 AMD_PG_SUPPORT_GDS | 2995 AMD_PG_SUPPORT_RLC_SMU_HS)) { 2996 WREG32(mmRLC_JUMP_TABLE_RESTORE, 2997 adev->gfx.rlc.cp_table_gpu_addr >> 8); 2998 gfx_v9_0_init_gfx_power_gating(adev); 2999 } 3000 } 3001 3002 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev) 3003 { 3004 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0); 3005 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3006 gfx_v9_0_wait_for_rlc_serdes(adev); 3007 } 3008 3009 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev) 3010 { 3011 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 3012 udelay(50); 3013 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 3014 udelay(50); 3015 } 3016 3017 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) 3018 { 3019 #ifdef AMDGPU_RLC_DEBUG_RETRY 3020 u32 rlc_ucode_ver; 3021 #endif 3022 3023 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 3024 udelay(50); 3025 3026 /* carrizo do enable cp interrupt after cp inited */ 3027 if (!(adev->flags & AMD_IS_APU)) { 3028 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3029 udelay(50); 3030 } 3031 3032 #ifdef AMDGPU_RLC_DEBUG_RETRY 3033 /* RLC_GPM_GENERAL_6 : RLC Ucode version */ 3034 rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6); 3035 if(rlc_ucode_ver == 0x108) { 3036 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n", 3037 rlc_ucode_ver, adev->gfx.rlc_fw_version); 3038 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles, 3039 * default is 0x9C4 to create a 100us interval */ 3040 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4); 3041 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr 3042 * to disable the page fault retry interrupts, default is 3043 * 0x100 (256) */ 3044 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100); 3045 } 3046 #endif 3047 } 3048 3049 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev) 3050 { 3051 const struct rlc_firmware_header_v2_0 *hdr; 3052 const __le32 *fw_data; 3053 unsigned i, fw_size; 3054 3055 if (!adev->gfx.rlc_fw) 3056 return -EINVAL; 3057 3058 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 3059 amdgpu_ucode_print_rlc_hdr(&hdr->header); 3060 3061 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 3062 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 3063 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 3064 3065 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 3066 RLCG_UCODE_LOADING_START_ADDRESS); 3067 for (i = 0; i < fw_size; i++) 3068 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); 3069 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 3070 3071 return 0; 3072 } 3073 3074 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) 3075 { 3076 int r; 3077 3078 if (amdgpu_sriov_vf(adev)) { 3079 gfx_v9_0_init_csb(adev); 3080 return 0; 3081 } 3082 3083 adev->gfx.rlc.funcs->stop(adev); 3084 3085 /* disable CG */ 3086 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 3087 3088 gfx_v9_0_init_pg(adev); 3089 3090 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3091 /* legacy rlc firmware loading */ 3092 r = gfx_v9_0_rlc_load_microcode(adev); 3093 if (r) 3094 return r; 3095 } 3096 3097 switch (adev->asic_type) { 3098 case CHIP_RAVEN: 3099 if (amdgpu_lbpw == 0) 3100 gfx_v9_0_enable_lbpw(adev, false); 3101 else 3102 gfx_v9_0_enable_lbpw(adev, true); 3103 break; 3104 case CHIP_VEGA20: 3105 if (amdgpu_lbpw > 0) 3106 gfx_v9_0_enable_lbpw(adev, true); 3107 else 3108 gfx_v9_0_enable_lbpw(adev, false); 3109 break; 3110 default: 3111 break; 3112 } 3113 3114 adev->gfx.rlc.funcs->start(adev); 3115 3116 return 0; 3117 } 3118 3119 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 3120 { 3121 int i; 3122 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 3123 3124 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 3125 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 3126 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 3127 if (!enable) { 3128 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3129 adev->gfx.gfx_ring[i].sched.ready = false; 3130 } 3131 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 3132 udelay(50); 3133 } 3134 3135 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 3136 { 3137 const struct gfx_firmware_header_v1_0 *pfp_hdr; 3138 const struct gfx_firmware_header_v1_0 *ce_hdr; 3139 const struct gfx_firmware_header_v1_0 *me_hdr; 3140 const __le32 *fw_data; 3141 unsigned i, fw_size; 3142 3143 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 3144 return -EINVAL; 3145 3146 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 3147 adev->gfx.pfp_fw->data; 3148 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 3149 adev->gfx.ce_fw->data; 3150 me_hdr = (const struct gfx_firmware_header_v1_0 *) 3151 adev->gfx.me_fw->data; 3152 3153 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 3154 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 3155 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 3156 3157 gfx_v9_0_cp_gfx_enable(adev, false); 3158 3159 /* PFP */ 3160 fw_data = (const __le32 *) 3161 (adev->gfx.pfp_fw->data + 3162 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 3163 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; 3164 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0); 3165 for (i = 0; i < fw_size; i++) 3166 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); 3167 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 3168 3169 /* CE */ 3170 fw_data = (const __le32 *) 3171 (adev->gfx.ce_fw->data + 3172 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 3173 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; 3174 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0); 3175 for (i = 0; i < fw_size; i++) 3176 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); 3177 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 3178 3179 /* ME */ 3180 fw_data = (const __le32 *) 3181 (adev->gfx.me_fw->data + 3182 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 3183 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; 3184 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0); 3185 for (i = 0; i < fw_size; i++) 3186 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++)); 3187 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); 3188 3189 return 0; 3190 } 3191 3192 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev) 3193 { 3194 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; 3195 const struct cs_section_def *sect = NULL; 3196 const struct cs_extent_def *ext = NULL; 3197 int r, i, tmp; 3198 3199 /* init the CP */ 3200 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); 3201 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 3202 3203 gfx_v9_0_cp_gfx_enable(adev, true); 3204 3205 r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3); 3206 if (r) { 3207 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 3208 return r; 3209 } 3210 3211 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3212 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 3213 3214 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 3215 amdgpu_ring_write(ring, 0x80000000); 3216 amdgpu_ring_write(ring, 0x80000000); 3217 3218 for (sect = gfx9_cs_data; sect->section != NULL; ++sect) { 3219 for (ext = sect->section; ext->extent != NULL; ++ext) { 3220 if (sect->id == SECT_CONTEXT) { 3221 amdgpu_ring_write(ring, 3222 PACKET3(PACKET3_SET_CONTEXT_REG, 3223 ext->reg_count)); 3224 amdgpu_ring_write(ring, 3225 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); 3226 for (i = 0; i < ext->reg_count; i++) 3227 amdgpu_ring_write(ring, ext->extent[i]); 3228 } 3229 } 3230 } 3231 3232 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 3233 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 3234 3235 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 3236 amdgpu_ring_write(ring, 0); 3237 3238 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 3239 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 3240 amdgpu_ring_write(ring, 0x8000); 3241 amdgpu_ring_write(ring, 0x8000); 3242 3243 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1)); 3244 tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE | 3245 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START)); 3246 amdgpu_ring_write(ring, tmp); 3247 amdgpu_ring_write(ring, 0); 3248 3249 amdgpu_ring_commit(ring); 3250 3251 return 0; 3252 } 3253 3254 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev) 3255 { 3256 struct amdgpu_ring *ring; 3257 u32 tmp; 3258 u32 rb_bufsz; 3259 u64 rb_addr, rptr_addr, wptr_gpu_addr; 3260 3261 /* Set the write pointer delay */ 3262 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 3263 3264 /* set the RB to use vmid 0 */ 3265 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 3266 3267 /* Set ring buffer size */ 3268 ring = &adev->gfx.gfx_ring[0]; 3269 rb_bufsz = order_base_2(ring->ring_size / 8); 3270 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 3271 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 3272 #ifdef __BIG_ENDIAN 3273 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 3274 #endif 3275 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3276 3277 /* Initialize the ring buffer's write pointers */ 3278 ring->wptr = 0; 3279 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 3280 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 3281 3282 /* set the wb address wether it's enabled or not */ 3283 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3284 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 3285 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 3286 3287 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3288 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); 3289 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); 3290 3291 mdelay(1); 3292 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 3293 3294 rb_addr = ring->gpu_addr >> 8; 3295 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 3296 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 3297 3298 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3299 if (ring->use_doorbell) { 3300 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3301 DOORBELL_OFFSET, ring->doorbell_index); 3302 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3303 DOORBELL_EN, 1); 3304 } else { 3305 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0); 3306 } 3307 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 3308 3309 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 3310 DOORBELL_RANGE_LOWER, ring->doorbell_index); 3311 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 3312 3313 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 3314 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 3315 3316 3317 /* start the ring */ 3318 gfx_v9_0_cp_gfx_start(adev); 3319 ring->sched.ready = true; 3320 3321 return 0; 3322 } 3323 3324 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 3325 { 3326 int i; 3327 3328 if (enable) { 3329 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); 3330 } else { 3331 WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 3332 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 3333 for (i = 0; i < adev->gfx.num_compute_rings; i++) 3334 adev->gfx.compute_ring[i].sched.ready = false; 3335 adev->gfx.kiq.ring.sched.ready = false; 3336 } 3337 udelay(50); 3338 } 3339 3340 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev) 3341 { 3342 const struct gfx_firmware_header_v1_0 *mec_hdr; 3343 const __le32 *fw_data; 3344 unsigned i; 3345 u32 tmp; 3346 3347 if (!adev->gfx.mec_fw) 3348 return -EINVAL; 3349 3350 gfx_v9_0_cp_compute_enable(adev, false); 3351 3352 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 3353 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 3354 3355 fw_data = (const __le32 *) 3356 (adev->gfx.mec_fw->data + 3357 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 3358 tmp = 0; 3359 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 3360 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 3361 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 3362 3363 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 3364 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000); 3365 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 3366 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3367 3368 /* MEC1 */ 3369 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3370 mec_hdr->jt_offset); 3371 for (i = 0; i < mec_hdr->jt_size; i++) 3372 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 3373 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3374 3375 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 3376 adev->gfx.mec_fw_version); 3377 /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */ 3378 3379 return 0; 3380 } 3381 3382 /* KIQ functions */ 3383 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring) 3384 { 3385 uint32_t tmp; 3386 struct amdgpu_device *adev = ring->adev; 3387 3388 /* tell RLC which is KIQ queue */ 3389 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 3390 tmp &= 0xffffff00; 3391 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3392 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3393 tmp |= 0x80; 3394 WREG32_SOC15_RLC(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3395 } 3396 3397 static void gfx_v9_0_mqd_set_priority(struct amdgpu_ring *ring, struct v9_mqd *mqd) 3398 { 3399 struct amdgpu_device *adev = ring->adev; 3400 3401 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3402 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) { 3403 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 3404 ring->has_high_prio = true; 3405 mqd->cp_hqd_queue_priority = 3406 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 3407 } else { 3408 ring->has_high_prio = false; 3409 } 3410 } 3411 } 3412 3413 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) 3414 { 3415 struct amdgpu_device *adev = ring->adev; 3416 struct v9_mqd *mqd = ring->mqd_ptr; 3417 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3418 uint32_t tmp; 3419 3420 mqd->header = 0xC0310800; 3421 mqd->compute_pipelinestat_enable = 0x00000001; 3422 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3423 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3424 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3425 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3426 mqd->compute_static_thread_mgmt_se4 = 0xffffffff; 3427 mqd->compute_static_thread_mgmt_se5 = 0xffffffff; 3428 mqd->compute_static_thread_mgmt_se6 = 0xffffffff; 3429 mqd->compute_static_thread_mgmt_se7 = 0xffffffff; 3430 mqd->compute_misc_reserved = 0x00000003; 3431 3432 mqd->dynamic_cu_mask_addr_lo = 3433 lower_32_bits(ring->mqd_gpu_addr 3434 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3435 mqd->dynamic_cu_mask_addr_hi = 3436 upper_32_bits(ring->mqd_gpu_addr 3437 + offsetof(struct v9_mqd_allocation, dynamic_cu_mask)); 3438 3439 eop_base_addr = ring->eop_gpu_addr >> 8; 3440 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3441 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3442 3443 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3444 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3445 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3446 (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1)); 3447 3448 mqd->cp_hqd_eop_control = tmp; 3449 3450 /* enable doorbell? */ 3451 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3452 3453 if (ring->use_doorbell) { 3454 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3455 DOORBELL_OFFSET, ring->doorbell_index); 3456 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3457 DOORBELL_EN, 1); 3458 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3459 DOORBELL_SOURCE, 0); 3460 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3461 DOORBELL_HIT, 0); 3462 } else { 3463 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3464 DOORBELL_EN, 0); 3465 } 3466 3467 mqd->cp_hqd_pq_doorbell_control = tmp; 3468 3469 /* disable the queue if it's active */ 3470 ring->wptr = 0; 3471 mqd->cp_hqd_dequeue_request = 0; 3472 mqd->cp_hqd_pq_rptr = 0; 3473 mqd->cp_hqd_pq_wptr_lo = 0; 3474 mqd->cp_hqd_pq_wptr_hi = 0; 3475 3476 /* set the pointer to the MQD */ 3477 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3478 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3479 3480 /* set MQD vmid to 0 */ 3481 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3482 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3483 mqd->cp_mqd_control = tmp; 3484 3485 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3486 hqd_gpu_addr = ring->gpu_addr >> 8; 3487 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3488 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3489 3490 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3491 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3492 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3493 (order_base_2(ring->ring_size / 4) - 1)); 3494 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3495 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3496 #ifdef __BIG_ENDIAN 3497 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3498 #endif 3499 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3500 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); 3501 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3502 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3503 mqd->cp_hqd_pq_control = tmp; 3504 3505 /* set the wb address whether it's enabled or not */ 3506 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3507 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3508 mqd->cp_hqd_pq_rptr_report_addr_hi = 3509 upper_32_bits(wb_gpu_addr) & 0xffff; 3510 3511 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3512 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3513 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3514 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3515 3516 tmp = 0; 3517 /* enable the doorbell if requested */ 3518 if (ring->use_doorbell) { 3519 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3520 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3521 DOORBELL_OFFSET, ring->doorbell_index); 3522 3523 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3524 DOORBELL_EN, 1); 3525 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3526 DOORBELL_SOURCE, 0); 3527 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3528 DOORBELL_HIT, 0); 3529 } 3530 3531 mqd->cp_hqd_pq_doorbell_control = tmp; 3532 3533 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3534 ring->wptr = 0; 3535 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3536 3537 /* set the vmid for the queue */ 3538 mqd->cp_hqd_vmid = 0; 3539 3540 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3541 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3542 mqd->cp_hqd_persistent_state = tmp; 3543 3544 /* set MIN_IB_AVAIL_SIZE */ 3545 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3546 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3547 mqd->cp_hqd_ib_control = tmp; 3548 3549 /* set static priority for a queue/ring */ 3550 gfx_v9_0_mqd_set_priority(ring, mqd); 3551 mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM); 3552 3553 /* map_queues packet doesn't need activate the queue, 3554 * so only kiq need set this field. 3555 */ 3556 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 3557 mqd->cp_hqd_active = 1; 3558 3559 return 0; 3560 } 3561 3562 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring) 3563 { 3564 struct amdgpu_device *adev = ring->adev; 3565 struct v9_mqd *mqd = ring->mqd_ptr; 3566 int j; 3567 3568 /* disable wptr polling */ 3569 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3570 3571 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3572 mqd->cp_hqd_eop_base_addr_lo); 3573 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3574 mqd->cp_hqd_eop_base_addr_hi); 3575 3576 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3577 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_EOP_CONTROL, 3578 mqd->cp_hqd_eop_control); 3579 3580 /* enable doorbell? */ 3581 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3582 mqd->cp_hqd_pq_doorbell_control); 3583 3584 /* disable the queue if it's active */ 3585 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3586 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3587 for (j = 0; j < adev->usec_timeout; j++) { 3588 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3589 break; 3590 udelay(1); 3591 } 3592 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3593 mqd->cp_hqd_dequeue_request); 3594 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 3595 mqd->cp_hqd_pq_rptr); 3596 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3597 mqd->cp_hqd_pq_wptr_lo); 3598 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3599 mqd->cp_hqd_pq_wptr_hi); 3600 } 3601 3602 /* set the pointer to the MQD */ 3603 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR, 3604 mqd->cp_mqd_base_addr_lo); 3605 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3606 mqd->cp_mqd_base_addr_hi); 3607 3608 /* set MQD vmid to 0 */ 3609 WREG32_SOC15_RLC(GC, 0, mmCP_MQD_CONTROL, 3610 mqd->cp_mqd_control); 3611 3612 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3613 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE, 3614 mqd->cp_hqd_pq_base_lo); 3615 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_BASE_HI, 3616 mqd->cp_hqd_pq_base_hi); 3617 3618 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3619 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_CONTROL, 3620 mqd->cp_hqd_pq_control); 3621 3622 /* set the wb address whether it's enabled or not */ 3623 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3624 mqd->cp_hqd_pq_rptr_report_addr_lo); 3625 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3626 mqd->cp_hqd_pq_rptr_report_addr_hi); 3627 3628 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3629 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3630 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3631 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3632 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3633 3634 /* enable the doorbell if requested */ 3635 if (ring->use_doorbell) { 3636 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3637 (adev->doorbell_index.kiq * 2) << 2); 3638 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3639 (adev->doorbell_index.userqueue_end * 2) << 2); 3640 } 3641 3642 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3643 mqd->cp_hqd_pq_doorbell_control); 3644 3645 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3646 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3647 mqd->cp_hqd_pq_wptr_lo); 3648 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3649 mqd->cp_hqd_pq_wptr_hi); 3650 3651 /* set the vmid for the queue */ 3652 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3653 3654 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3655 mqd->cp_hqd_persistent_state); 3656 3657 /* activate the queue */ 3658 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 3659 mqd->cp_hqd_active); 3660 3661 if (ring->use_doorbell) 3662 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3663 3664 return 0; 3665 } 3666 3667 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) 3668 { 3669 struct amdgpu_device *adev = ring->adev; 3670 int j; 3671 3672 /* disable the queue if it's active */ 3673 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3674 3675 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3676 3677 for (j = 0; j < adev->usec_timeout; j++) { 3678 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3679 break; 3680 udelay(1); 3681 } 3682 3683 if (j == AMDGPU_MAX_USEC_TIMEOUT) { 3684 DRM_DEBUG("KIQ dequeue request failed.\n"); 3685 3686 /* Manual disable if dequeue request times out */ 3687 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); 3688 } 3689 3690 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3691 0); 3692 } 3693 3694 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IQ_TIMER, 0); 3695 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_IB_CONTROL, 0); 3696 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0); 3697 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); 3698 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 3699 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_RPTR, 0); 3700 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); 3701 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0); 3702 3703 return 0; 3704 } 3705 3706 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) 3707 { 3708 struct amdgpu_device *adev = ring->adev; 3709 struct v9_mqd *mqd = ring->mqd_ptr; 3710 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3711 3712 gfx_v9_0_kiq_setting(ring); 3713 3714 if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3715 /* reset MQD to a clean status */ 3716 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3717 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3718 3719 /* reset ring buffer */ 3720 ring->wptr = 0; 3721 amdgpu_ring_clear_ring(ring); 3722 3723 mutex_lock(&adev->srbm_mutex); 3724 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3725 gfx_v9_0_kiq_init_register(ring); 3726 soc15_grbm_select(adev, 0, 0, 0, 0); 3727 mutex_unlock(&adev->srbm_mutex); 3728 } else { 3729 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3730 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3731 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3732 mutex_lock(&adev->srbm_mutex); 3733 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3734 gfx_v9_0_mqd_init(ring); 3735 gfx_v9_0_kiq_init_register(ring); 3736 soc15_grbm_select(adev, 0, 0, 0, 0); 3737 mutex_unlock(&adev->srbm_mutex); 3738 3739 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3740 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3741 } 3742 3743 return 0; 3744 } 3745 3746 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) 3747 { 3748 struct amdgpu_device *adev = ring->adev; 3749 struct v9_mqd *mqd = ring->mqd_ptr; 3750 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3751 3752 if (!adev->in_gpu_reset && !adev->in_suspend) { 3753 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); 3754 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; 3755 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; 3756 mutex_lock(&adev->srbm_mutex); 3757 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3758 gfx_v9_0_mqd_init(ring); 3759 soc15_grbm_select(adev, 0, 0, 0, 0); 3760 mutex_unlock(&adev->srbm_mutex); 3761 3762 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3763 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); 3764 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3765 /* reset MQD to a clean status */ 3766 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3767 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); 3768 3769 /* reset ring buffer */ 3770 ring->wptr = 0; 3771 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 3772 amdgpu_ring_clear_ring(ring); 3773 } else { 3774 amdgpu_ring_clear_ring(ring); 3775 } 3776 3777 return 0; 3778 } 3779 3780 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev) 3781 { 3782 struct amdgpu_ring *ring; 3783 int r; 3784 3785 ring = &adev->gfx.kiq.ring; 3786 3787 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3788 if (unlikely(r != 0)) 3789 return r; 3790 3791 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3792 if (unlikely(r != 0)) 3793 return r; 3794 3795 gfx_v9_0_kiq_init_queue(ring); 3796 amdgpu_bo_kunmap(ring->mqd_obj); 3797 ring->mqd_ptr = NULL; 3798 amdgpu_bo_unreserve(ring->mqd_obj); 3799 ring->sched.ready = true; 3800 return 0; 3801 } 3802 3803 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) 3804 { 3805 struct amdgpu_ring *ring = NULL; 3806 int r = 0, i; 3807 3808 gfx_v9_0_cp_compute_enable(adev, true); 3809 3810 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3811 ring = &adev->gfx.compute_ring[i]; 3812 3813 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3814 if (unlikely(r != 0)) 3815 goto done; 3816 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3817 if (!r) { 3818 r = gfx_v9_0_kcq_init_queue(ring); 3819 amdgpu_bo_kunmap(ring->mqd_obj); 3820 ring->mqd_ptr = NULL; 3821 } 3822 amdgpu_bo_unreserve(ring->mqd_obj); 3823 if (r) 3824 goto done; 3825 } 3826 3827 r = amdgpu_gfx_enable_kcq(adev); 3828 done: 3829 return r; 3830 } 3831 3832 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) 3833 { 3834 int r, i; 3835 struct amdgpu_ring *ring; 3836 3837 if (!(adev->flags & AMD_IS_APU)) 3838 gfx_v9_0_enable_gui_idle_interrupt(adev, false); 3839 3840 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 3841 if (adev->asic_type != CHIP_ARCTURUS) { 3842 /* legacy firmware loading */ 3843 r = gfx_v9_0_cp_gfx_load_microcode(adev); 3844 if (r) 3845 return r; 3846 } 3847 3848 r = gfx_v9_0_cp_compute_load_microcode(adev); 3849 if (r) 3850 return r; 3851 } 3852 3853 r = gfx_v9_0_kiq_resume(adev); 3854 if (r) 3855 return r; 3856 3857 if (adev->asic_type != CHIP_ARCTURUS) { 3858 r = gfx_v9_0_cp_gfx_resume(adev); 3859 if (r) 3860 return r; 3861 } 3862 3863 r = gfx_v9_0_kcq_resume(adev); 3864 if (r) 3865 return r; 3866 3867 if (adev->asic_type != CHIP_ARCTURUS) { 3868 ring = &adev->gfx.gfx_ring[0]; 3869 r = amdgpu_ring_test_helper(ring); 3870 if (r) 3871 return r; 3872 } 3873 3874 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3875 ring = &adev->gfx.compute_ring[i]; 3876 amdgpu_ring_test_helper(ring); 3877 } 3878 3879 gfx_v9_0_enable_gui_idle_interrupt(adev, true); 3880 3881 return 0; 3882 } 3883 3884 static void gfx_v9_0_init_tcp_config(struct amdgpu_device *adev) 3885 { 3886 u32 tmp; 3887 3888 if (adev->asic_type != CHIP_ARCTURUS) 3889 return; 3890 3891 tmp = RREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG); 3892 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE64KHASH, 3893 adev->df.hash_status.hash_64k); 3894 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE2MHASH, 3895 adev->df.hash_status.hash_2m); 3896 tmp = REG_SET_FIELD(tmp, TCP_ADDR_CONFIG, ENABLE1GHASH, 3897 adev->df.hash_status.hash_1g); 3898 WREG32_SOC15(GC, 0, mmTCP_ADDR_CONFIG, tmp); 3899 } 3900 3901 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) 3902 { 3903 if (adev->asic_type != CHIP_ARCTURUS) 3904 gfx_v9_0_cp_gfx_enable(adev, enable); 3905 gfx_v9_0_cp_compute_enable(adev, enable); 3906 } 3907 3908 static int gfx_v9_0_hw_init(void *handle) 3909 { 3910 int r; 3911 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3912 3913 if (!amdgpu_sriov_vf(adev)) 3914 gfx_v9_0_init_golden_registers(adev); 3915 3916 gfx_v9_0_constants_init(adev); 3917 3918 gfx_v9_0_init_tcp_config(adev); 3919 3920 r = adev->gfx.rlc.funcs->resume(adev); 3921 if (r) 3922 return r; 3923 3924 r = gfx_v9_0_cp_resume(adev); 3925 if (r) 3926 return r; 3927 3928 return r; 3929 } 3930 3931 static int gfx_v9_0_hw_fini(void *handle) 3932 { 3933 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3934 3935 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); 3936 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3937 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3938 3939 /* DF freeze and kcq disable will fail */ 3940 if (!amdgpu_ras_intr_triggered()) 3941 /* disable KCQ to avoid CPC touch memory not valid anymore */ 3942 amdgpu_gfx_disable_kcq(adev); 3943 3944 if (amdgpu_sriov_vf(adev)) { 3945 gfx_v9_0_cp_gfx_enable(adev, false); 3946 /* must disable polling for SRIOV when hw finished, otherwise 3947 * CPC engine may still keep fetching WB address which is already 3948 * invalid after sw finished and trigger DMAR reading error in 3949 * hypervisor side. 3950 */ 3951 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3952 return 0; 3953 } 3954 3955 /* Use deinitialize sequence from CAIL when unbinding device from driver, 3956 * otherwise KIQ is hanging when binding back 3957 */ 3958 if (!adev->in_gpu_reset && !adev->in_suspend) { 3959 mutex_lock(&adev->srbm_mutex); 3960 soc15_grbm_select(adev, adev->gfx.kiq.ring.me, 3961 adev->gfx.kiq.ring.pipe, 3962 adev->gfx.kiq.ring.queue, 0); 3963 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring); 3964 soc15_grbm_select(adev, 0, 0, 0, 0); 3965 mutex_unlock(&adev->srbm_mutex); 3966 } 3967 3968 gfx_v9_0_cp_enable(adev, false); 3969 adev->gfx.rlc.funcs->stop(adev); 3970 3971 return 0; 3972 } 3973 3974 static int gfx_v9_0_suspend(void *handle) 3975 { 3976 return gfx_v9_0_hw_fini(handle); 3977 } 3978 3979 static int gfx_v9_0_resume(void *handle) 3980 { 3981 return gfx_v9_0_hw_init(handle); 3982 } 3983 3984 static bool gfx_v9_0_is_idle(void *handle) 3985 { 3986 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3987 3988 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3989 GRBM_STATUS, GUI_ACTIVE)) 3990 return false; 3991 else 3992 return true; 3993 } 3994 3995 static int gfx_v9_0_wait_for_idle(void *handle) 3996 { 3997 unsigned i; 3998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3999 4000 for (i = 0; i < adev->usec_timeout; i++) { 4001 if (gfx_v9_0_is_idle(handle)) 4002 return 0; 4003 udelay(1); 4004 } 4005 return -ETIMEDOUT; 4006 } 4007 4008 static int gfx_v9_0_soft_reset(void *handle) 4009 { 4010 u32 grbm_soft_reset = 0; 4011 u32 tmp; 4012 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4013 4014 /* GRBM_STATUS */ 4015 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 4016 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 4017 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 4018 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 4019 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 4020 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 4021 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) { 4022 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4023 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 4024 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4025 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1); 4026 } 4027 4028 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 4029 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4030 GRBM_SOFT_RESET, SOFT_RESET_CP, 1); 4031 } 4032 4033 /* GRBM_STATUS2 */ 4034 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 4035 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 4036 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 4037 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 4038 4039 4040 if (grbm_soft_reset) { 4041 /* stop the rlc */ 4042 adev->gfx.rlc.funcs->stop(adev); 4043 4044 if (adev->asic_type != CHIP_ARCTURUS) 4045 /* Disable GFX parsing/prefetching */ 4046 gfx_v9_0_cp_gfx_enable(adev, false); 4047 4048 /* Disable MEC parsing/prefetching */ 4049 gfx_v9_0_cp_compute_enable(adev, false); 4050 4051 if (grbm_soft_reset) { 4052 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 4053 tmp |= grbm_soft_reset; 4054 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 4055 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 4056 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 4057 4058 udelay(50); 4059 4060 tmp &= ~grbm_soft_reset; 4061 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 4062 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 4063 } 4064 4065 /* Wait a little for things to settle down */ 4066 udelay(50); 4067 } 4068 return 0; 4069 } 4070 4071 static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev) 4072 { 4073 signed long r, cnt = 0; 4074 unsigned long flags; 4075 uint32_t seq; 4076 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4077 struct amdgpu_ring *ring = &kiq->ring; 4078 4079 BUG_ON(!ring->funcs->emit_rreg); 4080 4081 spin_lock_irqsave(&kiq->ring_lock, flags); 4082 amdgpu_ring_alloc(ring, 32); 4083 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4084 amdgpu_ring_write(ring, 9 | /* src: register*/ 4085 (5 << 8) | /* dst: memory */ 4086 (1 << 16) | /* count sel */ 4087 (1 << 20)); /* write confirm */ 4088 amdgpu_ring_write(ring, 0); 4089 amdgpu_ring_write(ring, 0); 4090 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4091 kiq->reg_val_offs * 4)); 4092 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4093 kiq->reg_val_offs * 4)); 4094 amdgpu_fence_emit_polling(ring, &seq); 4095 amdgpu_ring_commit(ring); 4096 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4097 4098 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 4099 4100 /* don't wait anymore for gpu reset case because this way may 4101 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 4102 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 4103 * never return if we keep waiting in virt_kiq_rreg, which cause 4104 * gpu_recover() hang there. 4105 * 4106 * also don't wait anymore for IRQ context 4107 * */ 4108 if (r < 1 && (adev->in_gpu_reset || in_interrupt())) 4109 goto failed_kiq_read; 4110 4111 might_sleep(); 4112 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 4113 drm_msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 4114 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 4115 } 4116 4117 if (cnt > MAX_KIQ_REG_TRY) 4118 goto failed_kiq_read; 4119 4120 return (uint64_t)adev->wb.wb[kiq->reg_val_offs] | 4121 (uint64_t)adev->wb.wb[kiq->reg_val_offs + 1 ] << 32ULL; 4122 4123 failed_kiq_read: 4124 pr_err("failed to read gpu clock\n"); 4125 return ~0; 4126 } 4127 4128 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4129 { 4130 uint64_t clock; 4131 4132 amdgpu_gfx_off_ctrl(adev, false); 4133 mutex_lock(&adev->gfx.gpu_clock_mutex); 4134 if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) { 4135 clock = gfx_v9_0_kiq_read_clock(adev); 4136 } else { 4137 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4138 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 4139 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4140 } 4141 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4142 amdgpu_gfx_off_ctrl(adev, true); 4143 return clock; 4144 } 4145 4146 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4147 uint32_t vmid, 4148 uint32_t gds_base, uint32_t gds_size, 4149 uint32_t gws_base, uint32_t gws_size, 4150 uint32_t oa_base, uint32_t oa_size) 4151 { 4152 struct amdgpu_device *adev = ring->adev; 4153 4154 /* GDS Base */ 4155 gfx_v9_0_write_data_to_reg(ring, 0, false, 4156 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 4157 gds_base); 4158 4159 /* GDS Size */ 4160 gfx_v9_0_write_data_to_reg(ring, 0, false, 4161 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 4162 gds_size); 4163 4164 /* GWS */ 4165 gfx_v9_0_write_data_to_reg(ring, 0, false, 4166 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 4167 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4168 4169 /* OA */ 4170 gfx_v9_0_write_data_to_reg(ring, 0, false, 4171 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 4172 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4173 } 4174 4175 static const u32 vgpr_init_compute_shader[] = 4176 { 4177 0xb07c0000, 0xbe8000ff, 4178 0x000000f8, 0xbf110800, 4179 0x7e000280, 0x7e020280, 4180 0x7e040280, 0x7e060280, 4181 0x7e080280, 0x7e0a0280, 4182 0x7e0c0280, 0x7e0e0280, 4183 0x80808800, 0xbe803200, 4184 0xbf84fff5, 0xbf9c0000, 4185 0xd28c0001, 0x0001007f, 4186 0xd28d0001, 0x0002027e, 4187 0x10020288, 0xb8810904, 4188 0xb7814000, 0xd1196a01, 4189 0x00000301, 0xbe800087, 4190 0xbefc00c1, 0xd89c4000, 4191 0x00020201, 0xd89cc080, 4192 0x00040401, 0x320202ff, 4193 0x00000800, 0x80808100, 4194 0xbf84fff8, 0x7e020280, 4195 0xbf810000, 0x00000000, 4196 }; 4197 4198 static const u32 sgpr_init_compute_shader[] = 4199 { 4200 0xb07c0000, 0xbe8000ff, 4201 0x0000005f, 0xbee50080, 4202 0xbe812c65, 0xbe822c65, 4203 0xbe832c65, 0xbe842c65, 4204 0xbe852c65, 0xb77c0005, 4205 0x80808500, 0xbf84fff8, 4206 0xbe800080, 0xbf810000, 4207 }; 4208 4209 static const u32 vgpr_init_compute_shader_arcturus[] = { 4210 0xd3d94000, 0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 4211 0xd3d94003, 0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 4212 0xd3d94006, 0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 4213 0xd3d94009, 0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 4214 0xd3d9400c, 0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 4215 0xd3d9400f, 0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 4216 0xd3d94012, 0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 4217 0xd3d94015, 0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 4218 0xd3d94018, 0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 4219 0xd3d9401b, 0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 4220 0xd3d9401e, 0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 4221 0xd3d94021, 0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 4222 0xd3d94024, 0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 4223 0xd3d94027, 0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 4224 0xd3d9402a, 0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 4225 0xd3d9402d, 0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 4226 0xd3d94030, 0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 4227 0xd3d94033, 0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 4228 0xd3d94036, 0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 4229 0xd3d94039, 0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 4230 0xd3d9403c, 0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 4231 0xd3d9403f, 0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 4232 0xd3d94042, 0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 4233 0xd3d94045, 0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 4234 0xd3d94048, 0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 4235 0xd3d9404b, 0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 4236 0xd3d9404e, 0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 4237 0xd3d94051, 0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 4238 0xd3d94054, 0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 4239 0xd3d94057, 0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 4240 0xd3d9405a, 0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 4241 0xd3d9405d, 0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 4242 0xd3d94060, 0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 4243 0xd3d94063, 0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 4244 0xd3d94066, 0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 4245 0xd3d94069, 0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 4246 0xd3d9406c, 0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 4247 0xd3d9406f, 0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 4248 0xd3d94072, 0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 4249 0xd3d94075, 0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 4250 0xd3d94078, 0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 4251 0xd3d9407b, 0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 4252 0xd3d9407e, 0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 4253 0xd3d94081, 0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 4254 0xd3d94084, 0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 4255 0xd3d94087, 0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 4256 0xd3d9408a, 0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 4257 0xd3d9408d, 0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 4258 0xd3d94090, 0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 4259 0xd3d94093, 0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 4260 0xd3d94096, 0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 4261 0xd3d94099, 0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 4262 0xd3d9409c, 0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 4263 0xd3d9409f, 0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 4264 0xd3d940a2, 0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 4265 0xd3d940a5, 0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 4266 0xd3d940a8, 0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 4267 0xd3d940ab, 0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 4268 0xd3d940ae, 0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 4269 0xd3d940b1, 0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 4270 0xd3d940b4, 0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 4271 0xd3d940b7, 0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 4272 0xd3d940ba, 0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 4273 0xd3d940bd, 0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 4274 0xd3d940c0, 0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 4275 0xd3d940c3, 0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 4276 0xd3d940c6, 0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 4277 0xd3d940c9, 0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 4278 0xd3d940cc, 0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 4279 0xd3d940cf, 0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 4280 0xd3d940d2, 0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 4281 0xd3d940d5, 0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 4282 0xd3d940d8, 0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 4283 0xd3d940db, 0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 4284 0xd3d940de, 0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 4285 0xd3d940e1, 0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 4286 0xd3d940e4, 0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 4287 0xd3d940e7, 0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 4288 0xd3d940ea, 0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 4289 0xd3d940ed, 0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 4290 0xd3d940f0, 0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 4291 0xd3d940f3, 0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 4292 0xd3d940f6, 0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 4293 0xd3d940f9, 0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 4294 0xd3d940fc, 0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 4295 0xd3d940ff, 0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 4296 0x7e000280, 0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 4297 0x7e0c0280, 0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 4298 0xd28c0001, 0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xb88b0904, 4299 0xb78b4000, 0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 4300 0x00020201, 0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 4301 0xbf84fff8, 0xbf810000, 4302 }; 4303 4304 /* When below register arrays changed, please update gpr_reg_size, 4305 and sec_ded_counter_reg_size in function gfx_v9_0_do_edc_gpr_workarounds, 4306 to cover all gfx9 ASICs */ 4307 static const struct soc15_reg_entry vgpr_init_regs[] = { 4308 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4309 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4310 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4311 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4312 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x3f }, 4313 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4314 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4315 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4316 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4317 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4318 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4319 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4320 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4321 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4322 }; 4323 4324 static const struct soc15_reg_entry vgpr_init_regs_arcturus[] = { 4325 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4326 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4327 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 4 }, 4328 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4329 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0xbf }, 4330 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x400000 }, /* 64KB LDS */ 4331 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff }, 4332 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff }, 4333 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff }, 4334 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff }, 4335 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff }, 4336 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff }, 4337 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff }, 4338 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff }, 4339 }; 4340 4341 static const struct soc15_reg_entry sgpr1_init_regs[] = { 4342 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4343 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4344 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4345 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4346 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4347 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4348 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x000000ff }, 4349 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x000000ff }, 4350 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x000000ff }, 4351 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x000000ff }, 4352 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x000000ff }, 4353 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x000000ff }, 4354 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x000000ff }, 4355 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x000000ff }, 4356 }; 4357 4358 static const struct soc15_reg_entry sgpr2_init_regs[] = { 4359 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_RESOURCE_LIMITS), 0x0000000 }, 4360 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_X), 0x40 }, 4361 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Y), 8 }, 4362 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_NUM_THREAD_Z), 1 }, 4363 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC1), 0x240 }, /* (80 GPRS) */ 4364 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_PGM_RSRC2), 0x0 }, 4365 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE0), 0x0000ff00 }, 4366 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE1), 0x0000ff00 }, 4367 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE2), 0x0000ff00 }, 4368 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE3), 0x0000ff00 }, 4369 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE4), 0x0000ff00 }, 4370 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE5), 0x0000ff00 }, 4371 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE6), 0x0000ff00 }, 4372 { SOC15_REG_ENTRY(GC, 0, mmCOMPUTE_STATIC_THREAD_MGMT_SE7), 0x0000ff00 }, 4373 }; 4374 4375 static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = { 4376 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1}, 4377 { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1}, 4378 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1}, 4379 { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1}, 4380 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 0, 1, 1}, 4381 { SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 0, 1, 1}, 4382 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1}, 4383 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1}, 4384 { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1}, 4385 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1}, 4386 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1}, 4387 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1}, 4388 { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1}, 4389 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6}, 4390 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 4, 16}, 4391 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 4, 16}, 4392 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16}, 4393 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16}, 4394 { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16}, 4395 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16}, 4396 { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16}, 4397 { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16}, 4398 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6}, 4399 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, 4400 { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16}, 4401 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1}, 4402 { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1}, 4403 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32}, 4404 { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32}, 4405 { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72}, 4406 { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16}, 4407 { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2}, 4408 { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6}, 4409 }; 4410 4411 static int gfx_v9_0_do_edc_gds_workarounds(struct amdgpu_device *adev) 4412 { 4413 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4414 int i, r; 4415 4416 /* only support when RAS is enabled */ 4417 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4418 return 0; 4419 4420 r = amdgpu_ring_alloc(ring, 7); 4421 if (r) { 4422 DRM_ERROR("amdgpu: GDS workarounds failed to lock ring %s (%d).\n", 4423 ring->name, r); 4424 return r; 4425 } 4426 4427 WREG32_SOC15(GC, 0, mmGDS_VMID0_BASE, 0x00000000); 4428 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, adev->gds.gds_size); 4429 4430 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 4431 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 4432 PACKET3_DMA_DATA_DST_SEL(1) | 4433 PACKET3_DMA_DATA_SRC_SEL(2) | 4434 PACKET3_DMA_DATA_ENGINE(0))); 4435 amdgpu_ring_write(ring, 0); 4436 amdgpu_ring_write(ring, 0); 4437 amdgpu_ring_write(ring, 0); 4438 amdgpu_ring_write(ring, 0); 4439 amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 4440 adev->gds.gds_size); 4441 4442 amdgpu_ring_commit(ring); 4443 4444 for (i = 0; i < adev->usec_timeout; i++) { 4445 if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring)) 4446 break; 4447 udelay(1); 4448 } 4449 4450 if (i >= adev->usec_timeout) 4451 r = -ETIMEDOUT; 4452 4453 WREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE, 0x00000000); 4454 4455 return r; 4456 } 4457 4458 static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) 4459 { 4460 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; 4461 struct amdgpu_ib ib; 4462 struct dma_fence *f = NULL; 4463 int r, i; 4464 unsigned total_size, vgpr_offset, sgpr_offset; 4465 u64 gpu_addr; 4466 4467 int compute_dim_x = adev->gfx.config.max_shader_engines * 4468 adev->gfx.config.max_cu_per_sh * 4469 adev->gfx.config.max_sh_per_se; 4470 int sgpr_work_group_size = 5; 4471 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6; 4472 int vgpr_init_shader_size; 4473 const u32 *vgpr_init_shader_ptr; 4474 const struct soc15_reg_entry *vgpr_init_regs_ptr; 4475 4476 /* only support when RAS is enabled */ 4477 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 4478 return 0; 4479 4480 /* bail if the compute ring is not ready */ 4481 if (!ring->sched.ready) 4482 return 0; 4483 4484 if (adev->asic_type == CHIP_ARCTURUS) { 4485 vgpr_init_shader_ptr = vgpr_init_compute_shader_arcturus; 4486 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader_arcturus); 4487 vgpr_init_regs_ptr = vgpr_init_regs_arcturus; 4488 } else { 4489 vgpr_init_shader_ptr = vgpr_init_compute_shader; 4490 vgpr_init_shader_size = sizeof(vgpr_init_compute_shader); 4491 vgpr_init_regs_ptr = vgpr_init_regs; 4492 } 4493 4494 total_size = 4495 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* VGPRS */ 4496 total_size += 4497 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS1 */ 4498 total_size += 4499 (gpr_reg_size * 3 + 4 + 5 + 2) * 4; /* SGPRS2 */ 4500 total_size = roundup2(total_size, 256); 4501 vgpr_offset = total_size; 4502 total_size += roundup2(vgpr_init_shader_size, 256); 4503 sgpr_offset = total_size; 4504 total_size += sizeof(sgpr_init_compute_shader); 4505 4506 /* allocate an indirect buffer to put the commands in */ 4507 memset(&ib, 0, sizeof(ib)); 4508 r = amdgpu_ib_get(adev, NULL, total_size, &ib); 4509 if (r) { 4510 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r); 4511 return r; 4512 } 4513 4514 /* load the compute shaders */ 4515 for (i = 0; i < vgpr_init_shader_size/sizeof(u32); i++) 4516 ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_shader_ptr[i]; 4517 4518 for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader); i++) 4519 ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; 4520 4521 /* init the ib length to 0 */ 4522 ib.length_dw = 0; 4523 4524 /* VGPR */ 4525 /* write the register state for the compute dispatch */ 4526 for (i = 0; i < gpr_reg_size; i++) { 4527 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4528 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(vgpr_init_regs_ptr[i]) 4529 - PACKET3_SET_SH_REG_START; 4530 ib.ptr[ib.length_dw++] = vgpr_init_regs_ptr[i].reg_value; 4531 } 4532 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4533 gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; 4534 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4535 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4536 - PACKET3_SET_SH_REG_START; 4537 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4538 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4539 4540 /* write dispatch packet */ 4541 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4542 ib.ptr[ib.length_dw++] = compute_dim_x * 2; /* x */ 4543 ib.ptr[ib.length_dw++] = 1; /* y */ 4544 ib.ptr[ib.length_dw++] = 1; /* z */ 4545 ib.ptr[ib.length_dw++] = 4546 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4547 4548 /* write CS partial flush packet */ 4549 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4550 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4551 4552 /* SGPR1 */ 4553 /* write the register state for the compute dispatch */ 4554 for (i = 0; i < gpr_reg_size; i++) { 4555 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4556 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr1_init_regs[i]) 4557 - PACKET3_SET_SH_REG_START; 4558 ib.ptr[ib.length_dw++] = sgpr1_init_regs[i].reg_value; 4559 } 4560 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4561 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4562 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4563 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4564 - PACKET3_SET_SH_REG_START; 4565 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4566 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4567 4568 /* write dispatch packet */ 4569 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4570 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4571 ib.ptr[ib.length_dw++] = 1; /* y */ 4572 ib.ptr[ib.length_dw++] = 1; /* z */ 4573 ib.ptr[ib.length_dw++] = 4574 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4575 4576 /* write CS partial flush packet */ 4577 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4578 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4579 4580 /* SGPR2 */ 4581 /* write the register state for the compute dispatch */ 4582 for (i = 0; i < gpr_reg_size; i++) { 4583 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); 4584 ib.ptr[ib.length_dw++] = SOC15_REG_ENTRY_OFFSET(sgpr2_init_regs[i]) 4585 - PACKET3_SET_SH_REG_START; 4586 ib.ptr[ib.length_dw++] = sgpr2_init_regs[i].reg_value; 4587 } 4588 /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ 4589 gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; 4590 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); 4591 ib.ptr[ib.length_dw++] = SOC15_REG_OFFSET(GC, 0, mmCOMPUTE_PGM_LO) 4592 - PACKET3_SET_SH_REG_START; 4593 ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr); 4594 ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr); 4595 4596 /* write dispatch packet */ 4597 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); 4598 ib.ptr[ib.length_dw++] = compute_dim_x / 2 * sgpr_work_group_size; /* x */ 4599 ib.ptr[ib.length_dw++] = 1; /* y */ 4600 ib.ptr[ib.length_dw++] = 1; /* z */ 4601 ib.ptr[ib.length_dw++] = 4602 REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1); 4603 4604 /* write CS partial flush packet */ 4605 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0); 4606 ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4); 4607 4608 /* shedule the ib on the ring */ 4609 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 4610 if (r) { 4611 DRM_ERROR("amdgpu: ib submit failed (%d).\n", r); 4612 goto fail; 4613 } 4614 4615 /* wait for the GPU to finish processing the IB */ 4616 r = dma_fence_wait(f, false); 4617 if (r) { 4618 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r); 4619 goto fail; 4620 } 4621 4622 fail: 4623 amdgpu_ib_free(adev, &ib, NULL); 4624 dma_fence_put(f); 4625 4626 return r; 4627 } 4628 4629 static int gfx_v9_0_early_init(void *handle) 4630 { 4631 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4632 4633 if (adev->asic_type == CHIP_ARCTURUS) 4634 adev->gfx.num_gfx_rings = 0; 4635 else 4636 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS; 4637 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 4638 gfx_v9_0_set_kiq_pm4_funcs(adev); 4639 gfx_v9_0_set_ring_funcs(adev); 4640 gfx_v9_0_set_irq_funcs(adev); 4641 gfx_v9_0_set_gds_init(adev); 4642 gfx_v9_0_set_rlc_funcs(adev); 4643 4644 return 0; 4645 } 4646 4647 static int gfx_v9_0_ecc_late_init(void *handle) 4648 { 4649 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4650 int r; 4651 4652 /* 4653 * Temp workaround to fix the issue that CP firmware fails to 4654 * update read pointer when CPDMA is writing clearing operation 4655 * to GDS in suspend/resume sequence on several cards. So just 4656 * limit this operation in cold boot sequence. 4657 */ 4658 if (!adev->in_suspend) { 4659 r = gfx_v9_0_do_edc_gds_workarounds(adev); 4660 if (r) 4661 return r; 4662 } 4663 4664 /* requires IBs so do in late init after IB pool is initialized */ 4665 r = gfx_v9_0_do_edc_gpr_workarounds(adev); 4666 if (r) 4667 return r; 4668 4669 if (adev->gfx.funcs && 4670 adev->gfx.funcs->reset_ras_error_count) 4671 adev->gfx.funcs->reset_ras_error_count(adev); 4672 4673 r = amdgpu_gfx_ras_late_init(adev); 4674 if (r) 4675 return r; 4676 4677 return 0; 4678 } 4679 4680 static int gfx_v9_0_late_init(void *handle) 4681 { 4682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4683 int r; 4684 4685 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4686 if (r) 4687 return r; 4688 4689 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4690 if (r) 4691 return r; 4692 4693 r = gfx_v9_0_ecc_late_init(handle); 4694 if (r) 4695 return r; 4696 4697 return 0; 4698 } 4699 4700 static bool gfx_v9_0_is_rlc_enabled(struct amdgpu_device *adev) 4701 { 4702 uint32_t rlc_setting; 4703 4704 /* if RLC is not enabled, do nothing */ 4705 rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4706 if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK)) 4707 return false; 4708 4709 return true; 4710 } 4711 4712 static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev) 4713 { 4714 uint32_t data; 4715 unsigned i; 4716 4717 data = RLC_SAFE_MODE__CMD_MASK; 4718 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4719 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4720 4721 /* wait for RLC_SAFE_MODE */ 4722 for (i = 0; i < adev->usec_timeout; i++) { 4723 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4724 break; 4725 udelay(1); 4726 } 4727 } 4728 4729 static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev) 4730 { 4731 uint32_t data; 4732 4733 data = RLC_SAFE_MODE__CMD_MASK; 4734 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4735 } 4736 4737 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev, 4738 bool enable) 4739 { 4740 amdgpu_gfx_rlc_enter_safe_mode(adev); 4741 4742 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) { 4743 gfx_v9_0_enable_gfx_cg_power_gating(adev, true); 4744 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4745 gfx_v9_0_enable_gfx_pipeline_powergating(adev, true); 4746 } else { 4747 gfx_v9_0_enable_gfx_cg_power_gating(adev, false); 4748 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE) 4749 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false); 4750 } 4751 4752 amdgpu_gfx_rlc_exit_safe_mode(adev); 4753 } 4754 4755 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev, 4756 bool enable) 4757 { 4758 /* TODO: double check if we need to perform under safe mode */ 4759 /* gfx_v9_0_enter_rlc_safe_mode(adev); */ 4760 4761 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable) 4762 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true); 4763 else 4764 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false); 4765 4766 if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable) 4767 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true); 4768 else 4769 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false); 4770 4771 /* gfx_v9_0_exit_rlc_safe_mode(adev); */ 4772 } 4773 4774 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4775 bool enable) 4776 { 4777 uint32_t data, def; 4778 4779 amdgpu_gfx_rlc_enter_safe_mode(adev); 4780 4781 /* It is disabled by HW by default */ 4782 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4783 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4784 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4785 4786 if (adev->asic_type != CHIP_VEGA12) 4787 data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4788 4789 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4790 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4791 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4792 4793 /* only for Vega10 & Raven1 */ 4794 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4795 4796 if (def != data) 4797 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4798 4799 /* MGLS is a global flag to control all MGLS in GFX */ 4800 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4801 /* 2 - RLC memory Light sleep */ 4802 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4803 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4804 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4805 if (def != data) 4806 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4807 } 4808 /* 3 - CP memory Light sleep */ 4809 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4810 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4811 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4812 if (def != data) 4813 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4814 } 4815 } 4816 } else { 4817 /* 1 - MGCG_OVERRIDE */ 4818 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4819 4820 if (adev->asic_type != CHIP_VEGA12) 4821 data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK; 4822 4823 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4824 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4825 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4826 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4827 4828 if (def != data) 4829 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4830 4831 /* 2 - disable MGLS in RLC */ 4832 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4833 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4834 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4835 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4836 } 4837 4838 /* 3 - disable MGLS in CP */ 4839 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4840 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4841 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4842 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4843 } 4844 } 4845 4846 amdgpu_gfx_rlc_exit_safe_mode(adev); 4847 } 4848 4849 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev, 4850 bool enable) 4851 { 4852 uint32_t data, def; 4853 4854 if (adev->asic_type == CHIP_ARCTURUS) 4855 return; 4856 4857 amdgpu_gfx_rlc_enter_safe_mode(adev); 4858 4859 /* Enable 3D CGCG/CGLS */ 4860 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 4861 /* write cmd to clear cgcg/cgls ov */ 4862 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4863 /* unset CGCG override */ 4864 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4865 /* update CGCG and CGLS override bits */ 4866 if (def != data) 4867 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4868 4869 /* enable 3Dcgcg FSM(0x0000363f) */ 4870 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4871 4872 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4873 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4874 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4875 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4876 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4877 if (def != data) 4878 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4879 4880 /* set IDLE_POLL_COUNT(0x00900100) */ 4881 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4882 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4883 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4884 if (def != data) 4885 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4886 } else { 4887 /* Disable CGCG/CGLS */ 4888 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4889 /* disable cgcg, cgls should be disabled */ 4890 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4891 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4892 /* disable cgcg and cgls in FSM */ 4893 if (def != data) 4894 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4895 } 4896 4897 amdgpu_gfx_rlc_exit_safe_mode(adev); 4898 } 4899 4900 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4901 bool enable) 4902 { 4903 uint32_t def, data; 4904 4905 amdgpu_gfx_rlc_enter_safe_mode(adev); 4906 4907 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4908 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4909 /* unset CGCG override */ 4910 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4911 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4912 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4913 else 4914 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4915 /* update CGCG and CGLS override bits */ 4916 if (def != data) 4917 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4918 4919 /* enable cgcg FSM(0x0000363F) */ 4920 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4921 4922 if (adev->asic_type == CHIP_ARCTURUS) 4923 data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4924 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4925 else 4926 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4927 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4928 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4929 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4930 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4931 if (def != data) 4932 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4933 4934 /* set IDLE_POLL_COUNT(0x00900100) */ 4935 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4936 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4937 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4938 if (def != data) 4939 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4940 } else { 4941 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4942 /* reset CGCG/CGLS bits */ 4943 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4944 /* disable cgcg and cgls in FSM */ 4945 if (def != data) 4946 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4947 } 4948 4949 amdgpu_gfx_rlc_exit_safe_mode(adev); 4950 } 4951 4952 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4953 bool enable) 4954 { 4955 if (enable) { 4956 /* CGCG/CGLS should be enabled after MGCG/MGLS 4957 * === MGCG + MGLS === 4958 */ 4959 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4960 /* === CGCG /CGLS for GFX 3D Only === */ 4961 gfx_v9_0_update_3d_clock_gating(adev, enable); 4962 /* === CGCG + CGLS === */ 4963 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4964 } else { 4965 /* CGCG/CGLS should be disabled before MGCG/MGLS 4966 * === CGCG + CGLS === 4967 */ 4968 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable); 4969 /* === CGCG /CGLS for GFX 3D Only === */ 4970 gfx_v9_0_update_3d_clock_gating(adev, enable); 4971 /* === MGCG + MGLS === */ 4972 gfx_v9_0_update_medium_grain_clock_gating(adev, enable); 4973 } 4974 return 0; 4975 } 4976 4977 static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 4978 { 4979 u32 data; 4980 4981 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 4982 4983 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4984 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4985 4986 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 4987 } 4988 4989 static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev, 4990 uint32_t offset, 4991 struct soc15_reg_rlcg *entries, int arr_size) 4992 { 4993 int i; 4994 uint32_t reg; 4995 4996 if (!entries) 4997 return false; 4998 4999 for (i = 0; i < arr_size; i++) { 5000 const struct soc15_reg_rlcg *entry; 5001 5002 entry = &entries[i]; 5003 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 5004 if (offset == reg) 5005 return true; 5006 } 5007 5008 return false; 5009 } 5010 5011 static bool gfx_v9_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 5012 { 5013 return gfx_v9_0_check_rlcg_range(adev, offset, 5014 (void *)rlcg_access_gc_9_0, 5015 ARRAY_SIZE(rlcg_access_gc_9_0)); 5016 } 5017 5018 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = { 5019 .is_rlc_enabled = gfx_v9_0_is_rlc_enabled, 5020 .set_safe_mode = gfx_v9_0_set_safe_mode, 5021 .unset_safe_mode = gfx_v9_0_unset_safe_mode, 5022 .init = gfx_v9_0_rlc_init, 5023 .get_csb_size = gfx_v9_0_get_csb_size, 5024 .get_csb_buffer = gfx_v9_0_get_csb_buffer, 5025 .get_cp_table_num = gfx_v9_0_cp_jump_table_num, 5026 .resume = gfx_v9_0_rlc_resume, 5027 .stop = gfx_v9_0_rlc_stop, 5028 .reset = gfx_v9_0_rlc_reset, 5029 .start = gfx_v9_0_rlc_start, 5030 .update_spm_vmid = gfx_v9_0_update_spm_vmid, 5031 .rlcg_wreg = gfx_v9_0_rlcg_wreg, 5032 .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range, 5033 }; 5034 5035 static int gfx_v9_0_set_powergating_state(void *handle, 5036 enum amd_powergating_state state) 5037 { 5038 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5039 bool enable = (state == AMD_PG_STATE_GATE); 5040 5041 switch (adev->asic_type) { 5042 case CHIP_RAVEN: 5043 case CHIP_RENOIR: 5044 if (!enable) 5045 amdgpu_gfx_off_ctrl(adev, false); 5046 5047 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) { 5048 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true); 5049 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true); 5050 } else { 5051 gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false); 5052 gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false); 5053 } 5054 5055 if (adev->pg_flags & AMD_PG_SUPPORT_CP) 5056 gfx_v9_0_enable_cp_power_gating(adev, true); 5057 else 5058 gfx_v9_0_enable_cp_power_gating(adev, false); 5059 5060 /* update gfx cgpg state */ 5061 gfx_v9_0_update_gfx_cg_power_gating(adev, enable); 5062 5063 /* update mgcg state */ 5064 gfx_v9_0_update_gfx_mg_power_gating(adev, enable); 5065 5066 if (enable) 5067 amdgpu_gfx_off_ctrl(adev, true); 5068 break; 5069 case CHIP_VEGA12: 5070 amdgpu_gfx_off_ctrl(adev, enable); 5071 break; 5072 default: 5073 break; 5074 } 5075 5076 return 0; 5077 } 5078 5079 static int gfx_v9_0_set_clockgating_state(void *handle, 5080 enum amd_clockgating_state state) 5081 { 5082 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5083 5084 if (amdgpu_sriov_vf(adev)) 5085 return 0; 5086 5087 switch (adev->asic_type) { 5088 case CHIP_VEGA10: 5089 case CHIP_VEGA12: 5090 case CHIP_VEGA20: 5091 case CHIP_RAVEN: 5092 case CHIP_ARCTURUS: 5093 case CHIP_RENOIR: 5094 gfx_v9_0_update_gfx_clock_gating(adev, 5095 state == AMD_CG_STATE_GATE); 5096 break; 5097 default: 5098 break; 5099 } 5100 return 0; 5101 } 5102 5103 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags) 5104 { 5105 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 5106 int data; 5107 5108 if (amdgpu_sriov_vf(adev)) 5109 *flags = 0; 5110 5111 /* AMD_CG_SUPPORT_GFX_MGCG */ 5112 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 5113 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 5114 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 5115 5116 /* AMD_CG_SUPPORT_GFX_CGCG */ 5117 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 5118 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 5119 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 5120 5121 /* AMD_CG_SUPPORT_GFX_CGLS */ 5122 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 5123 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 5124 5125 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 5126 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 5127 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 5128 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 5129 5130 /* AMD_CG_SUPPORT_GFX_CP_LS */ 5131 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 5132 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 5133 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 5134 5135 if (adev->asic_type != CHIP_ARCTURUS) { 5136 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 5137 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 5138 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 5139 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 5140 5141 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 5142 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 5143 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 5144 } 5145 } 5146 5147 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 5148 { 5149 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/ 5150 } 5151 5152 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 5153 { 5154 struct amdgpu_device *adev = ring->adev; 5155 u64 wptr; 5156 5157 /* XXX check if swapping is necessary on BE */ 5158 if (ring->use_doorbell) { 5159 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 5160 } else { 5161 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 5162 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 5163 } 5164 5165 return wptr; 5166 } 5167 5168 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 5169 { 5170 struct amdgpu_device *adev = ring->adev; 5171 5172 if (ring->use_doorbell) { 5173 /* XXX check if swapping is necessary on BE */ 5174 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 5175 WDOORBELL64(ring->doorbell_index, ring->wptr); 5176 } else { 5177 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 5178 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 5179 } 5180 } 5181 5182 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 5183 { 5184 struct amdgpu_device *adev = ring->adev; 5185 u32 ref_and_mask, reg_mem_engine; 5186 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 5187 5188 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 5189 switch (ring->me) { 5190 case 1: 5191 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 5192 break; 5193 case 2: 5194 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 5195 break; 5196 default: 5197 return; 5198 } 5199 reg_mem_engine = 0; 5200 } else { 5201 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 5202 reg_mem_engine = 1; /* pfp */ 5203 } 5204 5205 gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 5206 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 5207 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 5208 ref_and_mask, ref_and_mask, 0x20); 5209 } 5210 5211 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 5212 struct amdgpu_job *job, 5213 struct amdgpu_ib *ib, 5214 uint32_t flags) 5215 { 5216 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5217 u32 header, control = 0; 5218 5219 if (ib->flags & AMDGPU_IB_FLAG_CE) 5220 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 5221 else 5222 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 5223 5224 control |= ib->length_dw | (vmid << 24); 5225 5226 if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 5227 control |= INDIRECT_BUFFER_PRE_ENB(1); 5228 5229 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 5230 gfx_v9_0_ring_emit_de_meta(ring); 5231 } 5232 5233 amdgpu_ring_write(ring, header); 5234 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5235 amdgpu_ring_write(ring, 5236 #ifdef __BIG_ENDIAN 5237 (2 << 0) | 5238 #endif 5239 lower_32_bits(ib->gpu_addr)); 5240 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5241 amdgpu_ring_write(ring, control); 5242 } 5243 5244 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 5245 struct amdgpu_job *job, 5246 struct amdgpu_ib *ib, 5247 uint32_t flags) 5248 { 5249 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 5250 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 5251 5252 /* Currently, there is a high possibility to get wave ID mismatch 5253 * between ME and GDS, leading to a hw deadlock, because ME generates 5254 * different wave IDs than the GDS expects. This situation happens 5255 * randomly when at least 5 compute pipes use GDS ordered append. 5256 * The wave IDs generated by ME are also wrong after suspend/resume. 5257 * Those are probably bugs somewhere else in the kernel driver. 5258 * 5259 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 5260 * GDS to 0 for this ring (me/pipe). 5261 */ 5262 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 5263 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 5264 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 5265 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 5266 } 5267 5268 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 5269 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 5270 amdgpu_ring_write(ring, 5271 #ifdef __BIG_ENDIAN 5272 (2 << 0) | 5273 #endif 5274 lower_32_bits(ib->gpu_addr)); 5275 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 5276 amdgpu_ring_write(ring, control); 5277 } 5278 5279 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 5280 u64 seq, unsigned flags) 5281 { 5282 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 5283 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 5284 bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY; 5285 5286 /* RELEASE_MEM - flush caches, send int */ 5287 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 5288 amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN | 5289 EOP_TC_NC_ACTION_EN) : 5290 (EOP_TCL1_ACTION_EN | 5291 EOP_TC_ACTION_EN | 5292 EOP_TC_WB_ACTION_EN | 5293 EOP_TC_MD_ACTION_EN)) | 5294 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 5295 EVENT_INDEX(5))); 5296 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); 5297 5298 /* 5299 * the address should be Qword aligned if 64bit write, Dword 5300 * aligned if only send 32bit data low (discard data high) 5301 */ 5302 if (write64bit) 5303 BUG_ON(addr & 0x7); 5304 else 5305 BUG_ON(addr & 0x3); 5306 amdgpu_ring_write(ring, lower_32_bits(addr)); 5307 amdgpu_ring_write(ring, upper_32_bits(addr)); 5308 amdgpu_ring_write(ring, lower_32_bits(seq)); 5309 amdgpu_ring_write(ring, upper_32_bits(seq)); 5310 amdgpu_ring_write(ring, 0); 5311 } 5312 5313 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 5314 { 5315 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5316 uint32_t seq = ring->fence_drv.sync_seq; 5317 uint64_t addr = ring->fence_drv.gpu_addr; 5318 5319 gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0, 5320 lower_32_bits(addr), upper_32_bits(addr), 5321 seq, 0xffffffff, 4); 5322 } 5323 5324 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 5325 unsigned vmid, uint64_t pd_addr) 5326 { 5327 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 5328 5329 /* compute doesn't have PFP */ 5330 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 5331 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 5332 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 5333 amdgpu_ring_write(ring, 0x0); 5334 } 5335 } 5336 5337 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 5338 { 5339 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */ 5340 } 5341 5342 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 5343 { 5344 u64 wptr; 5345 5346 /* XXX check if swapping is necessary on BE */ 5347 if (ring->use_doorbell) 5348 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 5349 else 5350 BUG(); 5351 return wptr; 5352 } 5353 5354 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 5355 { 5356 struct amdgpu_device *adev = ring->adev; 5357 5358 /* XXX check if swapping is necessary on BE */ 5359 if (ring->use_doorbell) { 5360 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); 5361 WDOORBELL64(ring->doorbell_index, ring->wptr); 5362 } else{ 5363 BUG(); /* only DOORBELL method supported on gfx9 now */ 5364 } 5365 } 5366 5367 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 5368 u64 seq, unsigned int flags) 5369 { 5370 struct amdgpu_device *adev = ring->adev; 5371 5372 /* we only allocate 32bit for each seq wb address */ 5373 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 5374 5375 /* write fence seq to the "addr" */ 5376 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5377 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5378 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 5379 amdgpu_ring_write(ring, lower_32_bits(addr)); 5380 amdgpu_ring_write(ring, upper_32_bits(addr)); 5381 amdgpu_ring_write(ring, lower_32_bits(seq)); 5382 5383 if (flags & AMDGPU_FENCE_FLAG_INT) { 5384 /* set register to trigger INT */ 5385 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5386 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5387 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 5388 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 5389 amdgpu_ring_write(ring, 0); 5390 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 5391 } 5392 } 5393 5394 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring) 5395 { 5396 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 5397 amdgpu_ring_write(ring, 0); 5398 } 5399 5400 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring) 5401 { 5402 struct v9_ce_ib_state ce_payload = {0}; 5403 uint64_t csa_addr; 5404 int cnt; 5405 5406 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 5407 csa_addr = amdgpu_csa_vaddr(ring->adev); 5408 5409 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5410 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 5411 WRITE_DATA_DST_SEL(8) | 5412 WR_CONFIRM) | 5413 WRITE_DATA_CACHE_POLICY(0)); 5414 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 5415 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload))); 5416 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2); 5417 } 5418 5419 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring) 5420 { 5421 struct v9_de_ib_state de_payload = {0}; 5422 uint64_t csa_addr, gds_addr; 5423 int cnt; 5424 5425 csa_addr = amdgpu_csa_vaddr(ring->adev); 5426 gds_addr = csa_addr + 4096; 5427 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 5428 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 5429 5430 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 5431 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 5432 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 5433 WRITE_DATA_DST_SEL(8) | 5434 WR_CONFIRM) | 5435 WRITE_DATA_CACHE_POLICY(0)); 5436 amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 5437 amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload))); 5438 amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2); 5439 } 5440 5441 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 5442 { 5443 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 5444 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 5445 } 5446 5447 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 5448 { 5449 uint32_t dw2 = 0; 5450 5451 if (amdgpu_sriov_vf(ring->adev)) 5452 gfx_v9_0_ring_emit_ce_meta(ring); 5453 5454 gfx_v9_0_ring_emit_tmz(ring, true); 5455 5456 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 5457 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 5458 /* set load_global_config & load_global_uconfig */ 5459 dw2 |= 0x8001; 5460 /* set load_cs_sh_regs */ 5461 dw2 |= 0x01000000; 5462 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 5463 dw2 |= 0x10002; 5464 5465 /* set load_ce_ram if preamble presented */ 5466 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 5467 dw2 |= 0x10000000; 5468 } else { 5469 /* still load_ce_ram if this is the first time preamble presented 5470 * although there is no context switch happens. 5471 */ 5472 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 5473 dw2 |= 0x10000000; 5474 } 5475 5476 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 5477 amdgpu_ring_write(ring, dw2); 5478 amdgpu_ring_write(ring, 0); 5479 } 5480 5481 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 5482 { 5483 unsigned ret; 5484 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 5485 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 5486 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 5487 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 5488 ret = ring->wptr & ring->buf_mask; 5489 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 5490 return ret; 5491 } 5492 5493 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 5494 { 5495 unsigned cur; 5496 BUG_ON(offset > ring->buf_mask); 5497 BUG_ON(ring->ring[offset] != 0x55aa55aa); 5498 5499 cur = (ring->wptr & ring->buf_mask) - 1; 5500 if (likely(cur > offset)) 5501 ring->ring[offset] = cur - offset; 5502 else 5503 ring->ring[offset] = (ring->ring_size>>2) - offset + cur; 5504 } 5505 5506 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 5507 { 5508 struct amdgpu_device *adev = ring->adev; 5509 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 5510 5511 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 5512 amdgpu_ring_write(ring, 0 | /* src: register*/ 5513 (5 << 8) | /* dst: memory */ 5514 (1 << 20)); /* write confirm */ 5515 amdgpu_ring_write(ring, reg); 5516 amdgpu_ring_write(ring, 0); 5517 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 5518 kiq->reg_val_offs * 4)); 5519 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 5520 kiq->reg_val_offs * 4)); 5521 } 5522 5523 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 5524 uint32_t val) 5525 { 5526 uint32_t cmd = 0; 5527 5528 switch (ring->funcs->type) { 5529 case AMDGPU_RING_TYPE_GFX: 5530 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 5531 break; 5532 case AMDGPU_RING_TYPE_KIQ: 5533 cmd = (1 << 16); /* no inc addr */ 5534 break; 5535 default: 5536 cmd = WR_CONFIRM; 5537 break; 5538 } 5539 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5540 amdgpu_ring_write(ring, cmd); 5541 amdgpu_ring_write(ring, reg); 5542 amdgpu_ring_write(ring, 0); 5543 amdgpu_ring_write(ring, val); 5544 } 5545 5546 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 5547 uint32_t val, uint32_t mask) 5548 { 5549 gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 5550 } 5551 5552 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 5553 uint32_t reg0, uint32_t reg1, 5554 uint32_t ref, uint32_t mask) 5555 { 5556 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 5557 struct amdgpu_device *adev = ring->adev; 5558 bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ? 5559 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait; 5560 5561 if (fw_version_ok) 5562 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 5563 ref, mask, 0x20); 5564 else 5565 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 5566 ref, mask); 5567 } 5568 5569 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) 5570 { 5571 struct amdgpu_device *adev = ring->adev; 5572 uint32_t value = 0; 5573 5574 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 5575 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 5576 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 5577 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 5578 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 5579 } 5580 5581 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 5582 enum amdgpu_interrupt_state state) 5583 { 5584 switch (state) { 5585 case AMDGPU_IRQ_STATE_DISABLE: 5586 case AMDGPU_IRQ_STATE_ENABLE: 5587 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5588 TIME_STAMP_INT_ENABLE, 5589 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5590 break; 5591 default: 5592 break; 5593 } 5594 } 5595 5596 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 5597 int me, int pipe, 5598 enum amdgpu_interrupt_state state) 5599 { 5600 u32 mec_int_cntl, mec_int_cntl_reg; 5601 5602 /* 5603 * amdgpu controls only the first MEC. That's why this function only 5604 * handles the setting of interrupts for this specific MEC. All other 5605 * pipes' interrupts are set by amdkfd. 5606 */ 5607 5608 if (me == 1) { 5609 switch (pipe) { 5610 case 0: 5611 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5612 break; 5613 case 1: 5614 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5615 break; 5616 case 2: 5617 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5618 break; 5619 case 3: 5620 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5621 break; 5622 default: 5623 DRM_DEBUG("invalid pipe %d\n", pipe); 5624 return; 5625 } 5626 } else { 5627 DRM_DEBUG("invalid me %d\n", me); 5628 return; 5629 } 5630 5631 switch (state) { 5632 case AMDGPU_IRQ_STATE_DISABLE: 5633 mec_int_cntl = RREG32(mec_int_cntl_reg); 5634 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5635 TIME_STAMP_INT_ENABLE, 0); 5636 WREG32(mec_int_cntl_reg, mec_int_cntl); 5637 break; 5638 case AMDGPU_IRQ_STATE_ENABLE: 5639 mec_int_cntl = RREG32(mec_int_cntl_reg); 5640 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5641 TIME_STAMP_INT_ENABLE, 1); 5642 WREG32(mec_int_cntl_reg, mec_int_cntl); 5643 break; 5644 default: 5645 break; 5646 } 5647 } 5648 5649 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5650 struct amdgpu_irq_src *source, 5651 unsigned type, 5652 enum amdgpu_interrupt_state state) 5653 { 5654 switch (state) { 5655 case AMDGPU_IRQ_STATE_DISABLE: 5656 case AMDGPU_IRQ_STATE_ENABLE: 5657 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5658 PRIV_REG_INT_ENABLE, 5659 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5660 break; 5661 default: 5662 break; 5663 } 5664 5665 return 0; 5666 } 5667 5668 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5669 struct amdgpu_irq_src *source, 5670 unsigned type, 5671 enum amdgpu_interrupt_state state) 5672 { 5673 switch (state) { 5674 case AMDGPU_IRQ_STATE_DISABLE: 5675 case AMDGPU_IRQ_STATE_ENABLE: 5676 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5677 PRIV_INSTR_INT_ENABLE, 5678 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5679 default: 5680 break; 5681 } 5682 5683 return 0; 5684 } 5685 5686 #define ENABLE_ECC_ON_ME_PIPE(me, pipe) \ 5687 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5688 CP_ECC_ERROR_INT_ENABLE, 1) 5689 5690 #define DISABLE_ECC_ON_ME_PIPE(me, pipe) \ 5691 WREG32_FIELD15(GC, 0, CP_ME##me##_PIPE##pipe##_INT_CNTL,\ 5692 CP_ECC_ERROR_INT_ENABLE, 0) 5693 5694 static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, 5695 struct amdgpu_irq_src *source, 5696 unsigned type, 5697 enum amdgpu_interrupt_state state) 5698 { 5699 switch (state) { 5700 case AMDGPU_IRQ_STATE_DISABLE: 5701 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5702 CP_ECC_ERROR_INT_ENABLE, 0); 5703 DISABLE_ECC_ON_ME_PIPE(1, 0); 5704 DISABLE_ECC_ON_ME_PIPE(1, 1); 5705 DISABLE_ECC_ON_ME_PIPE(1, 2); 5706 DISABLE_ECC_ON_ME_PIPE(1, 3); 5707 break; 5708 5709 case AMDGPU_IRQ_STATE_ENABLE: 5710 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5711 CP_ECC_ERROR_INT_ENABLE, 1); 5712 ENABLE_ECC_ON_ME_PIPE(1, 0); 5713 ENABLE_ECC_ON_ME_PIPE(1, 1); 5714 ENABLE_ECC_ON_ME_PIPE(1, 2); 5715 ENABLE_ECC_ON_ME_PIPE(1, 3); 5716 break; 5717 default: 5718 break; 5719 } 5720 5721 return 0; 5722 } 5723 5724 5725 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5726 struct amdgpu_irq_src *src, 5727 unsigned type, 5728 enum amdgpu_interrupt_state state) 5729 { 5730 switch (type) { 5731 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5732 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); 5733 break; 5734 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5735 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5736 break; 5737 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5738 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5739 break; 5740 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5741 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5742 break; 5743 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5744 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5745 break; 5746 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 5747 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 5748 break; 5749 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 5750 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 5751 break; 5752 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 5753 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 5754 break; 5755 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 5756 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 5757 break; 5758 default: 5759 break; 5760 } 5761 return 0; 5762 } 5763 5764 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev, 5765 struct amdgpu_irq_src *source, 5766 struct amdgpu_iv_entry *entry) 5767 { 5768 int i; 5769 u8 me_id, pipe_id, queue_id; 5770 struct amdgpu_ring *ring; 5771 5772 DRM_DEBUG("IH: CP EOP\n"); 5773 me_id = (entry->ring_id & 0x0c) >> 2; 5774 pipe_id = (entry->ring_id & 0x03) >> 0; 5775 queue_id = (entry->ring_id & 0x70) >> 4; 5776 5777 switch (me_id) { 5778 case 0: 5779 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5780 break; 5781 case 1: 5782 case 2: 5783 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5784 ring = &adev->gfx.compute_ring[i]; 5785 /* Per-queue interrupt is supported for MEC starting from VI. 5786 * The interrupt can only be enabled/disabled per pipe instead of per queue. 5787 */ 5788 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 5789 amdgpu_fence_process(ring); 5790 } 5791 break; 5792 } 5793 return 0; 5794 } 5795 5796 static void gfx_v9_0_fault(struct amdgpu_device *adev, 5797 struct amdgpu_iv_entry *entry) 5798 { 5799 u8 me_id, pipe_id, queue_id; 5800 struct amdgpu_ring *ring; 5801 int i; 5802 5803 me_id = (entry->ring_id & 0x0c) >> 2; 5804 pipe_id = (entry->ring_id & 0x03) >> 0; 5805 queue_id = (entry->ring_id & 0x70) >> 4; 5806 5807 switch (me_id) { 5808 case 0: 5809 drm_sched_fault(&adev->gfx.gfx_ring[0].sched); 5810 break; 5811 case 1: 5812 case 2: 5813 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5814 ring = &adev->gfx.compute_ring[i]; 5815 if (ring->me == me_id && ring->pipe == pipe_id && 5816 ring->queue == queue_id) 5817 drm_sched_fault(&ring->sched); 5818 } 5819 break; 5820 } 5821 } 5822 5823 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev, 5824 struct amdgpu_irq_src *source, 5825 struct amdgpu_iv_entry *entry) 5826 { 5827 DRM_ERROR("Illegal register access in command stream\n"); 5828 gfx_v9_0_fault(adev, entry); 5829 return 0; 5830 } 5831 5832 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, 5833 struct amdgpu_irq_src *source, 5834 struct amdgpu_iv_entry *entry) 5835 { 5836 DRM_ERROR("Illegal instruction in command stream\n"); 5837 gfx_v9_0_fault(adev, entry); 5838 return 0; 5839 } 5840 5841 5842 static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = { 5843 { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 5844 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT), 5845 SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) 5846 }, 5847 { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 5848 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT), 5849 SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) 5850 }, 5851 { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5852 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME1), 5853 0, 0 5854 }, 5855 { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 5856 SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, COUNT_ME2), 5857 0, 0 5858 }, 5859 { "CPF_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 5860 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT), 5861 SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) 5862 }, 5863 { "CPG_DMA_ROQ", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5864 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, ROQ_COUNT), 5865 0, 0 5866 }, 5867 { "CPG_DMA_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_DMA_CNT), 5868 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_SEC_COUNT), 5869 SOC15_REG_FIELD(CPG_EDC_DMA_CNT, TAG_DED_COUNT) 5870 }, 5871 { "CPG_TAG", SOC15_REG_ENTRY(GC, 0, mmCPG_EDC_TAG_CNT), 5872 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, SEC_COUNT), 5873 SOC15_REG_FIELD(CPG_EDC_TAG_CNT, DED_COUNT) 5874 }, 5875 { "DC_CSINVOC", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 5876 SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, COUNT_ME1), 5877 0, 0 5878 }, 5879 { "DC_RESTORE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 5880 SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, COUNT_ME1), 5881 0, 0 5882 }, 5883 { "DC_STATE", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 5884 SOC15_REG_FIELD(DC_EDC_STATE_CNT, COUNT_ME1), 5885 0, 0 5886 }, 5887 { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5888 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC), 5889 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) 5890 }, 5891 { "GDS_INPUT_QUEUE", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 5892 SOC15_REG_FIELD(GDS_EDC_CNT, GDS_INPUT_QUEUE_SED), 5893 0, 0 5894 }, 5895 { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5896 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC), 5897 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) 5898 }, 5899 { "GDS_OA_PHY_PHY_CMD_RAM_MEM", 5900 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5901 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC), 5902 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) 5903 }, 5904 { "GDS_OA_PHY_PHY_DATA_RAM_MEM", 5905 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 5906 SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SED), 5907 0, 0 5908 }, 5909 { "GDS_OA_PIPE_ME1_PIPE0_PIPE_MEM", 5910 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5911 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC), 5912 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) 5913 }, 5914 { "GDS_OA_PIPE_ME1_PIPE1_PIPE_MEM", 5915 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5916 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC), 5917 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) 5918 }, 5919 { "GDS_OA_PIPE_ME1_PIPE2_PIPE_MEM", 5920 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5921 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC), 5922 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) 5923 }, 5924 { "GDS_OA_PIPE_ME1_PIPE3_PIPE_MEM", 5925 SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 5926 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC), 5927 SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) 5928 }, 5929 { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 5930 SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SED_COUNT), 5931 0, 0 5932 }, 5933 { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5934 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT), 5935 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) 5936 }, 5937 { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5938 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SED_COUNT), 5939 0, 0 5940 }, 5941 { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5942 SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SED_COUNT), 5943 0, 0 5944 }, 5945 { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5946 SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SED_COUNT), 5947 0, 0 5948 }, 5949 { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 5950 SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SED_COUNT), 5951 0, 0 5952 }, 5953 { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 5954 SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SED_COUNT), 5955 0, 0 5956 }, 5957 { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 5958 SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SED_COUNT), 5959 0, 0 5960 }, 5961 { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5962 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT), 5963 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) 5964 }, 5965 { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5966 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT), 5967 SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) 5968 }, 5969 { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5970 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT), 5971 SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) 5972 }, 5973 { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5974 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT), 5975 SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) 5976 }, 5977 { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5978 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT), 5979 SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) 5980 }, 5981 { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5982 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_DEC_SED_COUNT), 5983 0, 0 5984 }, 5985 { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5986 SOC15_REG_FIELD(TCC_EDC_CNT, IN_USE_TRANSFER_SED_COUNT), 5987 0, 0 5988 }, 5989 { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5990 SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SED_COUNT), 5991 0, 0 5992 }, 5993 { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5994 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_DATA_SED_COUNT), 5995 0, 0 5996 }, 5997 { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 5998 SOC15_REG_FIELD(TCC_EDC_CNT, RETURN_CONTROL_SED_COUNT), 5999 0, 0 6000 }, 6001 { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 6002 SOC15_REG_FIELD(TCC_EDC_CNT, UC_ATOMIC_FIFO_SED_COUNT), 6003 0, 0 6004 }, 6005 { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6006 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SED_COUNT), 6007 0, 0 6008 }, 6009 { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6010 SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SED_COUNT), 6011 0, 0 6012 }, 6013 { "TCC_SRC_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6014 SOC15_REG_FIELD(TCC_EDC_CNT2, SRC_FIFO_NEXT_RAM_SED_COUNT), 6015 0, 0 6016 }, 6017 { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6018 SOC15_REG_FIELD(TCC_EDC_CNT2, LATENCY_FIFO_NEXT_RAM_SED_COUNT), 6019 0, 0 6020 }, 6021 { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6022 SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SED_COUNT), 6023 0, 0 6024 }, 6025 { "TCC_WRRET_TAG_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6026 SOC15_REG_FIELD(TCC_EDC_CNT2, WRRET_TAG_WRITE_RETURN_SED_COUNT), 6027 0, 0 6028 }, 6029 { "TCC_ATOMIC_RETURN_BUFFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 6030 SOC15_REG_FIELD(TCC_EDC_CNT2, ATOMIC_RETURN_BUFFER_SED_COUNT), 6031 0, 0 6032 }, 6033 { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 6034 SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SED_COUNT), 6035 0, 0 6036 }, 6037 { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6038 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT), 6039 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) 6040 }, 6041 { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6042 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT), 6043 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) 6044 }, 6045 { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6046 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SED_COUNT), 6047 0, 0 6048 }, 6049 { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6050 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT), 6051 0, 0 6052 }, 6053 { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6054 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 6055 0, 0 6056 }, 6057 { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6058 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT), 6059 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) 6060 }, 6061 { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 6062 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT), 6063 SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) 6064 }, 6065 { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6066 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT), 6067 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) 6068 }, 6069 { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6070 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT), 6071 SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) 6072 }, 6073 { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 6074 SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SED_COUNT), 6075 0, 0 6076 }, 6077 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6078 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT), 6079 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) 6080 }, 6081 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6082 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT), 6083 SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) 6084 }, 6085 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6086 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT), 6087 SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) 6088 }, 6089 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6090 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT), 6091 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) 6092 }, 6093 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6094 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT), 6095 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) 6096 }, 6097 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6098 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT), 6099 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) 6100 }, 6101 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 6102 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT), 6103 SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) 6104 }, 6105 { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6106 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT), 6107 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) 6108 }, 6109 { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6110 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT), 6111 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) 6112 }, 6113 { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6114 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT), 6115 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) 6116 }, 6117 { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6118 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT), 6119 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) 6120 }, 6121 { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6122 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT), 6123 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) 6124 }, 6125 { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 6126 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT), 6127 SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) 6128 }, 6129 { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6130 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT), 6131 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) 6132 }, 6133 { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6134 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT), 6135 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) 6136 }, 6137 { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6138 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT), 6139 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) 6140 }, 6141 { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6142 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT), 6143 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) 6144 }, 6145 { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6146 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT), 6147 0, 0 6148 }, 6149 { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6150 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_MISS_FIFO_SED_COUNT), 6151 0, 0 6152 }, 6153 { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6154 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_HIT_FIFO_SED_COUNT), 6155 0, 0 6156 }, 6157 { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6158 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_MISS_FIFO_SED_COUNT), 6159 0, 0 6160 }, 6161 { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6162 SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT), 6163 0, 0 6164 }, 6165 { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 6166 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT), 6167 SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) 6168 }, 6169 { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6170 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT), 6171 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) 6172 }, 6173 { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6174 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT), 6175 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) 6176 }, 6177 { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6178 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT), 6179 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) 6180 }, 6181 { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6182 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT), 6183 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) 6184 }, 6185 { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6186 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT), 6187 0, 0 6188 }, 6189 { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6190 SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_MISS_FIFO_SED_COUNT), 6191 0, 0 6192 }, 6193 { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6194 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_HIT_FIFO_SED_COUNT), 6195 0, 0 6196 }, 6197 { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6198 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_MISS_FIFO_SED_COUNT), 6199 0, 0 6200 }, 6201 { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 6202 SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT), 6203 0, 0 6204 }, 6205 { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6206 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT), 6207 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) 6208 }, 6209 { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6210 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT), 6211 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) 6212 }, 6213 { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6214 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT), 6215 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) 6216 }, 6217 { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6218 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT), 6219 SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) 6220 }, 6221 { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6222 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT), 6223 SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) 6224 }, 6225 { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6226 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 6227 0, 0 6228 }, 6229 { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6230 SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 6231 0, 0 6232 }, 6233 { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6234 SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 6235 0, 0 6236 }, 6237 { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6238 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 6239 0, 0 6240 }, 6241 { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 6242 SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 6243 0, 0 6244 }, 6245 { "GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6246 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT), 6247 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) 6248 }, 6249 { "GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6250 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT), 6251 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) 6252 }, 6253 { "GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6254 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT), 6255 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) 6256 }, 6257 { "GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6258 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 6259 0, 0 6260 }, 6261 { "GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6262 SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 6263 0, 0 6264 }, 6265 { "MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6266 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT), 6267 0, 0 6268 }, 6269 { "MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6270 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT), 6271 0, 0 6272 }, 6273 { "MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6274 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT), 6275 0, 0 6276 }, 6277 { "MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 6278 SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT), 6279 0, 0 6280 } 6281 }; 6282 6283 static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, 6284 void *inject_if) 6285 { 6286 struct ras_inject_if *info = (struct ras_inject_if *)inject_if; 6287 int ret; 6288 struct ta_ras_trigger_error_input block_info = { 0 }; 6289 6290 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6291 return -EINVAL; 6292 6293 if (info->head.sub_block_index >= ARRAY_SIZE(ras_gfx_subblocks)) 6294 return -EINVAL; 6295 6296 if (!ras_gfx_subblocks[info->head.sub_block_index].name) 6297 return -EPERM; 6298 6299 if (!(ras_gfx_subblocks[info->head.sub_block_index].hw_supported_error_type & 6300 info->head.type)) { 6301 DRM_ERROR("GFX Subblock %s, hardware do not support type 0x%x\n", 6302 ras_gfx_subblocks[info->head.sub_block_index].name, 6303 info->head.type); 6304 return -EPERM; 6305 } 6306 6307 if (!(ras_gfx_subblocks[info->head.sub_block_index].sw_supported_error_type & 6308 info->head.type)) { 6309 DRM_ERROR("GFX Subblock %s, driver do not support type 0x%x\n", 6310 ras_gfx_subblocks[info->head.sub_block_index].name, 6311 info->head.type); 6312 return -EPERM; 6313 } 6314 6315 block_info.block_id = amdgpu_ras_block_to_ta(info->head.block); 6316 block_info.sub_block_index = 6317 ras_gfx_subblocks[info->head.sub_block_index].ta_subblock; 6318 block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); 6319 block_info.address = info->address; 6320 block_info.value = info->value; 6321 6322 mutex_lock(&adev->grbm_idx_mutex); 6323 ret = psp_ras_trigger_error(&adev->psp, &block_info); 6324 mutex_unlock(&adev->grbm_idx_mutex); 6325 6326 return ret; 6327 } 6328 6329 static const char *vml2_mems[] = { 6330 "UTC_VML2_BANK_CACHE_0_BIGK_MEM0", 6331 "UTC_VML2_BANK_CACHE_0_BIGK_MEM1", 6332 "UTC_VML2_BANK_CACHE_0_4K_MEM0", 6333 "UTC_VML2_BANK_CACHE_0_4K_MEM1", 6334 "UTC_VML2_BANK_CACHE_1_BIGK_MEM0", 6335 "UTC_VML2_BANK_CACHE_1_BIGK_MEM1", 6336 "UTC_VML2_BANK_CACHE_1_4K_MEM0", 6337 "UTC_VML2_BANK_CACHE_1_4K_MEM1", 6338 "UTC_VML2_BANK_CACHE_2_BIGK_MEM0", 6339 "UTC_VML2_BANK_CACHE_2_BIGK_MEM1", 6340 "UTC_VML2_BANK_CACHE_2_4K_MEM0", 6341 "UTC_VML2_BANK_CACHE_2_4K_MEM1", 6342 "UTC_VML2_BANK_CACHE_3_BIGK_MEM0", 6343 "UTC_VML2_BANK_CACHE_3_BIGK_MEM1", 6344 "UTC_VML2_BANK_CACHE_3_4K_MEM0", 6345 "UTC_VML2_BANK_CACHE_3_4K_MEM1", 6346 }; 6347 6348 static const char *vml2_walker_mems[] = { 6349 "UTC_VML2_CACHE_PDE0_MEM0", 6350 "UTC_VML2_CACHE_PDE0_MEM1", 6351 "UTC_VML2_CACHE_PDE1_MEM0", 6352 "UTC_VML2_CACHE_PDE1_MEM1", 6353 "UTC_VML2_CACHE_PDE2_MEM0", 6354 "UTC_VML2_CACHE_PDE2_MEM1", 6355 "UTC_VML2_RDIF_LOG_FIFO", 6356 }; 6357 6358 static const char *atc_l2_cache_2m_mems[] = { 6359 "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM", 6360 "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM", 6361 "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM", 6362 "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM", 6363 }; 6364 6365 static const char *atc_l2_cache_4k_mems[] = { 6366 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0", 6367 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1", 6368 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2", 6369 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3", 6370 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4", 6371 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5", 6372 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6", 6373 "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7", 6374 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0", 6375 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1", 6376 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2", 6377 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3", 6378 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4", 6379 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5", 6380 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6", 6381 "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7", 6382 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0", 6383 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1", 6384 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2", 6385 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3", 6386 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4", 6387 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5", 6388 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6", 6389 "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7", 6390 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0", 6391 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1", 6392 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2", 6393 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3", 6394 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4", 6395 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5", 6396 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6", 6397 "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7", 6398 }; 6399 6400 static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev, 6401 struct ras_err_data *err_data) 6402 { 6403 uint32_t i, data; 6404 uint32_t sec_count, ded_count; 6405 6406 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6407 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6408 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6409 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6410 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6411 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6412 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6413 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6414 6415 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6416 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6417 data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6418 6419 sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT); 6420 if (sec_count) { 6421 DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, 6422 vml2_mems[i], sec_count); 6423 err_data->ce_count += sec_count; 6424 } 6425 6426 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); 6427 if (ded_count) { 6428 DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, 6429 vml2_mems[i], ded_count); 6430 err_data->ue_count += ded_count; 6431 } 6432 } 6433 6434 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6435 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6436 data = RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6437 6438 sec_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6439 SEC_COUNT); 6440 if (sec_count) { 6441 DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, 6442 vml2_walker_mems[i], sec_count); 6443 err_data->ce_count += sec_count; 6444 } 6445 6446 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, 6447 DED_COUNT); 6448 if (ded_count) { 6449 DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, 6450 vml2_walker_mems[i], ded_count); 6451 err_data->ue_count += ded_count; 6452 } 6453 } 6454 6455 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6456 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6457 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6458 6459 sec_count = (data & 0x00006000L) >> 0xd; 6460 if (sec_count) { 6461 DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, 6462 atc_l2_cache_2m_mems[i], sec_count); 6463 err_data->ce_count += sec_count; 6464 } 6465 } 6466 6467 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6468 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6469 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6470 6471 sec_count = (data & 0x00006000L) >> 0xd; 6472 if (sec_count) { 6473 DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i, 6474 atc_l2_cache_4k_mems[i], sec_count); 6475 err_data->ce_count += sec_count; 6476 } 6477 6478 ded_count = (data & 0x00018000L) >> 0xf; 6479 if (ded_count) { 6480 DRM_INFO("Instance[%d]: SubBlock %s, DED %d\n", i, 6481 atc_l2_cache_4k_mems[i], ded_count); 6482 err_data->ue_count += ded_count; 6483 } 6484 } 6485 6486 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6487 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6488 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6489 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6490 6491 return 0; 6492 } 6493 6494 static int gfx_v9_0_ras_error_count(const struct soc15_reg_entry *reg, 6495 uint32_t se_id, uint32_t inst_id, uint32_t value, 6496 uint32_t *sec_count, uint32_t *ded_count) 6497 { 6498 uint32_t i; 6499 uint32_t sec_cnt, ded_cnt; 6500 6501 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_ras_fields); i++) { 6502 if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset || 6503 gfx_v9_0_ras_fields[i].seg != reg->seg || 6504 gfx_v9_0_ras_fields[i].inst != reg->inst) 6505 continue; 6506 6507 sec_cnt = (value & 6508 gfx_v9_0_ras_fields[i].sec_count_mask) >> 6509 gfx_v9_0_ras_fields[i].sec_count_shift; 6510 if (sec_cnt) { 6511 DRM_INFO("GFX SubBlock %s, Instance[%d][%d], SEC %d\n", 6512 gfx_v9_0_ras_fields[i].name, 6513 se_id, inst_id, 6514 sec_cnt); 6515 *sec_count += sec_cnt; 6516 } 6517 6518 ded_cnt = (value & 6519 gfx_v9_0_ras_fields[i].ded_count_mask) >> 6520 gfx_v9_0_ras_fields[i].ded_count_shift; 6521 if (ded_cnt) { 6522 DRM_INFO("GFX SubBlock %s, Instance[%d][%d], DED %d\n", 6523 gfx_v9_0_ras_fields[i].name, 6524 se_id, inst_id, 6525 ded_cnt); 6526 *ded_count += ded_cnt; 6527 } 6528 } 6529 6530 return 0; 6531 } 6532 6533 static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev) 6534 { 6535 int i, j, k; 6536 6537 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6538 return; 6539 6540 /* read back registers to clear the counters */ 6541 mutex_lock(&adev->grbm_idx_mutex); 6542 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6543 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6544 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6545 gfx_v9_0_select_se_sh(adev, j, 0x0, k); 6546 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6547 } 6548 } 6549 } 6550 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 6551 mutex_unlock(&adev->grbm_idx_mutex); 6552 6553 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6554 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0); 6555 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6556 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0); 6557 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6558 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0); 6559 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6560 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0); 6561 6562 for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) { 6563 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i); 6564 RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT); 6565 } 6566 6567 for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) { 6568 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, i); 6569 RREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT); 6570 } 6571 6572 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) { 6573 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, i); 6574 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT); 6575 } 6576 6577 for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) { 6578 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, i); 6579 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT); 6580 } 6581 6582 WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255); 6583 WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255); 6584 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255); 6585 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255); 6586 } 6587 6588 static int gfx_v9_0_query_ras_error_count(struct amdgpu_device *adev, 6589 void *ras_error_status) 6590 { 6591 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 6592 uint32_t sec_count = 0, ded_count = 0; 6593 uint32_t i, j, k; 6594 uint32_t reg_value; 6595 6596 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) 6597 return -EINVAL; 6598 6599 err_data->ue_count = 0; 6600 err_data->ce_count = 0; 6601 6602 mutex_lock(&adev->grbm_idx_mutex); 6603 6604 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6605 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6606 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6607 gfx_v9_0_select_se_sh(adev, j, 0, k); 6608 reg_value = 6609 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6610 if (reg_value) 6611 gfx_v9_0_ras_error_count(&gfx_v9_0_edc_counter_regs[i], 6612 j, k, reg_value, 6613 &sec_count, &ded_count); 6614 } 6615 } 6616 } 6617 6618 err_data->ce_count += sec_count; 6619 err_data->ue_count += ded_count; 6620 6621 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6622 mutex_unlock(&adev->grbm_idx_mutex); 6623 6624 gfx_v9_0_query_utc_edc_status(adev, err_data); 6625 6626 return 0; 6627 } 6628 6629 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { 6630 .name = "gfx_v9_0", 6631 .early_init = gfx_v9_0_early_init, 6632 .late_init = gfx_v9_0_late_init, 6633 .sw_init = gfx_v9_0_sw_init, 6634 .sw_fini = gfx_v9_0_sw_fini, 6635 .hw_init = gfx_v9_0_hw_init, 6636 .hw_fini = gfx_v9_0_hw_fini, 6637 .suspend = gfx_v9_0_suspend, 6638 .resume = gfx_v9_0_resume, 6639 .is_idle = gfx_v9_0_is_idle, 6640 .wait_for_idle = gfx_v9_0_wait_for_idle, 6641 .soft_reset = gfx_v9_0_soft_reset, 6642 .set_clockgating_state = gfx_v9_0_set_clockgating_state, 6643 .set_powergating_state = gfx_v9_0_set_powergating_state, 6644 .get_clockgating_state = gfx_v9_0_get_clockgating_state, 6645 }; 6646 6647 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 6648 .type = AMDGPU_RING_TYPE_GFX, 6649 .align_mask = 0xff, 6650 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6651 .support_64bit_ptrs = true, 6652 .vmhub = AMDGPU_GFXHUB_0, 6653 .get_rptr = gfx_v9_0_ring_get_rptr_gfx, 6654 .get_wptr = gfx_v9_0_ring_get_wptr_gfx, 6655 .set_wptr = gfx_v9_0_ring_set_wptr_gfx, 6656 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 6657 5 + /* COND_EXEC */ 6658 7 + /* PIPELINE_SYNC */ 6659 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6660 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6661 2 + /* VM_FLUSH */ 6662 8 + /* FENCE for VM_FLUSH */ 6663 20 + /* GDS switch */ 6664 4 + /* double SWITCH_BUFFER, 6665 the first COND_EXEC jump to the place just 6666 prior to this double SWITCH_BUFFER */ 6667 5 + /* COND_EXEC */ 6668 7 + /* HDP_flush */ 6669 4 + /* VGT_flush */ 6670 14 + /* CE_META */ 6671 31 + /* DE_META */ 6672 3 + /* CNTX_CTRL */ 6673 5 + /* HDP_INVL */ 6674 8 + 8 + /* FENCE x2 */ 6675 2, /* SWITCH_BUFFER */ 6676 .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ 6677 .emit_ib = gfx_v9_0_ring_emit_ib_gfx, 6678 .emit_fence = gfx_v9_0_ring_emit_fence, 6679 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6680 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6681 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6682 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6683 .test_ring = gfx_v9_0_ring_test_ring, 6684 .test_ib = gfx_v9_0_ring_test_ib, 6685 .insert_nop = amdgpu_ring_insert_nop, 6686 .pad_ib = amdgpu_ring_generic_pad_ib, 6687 .emit_switch_buffer = gfx_v9_ring_emit_sb, 6688 .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl, 6689 .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec, 6690 .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec, 6691 .emit_tmz = gfx_v9_0_ring_emit_tmz, 6692 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6693 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6694 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6695 .soft_recovery = gfx_v9_0_ring_soft_recovery, 6696 }; 6697 6698 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 6699 .type = AMDGPU_RING_TYPE_COMPUTE, 6700 .align_mask = 0xff, 6701 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6702 .support_64bit_ptrs = true, 6703 .vmhub = AMDGPU_GFXHUB_0, 6704 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6705 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6706 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6707 .emit_frame_size = 6708 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6709 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6710 5 + /* hdp invalidate */ 6711 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6712 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6713 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6714 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6715 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 6716 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6717 .emit_ib = gfx_v9_0_ring_emit_ib_compute, 6718 .emit_fence = gfx_v9_0_ring_emit_fence, 6719 .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync, 6720 .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, 6721 .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, 6722 .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, 6723 .test_ring = gfx_v9_0_ring_test_ring, 6724 .test_ib = gfx_v9_0_ring_test_ib, 6725 .insert_nop = amdgpu_ring_insert_nop, 6726 .pad_ib = amdgpu_ring_generic_pad_ib, 6727 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6728 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6729 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6730 }; 6731 6732 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { 6733 .type = AMDGPU_RING_TYPE_KIQ, 6734 .align_mask = 0xff, 6735 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6736 .support_64bit_ptrs = true, 6737 .vmhub = AMDGPU_GFXHUB_0, 6738 .get_rptr = gfx_v9_0_ring_get_rptr_compute, 6739 .get_wptr = gfx_v9_0_ring_get_wptr_compute, 6740 .set_wptr = gfx_v9_0_ring_set_wptr_compute, 6741 .emit_frame_size = 6742 20 + /* gfx_v9_0_ring_emit_gds_switch */ 6743 7 + /* gfx_v9_0_ring_emit_hdp_flush */ 6744 5 + /* hdp invalidate */ 6745 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ 6746 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 6747 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 6748 2 + /* gfx_v9_0_ring_emit_vm_flush */ 6749 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 6750 .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ 6751 .emit_fence = gfx_v9_0_ring_emit_fence_kiq, 6752 .test_ring = gfx_v9_0_ring_test_ring, 6753 .insert_nop = amdgpu_ring_insert_nop, 6754 .pad_ib = amdgpu_ring_generic_pad_ib, 6755 .emit_rreg = gfx_v9_0_ring_emit_rreg, 6756 .emit_wreg = gfx_v9_0_ring_emit_wreg, 6757 .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, 6758 .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, 6759 }; 6760 6761 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) 6762 { 6763 int i; 6764 6765 adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq; 6766 6767 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6768 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx; 6769 6770 for (i = 0; i < adev->gfx.num_compute_rings; i++) 6771 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute; 6772 } 6773 6774 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = { 6775 .set = gfx_v9_0_set_eop_interrupt_state, 6776 .process = gfx_v9_0_eop_irq, 6777 }; 6778 6779 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = { 6780 .set = gfx_v9_0_set_priv_reg_fault_state, 6781 .process = gfx_v9_0_priv_reg_irq, 6782 }; 6783 6784 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = { 6785 .set = gfx_v9_0_set_priv_inst_fault_state, 6786 .process = gfx_v9_0_priv_inst_irq, 6787 }; 6788 6789 static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { 6790 .set = gfx_v9_0_set_cp_ecc_error_state, 6791 .process = amdgpu_gfx_cp_ecc_error_irq, 6792 }; 6793 6794 6795 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) 6796 { 6797 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 6798 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; 6799 6800 adev->gfx.priv_reg_irq.num_types = 1; 6801 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; 6802 6803 adev->gfx.priv_inst_irq.num_types = 1; 6804 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs; 6805 6806 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/ 6807 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs; 6808 } 6809 6810 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) 6811 { 6812 switch (adev->asic_type) { 6813 case CHIP_VEGA10: 6814 case CHIP_VEGA12: 6815 case CHIP_VEGA20: 6816 case CHIP_RAVEN: 6817 case CHIP_ARCTURUS: 6818 case CHIP_RENOIR: 6819 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; 6820 break; 6821 default: 6822 break; 6823 } 6824 } 6825 6826 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev) 6827 { 6828 /* init asci gds info */ 6829 switch (adev->asic_type) { 6830 case CHIP_VEGA10: 6831 case CHIP_VEGA12: 6832 case CHIP_VEGA20: 6833 adev->gds.gds_size = 0x10000; 6834 break; 6835 case CHIP_RAVEN: 6836 case CHIP_ARCTURUS: 6837 adev->gds.gds_size = 0x1000; 6838 break; 6839 default: 6840 adev->gds.gds_size = 0x10000; 6841 break; 6842 } 6843 6844 switch (adev->asic_type) { 6845 case CHIP_VEGA10: 6846 case CHIP_VEGA20: 6847 adev->gds.gds_compute_max_wave_id = 0x7ff; 6848 break; 6849 case CHIP_VEGA12: 6850 adev->gds.gds_compute_max_wave_id = 0x27f; 6851 break; 6852 case CHIP_RAVEN: 6853 if (adev->rev_id >= 0x8) 6854 adev->gds.gds_compute_max_wave_id = 0x77; /* raven2 */ 6855 else 6856 adev->gds.gds_compute_max_wave_id = 0x15f; /* raven1 */ 6857 break; 6858 case CHIP_ARCTURUS: 6859 adev->gds.gds_compute_max_wave_id = 0xfff; 6860 break; 6861 default: 6862 /* this really depends on the chip */ 6863 adev->gds.gds_compute_max_wave_id = 0x7ff; 6864 break; 6865 } 6866 6867 adev->gds.gws_size = 64; 6868 adev->gds.oa_size = 16; 6869 } 6870 6871 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev, 6872 u32 bitmap) 6873 { 6874 u32 data; 6875 6876 if (!bitmap) 6877 return; 6878 6879 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 6880 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 6881 6882 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 6883 } 6884 6885 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev) 6886 { 6887 u32 data, mask; 6888 6889 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 6890 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 6891 6892 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK; 6893 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT; 6894 6895 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 6896 6897 return (~data) & mask; 6898 } 6899 6900 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev, 6901 struct amdgpu_cu_info *cu_info) 6902 { 6903 int i, j, k, counter, active_cu_number = 0; 6904 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 6905 unsigned disable_masks[4 * 4]; 6906 6907 if (!adev || !cu_info) 6908 return -EINVAL; 6909 6910 /* 6911 * 16 comes from bitmap array size 4*4, and it can cover all gfx9 ASICs 6912 */ 6913 if (adev->gfx.config.max_shader_engines * 6914 adev->gfx.config.max_sh_per_se > 16) 6915 return -EINVAL; 6916 6917 amdgpu_gfx_parse_disable_cu(disable_masks, 6918 adev->gfx.config.max_shader_engines, 6919 adev->gfx.config.max_sh_per_se); 6920 6921 mutex_lock(&adev->grbm_idx_mutex); 6922 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 6923 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6924 mask = 1; 6925 ao_bitmap = 0; 6926 counter = 0; 6927 gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff); 6928 gfx_v9_0_set_user_cu_inactive_bitmap( 6929 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 6930 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); 6931 6932 /* 6933 * The bitmap(and ao_cu_bitmap) in cu_info structure is 6934 * 4x4 size array, and it's usually suitable for Vega 6935 * ASICs which has 4*2 SE/SH layout. 6936 * But for Arcturus, SE/SH layout is changed to 8*1. 6937 * To mostly reduce the impact, we make it compatible 6938 * with current bitmap array as below: 6939 * SE4,SH0 --> bitmap[0][1] 6940 * SE5,SH0 --> bitmap[1][1] 6941 * SE6,SH0 --> bitmap[2][1] 6942 * SE7,SH0 --> bitmap[3][1] 6943 */ 6944 cu_info->bitmap[i % 4][j + i / 4] = bitmap; 6945 6946 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 6947 if (bitmap & mask) { 6948 if (counter < adev->gfx.config.max_cu_per_sh) 6949 ao_bitmap |= mask; 6950 counter ++; 6951 } 6952 mask <<= 1; 6953 } 6954 active_cu_number += counter; 6955 if (i < 2 && j < 2) 6956 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 6957 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 6958 } 6959 } 6960 gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6961 mutex_unlock(&adev->grbm_idx_mutex); 6962 6963 cu_info->number = active_cu_number; 6964 cu_info->ao_cu_mask = ao_cu_mask; 6965 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 6966 6967 return 0; 6968 } 6969 6970 const struct amdgpu_ip_block_version gfx_v9_0_ip_block = 6971 { 6972 .type = AMD_IP_BLOCK_TYPE_GFX, 6973 .major = 9, 6974 .minor = 0, 6975 .rev = 0, 6976 .funcs = &gfx_v9_0_ip_funcs, 6977 }; 6978