xref: /openbsd-src/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c (revision ff0e7be1ebbcc809ea8ad2b6dafe215824da9e46)
1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #include <linux/delay.h>
24 #include <linux/kernel.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include "amdgpu.h"
29 #include "amdgpu_gfx.h"
30 #include "amdgpu_psp.h"
31 #include "amdgpu_smu.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "imu_v11_0.h"
34 #include "soc21.h"
35 #include "nvd.h"
36 
37 #include "gc/gc_11_0_0_offset.h"
38 #include "gc/gc_11_0_0_sh_mask.h"
39 #include "smuio/smuio_13_0_6_offset.h"
40 #include "smuio/smuio_13_0_6_sh_mask.h"
41 #include "navi10_enum.h"
42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
43 
44 #include "soc15.h"
45 #include "soc15d.h"
46 #include "clearstate_gfx11.h"
47 #include "v11_structs.h"
48 #include "gfx_v11_0.h"
49 #include "nbio_v4_3.h"
50 #include "mes_v11_0.h"
51 
52 #define GFX11_NUM_GFX_RINGS		1
53 #define GFX11_MEC_HPD_SIZE	2048
54 
55 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
56 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1	0x1388
57 
58 #define regCGTT_WD_CLK_CTRL		0x5086
59 #define regCGTT_WD_CLK_CTRL_BASE_IDX	1
60 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1	0x4e7e
61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX	1
62 
63 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
64 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
65 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin");
66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin");
67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin");
68 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin");
69 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin");
70 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin");
71 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin");
72 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin");
73 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin");
74 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin");
75 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin");
76 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin");
77 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin");
78 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin");
79 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin");
80 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin");
81 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin");
82 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin");
83 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin");
84 
85 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
86 {
87 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
88 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
89 	SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
90 	SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
91 	SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
92 	SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
93 	SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
94 	SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
95 	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
96 };
97 
98 #define DEFAULT_SH_MEM_CONFIG \
99 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
100 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
101 	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
102 
103 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev);
104 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev);
105 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev);
106 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev);
107 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev);
108 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev);
109 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev);
110 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
111                                  struct amdgpu_cu_info *cu_info);
112 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev);
113 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
114 				   u32 sh_num, u32 instance);
115 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
116 
117 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
118 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
119 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
120 				     uint32_t val);
121 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
122 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
123 					   uint16_t pasid, uint32_t flush_type,
124 					   bool all_hub, uint8_t dst_sel);
125 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev);
126 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev);
127 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
128 				      bool enable);
129 
130 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
131 {
132 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
133 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
134 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
135 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
136 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
137 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */
138 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */
139 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
140 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
141 }
142 
143 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring,
144 				 struct amdgpu_ring *ring)
145 {
146 	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
147 	uint64_t wptr_addr = ring->wptr_gpu_addr;
148 	uint32_t me = 0, eng_sel = 0;
149 
150 	switch (ring->funcs->type) {
151 	case AMDGPU_RING_TYPE_COMPUTE:
152 		me = 1;
153 		eng_sel = 0;
154 		break;
155 	case AMDGPU_RING_TYPE_GFX:
156 		me = 0;
157 		eng_sel = 4;
158 		break;
159 	case AMDGPU_RING_TYPE_MES:
160 		me = 2;
161 		eng_sel = 5;
162 		break;
163 	default:
164 		WARN_ON(1);
165 	}
166 
167 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
168 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
169 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
170 			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
171 			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
172 			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
173 			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
174 			  PACKET3_MAP_QUEUES_ME((me)) |
175 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
176 			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
177 			  PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
178 			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
179 	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
180 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
181 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
182 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
183 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
184 }
185 
186 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
187 				   struct amdgpu_ring *ring,
188 				   enum amdgpu_unmap_queues_action action,
189 				   u64 gpu_addr, u64 seq)
190 {
191 	struct amdgpu_device *adev = kiq_ring->adev;
192 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
193 
194 	if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) {
195 		amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
196 		return;
197 	}
198 
199 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
200 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
201 			  PACKET3_UNMAP_QUEUES_ACTION(action) |
202 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
203 			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
204 			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
205 	amdgpu_ring_write(kiq_ring,
206 		  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
207 
208 	if (action == PREEMPT_QUEUES_NO_UNMAP) {
209 		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
210 		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
211 		amdgpu_ring_write(kiq_ring, seq);
212 	} else {
213 		amdgpu_ring_write(kiq_ring, 0);
214 		amdgpu_ring_write(kiq_ring, 0);
215 		amdgpu_ring_write(kiq_ring, 0);
216 	}
217 }
218 
219 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring,
220 				   struct amdgpu_ring *ring,
221 				   u64 addr,
222 				   u64 seq)
223 {
224 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
225 
226 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
227 	amdgpu_ring_write(kiq_ring,
228 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
229 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
230 			  PACKET3_QUERY_STATUS_COMMAND(2));
231 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
232 			  PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
233 			  PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
234 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
235 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
236 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
237 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
238 }
239 
240 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
241 				uint16_t pasid, uint32_t flush_type,
242 				bool all_hub)
243 {
244 	gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
245 }
246 
247 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = {
248 	.kiq_set_resources = gfx11_kiq_set_resources,
249 	.kiq_map_queues = gfx11_kiq_map_queues,
250 	.kiq_unmap_queues = gfx11_kiq_unmap_queues,
251 	.kiq_query_status = gfx11_kiq_query_status,
252 	.kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs,
253 	.set_resources_size = 8,
254 	.map_queues_size = 7,
255 	.unmap_queues_size = 6,
256 	.query_status_size = 7,
257 	.invalidate_tlbs_size = 2,
258 };
259 
260 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
261 {
262 	adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs;
263 }
264 
265 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
266 {
267 	switch (adev->ip_versions[GC_HWIP][0]) {
268 	case IP_VERSION(11, 0, 1):
269 	case IP_VERSION(11, 0, 4):
270 		soc15_program_register_sequence(adev,
271 						golden_settings_gc_11_0_1,
272 						(const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
273 		break;
274 	default:
275 		break;
276 	}
277 }
278 
279 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
280 				       bool wc, uint32_t reg, uint32_t val)
281 {
282 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
283 	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
284 			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
285 	amdgpu_ring_write(ring, reg);
286 	amdgpu_ring_write(ring, 0);
287 	amdgpu_ring_write(ring, val);
288 }
289 
290 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
291 				  int mem_space, int opt, uint32_t addr0,
292 				  uint32_t addr1, uint32_t ref, uint32_t mask,
293 				  uint32_t inv)
294 {
295 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
296 	amdgpu_ring_write(ring,
297 			  /* memory (1) or register (0) */
298 			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
299 			   WAIT_REG_MEM_OPERATION(opt) | /* wait */
300 			   WAIT_REG_MEM_FUNCTION(3) |  /* equal */
301 			   WAIT_REG_MEM_ENGINE(eng_sel)));
302 
303 	if (mem_space)
304 		BUG_ON(addr0 & 0x3); /* Dword align */
305 	amdgpu_ring_write(ring, addr0);
306 	amdgpu_ring_write(ring, addr1);
307 	amdgpu_ring_write(ring, ref);
308 	amdgpu_ring_write(ring, mask);
309 	amdgpu_ring_write(ring, inv); /* poll interval */
310 }
311 
312 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring)
313 {
314 	struct amdgpu_device *adev = ring->adev;
315 	uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
316 	uint32_t tmp = 0;
317 	unsigned i;
318 	int r;
319 
320 	WREG32(scratch, 0xCAFEDEAD);
321 	r = amdgpu_ring_alloc(ring, 5);
322 	if (r) {
323 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
324 			  ring->idx, r);
325 		return r;
326 	}
327 
328 	if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {
329 		gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
330 	} else {
331 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
332 		amdgpu_ring_write(ring, scratch -
333 				  PACKET3_SET_UCONFIG_REG_START);
334 		amdgpu_ring_write(ring, 0xDEADBEEF);
335 	}
336 	amdgpu_ring_commit(ring);
337 
338 	for (i = 0; i < adev->usec_timeout; i++) {
339 		tmp = RREG32(scratch);
340 		if (tmp == 0xDEADBEEF)
341 			break;
342 		if (amdgpu_emu_mode == 1)
343 			drm_msleep(1);
344 		else
345 			udelay(1);
346 	}
347 
348 	if (i >= adev->usec_timeout)
349 		r = -ETIMEDOUT;
350 	return r;
351 }
352 
353 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
354 {
355 	struct amdgpu_device *adev = ring->adev;
356 	struct amdgpu_ib ib;
357 	struct dma_fence *f = NULL;
358 	unsigned index;
359 	uint64_t gpu_addr;
360 	volatile uint32_t *cpu_ptr;
361 	long r;
362 
363 	/* MES KIQ fw hasn't indirect buffer support for now */
364 	if (adev->enable_mes_kiq &&
365 	    ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
366 		return 0;
367 
368 	memset(&ib, 0, sizeof(ib));
369 
370 	if (ring->is_mes_queue) {
371 		uint32_t padding, offset;
372 
373 		offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
374 		padding = amdgpu_mes_ctx_get_offs(ring,
375 						  AMDGPU_MES_CTX_PADDING_OFFS);
376 
377 		ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
378 		ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
379 
380 		gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
381 		cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
382 		*cpu_ptr = cpu_to_le32(0xCAFEDEAD);
383 	} else {
384 		r = amdgpu_device_wb_get(adev, &index);
385 		if (r)
386 			return r;
387 
388 		gpu_addr = adev->wb.gpu_addr + (index * 4);
389 		adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
390 		cpu_ptr = &adev->wb.wb[index];
391 
392 		r = amdgpu_ib_get(adev, NULL, 16, AMDGPU_IB_POOL_DIRECT, &ib);
393 		if (r) {
394 			DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
395 			goto err1;
396 		}
397 	}
398 
399 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
400 	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
401 	ib.ptr[2] = lower_32_bits(gpu_addr);
402 	ib.ptr[3] = upper_32_bits(gpu_addr);
403 	ib.ptr[4] = 0xDEADBEEF;
404 	ib.length_dw = 5;
405 
406 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
407 	if (r)
408 		goto err2;
409 
410 	r = dma_fence_wait_timeout(f, false, timeout);
411 	if (r == 0) {
412 		r = -ETIMEDOUT;
413 		goto err2;
414 	} else if (r < 0) {
415 		goto err2;
416 	}
417 
418 	if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
419 		r = 0;
420 	else
421 		r = -EINVAL;
422 err2:
423 	if (!ring->is_mes_queue)
424 		amdgpu_ib_free(adev, &ib, NULL);
425 	dma_fence_put(f);
426 err1:
427 	if (!ring->is_mes_queue)
428 		amdgpu_device_wb_free(adev, index);
429 	return r;
430 }
431 
432 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev)
433 {
434 	release_firmware(adev->gfx.pfp_fw);
435 	adev->gfx.pfp_fw = NULL;
436 	release_firmware(adev->gfx.me_fw);
437 	adev->gfx.me_fw = NULL;
438 	release_firmware(adev->gfx.rlc_fw);
439 	adev->gfx.rlc_fw = NULL;
440 	release_firmware(adev->gfx.mec_fw);
441 	adev->gfx.mec_fw = NULL;
442 
443 	kfree(adev->gfx.rlc.register_list_format);
444 }
445 
446 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
447 {
448 	char fw_name[40];
449 	char ucode_prefix[30];
450 	int err;
451 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
452 	uint16_t version_major;
453 	uint16_t version_minor;
454 
455 	DRM_DEBUG("\n");
456 
457 	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
458 
459 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix);
460 	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
461 	if (err)
462 		goto out;
463 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
464 	if (err)
465 		goto out;
466 	/* check pfp fw hdr version to decide if enable rs64 for gfx11.*/
467 	adev->gfx.rs64_enable = amdgpu_ucode_hdr_version(
468 				(union amdgpu_firmware_header *)
469 				adev->gfx.pfp_fw->data, 2, 0);
470 	if (adev->gfx.rs64_enable) {
471 		dev_info(adev->dev, "CP RS64 enable\n");
472 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
473 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
474 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK);
475 	} else {
476 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
477 	}
478 
479 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix);
480 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
481 	if (err)
482 		goto out;
483 	err = amdgpu_ucode_validate(adev->gfx.me_fw);
484 	if (err)
485 		goto out;
486 	if (adev->gfx.rs64_enable) {
487 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
488 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
489 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK);
490 	} else {
491 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
492 	}
493 
494 	if (!amdgpu_sriov_vf(adev)) {
495 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
496 		err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
497 		if (err)
498 			goto out;
499 		err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
500 		if (err)
501 			goto out;
502 		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
503 		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
504 		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
505 		err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
506 		if (err)
507 			goto out;
508 	}
509 
510 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix);
511 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
512 	if (err)
513 		goto out;
514 	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
515 	if (err)
516 		goto out;
517 	if (adev->gfx.rs64_enable) {
518 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
519 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
520 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
521 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK);
522 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK);
523 	} else {
524 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
525 		amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
526 	}
527 
528 	/* only one MEC for gfx 11.0.0. */
529 	adev->gfx.mec2_fw = NULL;
530 
531 out:
532 	if (err) {
533 		dev_err(adev->dev,
534 			"gfx11: Failed to init firmware \"%s\"\n",
535 			fw_name);
536 		release_firmware(adev->gfx.pfp_fw);
537 		adev->gfx.pfp_fw = NULL;
538 		release_firmware(adev->gfx.me_fw);
539 		adev->gfx.me_fw = NULL;
540 		release_firmware(adev->gfx.rlc_fw);
541 		adev->gfx.rlc_fw = NULL;
542 		release_firmware(adev->gfx.mec_fw);
543 		adev->gfx.mec_fw = NULL;
544 	}
545 
546 	return err;
547 }
548 
549 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev)
550 {
551 	const struct psp_firmware_header_v1_0 *toc_hdr;
552 	int err = 0;
553 	char fw_name[40];
554 	char ucode_prefix[30];
555 
556 	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
557 
558 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix);
559 	err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
560 	if (err)
561 		goto out;
562 
563 	err = amdgpu_ucode_validate(adev->psp.toc_fw);
564 	if (err)
565 		goto out;
566 
567 	toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
568 	adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
569 	adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
570 	adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
571 	adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
572 				le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
573 	return 0;
574 out:
575 	dev_err(adev->dev, "Failed to load TOC microcode\n");
576 	release_firmware(adev->psp.toc_fw);
577 	adev->psp.toc_fw = NULL;
578 	return err;
579 }
580 
581 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev)
582 {
583 	u32 count = 0;
584 	const struct cs_section_def *sect = NULL;
585 	const struct cs_extent_def *ext = NULL;
586 
587 	/* begin clear state */
588 	count += 2;
589 	/* context control state */
590 	count += 3;
591 
592 	for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
593 		for (ext = sect->section; ext->extent != NULL; ++ext) {
594 			if (sect->id == SECT_CONTEXT)
595 				count += 2 + ext->reg_count;
596 			else
597 				return 0;
598 		}
599 	}
600 
601 	/* set PA_SC_TILE_STEERING_OVERRIDE */
602 	count += 3;
603 	/* end clear state */
604 	count += 2;
605 	/* clear state */
606 	count += 2;
607 
608 	return count;
609 }
610 
611 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev,
612 				    volatile u32 *buffer)
613 {
614 	u32 count = 0, i;
615 	const struct cs_section_def *sect = NULL;
616 	const struct cs_extent_def *ext = NULL;
617 	int ctx_reg_offset;
618 
619 	if (adev->gfx.rlc.cs_data == NULL)
620 		return;
621 	if (buffer == NULL)
622 		return;
623 
624 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
625 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
626 
627 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
628 	buffer[count++] = cpu_to_le32(0x80000000);
629 	buffer[count++] = cpu_to_le32(0x80000000);
630 
631 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
632 		for (ext = sect->section; ext->extent != NULL; ++ext) {
633 			if (sect->id == SECT_CONTEXT) {
634 				buffer[count++] =
635 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
636 				buffer[count++] = cpu_to_le32(ext->reg_index -
637 						PACKET3_SET_CONTEXT_REG_START);
638 				for (i = 0; i < ext->reg_count; i++)
639 					buffer[count++] = cpu_to_le32(ext->extent[i]);
640 			} else {
641 				return;
642 			}
643 		}
644 	}
645 
646 	ctx_reg_offset =
647 		SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
648 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
649 	buffer[count++] = cpu_to_le32(ctx_reg_offset);
650 	buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
651 
652 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
653 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
654 
655 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
656 	buffer[count++] = cpu_to_le32(0);
657 }
658 
659 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev)
660 {
661 	/* clear state block */
662 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
663 			&adev->gfx.rlc.clear_state_gpu_addr,
664 			(void **)&adev->gfx.rlc.cs_ptr);
665 
666 	/* jump table block */
667 	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
668 			&adev->gfx.rlc.cp_table_gpu_addr,
669 			(void **)&adev->gfx.rlc.cp_table_ptr);
670 }
671 
672 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
673 {
674 	struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
675 
676 	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
677 	reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
678 	reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
679 	reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
680 	reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
681 	reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
682 	reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
683 	reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
684 	adev->gfx.rlc.rlcg_reg_access_supported = true;
685 }
686 
687 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev)
688 {
689 	const struct cs_section_def *cs_data;
690 	int r;
691 
692 	adev->gfx.rlc.cs_data = gfx11_cs_data;
693 
694 	cs_data = adev->gfx.rlc.cs_data;
695 
696 	if (cs_data) {
697 		/* init clear state block */
698 		r = amdgpu_gfx_rlc_init_csb(adev);
699 		if (r)
700 			return r;
701 	}
702 
703 	/* init spm vmid with 0xf */
704 	if (adev->gfx.rlc.funcs->update_spm_vmid)
705 		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
706 
707 	return 0;
708 }
709 
710 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev)
711 {
712 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
713 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
714 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
715 }
716 
717 static int gfx_v11_0_me_init(struct amdgpu_device *adev)
718 {
719 	int r;
720 
721 	bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
722 
723 	amdgpu_gfx_graphics_queue_acquire(adev);
724 
725 	r = gfx_v11_0_init_microcode(adev);
726 	if (r)
727 		DRM_ERROR("Failed to load gfx firmware!\n");
728 
729 	return r;
730 }
731 
732 static int gfx_v11_0_mec_init(struct amdgpu_device *adev)
733 {
734 	int r;
735 	u32 *hpd;
736 	size_t mec_hpd_size;
737 
738 	bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
739 
740 	/* take ownership of the relevant compute queues */
741 	amdgpu_gfx_compute_queue_acquire(adev);
742 	mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE;
743 
744 	if (mec_hpd_size) {
745 		r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
746 					      AMDGPU_GEM_DOMAIN_GTT,
747 					      &adev->gfx.mec.hpd_eop_obj,
748 					      &adev->gfx.mec.hpd_eop_gpu_addr,
749 					      (void **)&hpd);
750 		if (r) {
751 			dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
752 			gfx_v11_0_mec_fini(adev);
753 			return r;
754 		}
755 
756 		memset(hpd, 0, mec_hpd_size);
757 
758 		amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
759 		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
760 	}
761 
762 	return 0;
763 }
764 
765 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
766 {
767 	WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
768 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
769 		(address << SQ_IND_INDEX__INDEX__SHIFT));
770 	return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
771 }
772 
773 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
774 			   uint32_t thread, uint32_t regno,
775 			   uint32_t num, uint32_t *out)
776 {
777 	WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
778 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
779 		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
780 		(thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
781 		(SQ_IND_INDEX__AUTO_INCR_MASK));
782 	while (num--)
783 		*(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
784 }
785 
786 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
787 {
788 	/* in gfx11 the SIMD_ID is specified as part of the INSTANCE
789 	 * field when performing a select_se_sh so it should be
790 	 * zero here */
791 	WARN_ON(simd != 0);
792 
793 	/* type 3 wave data */
794 	dst[(*no_fields)++] = 3;
795 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
796 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
797 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
798 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
799 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
800 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
801 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
802 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
803 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
804 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
805 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
806 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
807 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
808 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
809 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
810 }
811 
812 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
813 				     uint32_t wave, uint32_t start,
814 				     uint32_t size, uint32_t *dst)
815 {
816 	WARN_ON(simd != 0);
817 
818 	wave_read_regs(
819 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
820 		dst);
821 }
822 
823 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
824 				      uint32_t wave, uint32_t thread,
825 				      uint32_t start, uint32_t size,
826 				      uint32_t *dst)
827 {
828 	wave_read_regs(
829 		adev, wave, thread,
830 		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
831 }
832 
833 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev,
834 									  u32 me, u32 pipe, u32 q, u32 vm)
835 {
836 	soc21_grbm_select(adev, me, pipe, q, vm);
837 }
838 
839 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
840 	.get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter,
841 	.select_se_sh = &gfx_v11_0_select_se_sh,
842 	.read_wave_data = &gfx_v11_0_read_wave_data,
843 	.read_wave_sgprs = &gfx_v11_0_read_wave_sgprs,
844 	.read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
845 	.select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,
846 	.update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,
847 };
848 
849 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
850 {
851 	adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
852 
853 	switch (adev->ip_versions[GC_HWIP][0]) {
854 	case IP_VERSION(11, 0, 0):
855 	case IP_VERSION(11, 0, 2):
856 	case IP_VERSION(11, 0, 3):
857 		adev->gfx.config.max_hw_contexts = 8;
858 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
859 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
860 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
861 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
862 		break;
863 	case IP_VERSION(11, 0, 1):
864 	case IP_VERSION(11, 0, 4):
865 		adev->gfx.config.max_hw_contexts = 8;
866 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
867 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
868 		adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
869 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300;
870 		break;
871 	default:
872 		BUG();
873 		break;
874 	}
875 
876 	return 0;
877 }
878 
879 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
880 				   int me, int pipe, int queue)
881 {
882 	int r;
883 	struct amdgpu_ring *ring;
884 	unsigned int irq_type;
885 
886 	ring = &adev->gfx.gfx_ring[ring_id];
887 
888 	ring->me = me;
889 	ring->pipe = pipe;
890 	ring->queue = queue;
891 
892 	ring->ring_obj = NULL;
893 	ring->use_doorbell = true;
894 
895 	if (!ring_id)
896 		ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
897 	else
898 		ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
899 	snprintf(ring->name, sizeof(ring->name), "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
900 
901 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
902 	r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
903 			     AMDGPU_RING_PRIO_DEFAULT, NULL);
904 	if (r)
905 		return r;
906 	return 0;
907 }
908 
909 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
910 				       int mec, int pipe, int queue)
911 {
912 	int r;
913 	unsigned irq_type;
914 	struct amdgpu_ring *ring;
915 	unsigned int hw_prio;
916 
917 	ring = &adev->gfx.compute_ring[ring_id];
918 
919 	/* mec0 is me1 */
920 	ring->me = mec + 1;
921 	ring->pipe = pipe;
922 	ring->queue = queue;
923 
924 	ring->ring_obj = NULL;
925 	ring->use_doorbell = true;
926 	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
927 	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
928 				+ (ring_id * GFX11_MEC_HPD_SIZE);
929 	snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
930 
931 	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
932 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
933 		+ ring->pipe;
934 	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
935 			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
936 	/* type-2 packets are deprecated on MEC, use type-3 instead */
937 	r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
938 			     hw_prio, NULL);
939 	if (r)
940 		return r;
941 
942 	return 0;
943 }
944 
945 static struct {
946 	SOC21_FIRMWARE_ID	id;
947 	unsigned int		offset;
948 	unsigned int		size;
949 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX];
950 
951 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)
952 {
953 	RLC_TABLE_OF_CONTENT *ucode = rlc_toc;
954 
955 	while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) &&
956 			(ucode->id < SOC21_FIRMWARE_ID_MAX)) {
957 		rlc_autoload_info[ucode->id].id = ucode->id;
958 		rlc_autoload_info[ucode->id].offset = ucode->offset * 4;
959 		rlc_autoload_info[ucode->id].size = ucode->size * 4;
960 
961 		ucode++;
962 	}
963 }
964 
965 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev)
966 {
967 	uint32_t total_size = 0;
968 	SOC21_FIRMWARE_ID id;
969 
970 	gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr);
971 
972 	for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++)
973 		total_size += rlc_autoload_info[id].size;
974 
975 	/* In case the offset in rlc toc ucode is aligned */
976 	if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset)
977 		total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset +
978 			rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size;
979 
980 	return total_size;
981 }
982 
983 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)
984 {
985 	int r;
986 	uint32_t total_size;
987 
988 	total_size = gfx_v11_0_calc_toc_total_size(adev);
989 
990 	r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
991 			AMDGPU_GEM_DOMAIN_VRAM,
992 			&adev->gfx.rlc.rlc_autoload_bo,
993 			&adev->gfx.rlc.rlc_autoload_gpu_addr,
994 			(void **)&adev->gfx.rlc.rlc_autoload_ptr);
995 
996 	if (r) {
997 		dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
998 		return r;
999 	}
1000 
1001 	return 0;
1002 }
1003 
1004 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1005 					      SOC21_FIRMWARE_ID id,
1006 			    		      const void *fw_data,
1007 					      uint32_t fw_size,
1008 					      uint32_t *fw_autoload_mask)
1009 {
1010 	uint32_t toc_offset;
1011 	uint32_t toc_fw_size;
1012 	char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1013 
1014 	if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX)
1015 		return;
1016 
1017 	toc_offset = rlc_autoload_info[id].offset;
1018 	toc_fw_size = rlc_autoload_info[id].size;
1019 
1020 	if (fw_size == 0)
1021 		fw_size = toc_fw_size;
1022 
1023 	if (fw_size > toc_fw_size)
1024 		fw_size = toc_fw_size;
1025 
1026 	memcpy(ptr + toc_offset, fw_data, fw_size);
1027 
1028 	if (fw_size < toc_fw_size)
1029 		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
1030 
1031 	if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME))
1032 		*(uint64_t *)fw_autoload_mask |= 1ULL << id;
1033 }
1034 
1035 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev,
1036 							uint32_t *fw_autoload_mask)
1037 {
1038 	void *data;
1039 	uint32_t size;
1040 	uint64_t *toc_ptr;
1041 
1042 	*(uint64_t *)fw_autoload_mask |= 0x1;
1043 
1044 	DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask);
1045 
1046 	data = adev->psp.toc.start_addr;
1047 	size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size;
1048 
1049 	toc_ptr = (uint64_t *)data + size / 8 - 1;
1050 	*toc_ptr = *(uint64_t *)fw_autoload_mask;
1051 
1052 	gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC,
1053 					data, size, fw_autoload_mask);
1054 }
1055 
1056 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev,
1057 							uint32_t *fw_autoload_mask)
1058 {
1059 	const __le32 *fw_data;
1060 	uint32_t fw_size;
1061 	const struct gfx_firmware_header_v1_0 *cp_hdr;
1062 	const struct gfx_firmware_header_v2_0 *cpv2_hdr;
1063 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
1064 	const struct rlc_firmware_header_v2_2 *rlcv22_hdr;
1065 	uint16_t version_major, version_minor;
1066 
1067 	if (adev->gfx.rs64_enable) {
1068 		/* pfp ucode */
1069 		cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1070 			adev->gfx.pfp_fw->data;
1071 		/* instruction */
1072 		fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1073 			le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1074 		fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1075 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP,
1076 						fw_data, fw_size, fw_autoload_mask);
1077 		/* data */
1078 		fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1079 			le32_to_cpu(cpv2_hdr->data_offset_bytes));
1080 		fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1081 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK,
1082 						fw_data, fw_size, fw_autoload_mask);
1083 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK,
1084 						fw_data, fw_size, fw_autoload_mask);
1085 		/* me ucode */
1086 		cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1087 			adev->gfx.me_fw->data;
1088 		/* instruction */
1089 		fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1090 			le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1091 		fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1092 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME,
1093 						fw_data, fw_size, fw_autoload_mask);
1094 		/* data */
1095 		fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1096 			le32_to_cpu(cpv2_hdr->data_offset_bytes));
1097 		fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1098 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK,
1099 						fw_data, fw_size, fw_autoload_mask);
1100 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK,
1101 						fw_data, fw_size, fw_autoload_mask);
1102 		/* mec ucode */
1103 		cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1104 			adev->gfx.mec_fw->data;
1105 		/* instruction */
1106 		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1107 			le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1108 		fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1109 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC,
1110 						fw_data, fw_size, fw_autoload_mask);
1111 		/* data */
1112 		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1113 			le32_to_cpu(cpv2_hdr->data_offset_bytes));
1114 		fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1115 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK,
1116 						fw_data, fw_size, fw_autoload_mask);
1117 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK,
1118 						fw_data, fw_size, fw_autoload_mask);
1119 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK,
1120 						fw_data, fw_size, fw_autoload_mask);
1121 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK,
1122 						fw_data, fw_size, fw_autoload_mask);
1123 	} else {
1124 		/* pfp ucode */
1125 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1126 			adev->gfx.pfp_fw->data;
1127 		fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1128 				le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1129 		fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1130 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP,
1131 						fw_data, fw_size, fw_autoload_mask);
1132 
1133 		/* me ucode */
1134 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1135 			adev->gfx.me_fw->data;
1136 		fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1137 				le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1138 		fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1139 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME,
1140 						fw_data, fw_size, fw_autoload_mask);
1141 
1142 		/* mec ucode */
1143 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1144 			adev->gfx.mec_fw->data;
1145 		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1146 				le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1147 		fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1148 			cp_hdr->jt_size * 4;
1149 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC,
1150 						fw_data, fw_size, fw_autoload_mask);
1151 	}
1152 
1153 	/* rlc ucode */
1154 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
1155 		adev->gfx.rlc_fw->data;
1156 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1157 			le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
1158 	fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
1159 	gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE,
1160 					fw_data, fw_size, fw_autoload_mask);
1161 
1162 	version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1163 	version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1164 	if (version_major == 2) {
1165 		if (version_minor >= 2) {
1166 			rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1167 
1168 			fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1169 					le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes));
1170 			fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes);
1171 			gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE,
1172 					fw_data, fw_size, fw_autoload_mask);
1173 
1174 			fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1175 					le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes));
1176 			fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes);
1177 			gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT,
1178 					fw_data, fw_size, fw_autoload_mask);
1179 		}
1180 	}
1181 }
1182 
1183 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev,
1184 							uint32_t *fw_autoload_mask)
1185 {
1186 	const __le32 *fw_data;
1187 	uint32_t fw_size;
1188 	const struct sdma_firmware_header_v2_0 *sdma_hdr;
1189 
1190 	sdma_hdr = (const struct sdma_firmware_header_v2_0 *)
1191 		adev->sdma.instance[0].fw->data;
1192 	fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1193 			le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
1194 	fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
1195 
1196 	gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1197 			SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask);
1198 
1199 	fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1200 			le32_to_cpu(sdma_hdr->ctl_ucode_offset));
1201 	fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
1202 
1203 	gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1204 			SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask);
1205 }
1206 
1207 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev,
1208 							uint32_t *fw_autoload_mask)
1209 {
1210 	const __le32 *fw_data;
1211 	unsigned fw_size;
1212 	const struct mes_firmware_header_v1_0 *mes_hdr;
1213 	int pipe, ucode_id, data_id;
1214 
1215 	for (pipe = 0; pipe < 2; pipe++) {
1216 		if (pipe==0) {
1217 			ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0;
1218 			data_id  = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK;
1219 		} else {
1220 			ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1;
1221 			data_id  = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK;
1222 		}
1223 
1224 		mes_hdr = (const struct mes_firmware_header_v1_0 *)
1225 			adev->mes.fw[pipe]->data;
1226 
1227 		fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1228 				le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1229 		fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1230 
1231 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1232 				ucode_id, fw_data, fw_size, fw_autoload_mask);
1233 
1234 		fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1235 				le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1236 		fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1237 
1238 		gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1239 				data_id, fw_data, fw_size, fw_autoload_mask);
1240 	}
1241 }
1242 
1243 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
1244 {
1245 	uint32_t rlc_g_offset, rlc_g_size;
1246 	uint64_t gpu_addr;
1247 	uint32_t autoload_fw_id[2];
1248 
1249 	memset(autoload_fw_id, 0, sizeof(uint32_t) * 2);
1250 
1251 	/* RLC autoload sequence 2: copy ucode */
1252 	gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id);
1253 	gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id);
1254 	gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id);
1255 	gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id);
1256 
1257 	rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset;
1258 	rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size;
1259 	gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
1260 
1261 	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1262 	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1263 
1264 	WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1265 
1266 	/* RLC autoload sequence 3: load IMU fw */
1267 	if (adev->gfx.imu.funcs->load_microcode)
1268 		adev->gfx.imu.funcs->load_microcode(adev);
1269 	/* RLC autoload sequence 4 init IMU fw */
1270 	if (adev->gfx.imu.funcs->setup_imu)
1271 		adev->gfx.imu.funcs->setup_imu(adev);
1272 	if (adev->gfx.imu.funcs->start_imu)
1273 		adev->gfx.imu.funcs->start_imu(adev);
1274 
1275 	/* RLC autoload sequence 5 disable gpa mode */
1276 	gfx_v11_0_disable_gpa_mode(adev);
1277 
1278 	return 0;
1279 }
1280 
1281 static int gfx_v11_0_sw_init(void *handle)
1282 {
1283 	int i, j, k, r, ring_id = 0;
1284 	struct amdgpu_kiq *kiq;
1285 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1286 
1287 	adev->gfxhub.funcs->init(adev);
1288 
1289 	switch (adev->ip_versions[GC_HWIP][0]) {
1290 	case IP_VERSION(11, 0, 0):
1291 	case IP_VERSION(11, 0, 2):
1292 	case IP_VERSION(11, 0, 3):
1293 		adev->gfx.me.num_me = 1;
1294 		adev->gfx.me.num_pipe_per_me = 1;
1295 		adev->gfx.me.num_queue_per_pipe = 1;
1296 		adev->gfx.mec.num_mec = 2;
1297 		adev->gfx.mec.num_pipe_per_mec = 4;
1298 		adev->gfx.mec.num_queue_per_pipe = 4;
1299 		break;
1300 	case IP_VERSION(11, 0, 1):
1301 	case IP_VERSION(11, 0, 4):
1302 		adev->gfx.me.num_me = 1;
1303 		adev->gfx.me.num_pipe_per_me = 1;
1304 		adev->gfx.me.num_queue_per_pipe = 1;
1305 		adev->gfx.mec.num_mec = 1;
1306 		adev->gfx.mec.num_pipe_per_mec = 4;
1307 		adev->gfx.mec.num_queue_per_pipe = 4;
1308 		break;
1309 	default:
1310 		adev->gfx.me.num_me = 1;
1311 		adev->gfx.me.num_pipe_per_me = 1;
1312 		adev->gfx.me.num_queue_per_pipe = 1;
1313 		adev->gfx.mec.num_mec = 1;
1314 		adev->gfx.mec.num_pipe_per_mec = 4;
1315 		adev->gfx.mec.num_queue_per_pipe = 8;
1316 		break;
1317 	}
1318 
1319 	/* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */
1320 	if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3) &&
1321 		amdgpu_sriov_is_pp_one_vf(adev))
1322 		adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG;
1323 
1324 	/* EOP Event */
1325 	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1326 			      GFX_11_0_0__SRCID__CP_EOP_INTERRUPT,
1327 			      &adev->gfx.eop_irq);
1328 	if (r)
1329 		return r;
1330 
1331 	/* Privileged reg */
1332 	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1333 			      GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT,
1334 			      &adev->gfx.priv_reg_irq);
1335 	if (r)
1336 		return r;
1337 
1338 	/* Privileged inst */
1339 	r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1340 			      GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1341 			      &adev->gfx.priv_inst_irq);
1342 	if (r)
1343 		return r;
1344 
1345 	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1346 
1347 	if (adev->gfx.imu.funcs) {
1348 		if (adev->gfx.imu.funcs->init_microcode) {
1349 			r = adev->gfx.imu.funcs->init_microcode(adev);
1350 			if (r)
1351 				DRM_ERROR("Failed to load imu firmware!\n");
1352 		}
1353 	}
1354 
1355 	r = gfx_v11_0_me_init(adev);
1356 	if (r)
1357 		return r;
1358 
1359 	r = gfx_v11_0_rlc_init(adev);
1360 	if (r) {
1361 		DRM_ERROR("Failed to init rlc BOs!\n");
1362 		return r;
1363 	}
1364 
1365 	r = gfx_v11_0_mec_init(adev);
1366 	if (r) {
1367 		DRM_ERROR("Failed to init MEC BOs!\n");
1368 		return r;
1369 	}
1370 
1371 	/* set up the gfx ring */
1372 	for (i = 0; i < adev->gfx.me.num_me; i++) {
1373 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1374 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1375 				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1376 					continue;
1377 
1378 				r = gfx_v11_0_gfx_ring_init(adev, ring_id,
1379 							    i, k, j);
1380 				if (r)
1381 					return r;
1382 				ring_id++;
1383 			}
1384 		}
1385 	}
1386 
1387 	ring_id = 0;
1388 	/* set up the compute queues - allocate horizontally across pipes */
1389 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1390 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1391 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1392 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1393 								     j))
1394 					continue;
1395 
1396 				r = gfx_v11_0_compute_ring_init(adev, ring_id,
1397 								i, k, j);
1398 				if (r)
1399 					return r;
1400 
1401 				ring_id++;
1402 			}
1403 		}
1404 	}
1405 
1406 	if (!adev->enable_mes_kiq) {
1407 		r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE);
1408 		if (r) {
1409 			DRM_ERROR("Failed to init KIQ BOs!\n");
1410 			return r;
1411 		}
1412 
1413 		kiq = &adev->gfx.kiq;
1414 		r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1415 		if (r)
1416 			return r;
1417 	}
1418 
1419 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd));
1420 	if (r)
1421 		return r;
1422 
1423 	/* allocate visible FB for rlc auto-loading fw */
1424 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1425 		r = gfx_v11_0_init_toc_microcode(adev);
1426 		if (r)
1427 			dev_err(adev->dev, "Failed to load toc firmware!\n");
1428 		r = gfx_v11_0_rlc_autoload_buffer_init(adev);
1429 		if (r)
1430 			return r;
1431 	}
1432 
1433 	r = gfx_v11_0_gpu_early_init(adev);
1434 	if (r)
1435 		return r;
1436 
1437 	return 0;
1438 }
1439 
1440 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev)
1441 {
1442 	amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1443 			      &adev->gfx.pfp.pfp_fw_gpu_addr,
1444 			      (void **)&adev->gfx.pfp.pfp_fw_ptr);
1445 
1446 	amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1447 			      &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1448 			      (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1449 }
1450 
1451 static void gfx_v11_0_me_fini(struct amdgpu_device *adev)
1452 {
1453 	amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1454 			      &adev->gfx.me.me_fw_gpu_addr,
1455 			      (void **)&adev->gfx.me.me_fw_ptr);
1456 
1457 	amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1458 			       &adev->gfx.me.me_fw_data_gpu_addr,
1459 			       (void **)&adev->gfx.me.me_fw_data_ptr);
1460 }
1461 
1462 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)
1463 {
1464 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1465 			&adev->gfx.rlc.rlc_autoload_gpu_addr,
1466 			(void **)&adev->gfx.rlc.rlc_autoload_ptr);
1467 }
1468 
1469 static int gfx_v11_0_sw_fini(void *handle)
1470 {
1471 	int i;
1472 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1473 
1474 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1475 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1476 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
1477 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1478 
1479 	amdgpu_gfx_mqd_sw_fini(adev);
1480 
1481 	if (!adev->enable_mes_kiq) {
1482 		amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
1483 		amdgpu_gfx_kiq_fini(adev);
1484 	}
1485 
1486 	gfx_v11_0_pfp_fini(adev);
1487 	gfx_v11_0_me_fini(adev);
1488 	gfx_v11_0_rlc_fini(adev);
1489 	gfx_v11_0_mec_fini(adev);
1490 
1491 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1492 		gfx_v11_0_rlc_autoload_buffer_fini(adev);
1493 
1494 	gfx_v11_0_free_microcode(adev);
1495 
1496 	return 0;
1497 }
1498 
1499 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1500 				   u32 sh_num, u32 instance)
1501 {
1502 	u32 data;
1503 
1504 	if (instance == 0xffffffff)
1505 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1506 				     INSTANCE_BROADCAST_WRITES, 1);
1507 	else
1508 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1509 				     instance);
1510 
1511 	if (se_num == 0xffffffff)
1512 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1513 				     1);
1514 	else
1515 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1516 
1517 	if (sh_num == 0xffffffff)
1518 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1519 				     1);
1520 	else
1521 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1522 
1523 	WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1524 }
1525 
1526 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1527 {
1528 	u32 data, mask;
1529 
1530 	data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1531 	data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1532 
1533 	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1534 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1535 
1536 	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1537 					 adev->gfx.config.max_sh_per_se);
1538 
1539 	return (~data) & mask;
1540 }
1541 
1542 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev)
1543 {
1544 	int i, j;
1545 	u32 data;
1546 	u32 active_rbs = 0;
1547 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1548 					adev->gfx.config.max_sh_per_se;
1549 
1550 	mutex_lock(&adev->grbm_idx_mutex);
1551 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1552 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1553 			gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff);
1554 			data = gfx_v11_0_get_rb_active_bitmap(adev);
1555 			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1556 					       rb_bitmap_width_per_sh);
1557 		}
1558 	}
1559 	gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1560 	mutex_unlock(&adev->grbm_idx_mutex);
1561 
1562 	adev->gfx.config.backend_enable_mask = active_rbs;
1563 	adev->gfx.config.num_rbs = hweight32(active_rbs);
1564 }
1565 
1566 #define DEFAULT_SH_MEM_BASES	(0x6000)
1567 #define LDS_APP_BASE           0x1
1568 #define SCRATCH_APP_BASE       0x2
1569 
1570 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev)
1571 {
1572 	int i;
1573 	uint32_t sh_mem_bases;
1574 	uint32_t data;
1575 
1576 	/*
1577 	 * Configure apertures:
1578 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1579 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1580 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1581 	 */
1582 	sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) |
1583 			SCRATCH_APP_BASE;
1584 
1585 	mutex_lock(&adev->srbm_mutex);
1586 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1587 		soc21_grbm_select(adev, 0, 0, 0, i);
1588 		/* CP and shaders */
1589 		WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1590 		WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1591 
1592 		/* Enable trap for each kfd vmid. */
1593 		data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1594 		data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1595 	}
1596 	soc21_grbm_select(adev, 0, 0, 0, 0);
1597 	mutex_unlock(&adev->srbm_mutex);
1598 
1599 	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
1600 	   acccess. These should be enabled by FW for target VMIDs. */
1601 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1602 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);
1603 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);
1604 		WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0);
1605 		WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0);
1606 	}
1607 }
1608 
1609 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev)
1610 {
1611 	int vmid;
1612 
1613 	/*
1614 	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1615 	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
1616 	 * the driver can enable them for graphics. VMID0 should maintain
1617 	 * access so that HWS firmware can save/restore entries.
1618 	 */
1619 	for (vmid = 1; vmid < 16; vmid++) {
1620 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0);
1621 		WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0);
1622 		WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0);
1623 		WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0);
1624 	}
1625 }
1626 
1627 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev)
1628 {
1629 	/* TODO: harvest feature to be added later. */
1630 }
1631 
1632 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev)
1633 {
1634 	/* TCCs are global (not instanced). */
1635 	uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) |
1636 			       RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE);
1637 
1638 	adev->gfx.config.tcc_disabled_mask =
1639 		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1640 		(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1641 }
1642 
1643 static void gfx_v11_0_constants_init(struct amdgpu_device *adev)
1644 {
1645 	u32 tmp;
1646 	int i;
1647 
1648 	WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1649 
1650 	gfx_v11_0_setup_rb(adev);
1651 	gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info);
1652 	gfx_v11_0_get_tcc_info(adev);
1653 	adev->gfx.config.pa_sc_tile_steering_override = 0;
1654 
1655 	/* XXX SH_MEM regs */
1656 	/* where to put LDS, scratch, GPUVM in FSA64 space */
1657 	mutex_lock(&adev->srbm_mutex);
1658 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
1659 		soc21_grbm_select(adev, 0, 0, 0, i);
1660 		/* CP and shaders */
1661 		WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1662 		if (i != 0) {
1663 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1664 				(adev->gmc.private_aperture_start >> 48));
1665 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1666 				(adev->gmc.shared_aperture_start >> 48));
1667 			WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
1668 		}
1669 	}
1670 	soc21_grbm_select(adev, 0, 0, 0, 0);
1671 
1672 	mutex_unlock(&adev->srbm_mutex);
1673 
1674 	gfx_v11_0_init_compute_vmid(adev);
1675 	gfx_v11_0_init_gds_vmid(adev);
1676 }
1677 
1678 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1679 					       bool enable)
1680 {
1681 	u32 tmp;
1682 
1683 	if (amdgpu_sriov_vf(adev))
1684 		return;
1685 
1686 	tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0);
1687 
1688 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1689 			    enable ? 1 : 0);
1690 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1691 			    enable ? 1 : 0);
1692 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1693 			    enable ? 1 : 0);
1694 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1695 			    enable ? 1 : 0);
1696 
1697 	WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);
1698 }
1699 
1700 static int gfx_v11_0_init_csb(struct amdgpu_device *adev)
1701 {
1702 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1703 
1704 	WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
1705 			adev->gfx.rlc.clear_state_gpu_addr >> 32);
1706 	WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
1707 			adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1708 	WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1709 
1710 	return 0;
1711 }
1712 
1713 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev)
1714 {
1715 	u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
1716 
1717 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1718 	WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
1719 }
1720 
1721 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev)
1722 {
1723 	WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1724 	udelay(50);
1725 	WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1726 	udelay(50);
1727 }
1728 
1729 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1730 					     bool enable)
1731 {
1732 	uint32_t rlc_pg_cntl;
1733 
1734 	rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
1735 
1736 	if (!enable) {
1737 		/* RLC_PG_CNTL[23] = 0 (default)
1738 		 * RLC will wait for handshake acks with SMU
1739 		 * GFXOFF will be enabled
1740 		 * RLC_PG_CNTL[23] = 1
1741 		 * RLC will not issue any message to SMU
1742 		 * hence no handshake between SMU & RLC
1743 		 * GFXOFF will be disabled
1744 		 */
1745 		rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1746 	} else
1747 		rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1748 	WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
1749 }
1750 
1751 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev)
1752 {
1753 	/* TODO: enable rlc & smu handshake until smu
1754 	 * and gfxoff feature works as expected */
1755 	if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1756 		gfx_v11_0_rlc_smu_handshake_cntl(adev, false);
1757 
1758 	WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1759 	udelay(50);
1760 }
1761 
1762 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev)
1763 {
1764 	uint32_t tmp;
1765 
1766 	/* enable Save Restore Machine */
1767 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
1768 	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1769 	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1770 	WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
1771 }
1772 
1773 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev)
1774 {
1775 	const struct rlc_firmware_header_v2_0 *hdr;
1776 	const __le32 *fw_data;
1777 	unsigned i, fw_size;
1778 
1779 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1780 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1781 			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1782 	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1783 
1784 	WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
1785 		     RLCG_UCODE_LOADING_START_ADDRESS);
1786 
1787 	for (i = 0; i < fw_size; i++)
1788 		WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
1789 			     le32_to_cpup(fw_data++));
1790 
1791 	WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1792 }
1793 
1794 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)
1795 {
1796 	const struct rlc_firmware_header_v2_2 *hdr;
1797 	const __le32 *fw_data;
1798 	unsigned i, fw_size;
1799 	u32 tmp;
1800 
1801 	hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1802 
1803 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1804 			le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes));
1805 	fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4;
1806 
1807 	WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
1808 
1809 	for (i = 0; i < fw_size; i++) {
1810 		if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1811 			drm_msleep(1);
1812 		WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
1813 				le32_to_cpup(fw_data++));
1814 	}
1815 
1816 	WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1817 
1818 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1819 			le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes));
1820 	fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4;
1821 
1822 	WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
1823 	for (i = 0; i < fw_size; i++) {
1824 		if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1825 			drm_msleep(1);
1826 		WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
1827 				le32_to_cpup(fw_data++));
1828 	}
1829 
1830 	WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1831 
1832 	tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
1833 	tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
1834 	tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
1835 	WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
1836 }
1837 
1838 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev)
1839 {
1840 	const struct rlc_firmware_header_v2_3 *hdr;
1841 	const __le32 *fw_data;
1842 	unsigned i, fw_size;
1843 	u32 tmp;
1844 
1845 	hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;
1846 
1847 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1848 			le32_to_cpu(hdr->rlcp_ucode_offset_bytes));
1849 	fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4;
1850 
1851 	WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0);
1852 
1853 	for (i = 0; i < fw_size; i++) {
1854 		if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1855 			drm_msleep(1);
1856 		WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA,
1857 				le32_to_cpup(fw_data++));
1858 	}
1859 
1860 	WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version);
1861 
1862 	tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
1863 	tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1864 	WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp);
1865 
1866 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1867 			le32_to_cpu(hdr->rlcv_ucode_offset_bytes));
1868 	fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4;
1869 
1870 	WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0);
1871 
1872 	for (i = 0; i < fw_size; i++) {
1873 		if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1874 			drm_msleep(1);
1875 		WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA,
1876 				le32_to_cpup(fw_data++));
1877 	}
1878 
1879 	WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version);
1880 
1881 	tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL);
1882 	tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1);
1883 	WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp);
1884 }
1885 
1886 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
1887 {
1888 	const struct rlc_firmware_header_v2_0 *hdr;
1889 	uint16_t version_major;
1890 	uint16_t version_minor;
1891 
1892 	if (!adev->gfx.rlc_fw)
1893 		return -EINVAL;
1894 
1895 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1896 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
1897 
1898 	version_major = le16_to_cpu(hdr->header.header_version_major);
1899 	version_minor = le16_to_cpu(hdr->header.header_version_minor);
1900 
1901 	if (version_major == 2) {
1902 		gfx_v11_0_load_rlcg_microcode(adev);
1903 		if (amdgpu_dpm == 1) {
1904 			if (version_minor >= 2)
1905 				gfx_v11_0_load_rlc_iram_dram_microcode(adev);
1906 			if (version_minor == 3)
1907 				gfx_v11_0_load_rlcp_rlcv_microcode(adev);
1908 		}
1909 
1910 		return 0;
1911 	}
1912 
1913 	return -EINVAL;
1914 }
1915 
1916 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev)
1917 {
1918 	int r;
1919 
1920 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1921 		gfx_v11_0_init_csb(adev);
1922 
1923 		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
1924 			gfx_v11_0_rlc_enable_srm(adev);
1925 	} else {
1926 		if (amdgpu_sriov_vf(adev)) {
1927 			gfx_v11_0_init_csb(adev);
1928 			return 0;
1929 		}
1930 
1931 		adev->gfx.rlc.funcs->stop(adev);
1932 
1933 		/* disable CG */
1934 		WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
1935 
1936 		/* disable PG */
1937 		WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
1938 
1939 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
1940 			/* legacy rlc firmware loading */
1941 			r = gfx_v11_0_rlc_load_microcode(adev);
1942 			if (r)
1943 				return r;
1944 		}
1945 
1946 		gfx_v11_0_init_csb(adev);
1947 
1948 		adev->gfx.rlc.funcs->start(adev);
1949 	}
1950 	return 0;
1951 }
1952 
1953 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr)
1954 {
1955 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
1956 	uint32_t tmp;
1957 	int i;
1958 
1959 	/* Trigger an invalidation of the L1 instruction caches */
1960 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
1961 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
1962 	WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
1963 
1964 	/* Wait for invalidation complete */
1965 	for (i = 0; i < usec_timeout; i++) {
1966 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
1967 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
1968 					INVALIDATE_CACHE_COMPLETE))
1969 			break;
1970 		udelay(1);
1971 	}
1972 
1973 	if (i >= usec_timeout) {
1974 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
1975 		return -EINVAL;
1976 	}
1977 
1978 	if (amdgpu_emu_mode == 1)
1979 		adev->hdp.funcs->flush_hdp(adev, NULL);
1980 
1981 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
1982 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
1983 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
1984 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
1985 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
1986 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
1987 
1988 	/* Program me ucode address into intruction cache address register */
1989 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
1990 			lower_32_bits(addr) & 0xFFFFF000);
1991 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
1992 			upper_32_bits(addr));
1993 
1994 	return 0;
1995 }
1996 
1997 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr)
1998 {
1999 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2000 	uint32_t tmp;
2001 	int i;
2002 
2003 	/* Trigger an invalidation of the L1 instruction caches */
2004 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2005 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2006 	WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2007 
2008 	/* Wait for invalidation complete */
2009 	for (i = 0; i < usec_timeout; i++) {
2010 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2011 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2012 					INVALIDATE_CACHE_COMPLETE))
2013 			break;
2014 		udelay(1);
2015 	}
2016 
2017 	if (i >= usec_timeout) {
2018 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2019 		return -EINVAL;
2020 	}
2021 
2022 	if (amdgpu_emu_mode == 1)
2023 		adev->hdp.funcs->flush_hdp(adev, NULL);
2024 
2025 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2026 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2027 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2028 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2029 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2030 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2031 
2032 	/* Program pfp ucode address into intruction cache address register */
2033 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2034 			lower_32_bits(addr) & 0xFFFFF000);
2035 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2036 			upper_32_bits(addr));
2037 
2038 	return 0;
2039 }
2040 
2041 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr)
2042 {
2043 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2044 	uint32_t tmp;
2045 	int i;
2046 
2047 	/* Trigger an invalidation of the L1 instruction caches */
2048 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2049 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2050 
2051 	WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2052 
2053 	/* Wait for invalidation complete */
2054 	for (i = 0; i < usec_timeout; i++) {
2055 		tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2056 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2057 					INVALIDATE_CACHE_COMPLETE))
2058 			break;
2059 		udelay(1);
2060 	}
2061 
2062 	if (i >= usec_timeout) {
2063 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2064 		return -EINVAL;
2065 	}
2066 
2067 	if (amdgpu_emu_mode == 1)
2068 		adev->hdp.funcs->flush_hdp(adev, NULL);
2069 
2070 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2071 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2072 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2073 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2074 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2075 
2076 	/* Program mec1 ucode address into intruction cache address register */
2077 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2078 			lower_32_bits(addr) & 0xFFFFF000);
2079 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2080 			upper_32_bits(addr));
2081 
2082 	return 0;
2083 }
2084 
2085 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2086 {
2087 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2088 	uint32_t tmp;
2089 	unsigned i, pipe_id;
2090 	const struct gfx_firmware_header_v2_0 *pfp_hdr;
2091 
2092 	pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2093 		adev->gfx.pfp_fw->data;
2094 
2095 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2096 		lower_32_bits(addr));
2097 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2098 		upper_32_bits(addr));
2099 
2100 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2101 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2102 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2103 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2104 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2105 
2106 	/*
2107 	 * Programming any of the CP_PFP_IC_BASE registers
2108 	 * forces invalidation of the ME L1 I$. Wait for the
2109 	 * invalidation complete
2110 	 */
2111 	for (i = 0; i < usec_timeout; i++) {
2112 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2113 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2114 			INVALIDATE_CACHE_COMPLETE))
2115 			break;
2116 		udelay(1);
2117 	}
2118 
2119 	if (i >= usec_timeout) {
2120 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2121 		return -EINVAL;
2122 	}
2123 
2124 	/* Prime the L1 instruction caches */
2125 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2126 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2127 	WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2128 	/* Waiting for cache primed*/
2129 	for (i = 0; i < usec_timeout; i++) {
2130 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2131 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2132 			ICACHE_PRIMED))
2133 			break;
2134 		udelay(1);
2135 	}
2136 
2137 	if (i >= usec_timeout) {
2138 		dev_err(adev->dev, "failed to prime instruction cache\n");
2139 		return -EINVAL;
2140 	}
2141 
2142 	mutex_lock(&adev->srbm_mutex);
2143 	for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2144 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2145 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2146 			(pfp_hdr->ucode_start_addr_hi << 30) |
2147 			(pfp_hdr->ucode_start_addr_lo >> 2));
2148 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2149 			pfp_hdr->ucode_start_addr_hi >> 2);
2150 
2151 		/*
2152 		 * Program CP_ME_CNTL to reset given PIPE to take
2153 		 * effect of CP_PFP_PRGRM_CNTR_START.
2154 		 */
2155 		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2156 		if (pipe_id == 0)
2157 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2158 					PFP_PIPE0_RESET, 1);
2159 		else
2160 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2161 					PFP_PIPE1_RESET, 1);
2162 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2163 
2164 		/* Clear pfp pipe0 reset bit. */
2165 		if (pipe_id == 0)
2166 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2167 					PFP_PIPE0_RESET, 0);
2168 		else
2169 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2170 					PFP_PIPE1_RESET, 0);
2171 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2172 
2173 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2174 			lower_32_bits(addr2));
2175 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2176 			upper_32_bits(addr2));
2177 	}
2178 	soc21_grbm_select(adev, 0, 0, 0, 0);
2179 	mutex_unlock(&adev->srbm_mutex);
2180 
2181 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2182 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2183 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2184 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2185 
2186 	/* Invalidate the data caches */
2187 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2188 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2189 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2190 
2191 	for (i = 0; i < usec_timeout; i++) {
2192 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2193 		if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2194 			INVALIDATE_DCACHE_COMPLETE))
2195 			break;
2196 		udelay(1);
2197 	}
2198 
2199 	if (i >= usec_timeout) {
2200 		dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2201 		return -EINVAL;
2202 	}
2203 
2204 	return 0;
2205 }
2206 
2207 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2208 {
2209 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2210 	uint32_t tmp;
2211 	unsigned i, pipe_id;
2212 	const struct gfx_firmware_header_v2_0 *me_hdr;
2213 
2214 	me_hdr = (const struct gfx_firmware_header_v2_0 *)
2215 		adev->gfx.me_fw->data;
2216 
2217 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2218 		lower_32_bits(addr));
2219 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2220 		upper_32_bits(addr));
2221 
2222 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2223 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2224 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2225 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2226 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2227 
2228 	/*
2229 	 * Programming any of the CP_ME_IC_BASE registers
2230 	 * forces invalidation of the ME L1 I$. Wait for the
2231 	 * invalidation complete
2232 	 */
2233 	for (i = 0; i < usec_timeout; i++) {
2234 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2235 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2236 			INVALIDATE_CACHE_COMPLETE))
2237 			break;
2238 		udelay(1);
2239 	}
2240 
2241 	if (i >= usec_timeout) {
2242 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2243 		return -EINVAL;
2244 	}
2245 
2246 	/* Prime the instruction caches */
2247 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2248 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2249 	WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2250 
2251 	/* Waiting for instruction cache primed*/
2252 	for (i = 0; i < usec_timeout; i++) {
2253 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2254 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2255 			ICACHE_PRIMED))
2256 			break;
2257 		udelay(1);
2258 	}
2259 
2260 	if (i >= usec_timeout) {
2261 		dev_err(adev->dev, "failed to prime instruction cache\n");
2262 		return -EINVAL;
2263 	}
2264 
2265 	mutex_lock(&adev->srbm_mutex);
2266 	for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2267 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2268 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2269 			(me_hdr->ucode_start_addr_hi << 30) |
2270 			(me_hdr->ucode_start_addr_lo >> 2) );
2271 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2272 			me_hdr->ucode_start_addr_hi>>2);
2273 
2274 		/*
2275 		 * Program CP_ME_CNTL to reset given PIPE to take
2276 		 * effect of CP_PFP_PRGRM_CNTR_START.
2277 		 */
2278 		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2279 		if (pipe_id == 0)
2280 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2281 					ME_PIPE0_RESET, 1);
2282 		else
2283 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2284 					ME_PIPE1_RESET, 1);
2285 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2286 
2287 		/* Clear pfp pipe0 reset bit. */
2288 		if (pipe_id == 0)
2289 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2290 					ME_PIPE0_RESET, 0);
2291 		else
2292 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2293 					ME_PIPE1_RESET, 0);
2294 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2295 
2296 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2297 			lower_32_bits(addr2));
2298 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2299 			upper_32_bits(addr2));
2300 	}
2301 	soc21_grbm_select(adev, 0, 0, 0, 0);
2302 	mutex_unlock(&adev->srbm_mutex);
2303 
2304 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2305 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2306 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2307 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2308 
2309 	/* Invalidate the data caches */
2310 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2311 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2312 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2313 
2314 	for (i = 0; i < usec_timeout; i++) {
2315 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2316 		if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2317 			INVALIDATE_DCACHE_COMPLETE))
2318 			break;
2319 		udelay(1);
2320 	}
2321 
2322 	if (i >= usec_timeout) {
2323 		dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2324 		return -EINVAL;
2325 	}
2326 
2327 	return 0;
2328 }
2329 
2330 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2331 {
2332 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2333 	uint32_t tmp;
2334 	unsigned i;
2335 	const struct gfx_firmware_header_v2_0 *mec_hdr;
2336 
2337 	mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2338 		adev->gfx.mec_fw->data;
2339 
2340 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2341 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2342 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2343 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2344 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2345 
2346 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2347 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
2348 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
2349 	WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2350 
2351 	mutex_lock(&adev->srbm_mutex);
2352 	for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2353 		soc21_grbm_select(adev, 1, i, 0, 0);
2354 
2355 		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2);
2356 		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2357 		     upper_32_bits(addr2));
2358 
2359 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2360 					mec_hdr->ucode_start_addr_lo >> 2 |
2361 					mec_hdr->ucode_start_addr_hi << 30);
2362 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2363 					mec_hdr->ucode_start_addr_hi >> 2);
2364 
2365 		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr);
2366 		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2367 		     upper_32_bits(addr));
2368 	}
2369 	mutex_unlock(&adev->srbm_mutex);
2370 	soc21_grbm_select(adev, 0, 0, 0, 0);
2371 
2372 	/* Trigger an invalidation of the L1 instruction caches */
2373 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2374 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2375 	WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2376 
2377 	/* Wait for invalidation complete */
2378 	for (i = 0; i < usec_timeout; i++) {
2379 		tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2380 		if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
2381 				       INVALIDATE_DCACHE_COMPLETE))
2382 			break;
2383 		udelay(1);
2384 	}
2385 
2386 	if (i >= usec_timeout) {
2387 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2388 		return -EINVAL;
2389 	}
2390 
2391 	/* Trigger an invalidation of the L1 instruction caches */
2392 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2393 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2394 	WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2395 
2396 	/* Wait for invalidation complete */
2397 	for (i = 0; i < usec_timeout; i++) {
2398 		tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2399 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2400 				       INVALIDATE_CACHE_COMPLETE))
2401 			break;
2402 		udelay(1);
2403 	}
2404 
2405 	if (i >= usec_timeout) {
2406 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2407 		return -EINVAL;
2408 	}
2409 
2410 	return 0;
2411 }
2412 
2413 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev)
2414 {
2415 	const struct gfx_firmware_header_v2_0 *pfp_hdr;
2416 	const struct gfx_firmware_header_v2_0 *me_hdr;
2417 	const struct gfx_firmware_header_v2_0 *mec_hdr;
2418 	uint32_t pipe_id, tmp;
2419 
2420 	mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2421 		adev->gfx.mec_fw->data;
2422 	me_hdr = (const struct gfx_firmware_header_v2_0 *)
2423 		adev->gfx.me_fw->data;
2424 	pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2425 		adev->gfx.pfp_fw->data;
2426 
2427 	/* config pfp program start addr */
2428 	for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2429 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2430 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2431 			(pfp_hdr->ucode_start_addr_hi << 30) |
2432 			(pfp_hdr->ucode_start_addr_lo >> 2));
2433 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2434 			pfp_hdr->ucode_start_addr_hi >> 2);
2435 	}
2436 	soc21_grbm_select(adev, 0, 0, 0, 0);
2437 
2438 	/* reset pfp pipe */
2439 	tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2440 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
2441 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
2442 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2443 
2444 	/* clear pfp pipe reset */
2445 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
2446 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
2447 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2448 
2449 	/* config me program start addr */
2450 	for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2451 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2452 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2453 			(me_hdr->ucode_start_addr_hi << 30) |
2454 			(me_hdr->ucode_start_addr_lo >> 2) );
2455 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2456 			me_hdr->ucode_start_addr_hi>>2);
2457 	}
2458 	soc21_grbm_select(adev, 0, 0, 0, 0);
2459 
2460 	/* reset me pipe */
2461 	tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2462 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
2463 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
2464 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2465 
2466 	/* clear me pipe reset */
2467 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
2468 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
2469 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2470 
2471 	/* config mec program start addr */
2472 	for (pipe_id = 0; pipe_id < 4; pipe_id++) {
2473 		soc21_grbm_select(adev, 1, pipe_id, 0, 0);
2474 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2475 					mec_hdr->ucode_start_addr_lo >> 2 |
2476 					mec_hdr->ucode_start_addr_hi << 30);
2477 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2478 					mec_hdr->ucode_start_addr_hi >> 2);
2479 	}
2480 	soc21_grbm_select(adev, 0, 0, 0, 0);
2481 
2482 	/* reset mec pipe */
2483 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2484 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
2485 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
2486 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
2487 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
2488 	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2489 
2490 	/* clear mec pipe reset */
2491 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
2492 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
2493 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
2494 	tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
2495 	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2496 }
2497 
2498 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2499 {
2500 	uint32_t cp_status;
2501 	uint32_t bootload_status;
2502 	int i, r;
2503 	uint64_t addr, addr2;
2504 
2505 	for (i = 0; i < adev->usec_timeout; i++) {
2506 		cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2507 
2508 		if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 1) ||
2509 				adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 4))
2510 			bootload_status = RREG32_SOC15(GC, 0,
2511 					regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
2512 		else
2513 			bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2514 
2515 		if ((cp_status == 0) &&
2516 		    (REG_GET_FIELD(bootload_status,
2517 			RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2518 			break;
2519 		}
2520 		udelay(1);
2521 	}
2522 
2523 	if (i >= adev->usec_timeout) {
2524 		dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2525 		return -ETIMEDOUT;
2526 	}
2527 
2528 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2529 		if (adev->gfx.rs64_enable) {
2530 			addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2531 				rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset;
2532 			addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2533 				rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset;
2534 			r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2);
2535 			if (r)
2536 				return r;
2537 			addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2538 				rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset;
2539 			addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2540 				rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset;
2541 			r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2);
2542 			if (r)
2543 				return r;
2544 			addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2545 				rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset;
2546 			addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2547 				rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset;
2548 			r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2);
2549 			if (r)
2550 				return r;
2551 		} else {
2552 			addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2553 				rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset;
2554 			r = gfx_v11_0_config_me_cache(adev, addr);
2555 			if (r)
2556 				return r;
2557 			addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2558 				rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset;
2559 			r = gfx_v11_0_config_pfp_cache(adev, addr);
2560 			if (r)
2561 				return r;
2562 			addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2563 				rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset;
2564 			r = gfx_v11_0_config_mec_cache(adev, addr);
2565 			if (r)
2566 				return r;
2567 		}
2568 	}
2569 
2570 	return 0;
2571 }
2572 
2573 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2574 {
2575 	int i;
2576 	u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2577 
2578 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2579 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2580 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2581 
2582 	for (i = 0; i < adev->usec_timeout; i++) {
2583 		if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
2584 			break;
2585 		udelay(1);
2586 	}
2587 
2588 	if (i >= adev->usec_timeout)
2589 		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2590 
2591 	return 0;
2592 }
2593 
2594 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2595 {
2596 	int r;
2597 	const struct gfx_firmware_header_v1_0 *pfp_hdr;
2598 	const __le32 *fw_data;
2599 	unsigned i, fw_size;
2600 
2601 	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2602 		adev->gfx.pfp_fw->data;
2603 
2604 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2605 
2606 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2607 		le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2608 	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2609 
2610 	r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2611 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2612 				      &adev->gfx.pfp.pfp_fw_obj,
2613 				      &adev->gfx.pfp.pfp_fw_gpu_addr,
2614 				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
2615 	if (r) {
2616 		dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2617 		gfx_v11_0_pfp_fini(adev);
2618 		return r;
2619 	}
2620 
2621 	memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2622 
2623 	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2624 	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2625 
2626 	gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr);
2627 
2628 	WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0);
2629 
2630 	for (i = 0; i < pfp_hdr->jt_size; i++)
2631 		WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA,
2632 			     le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
2633 
2634 	WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2635 
2636 	return 0;
2637 }
2638 
2639 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
2640 {
2641 	int r;
2642 	const struct gfx_firmware_header_v2_0 *pfp_hdr;
2643 	const __le32 *fw_ucode, *fw_data;
2644 	unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2645 	uint32_t tmp;
2646 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2647 
2648 	pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2649 		adev->gfx.pfp_fw->data;
2650 
2651 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2652 
2653 	/* instruction */
2654 	fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
2655 		le32_to_cpu(pfp_hdr->ucode_offset_bytes));
2656 	fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes);
2657 	/* data */
2658 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2659 		le32_to_cpu(pfp_hdr->data_offset_bytes));
2660 	fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes);
2661 
2662 	/* 64kb align */
2663 	r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2664 				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2665 				      &adev->gfx.pfp.pfp_fw_obj,
2666 				      &adev->gfx.pfp.pfp_fw_gpu_addr,
2667 				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
2668 	if (r) {
2669 		dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r);
2670 		gfx_v11_0_pfp_fini(adev);
2671 		return r;
2672 	}
2673 
2674 	r = amdgpu_bo_create_reserved(adev, fw_data_size,
2675 				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2676 				      &adev->gfx.pfp.pfp_fw_data_obj,
2677 				      &adev->gfx.pfp.pfp_fw_data_gpu_addr,
2678 				      (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
2679 	if (r) {
2680 		dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r);
2681 		gfx_v11_0_pfp_fini(adev);
2682 		return r;
2683 	}
2684 
2685 	memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
2686 	memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
2687 
2688 	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2689 	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
2690 	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2691 	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
2692 
2693 	if (amdgpu_emu_mode == 1)
2694 		adev->hdp.funcs->flush_hdp(adev, NULL);
2695 
2696 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2697 		lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2698 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2699 		upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2700 
2701 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2702 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2703 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2704 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2705 	WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2706 
2707 	/*
2708 	 * Programming any of the CP_PFP_IC_BASE registers
2709 	 * forces invalidation of the ME L1 I$. Wait for the
2710 	 * invalidation complete
2711 	 */
2712 	for (i = 0; i < usec_timeout; i++) {
2713 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2714 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2715 			INVALIDATE_CACHE_COMPLETE))
2716 			break;
2717 		udelay(1);
2718 	}
2719 
2720 	if (i >= usec_timeout) {
2721 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2722 		return -EINVAL;
2723 	}
2724 
2725 	/* Prime the L1 instruction caches */
2726 	tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2727 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2728 	WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2729 	/* Waiting for cache primed*/
2730 	for (i = 0; i < usec_timeout; i++) {
2731 		tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2732 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2733 			ICACHE_PRIMED))
2734 			break;
2735 		udelay(1);
2736 	}
2737 
2738 	if (i >= usec_timeout) {
2739 		dev_err(adev->dev, "failed to prime instruction cache\n");
2740 		return -EINVAL;
2741 	}
2742 
2743 	mutex_lock(&adev->srbm_mutex);
2744 	for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2745 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2746 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2747 			(pfp_hdr->ucode_start_addr_hi << 30) |
2748 			(pfp_hdr->ucode_start_addr_lo >> 2) );
2749 		WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2750 			pfp_hdr->ucode_start_addr_hi>>2);
2751 
2752 		/*
2753 		 * Program CP_ME_CNTL to reset given PIPE to take
2754 		 * effect of CP_PFP_PRGRM_CNTR_START.
2755 		 */
2756 		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2757 		if (pipe_id == 0)
2758 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2759 					PFP_PIPE0_RESET, 1);
2760 		else
2761 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2762 					PFP_PIPE1_RESET, 1);
2763 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2764 
2765 		/* Clear pfp pipe0 reset bit. */
2766 		if (pipe_id == 0)
2767 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2768 					PFP_PIPE0_RESET, 0);
2769 		else
2770 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2771 					PFP_PIPE1_RESET, 0);
2772 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2773 
2774 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2775 			lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2776 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2777 			upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2778 	}
2779 	soc21_grbm_select(adev, 0, 0, 0, 0);
2780 	mutex_unlock(&adev->srbm_mutex);
2781 
2782 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2783 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2784 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2785 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2786 
2787 	/* Invalidate the data caches */
2788 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2789 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2790 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2791 
2792 	for (i = 0; i < usec_timeout; i++) {
2793 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2794 		if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2795 			INVALIDATE_DCACHE_COMPLETE))
2796 			break;
2797 		udelay(1);
2798 	}
2799 
2800 	if (i >= usec_timeout) {
2801 		dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2802 		return -EINVAL;
2803 	}
2804 
2805 	return 0;
2806 }
2807 
2808 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2809 {
2810 	int r;
2811 	const struct gfx_firmware_header_v1_0 *me_hdr;
2812 	const __le32 *fw_data;
2813 	unsigned i, fw_size;
2814 
2815 	me_hdr = (const struct gfx_firmware_header_v1_0 *)
2816 		adev->gfx.me_fw->data;
2817 
2818 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2819 
2820 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2821 		le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2822 	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2823 
2824 	r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2825 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2826 				      &adev->gfx.me.me_fw_obj,
2827 				      &adev->gfx.me.me_fw_gpu_addr,
2828 				      (void **)&adev->gfx.me.me_fw_ptr);
2829 	if (r) {
2830 		dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2831 		gfx_v11_0_me_fini(adev);
2832 		return r;
2833 	}
2834 
2835 	memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2836 
2837 	amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2838 	amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2839 
2840 	gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr);
2841 
2842 	WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0);
2843 
2844 	for (i = 0; i < me_hdr->jt_size; i++)
2845 		WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA,
2846 			     le32_to_cpup(fw_data + me_hdr->jt_offset + i));
2847 
2848 	WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
2849 
2850 	return 0;
2851 }
2852 
2853 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
2854 {
2855 	int r;
2856 	const struct gfx_firmware_header_v2_0 *me_hdr;
2857 	const __le32 *fw_ucode, *fw_data;
2858 	unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2859 	uint32_t tmp;
2860 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
2861 
2862 	me_hdr = (const struct gfx_firmware_header_v2_0 *)
2863 		adev->gfx.me_fw->data;
2864 
2865 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2866 
2867 	/* instruction */
2868 	fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
2869 		le32_to_cpu(me_hdr->ucode_offset_bytes));
2870 	fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes);
2871 	/* data */
2872 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2873 		le32_to_cpu(me_hdr->data_offset_bytes));
2874 	fw_data_size = le32_to_cpu(me_hdr->data_size_bytes);
2875 
2876 	/* 64kb align*/
2877 	r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2878 				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2879 				      &adev->gfx.me.me_fw_obj,
2880 				      &adev->gfx.me.me_fw_gpu_addr,
2881 				      (void **)&adev->gfx.me.me_fw_ptr);
2882 	if (r) {
2883 		dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r);
2884 		gfx_v11_0_me_fini(adev);
2885 		return r;
2886 	}
2887 
2888 	r = amdgpu_bo_create_reserved(adev, fw_data_size,
2889 				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
2890 				      &adev->gfx.me.me_fw_data_obj,
2891 				      &adev->gfx.me.me_fw_data_gpu_addr,
2892 				      (void **)&adev->gfx.me.me_fw_data_ptr);
2893 	if (r) {
2894 		dev_err(adev->dev, "(%d) failed to create me data bo\n", r);
2895 		gfx_v11_0_pfp_fini(adev);
2896 		return r;
2897 	}
2898 
2899 	memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
2900 	memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
2901 
2902 	amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2903 	amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
2904 	amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2905 	amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
2906 
2907 	if (amdgpu_emu_mode == 1)
2908 		adev->hdp.funcs->flush_hdp(adev, NULL);
2909 
2910 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2911 		lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
2912 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2913 		upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
2914 
2915 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2916 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2917 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2918 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2919 	WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2920 
2921 	/*
2922 	 * Programming any of the CP_ME_IC_BASE registers
2923 	 * forces invalidation of the ME L1 I$. Wait for the
2924 	 * invalidation complete
2925 	 */
2926 	for (i = 0; i < usec_timeout; i++) {
2927 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2928 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2929 			INVALIDATE_CACHE_COMPLETE))
2930 			break;
2931 		udelay(1);
2932 	}
2933 
2934 	if (i >= usec_timeout) {
2935 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
2936 		return -EINVAL;
2937 	}
2938 
2939 	/* Prime the instruction caches */
2940 	tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2941 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2942 	WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2943 
2944 	/* Waiting for instruction cache primed*/
2945 	for (i = 0; i < usec_timeout; i++) {
2946 		tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2947 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2948 			ICACHE_PRIMED))
2949 			break;
2950 		udelay(1);
2951 	}
2952 
2953 	if (i >= usec_timeout) {
2954 		dev_err(adev->dev, "failed to prime instruction cache\n");
2955 		return -EINVAL;
2956 	}
2957 
2958 	mutex_lock(&adev->srbm_mutex);
2959 	for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2960 		soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2961 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2962 			(me_hdr->ucode_start_addr_hi << 30) |
2963 			(me_hdr->ucode_start_addr_lo >> 2) );
2964 		WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2965 			me_hdr->ucode_start_addr_hi>>2);
2966 
2967 		/*
2968 		 * Program CP_ME_CNTL to reset given PIPE to take
2969 		 * effect of CP_PFP_PRGRM_CNTR_START.
2970 		 */
2971 		tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2972 		if (pipe_id == 0)
2973 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2974 					ME_PIPE0_RESET, 1);
2975 		else
2976 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2977 					ME_PIPE1_RESET, 1);
2978 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2979 
2980 		/* Clear pfp pipe0 reset bit. */
2981 		if (pipe_id == 0)
2982 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2983 					ME_PIPE0_RESET, 0);
2984 		else
2985 			tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2986 					ME_PIPE1_RESET, 0);
2987 		WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2988 
2989 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2990 			lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2991 		WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2992 			upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
2993 	}
2994 	soc21_grbm_select(adev, 0, 0, 0, 0);
2995 	mutex_unlock(&adev->srbm_mutex);
2996 
2997 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2998 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2999 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
3000 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
3001 
3002 	/* Invalidate the data caches */
3003 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
3004 	tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3005 	WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
3006 
3007 	for (i = 0; i < usec_timeout; i++) {
3008 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
3009 		if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
3010 			INVALIDATE_DCACHE_COMPLETE))
3011 			break;
3012 		udelay(1);
3013 	}
3014 
3015 	if (i >= usec_timeout) {
3016 		dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
3017 		return -EINVAL;
3018 	}
3019 
3020 	return 0;
3021 }
3022 
3023 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3024 {
3025 	int r;
3026 
3027 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
3028 		return -EINVAL;
3029 
3030 	gfx_v11_0_cp_gfx_enable(adev, false);
3031 
3032 	if (adev->gfx.rs64_enable)
3033 		r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev);
3034 	else
3035 		r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev);
3036 	if (r) {
3037 		dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
3038 		return r;
3039 	}
3040 
3041 	if (adev->gfx.rs64_enable)
3042 		r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev);
3043 	else
3044 		r = gfx_v11_0_cp_gfx_load_me_microcode(adev);
3045 	if (r) {
3046 		dev_err(adev->dev, "(%d) failed to load me fw\n", r);
3047 		return r;
3048 	}
3049 
3050 	return 0;
3051 }
3052 
3053 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev)
3054 {
3055 	struct amdgpu_ring *ring;
3056 	const struct cs_section_def *sect = NULL;
3057 	const struct cs_extent_def *ext = NULL;
3058 	int r, i;
3059 	int ctx_reg_offset;
3060 
3061 	/* init the CP */
3062 	WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
3063 		     adev->gfx.config.max_hw_contexts - 1);
3064 	WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
3065 
3066 	if (!amdgpu_async_gfx_ring)
3067 		gfx_v11_0_cp_gfx_enable(adev, true);
3068 
3069 	ring = &adev->gfx.gfx_ring[0];
3070 	r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev));
3071 	if (r) {
3072 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3073 		return r;
3074 	}
3075 
3076 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3077 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3078 
3079 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3080 	amdgpu_ring_write(ring, 0x80000000);
3081 	amdgpu_ring_write(ring, 0x80000000);
3082 
3083 	for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
3084 		for (ext = sect->section; ext->extent != NULL; ++ext) {
3085 			if (sect->id == SECT_CONTEXT) {
3086 				amdgpu_ring_write(ring,
3087 						  PACKET3(PACKET3_SET_CONTEXT_REG,
3088 							  ext->reg_count));
3089 				amdgpu_ring_write(ring, ext->reg_index -
3090 						  PACKET3_SET_CONTEXT_REG_START);
3091 				for (i = 0; i < ext->reg_count; i++)
3092 					amdgpu_ring_write(ring, ext->extent[i]);
3093 			}
3094 		}
3095 	}
3096 
3097 	ctx_reg_offset =
3098 		SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3099 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3100 	amdgpu_ring_write(ring, ctx_reg_offset);
3101 	amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
3102 
3103 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3104 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3105 
3106 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3107 	amdgpu_ring_write(ring, 0);
3108 
3109 	amdgpu_ring_commit(ring);
3110 
3111 	/* submit cs packet to copy state 0 to next available state */
3112 	if (adev->gfx.num_gfx_rings > 1) {
3113 		/* maximum supported gfx ring is 2 */
3114 		ring = &adev->gfx.gfx_ring[1];
3115 		r = amdgpu_ring_alloc(ring, 2);
3116 		if (r) {
3117 			DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3118 			return r;
3119 		}
3120 
3121 		amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3122 		amdgpu_ring_write(ring, 0);
3123 
3124 		amdgpu_ring_commit(ring);
3125 	}
3126 	return 0;
3127 }
3128 
3129 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
3130 					 CP_PIPE_ID pipe)
3131 {
3132 	u32 tmp;
3133 
3134 	tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
3135 	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
3136 
3137 	WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
3138 }
3139 
3140 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
3141 					  struct amdgpu_ring *ring)
3142 {
3143 	u32 tmp;
3144 
3145 	tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3146 	if (ring->use_doorbell) {
3147 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3148 				    DOORBELL_OFFSET, ring->doorbell_index);
3149 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3150 				    DOORBELL_EN, 1);
3151 	} else {
3152 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3153 				    DOORBELL_EN, 0);
3154 	}
3155 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
3156 
3157 	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3158 			    DOORBELL_RANGE_LOWER, ring->doorbell_index);
3159 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
3160 
3161 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3162 		     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3163 }
3164 
3165 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev)
3166 {
3167 	struct amdgpu_ring *ring;
3168 	u32 tmp;
3169 	u32 rb_bufsz;
3170 	u64 rb_addr, rptr_addr, wptr_gpu_addr;
3171 	u32 i;
3172 
3173 	/* Set the write pointer delay */
3174 	WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
3175 
3176 	/* set the RB to use vmid 0 */
3177 	WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
3178 
3179 	/* Init gfx ring 0 for pipe 0 */
3180 	mutex_lock(&adev->srbm_mutex);
3181 	gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3182 
3183 	/* Set ring buffer size */
3184 	ring = &adev->gfx.gfx_ring[0];
3185 	rb_bufsz = order_base_2(ring->ring_size / 8);
3186 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3187 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3188 	WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3189 
3190 	/* Initialize the ring buffer's write pointers */
3191 	ring->wptr = 0;
3192 	WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
3193 	WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3194 
3195 	/* set the wb address wether it's enabled or not */
3196 	rptr_addr = ring->rptr_gpu_addr;
3197 	WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3198 	WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3199 		     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3200 
3201 	wptr_gpu_addr = ring->wptr_gpu_addr;
3202 	WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3203 		     lower_32_bits(wptr_gpu_addr));
3204 	WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3205 		     upper_32_bits(wptr_gpu_addr));
3206 
3207 	mdelay(1);
3208 	WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3209 
3210 	rb_addr = ring->gpu_addr >> 8;
3211 	WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
3212 	WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3213 
3214 	WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
3215 
3216 	gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3217 	mutex_unlock(&adev->srbm_mutex);
3218 
3219 	/* Init gfx ring 1 for pipe 1 */
3220 	if (adev->gfx.num_gfx_rings > 1) {
3221 		mutex_lock(&adev->srbm_mutex);
3222 		gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
3223 		/* maximum supported gfx ring is 2 */
3224 		ring = &adev->gfx.gfx_ring[1];
3225 		rb_bufsz = order_base_2(ring->ring_size / 8);
3226 		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
3227 		tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
3228 		WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3229 		/* Initialize the ring buffer's write pointers */
3230 		ring->wptr = 0;
3231 		WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr));
3232 		WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
3233 		/* Set the wb address wether it's enabled or not */
3234 		rptr_addr = ring->rptr_gpu_addr;
3235 		WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
3236 		WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3237 			     CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3238 		wptr_gpu_addr = ring->wptr_gpu_addr;
3239 		WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3240 			     lower_32_bits(wptr_gpu_addr));
3241 		WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3242 			     upper_32_bits(wptr_gpu_addr));
3243 
3244 		mdelay(1);
3245 		WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3246 
3247 		rb_addr = ring->gpu_addr >> 8;
3248 		WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr);
3249 		WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr));
3250 		WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1);
3251 
3252 		gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3253 		mutex_unlock(&adev->srbm_mutex);
3254 	}
3255 	/* Switch to pipe 0 */
3256 	mutex_lock(&adev->srbm_mutex);
3257 	gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3258 	mutex_unlock(&adev->srbm_mutex);
3259 
3260 	/* start the ring */
3261 	gfx_v11_0_cp_gfx_start(adev);
3262 
3263 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3264 		ring = &adev->gfx.gfx_ring[i];
3265 		ring->sched.ready = true;
3266 	}
3267 
3268 	return 0;
3269 }
3270 
3271 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3272 {
3273 	u32 data;
3274 
3275 	if (adev->gfx.rs64_enable) {
3276 		data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
3277 		data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,
3278 							 enable ? 0 : 1);
3279 		data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,
3280 							 enable ? 0 : 1);
3281 		data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,
3282 							 enable ? 0 : 1);
3283 		data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,
3284 							 enable ? 0 : 1);
3285 		data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,
3286 							 enable ? 0 : 1);
3287 		data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,
3288 							 enable ? 1 : 0);
3289 		data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,
3290 				                         enable ? 1 : 0);
3291 		data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,
3292 							 enable ? 1 : 0);
3293 		data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,
3294 							 enable ? 1 : 0);
3295 		data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,
3296 							 enable ? 0 : 1);
3297 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
3298 	} else {
3299 		data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);
3300 
3301 		if (enable) {
3302 			data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0);
3303 			if (!adev->enable_mes_kiq)
3304 				data = REG_SET_FIELD(data, CP_MEC_CNTL,
3305 						     MEC_ME2_HALT, 0);
3306 		} else {
3307 			data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1);
3308 			data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1);
3309 		}
3310 		WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data);
3311 	}
3312 
3313 	adev->gfx.kiq.ring.sched.ready = enable;
3314 
3315 	udelay(50);
3316 }
3317 
3318 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3319 {
3320 	const struct gfx_firmware_header_v1_0 *mec_hdr;
3321 	const __le32 *fw_data;
3322 	unsigned i, fw_size;
3323 	u32 *fw = NULL;
3324 	int r;
3325 
3326 	if (!adev->gfx.mec_fw)
3327 		return -EINVAL;
3328 
3329 	gfx_v11_0_cp_compute_enable(adev, false);
3330 
3331 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3332 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3333 
3334 	fw_data = (const __le32 *)
3335 		(adev->gfx.mec_fw->data +
3336 		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3337 	fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
3338 
3339 	r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
3340 					  PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
3341 					  &adev->gfx.mec.mec_fw_obj,
3342 					  &adev->gfx.mec.mec_fw_gpu_addr,
3343 					  (void **)&fw);
3344 	if (r) {
3345 		dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
3346 		gfx_v11_0_mec_fini(adev);
3347 		return r;
3348 	}
3349 
3350 	memcpy(fw, fw_data, fw_size);
3351 
3352 	amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3353 	amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3354 
3355 	gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr);
3356 
3357 	/* MEC1 */
3358 	WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0);
3359 
3360 	for (i = 0; i < mec_hdr->jt_size; i++)
3361 		WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA,
3362 			     le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
3363 
3364 	WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3365 
3366 	return 0;
3367 }
3368 
3369 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)
3370 {
3371 	const struct gfx_firmware_header_v2_0 *mec_hdr;
3372 	const __le32 *fw_ucode, *fw_data;
3373 	u32 tmp, fw_ucode_size, fw_data_size;
3374 	u32 i, usec_timeout = 50000; /* Wait for 50 ms */
3375 	u32 *fw_ucode_ptr, *fw_data_ptr;
3376 	int r;
3377 
3378 	if (!adev->gfx.mec_fw)
3379 		return -EINVAL;
3380 
3381 	gfx_v11_0_cp_compute_enable(adev, false);
3382 
3383 	mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
3384 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3385 
3386 	fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
3387 				le32_to_cpu(mec_hdr->ucode_offset_bytes));
3388 	fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes);
3389 
3390 	fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
3391 				le32_to_cpu(mec_hdr->data_offset_bytes));
3392 	fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
3393 
3394 	r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
3395 				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
3396 				      &adev->gfx.mec.mec_fw_obj,
3397 				      &adev->gfx.mec.mec_fw_gpu_addr,
3398 				      (void **)&fw_ucode_ptr);
3399 	if (r) {
3400 		dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3401 		gfx_v11_0_mec_fini(adev);
3402 		return r;
3403 	}
3404 
3405 	r = amdgpu_bo_create_reserved(adev, fw_data_size,
3406 				      64 * 1024, AMDGPU_GEM_DOMAIN_VRAM,
3407 				      &adev->gfx.mec.mec_fw_data_obj,
3408 				      &adev->gfx.mec.mec_fw_data_gpu_addr,
3409 				      (void **)&fw_data_ptr);
3410 	if (r) {
3411 		dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3412 		gfx_v11_0_mec_fini(adev);
3413 		return r;
3414 	}
3415 
3416 	memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
3417 	memcpy(fw_data_ptr, fw_data, fw_data_size);
3418 
3419 	amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3420 	amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
3421 	amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3422 	amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
3423 
3424 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
3425 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
3426 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
3427 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
3428 	WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
3429 
3430 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
3431 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
3432 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
3433 	WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
3434 
3435 	mutex_lock(&adev->srbm_mutex);
3436 	for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3437 		soc21_grbm_select(adev, 1, i, 0, 0);
3438 
3439 		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr);
3440 		WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
3441 		     upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr));
3442 
3443 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
3444 					mec_hdr->ucode_start_addr_lo >> 2 |
3445 					mec_hdr->ucode_start_addr_hi << 30);
3446 		WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
3447 					mec_hdr->ucode_start_addr_hi >> 2);
3448 
3449 		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr);
3450 		WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
3451 		     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
3452 	}
3453 	mutex_unlock(&adev->srbm_mutex);
3454 	soc21_grbm_select(adev, 0, 0, 0, 0);
3455 
3456 	/* Trigger an invalidation of the L1 instruction caches */
3457 	tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3458 	tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3459 	WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
3460 
3461 	/* Wait for invalidation complete */
3462 	for (i = 0; i < usec_timeout; i++) {
3463 		tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3464 		if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
3465 				       INVALIDATE_DCACHE_COMPLETE))
3466 			break;
3467 		udelay(1);
3468 	}
3469 
3470 	if (i >= usec_timeout) {
3471 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
3472 		return -EINVAL;
3473 	}
3474 
3475 	/* Trigger an invalidation of the L1 instruction caches */
3476 	tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3477 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
3478 	WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
3479 
3480 	/* Wait for invalidation complete */
3481 	for (i = 0; i < usec_timeout; i++) {
3482 		tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3483 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
3484 				       INVALIDATE_CACHE_COMPLETE))
3485 			break;
3486 		udelay(1);
3487 	}
3488 
3489 	if (i >= usec_timeout) {
3490 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
3491 		return -EINVAL;
3492 	}
3493 
3494 	return 0;
3495 }
3496 
3497 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring)
3498 {
3499 	uint32_t tmp;
3500 	struct amdgpu_device *adev = ring->adev;
3501 
3502 	/* tell RLC which is KIQ queue */
3503 	tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3504 	tmp &= 0xffffff00;
3505 	tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
3506 	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3507 	tmp |= 0x80;
3508 	WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3509 }
3510 
3511 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev)
3512 {
3513 	/* set graphics engine doorbell range */
3514 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
3515 		     (adev->doorbell_index.gfx_ring0 * 2) << 2);
3516 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3517 		     (adev->doorbell_index.gfx_userqueue_end * 2) << 2);
3518 
3519 	/* set compute engine doorbell range */
3520 	WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3521 		     (adev->doorbell_index.kiq * 2) << 2);
3522 	WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3523 		     (adev->doorbell_index.userqueue_end * 2) << 2);
3524 }
3525 
3526 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
3527 				  struct amdgpu_mqd_prop *prop)
3528 {
3529 	struct v11_gfx_mqd *mqd = m;
3530 	uint64_t hqd_gpu_addr, wb_gpu_addr;
3531 	uint32_t tmp;
3532 	uint32_t rb_bufsz;
3533 
3534 	/* set up gfx hqd wptr */
3535 	mqd->cp_gfx_hqd_wptr = 0;
3536 	mqd->cp_gfx_hqd_wptr_hi = 0;
3537 
3538 	/* set the pointer to the MQD */
3539 	mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
3540 	mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3541 
3542 	/* set up mqd control */
3543 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL);
3544 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
3545 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
3546 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
3547 	mqd->cp_gfx_mqd_control = tmp;
3548 
3549 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
3550 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);
3551 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
3552 	mqd->cp_gfx_hqd_vmid = 0;
3553 
3554 	/* set up default queue priority level
3555 	 * 0x0 = low priority, 0x1 = high priority */
3556 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);
3557 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
3558 	mqd->cp_gfx_hqd_queue_priority = tmp;
3559 
3560 	/* set up time quantum */
3561 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);
3562 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3563 	mqd->cp_gfx_hqd_quantum = tmp;
3564 
3565 	/* set up gfx hqd base. this is similar as CP_RB_BASE */
3566 	hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3567 	mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3568 	mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3569 
3570 	/* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3571 	wb_gpu_addr = prop->rptr_gpu_addr;
3572 	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3573 	mqd->cp_gfx_hqd_rptr_addr_hi =
3574 		upper_32_bits(wb_gpu_addr) & 0xffff;
3575 
3576 	/* set up rb_wptr_poll addr */
3577 	wb_gpu_addr = prop->wptr_gpu_addr;
3578 	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3579 	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3580 
3581 	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3582 	rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
3583 	tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL);
3584 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3585 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3586 #ifdef __BIG_ENDIAN
3587 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3588 #endif
3589 	mqd->cp_gfx_hqd_cntl = tmp;
3590 
3591 	/* set up cp_doorbell_control */
3592 	tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3593 	if (prop->use_doorbell) {
3594 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3595 				    DOORBELL_OFFSET, prop->doorbell_index);
3596 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3597 				    DOORBELL_EN, 1);
3598 	} else
3599 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3600 				    DOORBELL_EN, 0);
3601 	mqd->cp_rb_doorbell_control = tmp;
3602 
3603 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3604 	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR);
3605 
3606 	/* active the queue */
3607 	mqd->cp_gfx_hqd_active = 1;
3608 
3609 	return 0;
3610 }
3611 
3612 #ifdef BRING_UP_DEBUG
3613 static int gfx_v11_0_gfx_queue_init_register(struct amdgpu_ring *ring)
3614 {
3615 	struct amdgpu_device *adev = ring->adev;
3616 	struct v11_gfx_mqd *mqd = ring->mqd_ptr;
3617 
3618 	/* set mmCP_GFX_HQD_WPTR/_HI to 0 */
3619 	WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
3620 	WREG32_SOC15(GC, 0, regCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
3621 
3622 	/* set GFX_MQD_BASE */
3623 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
3624 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3625 
3626 	/* set GFX_MQD_CONTROL */
3627 	WREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
3628 
3629 	/* set GFX_HQD_VMID to 0 */
3630 	WREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
3631 
3632 	WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY,
3633 			mqd->cp_gfx_hqd_queue_priority);
3634 	WREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
3635 
3636 	/* set GFX_HQD_BASE, similar as CP_RB_BASE */
3637 	WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
3638 	WREG32_SOC15(GC, 0, regCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
3639 
3640 	/* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
3641 	WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
3642 	WREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
3643 
3644 	/* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
3645 	WREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
3646 
3647 	/* set RB_WPTR_POLL_ADDR */
3648 	WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
3649 	WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
3650 
3651 	/* set RB_DOORBELL_CONTROL */
3652 	WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
3653 
3654 	/* active the queue */
3655 	WREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
3656 
3657 	return 0;
3658 }
3659 #endif
3660 
3661 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring)
3662 {
3663 	struct amdgpu_device *adev = ring->adev;
3664 	struct v11_gfx_mqd *mqd = ring->mqd_ptr;
3665 	int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3666 
3667 	if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
3668 		memset((void *)mqd, 0, sizeof(*mqd));
3669 		mutex_lock(&adev->srbm_mutex);
3670 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3671 		amdgpu_ring_init_mqd(ring);
3672 #ifdef BRING_UP_DEBUG
3673 		gfx_v11_0_gfx_queue_init_register(ring);
3674 #endif
3675 		soc21_grbm_select(adev, 0, 0, 0, 0);
3676 		mutex_unlock(&adev->srbm_mutex);
3677 		if (adev->gfx.me.mqd_backup[mqd_idx])
3678 			memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3679 	} else if (amdgpu_in_reset(adev)) {
3680 		/* reset mqd with the backup copy */
3681 		if (adev->gfx.me.mqd_backup[mqd_idx])
3682 			memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3683 		/* reset the ring */
3684 		ring->wptr = 0;
3685 		*ring->wptr_cpu_addr = 0;
3686 		amdgpu_ring_clear_ring(ring);
3687 #ifdef BRING_UP_DEBUG
3688 		mutex_lock(&adev->srbm_mutex);
3689 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3690 		gfx_v11_0_gfx_queue_init_register(ring);
3691 		soc21_grbm_select(adev, 0, 0, 0, 0);
3692 		mutex_unlock(&adev->srbm_mutex);
3693 #endif
3694 	} else {
3695 		amdgpu_ring_clear_ring(ring);
3696 	}
3697 
3698 	return 0;
3699 }
3700 
3701 #ifndef BRING_UP_DEBUG
3702 static int gfx_v11_0_kiq_enable_kgq(struct amdgpu_device *adev)
3703 {
3704 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
3705 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3706 	int r, i;
3707 
3708 	if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
3709 		return -EINVAL;
3710 
3711 	r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
3712 					adev->gfx.num_gfx_rings);
3713 	if (r) {
3714 		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3715 		return r;
3716 	}
3717 
3718 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3719 		kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
3720 
3721 	return amdgpu_ring_test_helper(kiq_ring);
3722 }
3723 #endif
3724 
3725 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3726 {
3727 	int r, i;
3728 	struct amdgpu_ring *ring;
3729 
3730 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3731 		ring = &adev->gfx.gfx_ring[i];
3732 
3733 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
3734 		if (unlikely(r != 0))
3735 			goto done;
3736 
3737 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3738 		if (!r) {
3739 			r = gfx_v11_0_gfx_init_queue(ring);
3740 			amdgpu_bo_kunmap(ring->mqd_obj);
3741 			ring->mqd_ptr = NULL;
3742 		}
3743 		amdgpu_bo_unreserve(ring->mqd_obj);
3744 		if (r)
3745 			goto done;
3746 	}
3747 #ifndef BRING_UP_DEBUG
3748 	r = gfx_v11_0_kiq_enable_kgq(adev);
3749 	if (r)
3750 		goto done;
3751 #endif
3752 	r = gfx_v11_0_cp_gfx_start(adev);
3753 	if (r)
3754 		goto done;
3755 
3756 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3757 		ring = &adev->gfx.gfx_ring[i];
3758 		ring->sched.ready = true;
3759 	}
3760 done:
3761 	return r;
3762 }
3763 
3764 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
3765 				      struct amdgpu_mqd_prop *prop)
3766 {
3767 	struct v11_compute_mqd *mqd = m;
3768 	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3769 	uint32_t tmp;
3770 
3771 	mqd->header = 0xC0310800;
3772 	mqd->compute_pipelinestat_enable = 0x00000001;
3773 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3774 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3775 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3776 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3777 	mqd->compute_misc_reserved = 0x00000007;
3778 
3779 	eop_base_addr = prop->eop_gpu_addr >> 8;
3780 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3781 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3782 
3783 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3784 	tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);
3785 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3786 			(order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1));
3787 
3788 	mqd->cp_hqd_eop_control = tmp;
3789 
3790 	/* enable doorbell? */
3791 	tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3792 
3793 	if (prop->use_doorbell) {
3794 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3795 				    DOORBELL_OFFSET, prop->doorbell_index);
3796 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3797 				    DOORBELL_EN, 1);
3798 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3799 				    DOORBELL_SOURCE, 0);
3800 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3801 				    DOORBELL_HIT, 0);
3802 	} else {
3803 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3804 				    DOORBELL_EN, 0);
3805 	}
3806 
3807 	mqd->cp_hqd_pq_doorbell_control = tmp;
3808 
3809 	/* disable the queue if it's active */
3810 	mqd->cp_hqd_dequeue_request = 0;
3811 	mqd->cp_hqd_pq_rptr = 0;
3812 	mqd->cp_hqd_pq_wptr_lo = 0;
3813 	mqd->cp_hqd_pq_wptr_hi = 0;
3814 
3815 	/* set the pointer to the MQD */
3816 	mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
3817 	mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3818 
3819 	/* set MQD vmid to 0 */
3820 	tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
3821 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3822 	mqd->cp_mqd_control = tmp;
3823 
3824 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3825 	hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3826 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3827 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3828 
3829 	/* set up the HQD, this is similar to CP_RB0_CNTL */
3830 	tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);
3831 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3832 			    (order_base_2(prop->queue_size / 4) - 1));
3833 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3834 			    (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3835 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3836 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3837 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3838 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3839 	mqd->cp_hqd_pq_control = tmp;
3840 
3841 	/* set the wb address whether it's enabled or not */
3842 	wb_gpu_addr = prop->rptr_gpu_addr;
3843 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3844 	mqd->cp_hqd_pq_rptr_report_addr_hi =
3845 		upper_32_bits(wb_gpu_addr) & 0xffff;
3846 
3847 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3848 	wb_gpu_addr = prop->wptr_gpu_addr;
3849 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3850 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3851 
3852 	tmp = 0;
3853 	/* enable the doorbell if requested */
3854 	if (prop->use_doorbell) {
3855 		tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3856 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3857 				DOORBELL_OFFSET, prop->doorbell_index);
3858 
3859 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3860 				    DOORBELL_EN, 1);
3861 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3862 				    DOORBELL_SOURCE, 0);
3863 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3864 				    DOORBELL_HIT, 0);
3865 	}
3866 
3867 	mqd->cp_hqd_pq_doorbell_control = tmp;
3868 
3869 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3870 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);
3871 
3872 	/* set the vmid for the queue */
3873 	mqd->cp_hqd_vmid = 0;
3874 
3875 	tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);
3876 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
3877 	mqd->cp_hqd_persistent_state = tmp;
3878 
3879 	/* set MIN_IB_AVAIL_SIZE */
3880 	tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);
3881 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3882 	mqd->cp_hqd_ib_control = tmp;
3883 
3884 	/* set static priority for a compute queue/ring */
3885 	mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
3886 	mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
3887 
3888 	mqd->cp_hqd_active = prop->hqd_active;
3889 
3890 	return 0;
3891 }
3892 
3893 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring)
3894 {
3895 	struct amdgpu_device *adev = ring->adev;
3896 	struct v11_compute_mqd *mqd = ring->mqd_ptr;
3897 	int j;
3898 
3899 	/* inactivate the queue */
3900 	if (amdgpu_sriov_vf(adev))
3901 		WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
3902 
3903 	/* disable wptr polling */
3904 	WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3905 
3906 	/* write the EOP addr */
3907 	WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
3908 	       mqd->cp_hqd_eop_base_addr_lo);
3909 	WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
3910 	       mqd->cp_hqd_eop_base_addr_hi);
3911 
3912 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3913 	WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
3914 	       mqd->cp_hqd_eop_control);
3915 
3916 	/* enable doorbell? */
3917 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3918 	       mqd->cp_hqd_pq_doorbell_control);
3919 
3920 	/* disable the queue if it's active */
3921 	if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
3922 		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3923 		for (j = 0; j < adev->usec_timeout; j++) {
3924 			if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
3925 				break;
3926 			udelay(1);
3927 		}
3928 		WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
3929 		       mqd->cp_hqd_dequeue_request);
3930 		WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
3931 		       mqd->cp_hqd_pq_rptr);
3932 		WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3933 		       mqd->cp_hqd_pq_wptr_lo);
3934 		WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3935 		       mqd->cp_hqd_pq_wptr_hi);
3936 	}
3937 
3938 	/* set the pointer to the MQD */
3939 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
3940 	       mqd->cp_mqd_base_addr_lo);
3941 	WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
3942 	       mqd->cp_mqd_base_addr_hi);
3943 
3944 	/* set MQD vmid to 0 */
3945 	WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
3946 	       mqd->cp_mqd_control);
3947 
3948 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3949 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
3950 	       mqd->cp_hqd_pq_base_lo);
3951 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
3952 	       mqd->cp_hqd_pq_base_hi);
3953 
3954 	/* set up the HQD, this is similar to CP_RB0_CNTL */
3955 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
3956 	       mqd->cp_hqd_pq_control);
3957 
3958 	/* set the wb address whether it's enabled or not */
3959 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
3960 		mqd->cp_hqd_pq_rptr_report_addr_lo);
3961 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3962 		mqd->cp_hqd_pq_rptr_report_addr_hi);
3963 
3964 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3965 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
3966 	       mqd->cp_hqd_pq_wptr_poll_addr_lo);
3967 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3968 	       mqd->cp_hqd_pq_wptr_poll_addr_hi);
3969 
3970 	/* enable the doorbell if requested */
3971 	if (ring->use_doorbell) {
3972 		WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3973 			(adev->doorbell_index.kiq * 2) << 2);
3974 		WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3975 			(adev->doorbell_index.userqueue_end * 2) << 2);
3976 	}
3977 
3978 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3979 	       mqd->cp_hqd_pq_doorbell_control);
3980 
3981 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3982 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3983 	       mqd->cp_hqd_pq_wptr_lo);
3984 	WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3985 	       mqd->cp_hqd_pq_wptr_hi);
3986 
3987 	/* set the vmid for the queue */
3988 	WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
3989 
3990 	WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
3991 	       mqd->cp_hqd_persistent_state);
3992 
3993 	/* activate the queue */
3994 	WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
3995 	       mqd->cp_hqd_active);
3996 
3997 	if (ring->use_doorbell)
3998 		WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3999 
4000 	return 0;
4001 }
4002 
4003 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring)
4004 {
4005 	struct amdgpu_device *adev = ring->adev;
4006 	struct v11_compute_mqd *mqd = ring->mqd_ptr;
4007 	int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
4008 
4009 	gfx_v11_0_kiq_setting(ring);
4010 
4011 	if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4012 		/* reset MQD to a clean status */
4013 		if (adev->gfx.mec.mqd_backup[mqd_idx])
4014 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
4015 
4016 		/* reset ring buffer */
4017 		ring->wptr = 0;
4018 		amdgpu_ring_clear_ring(ring);
4019 
4020 		mutex_lock(&adev->srbm_mutex);
4021 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4022 		gfx_v11_0_kiq_init_register(ring);
4023 		soc21_grbm_select(adev, 0, 0, 0, 0);
4024 		mutex_unlock(&adev->srbm_mutex);
4025 	} else {
4026 		memset((void *)mqd, 0, sizeof(*mqd));
4027 		mutex_lock(&adev->srbm_mutex);
4028 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4029 		amdgpu_ring_init_mqd(ring);
4030 		gfx_v11_0_kiq_init_register(ring);
4031 		soc21_grbm_select(adev, 0, 0, 0, 0);
4032 		mutex_unlock(&adev->srbm_mutex);
4033 
4034 		if (adev->gfx.mec.mqd_backup[mqd_idx])
4035 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
4036 	}
4037 
4038 	return 0;
4039 }
4040 
4041 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring)
4042 {
4043 	struct amdgpu_device *adev = ring->adev;
4044 	struct v11_compute_mqd *mqd = ring->mqd_ptr;
4045 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
4046 
4047 	if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
4048 		memset((void *)mqd, 0, sizeof(*mqd));
4049 		mutex_lock(&adev->srbm_mutex);
4050 		soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4051 		amdgpu_ring_init_mqd(ring);
4052 		soc21_grbm_select(adev, 0, 0, 0, 0);
4053 		mutex_unlock(&adev->srbm_mutex);
4054 
4055 		if (adev->gfx.mec.mqd_backup[mqd_idx])
4056 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
4057 	} else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4058 		/* reset MQD to a clean status */
4059 		if (adev->gfx.mec.mqd_backup[mqd_idx])
4060 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
4061 
4062 		/* reset ring buffer */
4063 		ring->wptr = 0;
4064 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
4065 		amdgpu_ring_clear_ring(ring);
4066 	} else {
4067 		amdgpu_ring_clear_ring(ring);
4068 	}
4069 
4070 	return 0;
4071 }
4072 
4073 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev)
4074 {
4075 	struct amdgpu_ring *ring;
4076 	int r;
4077 
4078 	ring = &adev->gfx.kiq.ring;
4079 
4080 	r = amdgpu_bo_reserve(ring->mqd_obj, false);
4081 	if (unlikely(r != 0))
4082 		return r;
4083 
4084 	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4085 	if (unlikely(r != 0)) {
4086 		amdgpu_bo_unreserve(ring->mqd_obj);
4087 		return r;
4088 	}
4089 
4090 	gfx_v11_0_kiq_init_queue(ring);
4091 	amdgpu_bo_kunmap(ring->mqd_obj);
4092 	ring->mqd_ptr = NULL;
4093 	amdgpu_bo_unreserve(ring->mqd_obj);
4094 	ring->sched.ready = true;
4095 	return 0;
4096 }
4097 
4098 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)
4099 {
4100 	struct amdgpu_ring *ring = NULL;
4101 	int r = 0, i;
4102 
4103 	if (!amdgpu_async_gfx_ring)
4104 		gfx_v11_0_cp_compute_enable(adev, true);
4105 
4106 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4107 		ring = &adev->gfx.compute_ring[i];
4108 
4109 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
4110 		if (unlikely(r != 0))
4111 			goto done;
4112 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4113 		if (!r) {
4114 			r = gfx_v11_0_kcq_init_queue(ring);
4115 			amdgpu_bo_kunmap(ring->mqd_obj);
4116 			ring->mqd_ptr = NULL;
4117 		}
4118 		amdgpu_bo_unreserve(ring->mqd_obj);
4119 		if (r)
4120 			goto done;
4121 	}
4122 
4123 	r = amdgpu_gfx_enable_kcq(adev);
4124 done:
4125 	return r;
4126 }
4127 
4128 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)
4129 {
4130 	int r, i;
4131 	struct amdgpu_ring *ring;
4132 
4133 	if (!(adev->flags & AMD_IS_APU))
4134 		gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4135 
4136 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4137 		/* legacy firmware loading */
4138 		r = gfx_v11_0_cp_gfx_load_microcode(adev);
4139 		if (r)
4140 			return r;
4141 
4142 		if (adev->gfx.rs64_enable)
4143 			r = gfx_v11_0_cp_compute_load_microcode_rs64(adev);
4144 		else
4145 			r = gfx_v11_0_cp_compute_load_microcode(adev);
4146 		if (r)
4147 			return r;
4148 	}
4149 
4150 	gfx_v11_0_cp_set_doorbell_range(adev);
4151 
4152 	if (amdgpu_async_gfx_ring) {
4153 		gfx_v11_0_cp_compute_enable(adev, true);
4154 		gfx_v11_0_cp_gfx_enable(adev, true);
4155 	}
4156 
4157 	if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
4158 		r = amdgpu_mes_kiq_hw_init(adev);
4159 	else
4160 		r = gfx_v11_0_kiq_resume(adev);
4161 	if (r)
4162 		return r;
4163 
4164 	r = gfx_v11_0_kcq_resume(adev);
4165 	if (r)
4166 		return r;
4167 
4168 	if (!amdgpu_async_gfx_ring) {
4169 		r = gfx_v11_0_cp_gfx_resume(adev);
4170 		if (r)
4171 			return r;
4172 	} else {
4173 		r = gfx_v11_0_cp_async_gfx_ring_resume(adev);
4174 		if (r)
4175 			return r;
4176 	}
4177 
4178 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4179 		ring = &adev->gfx.gfx_ring[i];
4180 		r = amdgpu_ring_test_helper(ring);
4181 		if (r)
4182 			return r;
4183 	}
4184 
4185 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4186 		ring = &adev->gfx.compute_ring[i];
4187 		r = amdgpu_ring_test_helper(ring);
4188 		if (r)
4189 			return r;
4190 	}
4191 
4192 	return 0;
4193 }
4194 
4195 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable)
4196 {
4197 	gfx_v11_0_cp_gfx_enable(adev, enable);
4198 	gfx_v11_0_cp_compute_enable(adev, enable);
4199 }
4200 
4201 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
4202 {
4203 	int r;
4204 	bool value;
4205 
4206 	r = adev->gfxhub.funcs->gart_enable(adev);
4207 	if (r)
4208 		return r;
4209 
4210 	adev->hdp.funcs->flush_hdp(adev, NULL);
4211 
4212 	value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
4213 		false : true;
4214 
4215 	adev->gfxhub.funcs->set_fault_enable_default(adev, value);
4216 	amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
4217 
4218 	return 0;
4219 }
4220 
4221 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev)
4222 {
4223 	u32 tmp;
4224 
4225 	/* select RS64 */
4226 	if (adev->gfx.rs64_enable) {
4227 		tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);
4228 		tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1);
4229 		WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp);
4230 
4231 		tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL);
4232 		tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1);
4233 		WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp);
4234 	}
4235 
4236 	if (amdgpu_emu_mode == 1)
4237 		drm_msleep(100);
4238 }
4239 
4240 static int get_gb_addr_config(struct amdgpu_device * adev)
4241 {
4242 	u32 gb_addr_config;
4243 
4244 	gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
4245 	if (gb_addr_config == 0)
4246 		return -EINVAL;
4247 
4248 	adev->gfx.config.gb_addr_config_fields.num_pkrs =
4249 		1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4250 
4251 	adev->gfx.config.gb_addr_config = gb_addr_config;
4252 
4253 	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4254 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4255 				      GB_ADDR_CONFIG, NUM_PIPES);
4256 
4257 	adev->gfx.config.max_tile_pipes =
4258 		adev->gfx.config.gb_addr_config_fields.num_pipes;
4259 
4260 	adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4261 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4262 				      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4263 	adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4264 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4265 				      GB_ADDR_CONFIG, NUM_RB_PER_SE);
4266 	adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4267 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4268 				      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4269 	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4270 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4271 				      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4272 
4273 	return 0;
4274 }
4275 
4276 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev)
4277 {
4278 	uint32_t data;
4279 
4280 	data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
4281 	data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
4282 	WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
4283 
4284 	data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
4285 	data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
4286 	WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
4287 }
4288 
4289 static int gfx_v11_0_hw_init(void *handle)
4290 {
4291 	int r;
4292 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4293 
4294 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4295 		if (adev->gfx.imu.funcs) {
4296 			/* RLC autoload sequence 1: Program rlc ram */
4297 			if (adev->gfx.imu.funcs->program_rlc_ram)
4298 				adev->gfx.imu.funcs->program_rlc_ram(adev);
4299 		}
4300 		/* rlc autoload firmware */
4301 		r = gfx_v11_0_rlc_backdoor_autoload_enable(adev);
4302 		if (r)
4303 			return r;
4304 	} else {
4305 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4306 			if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
4307 				if (adev->gfx.imu.funcs->load_microcode)
4308 					adev->gfx.imu.funcs->load_microcode(adev);
4309 				if (adev->gfx.imu.funcs->setup_imu)
4310 					adev->gfx.imu.funcs->setup_imu(adev);
4311 				if (adev->gfx.imu.funcs->start_imu)
4312 					adev->gfx.imu.funcs->start_imu(adev);
4313 			}
4314 
4315 			/* disable gpa mode in backdoor loading */
4316 			gfx_v11_0_disable_gpa_mode(adev);
4317 		}
4318 	}
4319 
4320 	if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||
4321 	    (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
4322 		r = gfx_v11_0_wait_for_rlc_autoload_complete(adev);
4323 		if (r) {
4324 			dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r);
4325 			return r;
4326 		}
4327 	}
4328 
4329 	adev->gfx.is_poweron = true;
4330 
4331 	if(get_gb_addr_config(adev))
4332 		DRM_WARN("Invalid gb_addr_config !\n");
4333 
4334 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
4335 	    adev->gfx.rs64_enable)
4336 		gfx_v11_0_config_gfx_rs64(adev);
4337 
4338 	r = gfx_v11_0_gfxhub_enable(adev);
4339 	if (r)
4340 		return r;
4341 
4342 	if (!amdgpu_emu_mode)
4343 		gfx_v11_0_init_golden_registers(adev);
4344 
4345 	if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
4346 	    (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
4347 		/**
4348 		 * For gfx 11, rlc firmware loading relies on smu firmware is
4349 		 * loaded firstly, so in direct type, it has to load smc ucode
4350 		 * here before rlc.
4351 		 */
4352 		if (!(adev->flags & AMD_IS_APU)) {
4353 			r = amdgpu_pm_load_smu_firmware(adev, NULL);
4354 			if (r)
4355 				return r;
4356 		}
4357 	}
4358 
4359 	gfx_v11_0_constants_init(adev);
4360 
4361 	if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
4362 		gfx_v11_0_select_cp_fw_arch(adev);
4363 
4364 	if (adev->nbio.funcs->gc_doorbell_init)
4365 		adev->nbio.funcs->gc_doorbell_init(adev);
4366 
4367 	r = gfx_v11_0_rlc_resume(adev);
4368 	if (r)
4369 		return r;
4370 
4371 	/*
4372 	 * init golden registers and rlc resume may override some registers,
4373 	 * reconfig them here
4374 	 */
4375 	gfx_v11_0_tcp_harvest(adev);
4376 
4377 	r = gfx_v11_0_cp_resume(adev);
4378 	if (r)
4379 		return r;
4380 
4381 	return r;
4382 }
4383 
4384 #ifndef BRING_UP_DEBUG
4385 static int gfx_v11_0_kiq_disable_kgq(struct amdgpu_device *adev)
4386 {
4387 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
4388 	struct amdgpu_ring *kiq_ring = &kiq->ring;
4389 	int i, r = 0;
4390 
4391 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
4392 		return -EINVAL;
4393 
4394 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
4395 					adev->gfx.num_gfx_rings))
4396 		return -ENOMEM;
4397 
4398 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4399 		kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
4400 					   PREEMPT_QUEUES, 0, 0);
4401 
4402 	if (adev->gfx.kiq.ring.sched.ready)
4403 		r = amdgpu_ring_test_helper(kiq_ring);
4404 
4405 	return r;
4406 }
4407 #endif
4408 
4409 static int gfx_v11_0_hw_fini(void *handle)
4410 {
4411 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4412 	int r;
4413 	uint32_t tmp;
4414 
4415 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4416 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4417 
4418 	if (!adev->no_hw_access) {
4419 #ifndef BRING_UP_DEBUG
4420 		if (amdgpu_async_gfx_ring) {
4421 			r = gfx_v11_0_kiq_disable_kgq(adev);
4422 			if (r)
4423 				DRM_ERROR("KGQ disable failed\n");
4424 		}
4425 #endif
4426 		if (amdgpu_gfx_disable_kcq(adev))
4427 			DRM_ERROR("KCQ disable failed\n");
4428 
4429 		amdgpu_mes_kiq_hw_fini(adev);
4430 	}
4431 
4432 	if (amdgpu_sriov_vf(adev)) {
4433 		gfx_v11_0_cp_gfx_enable(adev, false);
4434 		/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
4435 		tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
4436 		tmp &= 0xffffff00;
4437 		WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
4438 
4439 		return 0;
4440 	}
4441 	gfx_v11_0_cp_enable(adev, false);
4442 	gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4443 
4444 	adev->gfxhub.funcs->gart_disable(adev);
4445 
4446 	adev->gfx.is_poweron = false;
4447 
4448 	return 0;
4449 }
4450 
4451 static int gfx_v11_0_suspend(void *handle)
4452 {
4453 	return gfx_v11_0_hw_fini(handle);
4454 }
4455 
4456 static int gfx_v11_0_resume(void *handle)
4457 {
4458 	return gfx_v11_0_hw_init(handle);
4459 }
4460 
4461 static bool gfx_v11_0_is_idle(void *handle)
4462 {
4463 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4464 
4465 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
4466 				GRBM_STATUS, GUI_ACTIVE))
4467 		return false;
4468 	else
4469 		return true;
4470 }
4471 
4472 static int gfx_v11_0_wait_for_idle(void *handle)
4473 {
4474 	unsigned i;
4475 	u32 tmp;
4476 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4477 
4478 	for (i = 0; i < adev->usec_timeout; i++) {
4479 		/* read MC_STATUS */
4480 		tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
4481 			GRBM_STATUS__GUI_ACTIVE_MASK;
4482 
4483 		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
4484 			return 0;
4485 		udelay(1);
4486 	}
4487 	return -ETIMEDOUT;
4488 }
4489 
4490 static int gfx_v11_0_soft_reset(void *handle)
4491 {
4492 	u32 grbm_soft_reset = 0;
4493 	u32 tmp;
4494 	int i, j, k;
4495 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4496 
4497 	tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4498 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);
4499 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);
4500 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);
4501 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);
4502 	WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4503 
4504 	gfx_v11_0_set_safe_mode(adev);
4505 
4506 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4507 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4508 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4509 				tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
4510 				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
4511 				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
4512 				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
4513 				WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
4514 
4515 				WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
4516 				WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
4517 			}
4518 		}
4519 	}
4520 	for (i = 0; i < adev->gfx.me.num_me; ++i) {
4521 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4522 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4523 				tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
4524 				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
4525 				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
4526 				tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
4527 				WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
4528 
4529 				WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1);
4530 			}
4531 		}
4532 	}
4533 
4534 	WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe);
4535 
4536 	// Read CP_VMID_RESET register three times.
4537 	// to get sufficient time for GFX_HQD_ACTIVE reach 0
4538 	RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4539 	RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4540 	RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4541 
4542 	for (i = 0; i < adev->usec_timeout; i++) {
4543 		if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&
4544 		    !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))
4545 			break;
4546 		udelay(1);
4547 	}
4548 	if (i >= adev->usec_timeout) {
4549 		printk("Failed to wait all pipes clean\n");
4550 		return -EINVAL;
4551 	}
4552 
4553 	/**********  trigger soft reset  ***********/
4554 	grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4555 	grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4556 					SOFT_RESET_CP, 1);
4557 	grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4558 					SOFT_RESET_GFX, 1);
4559 	grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4560 					SOFT_RESET_CPF, 1);
4561 	grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4562 					SOFT_RESET_CPC, 1);
4563 	grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4564 					SOFT_RESET_CPG, 1);
4565 	WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4566 	/**********  exit soft reset  ***********/
4567 	grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4568 	grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4569 					SOFT_RESET_CP, 0);
4570 	grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4571 					SOFT_RESET_GFX, 0);
4572 	grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4573 					SOFT_RESET_CPF, 0);
4574 	grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4575 					SOFT_RESET_CPC, 0);
4576 	grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4577 					SOFT_RESET_CPG, 0);
4578 	WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4579 
4580 	tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL);
4581 	tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1);
4582 	WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp);
4583 
4584 	WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0);
4585 	WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0);
4586 
4587 	for (i = 0; i < adev->usec_timeout; i++) {
4588 		if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET))
4589 			break;
4590 		udelay(1);
4591 	}
4592 	if (i >= adev->usec_timeout) {
4593 		printk("Failed to wait CP_VMID_RESET to 0\n");
4594 		return -EINVAL;
4595 	}
4596 
4597 	tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4598 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4599 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4600 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4601 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4602 	WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4603 
4604 	gfx_v11_0_unset_safe_mode(adev);
4605 
4606 	return gfx_v11_0_cp_resume(adev);
4607 }
4608 
4609 static bool gfx_v11_0_check_soft_reset(void *handle)
4610 {
4611 	int i, r;
4612 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4613 	struct amdgpu_ring *ring;
4614 	long tmo = msecs_to_jiffies(1000);
4615 
4616 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4617 		ring = &adev->gfx.gfx_ring[i];
4618 		r = amdgpu_ring_test_ib(ring, tmo);
4619 		if (r)
4620 			return true;
4621 	}
4622 
4623 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4624 		ring = &adev->gfx.compute_ring[i];
4625 		r = amdgpu_ring_test_ib(ring, tmo);
4626 		if (r)
4627 			return true;
4628 	}
4629 
4630 	return false;
4631 }
4632 
4633 static int gfx_v11_0_post_soft_reset(void *handle)
4634 {
4635 	/**
4636 	 * GFX soft reset will impact MES, need resume MES when do GFX soft reset
4637 	 */
4638 	return amdgpu_mes_resume((struct amdgpu_device *)handle);
4639 }
4640 
4641 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4642 {
4643 	uint64_t clock;
4644 
4645 	amdgpu_gfx_off_ctrl(adev, false);
4646 	mutex_lock(&adev->gfx.gpu_clock_mutex);
4647 	clock = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER) |
4648 		((uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER) << 32ULL);
4649 	mutex_unlock(&adev->gfx.gpu_clock_mutex);
4650 	amdgpu_gfx_off_ctrl(adev, true);
4651 	return clock;
4652 }
4653 
4654 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4655 					   uint32_t vmid,
4656 					   uint32_t gds_base, uint32_t gds_size,
4657 					   uint32_t gws_base, uint32_t gws_size,
4658 					   uint32_t oa_base, uint32_t oa_size)
4659 {
4660 	struct amdgpu_device *adev = ring->adev;
4661 
4662 	/* GDS Base */
4663 	gfx_v11_0_write_data_to_reg(ring, 0, false,
4664 				    SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid,
4665 				    gds_base);
4666 
4667 	/* GDS Size */
4668 	gfx_v11_0_write_data_to_reg(ring, 0, false,
4669 				    SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid,
4670 				    gds_size);
4671 
4672 	/* GWS */
4673 	gfx_v11_0_write_data_to_reg(ring, 0, false,
4674 				    SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid,
4675 				    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4676 
4677 	/* OA */
4678 	gfx_v11_0_write_data_to_reg(ring, 0, false,
4679 				    SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid,
4680 				    (1 << (oa_size + oa_base)) - (1 << oa_base));
4681 }
4682 
4683 static int gfx_v11_0_early_init(void *handle)
4684 {
4685 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4686 
4687 	adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
4688 	adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
4689 					  AMDGPU_MAX_COMPUTE_RINGS);
4690 
4691 	gfx_v11_0_set_kiq_pm4_funcs(adev);
4692 	gfx_v11_0_set_ring_funcs(adev);
4693 	gfx_v11_0_set_irq_funcs(adev);
4694 	gfx_v11_0_set_gds_init(adev);
4695 	gfx_v11_0_set_rlc_funcs(adev);
4696 	gfx_v11_0_set_mqd_funcs(adev);
4697 	gfx_v11_0_set_imu_funcs(adev);
4698 
4699 	gfx_v11_0_init_rlcg_reg_access_ctrl(adev);
4700 
4701 	return 0;
4702 }
4703 
4704 static int gfx_v11_0_late_init(void *handle)
4705 {
4706 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4707 	int r;
4708 
4709 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4710 	if (r)
4711 		return r;
4712 
4713 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4714 	if (r)
4715 		return r;
4716 
4717 	return 0;
4718 }
4719 
4720 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)
4721 {
4722 	uint32_t rlc_cntl;
4723 
4724 	/* if RLC is not enabled, do nothing */
4725 	rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
4726 	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
4727 }
4728 
4729 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev)
4730 {
4731 	uint32_t data;
4732 	unsigned i;
4733 
4734 	data = RLC_SAFE_MODE__CMD_MASK;
4735 	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4736 
4737 	WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
4738 
4739 	/* wait for RLC_SAFE_MODE */
4740 	for (i = 0; i < adev->usec_timeout; i++) {
4741 		if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
4742 				   RLC_SAFE_MODE, CMD))
4743 			break;
4744 		udelay(1);
4745 	}
4746 }
4747 
4748 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev)
4749 {
4750 	WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
4751 }
4752 
4753 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
4754 				      bool enable)
4755 {
4756 	uint32_t def, data;
4757 
4758 	if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
4759 		return;
4760 
4761 	def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4762 
4763 	if (enable)
4764 		data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
4765 	else
4766 		data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
4767 
4768 	if (def != data)
4769 		WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4770 }
4771 
4772 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev,
4773 				       bool enable)
4774 {
4775 	uint32_t def, data;
4776 
4777 	if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
4778 		return;
4779 
4780 	def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4781 
4782 	if (enable)
4783 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4784 	else
4785 		data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4786 
4787 	if (def != data)
4788 		WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4789 }
4790 
4791 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev,
4792 					   bool enable)
4793 {
4794 	uint32_t def, data;
4795 
4796 	if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
4797 		return;
4798 
4799 	def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4800 
4801 	if (enable)
4802 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
4803 	else
4804 		data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
4805 
4806 	if (def != data)
4807 		WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4808 }
4809 
4810 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4811 						       bool enable)
4812 {
4813 	uint32_t data, def;
4814 
4815 	if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
4816 		return;
4817 
4818 	/* It is disabled by HW by default */
4819 	if (enable) {
4820 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4821 			/* 1 - RLC_CGTT_MGCG_OVERRIDE */
4822 			def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4823 
4824 			data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4825 				  RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4826 				  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4827 
4828 			if (def != data)
4829 				WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4830 		}
4831 	} else {
4832 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4833 			def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4834 
4835 			data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4836 				 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4837 				 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4838 
4839 			if (def != data)
4840 				WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4841 		}
4842 	}
4843 }
4844 
4845 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4846 						       bool enable)
4847 {
4848 	uint32_t def, data;
4849 
4850 	if (!(adev->cg_flags &
4851 	      (AMD_CG_SUPPORT_GFX_CGCG |
4852 	      AMD_CG_SUPPORT_GFX_CGLS |
4853 	      AMD_CG_SUPPORT_GFX_3D_CGCG |
4854 	      AMD_CG_SUPPORT_GFX_3D_CGLS)))
4855 		return;
4856 
4857 	if (enable) {
4858 		def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4859 
4860 		/* unset CGCG override */
4861 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4862 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4863 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4864 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4865 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG ||
4866 		    adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4867 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4868 
4869 		/* update CGCG override bits */
4870 		if (def != data)
4871 			WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4872 
4873 		/* enable cgcg FSM(0x0000363F) */
4874 		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4875 
4876 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
4877 			data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;
4878 			data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4879 				 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4880 		}
4881 
4882 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
4883 			data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;
4884 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4885 				 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4886 		}
4887 
4888 		if (def != data)
4889 			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4890 
4891 		/* Program RLC_CGCG_CGLS_CTRL_3D */
4892 		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4893 
4894 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
4895 			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;
4896 			data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4897 				 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4898 		}
4899 
4900 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
4901 			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;
4902 			data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4903 				 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4904 		}
4905 
4906 		if (def != data)
4907 			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4908 
4909 		/* set IDLE_POLL_COUNT(0x00900100) */
4910 		def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
4911 
4912 		data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);
4913 		data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4914 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4915 
4916 		if (def != data)
4917 			WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
4918 
4919 		data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4920 		data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4921 		data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4922 		data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4923 		data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4924 		WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
4925 
4926 		data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4927 		data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4928 		WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4929 
4930 		/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4931 		if (adev->sdma.num_instances > 1) {
4932 			data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4933 			data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4934 			WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4935 		}
4936 	} else {
4937 		/* Program RLC_CGCG_CGLS_CTRL */
4938 		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4939 
4940 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4941 			data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4942 
4943 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4944 			data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4945 
4946 		if (def != data)
4947 			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4948 
4949 		/* Program RLC_CGCG_CGLS_CTRL_3D */
4950 		def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4951 
4952 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
4953 			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4954 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4955 			data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4956 
4957 		if (def != data)
4958 			WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4959 
4960 		data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4961 		data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4962 		WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4963 
4964 		/* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4965 		if (adev->sdma.num_instances > 1) {
4966 			data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4967 			data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4968 			WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4969 		}
4970 	}
4971 }
4972 
4973 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4974 					    bool enable)
4975 {
4976 	amdgpu_gfx_rlc_enter_safe_mode(adev);
4977 
4978 	gfx_v11_0_update_coarse_grain_clock_gating(adev, enable);
4979 
4980 	gfx_v11_0_update_medium_grain_clock_gating(adev, enable);
4981 
4982 	gfx_v11_0_update_repeater_fgcg(adev, enable);
4983 
4984 	gfx_v11_0_update_sram_fgcg(adev, enable);
4985 
4986 	gfx_v11_0_update_perf_clk(adev, enable);
4987 
4988 	if (adev->cg_flags &
4989 	    (AMD_CG_SUPPORT_GFX_MGCG |
4990 	     AMD_CG_SUPPORT_GFX_CGLS |
4991 	     AMD_CG_SUPPORT_GFX_CGCG |
4992 	     AMD_CG_SUPPORT_GFX_3D_CGCG |
4993 	     AMD_CG_SUPPORT_GFX_3D_CGLS))
4994 	        gfx_v11_0_enable_gui_idle_interrupt(adev, enable);
4995 
4996 	amdgpu_gfx_rlc_exit_safe_mode(adev);
4997 
4998 	return 0;
4999 }
5000 
5001 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
5002 {
5003 	u32 reg, data;
5004 
5005 	amdgpu_gfx_off_ctrl(adev, false);
5006 
5007 	reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
5008 	if (amdgpu_sriov_is_pp_one_vf(adev))
5009 		data = RREG32_NO_KIQ(reg);
5010 	else
5011 		data = RREG32(reg);
5012 
5013 	data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
5014 	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
5015 
5016 	if (amdgpu_sriov_is_pp_one_vf(adev))
5017 		WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
5018 	else
5019 		WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
5020 
5021 	amdgpu_gfx_off_ctrl(adev, true);
5022 }
5023 
5024 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
5025 	.is_rlc_enabled = gfx_v11_0_is_rlc_enabled,
5026 	.set_safe_mode = gfx_v11_0_set_safe_mode,
5027 	.unset_safe_mode = gfx_v11_0_unset_safe_mode,
5028 	.init = gfx_v11_0_rlc_init,
5029 	.get_csb_size = gfx_v11_0_get_csb_size,
5030 	.get_csb_buffer = gfx_v11_0_get_csb_buffer,
5031 	.resume = gfx_v11_0_rlc_resume,
5032 	.stop = gfx_v11_0_rlc_stop,
5033 	.reset = gfx_v11_0_rlc_reset,
5034 	.start = gfx_v11_0_rlc_start,
5035 	.update_spm_vmid = gfx_v11_0_update_spm_vmid,
5036 };
5037 
5038 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
5039 {
5040 	u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
5041 
5042 	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5043 		data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5044 	else
5045 		data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5046 
5047 	WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);
5048 
5049 	// Program RLC_PG_DELAY3 for CGPG hysteresis
5050 	if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
5051 		switch (adev->ip_versions[GC_HWIP][0]) {
5052 		case IP_VERSION(11, 0, 1):
5053 		case IP_VERSION(11, 0, 4):
5054 			WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
5055 			break;
5056 		default:
5057 			break;
5058 		}
5059 	}
5060 }
5061 
5062 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
5063 {
5064 	amdgpu_gfx_rlc_enter_safe_mode(adev);
5065 
5066 	gfx_v11_cntl_power_gating(adev, enable);
5067 
5068 	amdgpu_gfx_rlc_exit_safe_mode(adev);
5069 }
5070 
5071 static int gfx_v11_0_set_powergating_state(void *handle,
5072 					   enum amd_powergating_state state)
5073 {
5074 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5075 	bool enable = (state == AMD_PG_STATE_GATE);
5076 
5077 	if (amdgpu_sriov_vf(adev))
5078 		return 0;
5079 
5080 	switch (adev->ip_versions[GC_HWIP][0]) {
5081 	case IP_VERSION(11, 0, 0):
5082 	case IP_VERSION(11, 0, 2):
5083 	case IP_VERSION(11, 0, 3):
5084 		amdgpu_gfx_off_ctrl(adev, enable);
5085 		break;
5086 	case IP_VERSION(11, 0, 1):
5087 	case IP_VERSION(11, 0, 4):
5088 		gfx_v11_cntl_pg(adev, enable);
5089 		amdgpu_gfx_off_ctrl(adev, enable);
5090 		break;
5091 	default:
5092 		break;
5093 	}
5094 
5095 	return 0;
5096 }
5097 
5098 static int gfx_v11_0_set_clockgating_state(void *handle,
5099 					  enum amd_clockgating_state state)
5100 {
5101 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5102 
5103 	if (amdgpu_sriov_vf(adev))
5104 	        return 0;
5105 
5106 	switch (adev->ip_versions[GC_HWIP][0]) {
5107 	case IP_VERSION(11, 0, 0):
5108 	case IP_VERSION(11, 0, 1):
5109 	case IP_VERSION(11, 0, 2):
5110 	case IP_VERSION(11, 0, 3):
5111 	case IP_VERSION(11, 0, 4):
5112 	        gfx_v11_0_update_gfx_clock_gating(adev,
5113 	                        state ==  AMD_CG_STATE_GATE);
5114 	        break;
5115 	default:
5116 	        break;
5117 	}
5118 
5119 	return 0;
5120 }
5121 
5122 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags)
5123 {
5124 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5125 	int data;
5126 
5127 	/* AMD_CG_SUPPORT_GFX_MGCG */
5128 	data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5129 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
5130 		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
5131 
5132 	/* AMD_CG_SUPPORT_REPEATER_FGCG */
5133 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
5134 		*flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
5135 
5136 	/* AMD_CG_SUPPORT_GFX_FGCG */
5137 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
5138 		*flags |= AMD_CG_SUPPORT_GFX_FGCG;
5139 
5140 	/* AMD_CG_SUPPORT_GFX_PERF_CLK */
5141 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
5142 		*flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
5143 
5144 	/* AMD_CG_SUPPORT_GFX_CGCG */
5145 	data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
5146 	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5147 		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
5148 
5149 	/* AMD_CG_SUPPORT_GFX_CGLS */
5150 	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5151 		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
5152 
5153 	/* AMD_CG_SUPPORT_GFX_3D_CGCG */
5154 	data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
5155 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
5156 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
5157 
5158 	/* AMD_CG_SUPPORT_GFX_3D_CGLS */
5159 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
5160 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
5161 }
5162 
5163 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5164 {
5165 	/* gfx11 is 32bit rptr*/
5166 	return *(uint32_t *)ring->rptr_cpu_addr;
5167 }
5168 
5169 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5170 {
5171 	struct amdgpu_device *adev = ring->adev;
5172 	u64 wptr;
5173 
5174 	/* XXX check if swapping is necessary on BE */
5175 	if (ring->use_doorbell) {
5176 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5177 	} else {
5178 		wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
5179 		wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
5180 	}
5181 
5182 	return wptr;
5183 }
5184 
5185 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5186 {
5187 	struct amdgpu_device *adev = ring->adev;
5188 	uint32_t *wptr_saved;
5189 	uint32_t *is_queue_unmap;
5190 	uint64_t aggregated_db_index;
5191 	uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
5192 	uint64_t wptr_tmp;
5193 
5194 	if (ring->is_mes_queue) {
5195 		wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
5196 		is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
5197 					      sizeof(uint32_t));
5198 		aggregated_db_index =
5199 			amdgpu_mes_get_aggregated_doorbell_index(adev,
5200 								 ring->hw_prio);
5201 
5202 		wptr_tmp = ring->wptr & ring->buf_mask;
5203 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
5204 		*wptr_saved = wptr_tmp;
5205 		/* assume doorbell always being used by mes mapped queue */
5206 		if (*is_queue_unmap) {
5207 			WDOORBELL64(aggregated_db_index, wptr_tmp);
5208 			WDOORBELL64(ring->doorbell_index, wptr_tmp);
5209 		} else {
5210 			WDOORBELL64(ring->doorbell_index, wptr_tmp);
5211 
5212 			if (*is_queue_unmap)
5213 				WDOORBELL64(aggregated_db_index, wptr_tmp);
5214 		}
5215 	} else {
5216 		if (ring->use_doorbell) {
5217 			/* XXX check if swapping is necessary on BE */
5218 			atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5219 				     ring->wptr);
5220 			WDOORBELL64(ring->doorbell_index, ring->wptr);
5221 		} else {
5222 			WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
5223 				     lower_32_bits(ring->wptr));
5224 			WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
5225 				     upper_32_bits(ring->wptr));
5226 		}
5227 	}
5228 }
5229 
5230 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5231 {
5232 	/* gfx11 hardware is 32bit rptr */
5233 	return *(uint32_t *)ring->rptr_cpu_addr;
5234 }
5235 
5236 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
5237 {
5238 	u64 wptr;
5239 
5240 	/* XXX check if swapping is necessary on BE */
5241 	if (ring->use_doorbell)
5242 		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5243 	else
5244 		BUG();
5245 	return wptr;
5246 }
5247 
5248 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
5249 {
5250 	struct amdgpu_device *adev = ring->adev;
5251 	uint32_t *wptr_saved;
5252 	uint32_t *is_queue_unmap;
5253 	uint64_t aggregated_db_index;
5254 	uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
5255 	uint64_t wptr_tmp;
5256 
5257 	if (ring->is_mes_queue) {
5258 		wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
5259 		is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
5260 					      sizeof(uint32_t));
5261 		aggregated_db_index =
5262 			amdgpu_mes_get_aggregated_doorbell_index(adev,
5263 								 ring->hw_prio);
5264 
5265 		wptr_tmp = ring->wptr & ring->buf_mask;
5266 		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
5267 		*wptr_saved = wptr_tmp;
5268 		/* assume doorbell always used by mes mapped queue */
5269 		if (*is_queue_unmap) {
5270 			WDOORBELL64(aggregated_db_index, wptr_tmp);
5271 			WDOORBELL64(ring->doorbell_index, wptr_tmp);
5272 		} else {
5273 			WDOORBELL64(ring->doorbell_index, wptr_tmp);
5274 
5275 			if (*is_queue_unmap)
5276 				WDOORBELL64(aggregated_db_index, wptr_tmp);
5277 		}
5278 	} else {
5279 		/* XXX check if swapping is necessary on BE */
5280 		if (ring->use_doorbell) {
5281 			atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5282 				     ring->wptr);
5283 			WDOORBELL64(ring->doorbell_index, ring->wptr);
5284 		} else {
5285 			BUG(); /* only DOORBELL method supported on gfx11 now */
5286 		}
5287 	}
5288 }
5289 
5290 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
5291 {
5292 	struct amdgpu_device *adev = ring->adev;
5293 	u32 ref_and_mask, reg_mem_engine;
5294 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
5295 
5296 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
5297 		switch (ring->me) {
5298 		case 1:
5299 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
5300 			break;
5301 		case 2:
5302 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
5303 			break;
5304 		default:
5305 			return;
5306 		}
5307 		reg_mem_engine = 0;
5308 	} else {
5309 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
5310 		reg_mem_engine = 1; /* pfp */
5311 	}
5312 
5313 	gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
5314 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
5315 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
5316 			       ref_and_mask, ref_and_mask, 0x20);
5317 }
5318 
5319 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
5320 				       struct amdgpu_job *job,
5321 				       struct amdgpu_ib *ib,
5322 				       uint32_t flags)
5323 {
5324 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5325 	u32 header, control = 0;
5326 
5327 	BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE);
5328 
5329 	header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5330 
5331 	control |= ib->length_dw | (vmid << 24);
5332 
5333 	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
5334 		control |= INDIRECT_BUFFER_PRE_ENB(1);
5335 
5336 		if (flags & AMDGPU_IB_PREEMPTED)
5337 			control |= INDIRECT_BUFFER_PRE_RESUME(1);
5338 
5339 		if (vmid)
5340 			gfx_v11_0_ring_emit_de_meta(ring,
5341 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
5342 	}
5343 
5344 	if (ring->is_mes_queue)
5345 		/* inherit vmid from mqd */
5346 		control |= 0x400000;
5347 
5348 	amdgpu_ring_write(ring, header);
5349 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5350 	amdgpu_ring_write(ring,
5351 #ifdef __BIG_ENDIAN
5352 		(2 << 0) |
5353 #endif
5354 		lower_32_bits(ib->gpu_addr));
5355 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5356 	amdgpu_ring_write(ring, control);
5357 }
5358 
5359 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
5360 					   struct amdgpu_job *job,
5361 					   struct amdgpu_ib *ib,
5362 					   uint32_t flags)
5363 {
5364 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5365 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
5366 
5367 	if (ring->is_mes_queue)
5368 		/* inherit vmid from mqd */
5369 		control |= 0x40000000;
5370 
5371 	/* Currently, there is a high possibility to get wave ID mismatch
5372 	 * between ME and GDS, leading to a hw deadlock, because ME generates
5373 	 * different wave IDs than the GDS expects. This situation happens
5374 	 * randomly when at least 5 compute pipes use GDS ordered append.
5375 	 * The wave IDs generated by ME are also wrong after suspend/resume.
5376 	 * Those are probably bugs somewhere else in the kernel driver.
5377 	 *
5378 	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
5379 	 * GDS to 0 for this ring (me/pipe).
5380 	 */
5381 	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
5382 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
5383 		amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
5384 		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
5385 	}
5386 
5387 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
5388 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5389 	amdgpu_ring_write(ring,
5390 #ifdef __BIG_ENDIAN
5391 				(2 << 0) |
5392 #endif
5393 				lower_32_bits(ib->gpu_addr));
5394 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5395 	amdgpu_ring_write(ring, control);
5396 }
5397 
5398 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
5399 				     u64 seq, unsigned flags)
5400 {
5401 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5402 	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5403 
5404 	/* RELEASE_MEM - flush caches, send int */
5405 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
5406 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
5407 				 PACKET3_RELEASE_MEM_GCR_GL2_WB |
5408 				 PACKET3_RELEASE_MEM_GCR_GL2_INV |
5409 				 PACKET3_RELEASE_MEM_GCR_GL2_US |
5410 				 PACKET3_RELEASE_MEM_GCR_GL1_INV |
5411 				 PACKET3_RELEASE_MEM_GCR_GLV_INV |
5412 				 PACKET3_RELEASE_MEM_GCR_GLM_INV |
5413 				 PACKET3_RELEASE_MEM_GCR_GLM_WB |
5414 				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
5415 				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5416 				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
5417 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
5418 				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
5419 
5420 	/*
5421 	 * the address should be Qword aligned if 64bit write, Dword
5422 	 * aligned if only send 32bit data low (discard data high)
5423 	 */
5424 	if (write64bit)
5425 		BUG_ON(addr & 0x7);
5426 	else
5427 		BUG_ON(addr & 0x3);
5428 	amdgpu_ring_write(ring, lower_32_bits(addr));
5429 	amdgpu_ring_write(ring, upper_32_bits(addr));
5430 	amdgpu_ring_write(ring, lower_32_bits(seq));
5431 	amdgpu_ring_write(ring, upper_32_bits(seq));
5432 	amdgpu_ring_write(ring, ring->is_mes_queue ?
5433 			 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
5434 }
5435 
5436 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
5437 {
5438 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5439 	uint32_t seq = ring->fence_drv.sync_seq;
5440 	uint64_t addr = ring->fence_drv.gpu_addr;
5441 
5442 	gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
5443 			       upper_32_bits(addr), seq, 0xffffffff, 4);
5444 }
5445 
5446 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
5447 				   uint16_t pasid, uint32_t flush_type,
5448 				   bool all_hub, uint8_t dst_sel)
5449 {
5450 	amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
5451 	amdgpu_ring_write(ring,
5452 			  PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
5453 			  PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
5454 			  PACKET3_INVALIDATE_TLBS_PASID(pasid) |
5455 			  PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
5456 }
5457 
5458 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5459 					 unsigned vmid, uint64_t pd_addr)
5460 {
5461 	if (ring->is_mes_queue)
5462 		gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
5463 	else
5464 		amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
5465 
5466 	/* compute doesn't have PFP */
5467 	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
5468 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
5469 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5470 		amdgpu_ring_write(ring, 0x0);
5471 	}
5472 }
5473 
5474 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
5475 					  u64 seq, unsigned int flags)
5476 {
5477 	struct amdgpu_device *adev = ring->adev;
5478 
5479 	/* we only allocate 32bit for each seq wb address */
5480 	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
5481 
5482 	/* write fence seq to the "addr" */
5483 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5484 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5485 				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
5486 	amdgpu_ring_write(ring, lower_32_bits(addr));
5487 	amdgpu_ring_write(ring, upper_32_bits(addr));
5488 	amdgpu_ring_write(ring, lower_32_bits(seq));
5489 
5490 	if (flags & AMDGPU_FENCE_FLAG_INT) {
5491 		/* set register to trigger INT */
5492 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5493 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5494 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
5495 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
5496 		amdgpu_ring_write(ring, 0);
5497 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
5498 	}
5499 }
5500 
5501 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
5502 					 uint32_t flags)
5503 {
5504 	uint32_t dw2 = 0;
5505 
5506 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
5507 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
5508 		/* set load_global_config & load_global_uconfig */
5509 		dw2 |= 0x8001;
5510 		/* set load_cs_sh_regs */
5511 		dw2 |= 0x01000000;
5512 		/* set load_per_context_state & load_gfx_sh_regs for GFX */
5513 		dw2 |= 0x10002;
5514 	}
5515 
5516 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5517 	amdgpu_ring_write(ring, dw2);
5518 	amdgpu_ring_write(ring, 0);
5519 }
5520 
5521 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
5522 {
5523 	unsigned ret;
5524 
5525 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
5526 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
5527 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
5528 	amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
5529 	ret = ring->wptr & ring->buf_mask;
5530 	amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
5531 
5532 	return ret;
5533 }
5534 
5535 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
5536 {
5537 	unsigned cur;
5538 	BUG_ON(offset > ring->buf_mask);
5539 	BUG_ON(ring->ring[offset] != 0x55aa55aa);
5540 
5541 	cur = (ring->wptr - 1) & ring->buf_mask;
5542 	if (likely(cur > offset))
5543 		ring->ring[offset] = cur - offset;
5544 	else
5545 		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
5546 }
5547 
5548 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring)
5549 {
5550 	int i, r = 0;
5551 	struct amdgpu_device *adev = ring->adev;
5552 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
5553 	struct amdgpu_ring *kiq_ring = &kiq->ring;
5554 	unsigned long flags;
5555 
5556 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
5557 		return -EINVAL;
5558 
5559 	spin_lock_irqsave(&kiq->ring_lock, flags);
5560 
5561 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
5562 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
5563 		return -ENOMEM;
5564 	}
5565 
5566 	/* assert preemption condition */
5567 	amdgpu_ring_set_preempt_cond_exec(ring, false);
5568 
5569 	/* assert IB preemption, emit the trailing fence */
5570 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
5571 				   ring->trail_fence_gpu_addr,
5572 				   ++ring->trail_seq);
5573 	amdgpu_ring_commit(kiq_ring);
5574 
5575 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
5576 
5577 	/* poll the trailing fence */
5578 	for (i = 0; i < adev->usec_timeout; i++) {
5579 		if (ring->trail_seq ==
5580 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
5581 			break;
5582 		udelay(1);
5583 	}
5584 
5585 	if (i >= adev->usec_timeout) {
5586 		r = -EINVAL;
5587 		DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
5588 	}
5589 
5590 	/* deassert preemption condition */
5591 	amdgpu_ring_set_preempt_cond_exec(ring, true);
5592 	return r;
5593 }
5594 
5595 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
5596 {
5597 	struct amdgpu_device *adev = ring->adev;
5598 	struct v10_de_ib_state de_payload = {0};
5599 	uint64_t offset, gds_addr, de_payload_gpu_addr;
5600 	void *de_payload_cpu_addr;
5601 	int cnt;
5602 
5603 	if (ring->is_mes_queue) {
5604 		offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5605 				  gfx[0].gfx_meta_data) +
5606 			offsetof(struct v10_gfx_meta_data, de_payload);
5607 		de_payload_gpu_addr =
5608 			amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5609 		de_payload_cpu_addr =
5610 			amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
5611 
5612 		offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5613 				  gfx[0].gds_backup) +
5614 			offsetof(struct v10_gfx_meta_data, de_payload);
5615 		gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5616 	} else {
5617 		offset = offsetof(struct v10_gfx_meta_data, de_payload);
5618 		de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
5619 		de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
5620 
5621 		gds_addr = roundup2(amdgpu_csa_vaddr(ring->adev) +
5622 				 AMDGPU_CSA_SIZE - adev->gds.gds_size,
5623 				 PAGE_SIZE);
5624 	}
5625 
5626 	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
5627 	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
5628 
5629 	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
5630 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
5631 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5632 				 WRITE_DATA_DST_SEL(8) |
5633 				 WR_CONFIRM) |
5634 				 WRITE_DATA_CACHE_POLICY(0));
5635 	amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
5636 	amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
5637 
5638 	if (resume)
5639 		amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
5640 					   sizeof(de_payload) >> 2);
5641 	else
5642 		amdgpu_ring_write_multiple(ring, (void *)&de_payload,
5643 					   sizeof(de_payload) >> 2);
5644 }
5645 
5646 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
5647 				    bool secure)
5648 {
5649 	uint32_t v = secure ? FRAME_TMZ : 0;
5650 
5651 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
5652 	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
5653 }
5654 
5655 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
5656 				     uint32_t reg_val_offs)
5657 {
5658 	struct amdgpu_device *adev = ring->adev;
5659 
5660 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
5661 	amdgpu_ring_write(ring, 0 |	/* src: register*/
5662 				(5 << 8) |	/* dst: memory */
5663 				(1 << 20));	/* write confirm */
5664 	amdgpu_ring_write(ring, reg);
5665 	amdgpu_ring_write(ring, 0);
5666 	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
5667 				reg_val_offs * 4));
5668 	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
5669 				reg_val_offs * 4));
5670 }
5671 
5672 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
5673 				   uint32_t val)
5674 {
5675 	uint32_t cmd = 0;
5676 
5677 	switch (ring->funcs->type) {
5678 	case AMDGPU_RING_TYPE_GFX:
5679 		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
5680 		break;
5681 	case AMDGPU_RING_TYPE_KIQ:
5682 		cmd = (1 << 16); /* no inc addr */
5683 		break;
5684 	default:
5685 		cmd = WR_CONFIRM;
5686 		break;
5687 	}
5688 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5689 	amdgpu_ring_write(ring, cmd);
5690 	amdgpu_ring_write(ring, reg);
5691 	amdgpu_ring_write(ring, 0);
5692 	amdgpu_ring_write(ring, val);
5693 }
5694 
5695 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
5696 					uint32_t val, uint32_t mask)
5697 {
5698 	gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
5699 }
5700 
5701 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
5702 						   uint32_t reg0, uint32_t reg1,
5703 						   uint32_t ref, uint32_t mask)
5704 {
5705 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5706 
5707 	gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
5708 			       ref, mask, 0x20);
5709 }
5710 
5711 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring,
5712 					 unsigned vmid)
5713 {
5714 	struct amdgpu_device *adev = ring->adev;
5715 	uint32_t value = 0;
5716 
5717 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
5718 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
5719 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
5720 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
5721 	WREG32_SOC15(GC, 0, regSQ_CMD, value);
5722 }
5723 
5724 static void
5725 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5726 				      uint32_t me, uint32_t pipe,
5727 				      enum amdgpu_interrupt_state state)
5728 {
5729 	uint32_t cp_int_cntl, cp_int_cntl_reg;
5730 
5731 	if (!me) {
5732 		switch (pipe) {
5733 		case 0:
5734 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
5735 			break;
5736 		case 1:
5737 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);
5738 			break;
5739 		default:
5740 			DRM_DEBUG("invalid pipe %d\n", pipe);
5741 			return;
5742 		}
5743 	} else {
5744 		DRM_DEBUG("invalid me %d\n", me);
5745 		return;
5746 	}
5747 
5748 	switch (state) {
5749 	case AMDGPU_IRQ_STATE_DISABLE:
5750 		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5751 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5752 					    TIME_STAMP_INT_ENABLE, 0);
5753 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5754 					    GENERIC0_INT_ENABLE, 0);
5755 		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5756 		break;
5757 	case AMDGPU_IRQ_STATE_ENABLE:
5758 		cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5759 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5760 					    TIME_STAMP_INT_ENABLE, 1);
5761 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5762 					    GENERIC0_INT_ENABLE, 1);
5763 		WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5764 		break;
5765 	default:
5766 		break;
5767 	}
5768 }
5769 
5770 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5771 						     int me, int pipe,
5772 						     enum amdgpu_interrupt_state state)
5773 {
5774 	u32 mec_int_cntl, mec_int_cntl_reg;
5775 
5776 	/*
5777 	 * amdgpu controls only the first MEC. That's why this function only
5778 	 * handles the setting of interrupts for this specific MEC. All other
5779 	 * pipes' interrupts are set by amdkfd.
5780 	 */
5781 
5782 	if (me == 1) {
5783 		switch (pipe) {
5784 		case 0:
5785 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5786 			break;
5787 		case 1:
5788 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
5789 			break;
5790 		case 2:
5791 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
5792 			break;
5793 		case 3:
5794 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
5795 			break;
5796 		default:
5797 			DRM_DEBUG("invalid pipe %d\n", pipe);
5798 			return;
5799 		}
5800 	} else {
5801 		DRM_DEBUG("invalid me %d\n", me);
5802 		return;
5803 	}
5804 
5805 	switch (state) {
5806 	case AMDGPU_IRQ_STATE_DISABLE:
5807 		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5808 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5809 					     TIME_STAMP_INT_ENABLE, 0);
5810 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5811 					     GENERIC0_INT_ENABLE, 0);
5812 		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5813 		break;
5814 	case AMDGPU_IRQ_STATE_ENABLE:
5815 		mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5816 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5817 					     TIME_STAMP_INT_ENABLE, 1);
5818 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5819 					     GENERIC0_INT_ENABLE, 1);
5820 		WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5821 		break;
5822 	default:
5823 		break;
5824 	}
5825 }
5826 
5827 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5828 					    struct amdgpu_irq_src *src,
5829 					    unsigned type,
5830 					    enum amdgpu_interrupt_state state)
5831 {
5832 	switch (type) {
5833 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
5834 		gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
5835 		break;
5836 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
5837 		gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
5838 		break;
5839 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5840 		gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5841 		break;
5842 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5843 		gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5844 		break;
5845 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5846 		gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5847 		break;
5848 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5849 		gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5850 		break;
5851 	default:
5852 		break;
5853 	}
5854 	return 0;
5855 }
5856 
5857 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev,
5858 			     struct amdgpu_irq_src *source,
5859 			     struct amdgpu_iv_entry *entry)
5860 {
5861 	int i;
5862 	u8 me_id, pipe_id, queue_id;
5863 	struct amdgpu_ring *ring;
5864 	uint32_t mes_queue_id = entry->src_data[0];
5865 
5866 	DRM_DEBUG("IH: CP EOP\n");
5867 
5868 	if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
5869 		struct amdgpu_mes_queue *queue;
5870 
5871 		mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
5872 
5873 		spin_lock(&adev->mes.queue_id_lock);
5874 		queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
5875 		if (queue) {
5876 			DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
5877 			amdgpu_fence_process(queue->ring);
5878 		}
5879 		spin_unlock(&adev->mes.queue_id_lock);
5880 	} else {
5881 		me_id = (entry->ring_id & 0x0c) >> 2;
5882 		pipe_id = (entry->ring_id & 0x03) >> 0;
5883 		queue_id = (entry->ring_id & 0x70) >> 4;
5884 
5885 		switch (me_id) {
5886 		case 0:
5887 			if (pipe_id == 0)
5888 				amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5889 			else
5890 				amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
5891 			break;
5892 		case 1:
5893 		case 2:
5894 			for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5895 				ring = &adev->gfx.compute_ring[i];
5896 				/* Per-queue interrupt is supported for MEC starting from VI.
5897 				 * The interrupt can only be enabled/disabled per pipe instead
5898 				 * of per queue.
5899 				 */
5900 				if ((ring->me == me_id) &&
5901 				    (ring->pipe == pipe_id) &&
5902 				    (ring->queue == queue_id))
5903 					amdgpu_fence_process(ring);
5904 			}
5905 			break;
5906 		}
5907 	}
5908 
5909 	return 0;
5910 }
5911 
5912 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5913 					      struct amdgpu_irq_src *source,
5914 					      unsigned type,
5915 					      enum amdgpu_interrupt_state state)
5916 {
5917 	switch (state) {
5918 	case AMDGPU_IRQ_STATE_DISABLE:
5919 	case AMDGPU_IRQ_STATE_ENABLE:
5920 		WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
5921 			       PRIV_REG_INT_ENABLE,
5922 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5923 		break;
5924 	default:
5925 		break;
5926 	}
5927 
5928 	return 0;
5929 }
5930 
5931 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5932 					       struct amdgpu_irq_src *source,
5933 					       unsigned type,
5934 					       enum amdgpu_interrupt_state state)
5935 {
5936 	switch (state) {
5937 	case AMDGPU_IRQ_STATE_DISABLE:
5938 	case AMDGPU_IRQ_STATE_ENABLE:
5939 		WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
5940 			       PRIV_INSTR_INT_ENABLE,
5941 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5942 		break;
5943 	default:
5944 		break;
5945 	}
5946 
5947 	return 0;
5948 }
5949 
5950 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,
5951 					struct amdgpu_iv_entry *entry)
5952 {
5953 	u8 me_id, pipe_id, queue_id;
5954 	struct amdgpu_ring *ring;
5955 	int i;
5956 
5957 	me_id = (entry->ring_id & 0x0c) >> 2;
5958 	pipe_id = (entry->ring_id & 0x03) >> 0;
5959 	queue_id = (entry->ring_id & 0x70) >> 4;
5960 
5961 	switch (me_id) {
5962 	case 0:
5963 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5964 			ring = &adev->gfx.gfx_ring[i];
5965 			/* we only enabled 1 gfx queue per pipe for now */
5966 			if (ring->me == me_id && ring->pipe == pipe_id)
5967 				drm_sched_fault(&ring->sched);
5968 		}
5969 		break;
5970 	case 1:
5971 	case 2:
5972 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5973 			ring = &adev->gfx.compute_ring[i];
5974 			if (ring->me == me_id && ring->pipe == pipe_id &&
5975 			    ring->queue == queue_id)
5976 				drm_sched_fault(&ring->sched);
5977 		}
5978 		break;
5979 	default:
5980 		BUG();
5981 		break;
5982 	}
5983 }
5984 
5985 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev,
5986 				  struct amdgpu_irq_src *source,
5987 				  struct amdgpu_iv_entry *entry)
5988 {
5989 	DRM_ERROR("Illegal register access in command stream\n");
5990 	gfx_v11_0_handle_priv_fault(adev, entry);
5991 	return 0;
5992 }
5993 
5994 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev,
5995 				   struct amdgpu_irq_src *source,
5996 				   struct amdgpu_iv_entry *entry)
5997 {
5998 	DRM_ERROR("Illegal instruction in command stream\n");
5999 	gfx_v11_0_handle_priv_fault(adev, entry);
6000 	return 0;
6001 }
6002 
6003 #if 0
6004 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
6005 					     struct amdgpu_irq_src *src,
6006 					     unsigned int type,
6007 					     enum amdgpu_interrupt_state state)
6008 {
6009 	uint32_t tmp, target;
6010 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
6011 
6012 	target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
6013 	target += ring->pipe;
6014 
6015 	switch (type) {
6016 	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
6017 		if (state == AMDGPU_IRQ_STATE_DISABLE) {
6018 			tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6019 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
6020 					    GENERIC2_INT_ENABLE, 0);
6021 			WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6022 
6023 			tmp = RREG32_SOC15_IP(GC, target);
6024 			tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6025 					    GENERIC2_INT_ENABLE, 0);
6026 			WREG32_SOC15_IP(GC, target, tmp);
6027 		} else {
6028 			tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6029 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
6030 					    GENERIC2_INT_ENABLE, 1);
6031 			WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6032 
6033 			tmp = RREG32_SOC15_IP(GC, target);
6034 			tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6035 					    GENERIC2_INT_ENABLE, 1);
6036 			WREG32_SOC15_IP(GC, target, tmp);
6037 		}
6038 		break;
6039 	default:
6040 		BUG(); /* kiq only support GENERIC2_INT now */
6041 		break;
6042 	}
6043 	return 0;
6044 }
6045 #endif
6046 
6047 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring)
6048 {
6049 	const unsigned int gcr_cntl =
6050 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
6051 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
6052 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
6053 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
6054 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
6055 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
6056 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
6057 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
6058 
6059 	/* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
6060 	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
6061 	amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
6062 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
6063 	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
6064 	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6065 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
6066 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
6067 	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
6068 }
6069 
6070 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
6071 	.name = "gfx_v11_0",
6072 	.early_init = gfx_v11_0_early_init,
6073 	.late_init = gfx_v11_0_late_init,
6074 	.sw_init = gfx_v11_0_sw_init,
6075 	.sw_fini = gfx_v11_0_sw_fini,
6076 	.hw_init = gfx_v11_0_hw_init,
6077 	.hw_fini = gfx_v11_0_hw_fini,
6078 	.suspend = gfx_v11_0_suspend,
6079 	.resume = gfx_v11_0_resume,
6080 	.is_idle = gfx_v11_0_is_idle,
6081 	.wait_for_idle = gfx_v11_0_wait_for_idle,
6082 	.soft_reset = gfx_v11_0_soft_reset,
6083 	.check_soft_reset = gfx_v11_0_check_soft_reset,
6084 	.post_soft_reset = gfx_v11_0_post_soft_reset,
6085 	.set_clockgating_state = gfx_v11_0_set_clockgating_state,
6086 	.set_powergating_state = gfx_v11_0_set_powergating_state,
6087 	.get_clockgating_state = gfx_v11_0_get_clockgating_state,
6088 };
6089 
6090 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
6091 	.type = AMDGPU_RING_TYPE_GFX,
6092 	.align_mask = 0xff,
6093 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6094 	.support_64bit_ptrs = true,
6095 	.vmhub = AMDGPU_GFXHUB_0,
6096 	.get_rptr = gfx_v11_0_ring_get_rptr_gfx,
6097 	.get_wptr = gfx_v11_0_ring_get_wptr_gfx,
6098 	.set_wptr = gfx_v11_0_ring_set_wptr_gfx,
6099 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
6100 		5 + /* COND_EXEC */
6101 		7 + /* PIPELINE_SYNC */
6102 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6103 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6104 		2 + /* VM_FLUSH */
6105 		8 + /* FENCE for VM_FLUSH */
6106 		20 + /* GDS switch */
6107 		5 + /* COND_EXEC */
6108 		7 + /* HDP_flush */
6109 		4 + /* VGT_flush */
6110 		31 + /*	DE_META */
6111 		3 + /* CNTX_CTRL */
6112 		5 + /* HDP_INVL */
6113 		8 + 8 + /* FENCE x2 */
6114 		8, /* gfx_v11_0_emit_mem_sync */
6115 	.emit_ib_size =	4, /* gfx_v11_0_ring_emit_ib_gfx */
6116 	.emit_ib = gfx_v11_0_ring_emit_ib_gfx,
6117 	.emit_fence = gfx_v11_0_ring_emit_fence,
6118 	.emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6119 	.emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6120 	.emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6121 	.emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6122 	.test_ring = gfx_v11_0_ring_test_ring,
6123 	.test_ib = gfx_v11_0_ring_test_ib,
6124 	.insert_nop = amdgpu_ring_insert_nop,
6125 	.pad_ib = amdgpu_ring_generic_pad_ib,
6126 	.emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl,
6127 	.init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec,
6128 	.patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec,
6129 	.preempt_ib = gfx_v11_0_ring_preempt_ib,
6130 	.emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl,
6131 	.emit_wreg = gfx_v11_0_ring_emit_wreg,
6132 	.emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6133 	.emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6134 	.soft_recovery = gfx_v11_0_ring_soft_recovery,
6135 	.emit_mem_sync = gfx_v11_0_emit_mem_sync,
6136 };
6137 
6138 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
6139 	.type = AMDGPU_RING_TYPE_COMPUTE,
6140 	.align_mask = 0xff,
6141 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6142 	.support_64bit_ptrs = true,
6143 	.vmhub = AMDGPU_GFXHUB_0,
6144 	.get_rptr = gfx_v11_0_ring_get_rptr_compute,
6145 	.get_wptr = gfx_v11_0_ring_get_wptr_compute,
6146 	.set_wptr = gfx_v11_0_ring_set_wptr_compute,
6147 	.emit_frame_size =
6148 		20 + /* gfx_v11_0_ring_emit_gds_switch */
6149 		7 + /* gfx_v11_0_ring_emit_hdp_flush */
6150 		5 + /* hdp invalidate */
6151 		7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6152 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6153 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6154 		2 + /* gfx_v11_0_ring_emit_vm_flush */
6155 		8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */
6156 		8, /* gfx_v11_0_emit_mem_sync */
6157 	.emit_ib_size =	7, /* gfx_v11_0_ring_emit_ib_compute */
6158 	.emit_ib = gfx_v11_0_ring_emit_ib_compute,
6159 	.emit_fence = gfx_v11_0_ring_emit_fence,
6160 	.emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6161 	.emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6162 	.emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6163 	.emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6164 	.test_ring = gfx_v11_0_ring_test_ring,
6165 	.test_ib = gfx_v11_0_ring_test_ib,
6166 	.insert_nop = amdgpu_ring_insert_nop,
6167 	.pad_ib = amdgpu_ring_generic_pad_ib,
6168 	.emit_wreg = gfx_v11_0_ring_emit_wreg,
6169 	.emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6170 	.emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6171 	.emit_mem_sync = gfx_v11_0_emit_mem_sync,
6172 };
6173 
6174 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {
6175 	.type = AMDGPU_RING_TYPE_KIQ,
6176 	.align_mask = 0xff,
6177 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
6178 	.support_64bit_ptrs = true,
6179 	.vmhub = AMDGPU_GFXHUB_0,
6180 	.get_rptr = gfx_v11_0_ring_get_rptr_compute,
6181 	.get_wptr = gfx_v11_0_ring_get_wptr_compute,
6182 	.set_wptr = gfx_v11_0_ring_set_wptr_compute,
6183 	.emit_frame_size =
6184 		20 + /* gfx_v11_0_ring_emit_gds_switch */
6185 		7 + /* gfx_v11_0_ring_emit_hdp_flush */
6186 		5 + /*hdp invalidate */
6187 		7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6188 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6189 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6190 		2 + /* gfx_v11_0_ring_emit_vm_flush */
6191 		8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6192 	.emit_ib_size =	7, /* gfx_v11_0_ring_emit_ib_compute */
6193 	.emit_ib = gfx_v11_0_ring_emit_ib_compute,
6194 	.emit_fence = gfx_v11_0_ring_emit_fence_kiq,
6195 	.test_ring = gfx_v11_0_ring_test_ring,
6196 	.test_ib = gfx_v11_0_ring_test_ib,
6197 	.insert_nop = amdgpu_ring_insert_nop,
6198 	.pad_ib = amdgpu_ring_generic_pad_ib,
6199 	.emit_rreg = gfx_v11_0_ring_emit_rreg,
6200 	.emit_wreg = gfx_v11_0_ring_emit_wreg,
6201 	.emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6202 	.emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6203 };
6204 
6205 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev)
6206 {
6207 	int i;
6208 
6209 	adev->gfx.kiq.ring.funcs = &gfx_v11_0_ring_funcs_kiq;
6210 
6211 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6212 		adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx;
6213 
6214 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
6215 		adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute;
6216 }
6217 
6218 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = {
6219 	.set = gfx_v11_0_set_eop_interrupt_state,
6220 	.process = gfx_v11_0_eop_irq,
6221 };
6222 
6223 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = {
6224 	.set = gfx_v11_0_set_priv_reg_fault_state,
6225 	.process = gfx_v11_0_priv_reg_irq,
6226 };
6227 
6228 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = {
6229 	.set = gfx_v11_0_set_priv_inst_fault_state,
6230 	.process = gfx_v11_0_priv_inst_irq,
6231 };
6232 
6233 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
6234 {
6235 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6236 	adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs;
6237 
6238 	adev->gfx.priv_reg_irq.num_types = 1;
6239 	adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs;
6240 
6241 	adev->gfx.priv_inst_irq.num_types = 1;
6242 	adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;
6243 }
6244 
6245 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
6246 {
6247 	if (adev->flags & AMD_IS_APU)
6248 		adev->gfx.imu.mode = MISSION_MODE;
6249 	else
6250 		adev->gfx.imu.mode = DEBUG_MODE;
6251 
6252 	adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
6253 }
6254 
6255 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev)
6256 {
6257 	adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs;
6258 }
6259 
6260 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev)
6261 {
6262 	unsigned total_cu = adev->gfx.config.max_cu_per_sh *
6263 			    adev->gfx.config.max_sh_per_se *
6264 			    adev->gfx.config.max_shader_engines;
6265 
6266 	adev->gds.gds_size = 0x1000;
6267 	adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
6268 	adev->gds.gws_size = 64;
6269 	adev->gds.oa_size = 16;
6270 }
6271 
6272 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev)
6273 {
6274 	/* set gfx eng mqd */
6275 	adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
6276 		sizeof(struct v11_gfx_mqd);
6277 	adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
6278 		gfx_v11_0_gfx_mqd_init;
6279 	/* set compute eng mqd */
6280 	adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
6281 		sizeof(struct v11_compute_mqd);
6282 	adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
6283 		gfx_v11_0_compute_mqd_init;
6284 }
6285 
6286 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
6287 							  u32 bitmap)
6288 {
6289 	u32 data;
6290 
6291 	if (!bitmap)
6292 		return;
6293 
6294 	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
6295 	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
6296 
6297 	WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
6298 }
6299 
6300 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
6301 {
6302 	u32 data, wgp_bitmask;
6303 	data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
6304 	data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
6305 
6306 	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
6307 	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
6308 
6309 	wgp_bitmask =
6310 		amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
6311 
6312 	return (~data) & wgp_bitmask;
6313 }
6314 
6315 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
6316 {
6317 	u32 wgp_idx, wgp_active_bitmap;
6318 	u32 cu_bitmap_per_wgp, cu_active_bitmap;
6319 
6320 	wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev);
6321 	cu_active_bitmap = 0;
6322 
6323 	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
6324 		/* if there is one WGP enabled, it means 2 CUs will be enabled */
6325 		cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
6326 		if (wgp_active_bitmap & (1 << wgp_idx))
6327 			cu_active_bitmap |= cu_bitmap_per_wgp;
6328 	}
6329 
6330 	return cu_active_bitmap;
6331 }
6332 
6333 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
6334 				 struct amdgpu_cu_info *cu_info)
6335 {
6336 	int i, j, k, counter, active_cu_number = 0;
6337 	u32 mask, bitmap;
6338 	unsigned disable_masks[8 * 2];
6339 
6340 	if (!adev || !cu_info)
6341 		return -EINVAL;
6342 
6343 	amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
6344 
6345 	mutex_lock(&adev->grbm_idx_mutex);
6346 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
6347 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
6348 			mask = 1;
6349 			counter = 0;
6350 			gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff);
6351 			if (i < 8 && j < 2)
6352 				gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(
6353 					adev, disable_masks[i * 2 + j]);
6354 			bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev);
6355 
6356 			/**
6357 			 * GFX11 could support more than 4 SEs, while the bitmap
6358 			 * in cu_info struct is 4x4 and ioctl interface struct
6359 			 * drm_amdgpu_info_device should keep stable.
6360 			 * So we use last two columns of bitmap to store cu mask for
6361 			 * SEs 4 to 7, the layout of the bitmap is as below:
6362 			 *    SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}
6363 			 *    SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}
6364 			 *    SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}
6365 			 *    SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}
6366 			 *    SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}
6367 			 *    SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]}
6368 			 *    SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
6369 			 *    SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
6370 			 */
6371 			cu_info->bitmap[i % 4][j + (i / 4) * 2] = bitmap;
6372 
6373 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
6374 				if (bitmap & mask)
6375 					counter++;
6376 
6377 				mask <<= 1;
6378 			}
6379 			active_cu_number += counter;
6380 		}
6381 	}
6382 	gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
6383 	mutex_unlock(&adev->grbm_idx_mutex);
6384 
6385 	cu_info->number = active_cu_number;
6386 	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
6387 
6388 	return 0;
6389 }
6390 
6391 const struct amdgpu_ip_block_version gfx_v11_0_ip_block =
6392 {
6393 	.type = AMD_IP_BLOCK_TYPE_GFX,
6394 	.major = 11,
6395 	.minor = 0,
6396 	.rev = 0,
6397 	.funcs = &gfx_v11_0_ip_funcs,
6398 };
6399