xref: /openbsd-src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c (revision 24bb5fcea3ed904bc467217bdaadb5dfc618d5bf) 
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "amdgpu_smu.h"
33 #include "nv.h"
34 #include "nvd.h"
35 
36 #include "gc/gc_10_1_0_offset.h"
37 #include "gc/gc_10_1_0_sh_mask.h"
38 #include "smuio/smuio_11_0_0_offset.h"
39 #include "smuio/smuio_11_0_0_sh_mask.h"
40 #include "navi10_enum.h"
41 #include "hdp/hdp_5_0_0_offset.h"
42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
43 
44 #include "soc15.h"
45 #include "soc15d.h"
46 #include "soc15_common.h"
47 #include "clearstate_gfx10.h"
48 #include "v10_structs.h"
49 #include "gfx_v10_0.h"
50 #include "nbio_v2_3.h"
51 
52 /**
53  * Navi10 has two graphic rings to share each graphic pipe.
54  * 1. Primary ring
55  * 2. Async ring
56  */
57 #define GFX10_NUM_GFX_RINGS_NV1X	1
58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid	1
59 #define GFX10_MEC_HPD_SIZE	2048
60 
61 #define F32_CE_PROGRAM_RAM_SIZE		65536
62 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
63 
64 #define mmCGTT_GS_NGG_CLK_CTRL	0x5087
65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX	1
66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
70 
71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
73 
74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
76 #define mmRLC_SAFE_MODE_Sienna_Cichlid			0x4ca0
77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX		1
78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid		0x4ca1
79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX	1
80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid			0x11ec
81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX		0
82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid		0x0fc1
83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid		0x0fc2
85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid			0x0fc3
87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX	0
88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid		0x0fc4
89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX	0
90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid		0x0fc5
91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX	0
92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid		0x0fc6
93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX	0
94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT	0x1a
95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK	0x04000000L
96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK	0x00000FFCL
97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT	0x2
98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK	0x00000FFCL
99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580
100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0
101 
102 #define mmCP_HYP_PFP_UCODE_ADDR			0x5814
103 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX	1
104 #define mmCP_HYP_PFP_UCODE_DATA			0x5815
105 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX	1
106 #define mmCP_HYP_CE_UCODE_ADDR			0x5818
107 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX		1
108 #define mmCP_HYP_CE_UCODE_DATA			0x5819
109 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX		1
110 #define mmCP_HYP_ME_UCODE_ADDR			0x5816
111 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX		1
112 #define mmCP_HYP_ME_UCODE_DATA			0x5817
113 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX		1
114 
115 //CC_GC_SA_UNIT_DISABLE
116 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
117 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
118 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT	0x8
119 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK		0x0000FF00L
120 //GC_USER_SA_UNIT_DISABLE
121 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
122 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
123 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT	0x8
124 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK	0x0000FF00L
125 //PA_SC_ENHANCE_3
126 #define mmPA_SC_ENHANCE_3                       0x1085
127 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
128 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
129 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
130 
131 #define mmCGTT_SPI_CS_CLK_CTRL			0x507c
132 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
133 
134 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
135 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
136 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
137 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
138 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
139 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
140 
141 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
142 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
143 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
144 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
145 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
146 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
147 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
148 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
149 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
150 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
151 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
152 
153 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
154 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
155 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
156 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
157 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
158 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
159 
160 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
161 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
162 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
163 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
164 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
165 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
166 
167 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
168 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
169 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
170 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
171 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
172 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
173 
174 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
175 {
176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
216 };
217 
218 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
219 {
220 	/* Pending on emulation bring up */
221 };
222 
223 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
224 {
225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1277 };
1278 
1279 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1280 {
1281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1319 };
1320 
1321 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1322 {
1323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1365 };
1366 
1367 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1368 {
1369 	static void *scratch_reg0;
1370 	static void *scratch_reg1;
1371 	static void *scratch_reg2;
1372 	static void *scratch_reg3;
1373 	static void *spare_int;
1374 	static uint32_t grbm_cntl;
1375 	static uint32_t grbm_idx;
1376 	uint32_t i = 0;
1377 	uint32_t retries = 50000;
1378 
1379 	scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1380 	scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1381 	scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1382 	scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1383 	spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1384 
1385 	grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1386 	grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1387 
1388 	if (amdgpu_sriov_runtime(adev)) {
1389 		pr_err("shouldn't call rlcg write register during runtime\n");
1390 		return;
1391 	}
1392 
1393 	writel(v, scratch_reg0);
1394 	writel(offset | 0x80000000, scratch_reg1);
1395 	writel(1, spare_int);
1396 	for (i = 0; i < retries; i++) {
1397 		u32 tmp;
1398 
1399 		tmp = readl(scratch_reg1);
1400 		if (!(tmp & 0x80000000))
1401 			break;
1402 
1403 		udelay(10);
1404 	}
1405 
1406 	if (i >= retries)
1407 		pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1408 }
1409 
1410 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1411 {
1412 	/* Pending on emulation bring up */
1413 };
1414 
1415 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1416 {
1417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2037 };
2038 
2039 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2040 {
2041 	/* Pending on emulation bring up */
2042 };
2043 
2044 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2045 {
2046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3098 };
3099 
3100 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3101 {
3102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3110 	SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3142 };
3143 
3144 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3145 {
3146 	/* Pending on emulation bring up */
3147 };
3148 
3149 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3150 {
3151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
3189 };
3190 
3191 #define DEFAULT_SH_MEM_CONFIG \
3192 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3193 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3194 	 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3195 	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3196 
3197 
3198 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3199 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3200 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3201 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3202 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3203                                  struct amdgpu_cu_info *cu_info);
3204 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3205 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3206 				   u32 sh_num, u32 instance);
3207 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3208 
3209 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3210 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3211 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3212 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3213 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3214 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3215 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3216 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3217 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3218 
3219 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3220 {
3221 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3222 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3223 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
3224 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
3225 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
3226 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */
3227 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */
3228 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
3229 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
3230 }
3231 
3232 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3233 				 struct amdgpu_ring *ring)
3234 {
3235 	struct amdgpu_device *adev = kiq_ring->adev;
3236 	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3237 	uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3238 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3239 
3240 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3241 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3242 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3243 			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3244 			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3245 			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3246 			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3247 			  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3248 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3249 			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3250 			  PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3251 			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3252 	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3253 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3254 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3255 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3256 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3257 }
3258 
3259 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3260 				   struct amdgpu_ring *ring,
3261 				   enum amdgpu_unmap_queues_action action,
3262 				   u64 gpu_addr, u64 seq)
3263 {
3264 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3265 
3266 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3267 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3268 			  PACKET3_UNMAP_QUEUES_ACTION(action) |
3269 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3270 			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3271 			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3272 	amdgpu_ring_write(kiq_ring,
3273 		  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3274 
3275 	if (action == PREEMPT_QUEUES_NO_UNMAP) {
3276 		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3277 		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3278 		amdgpu_ring_write(kiq_ring, seq);
3279 	} else {
3280 		amdgpu_ring_write(kiq_ring, 0);
3281 		amdgpu_ring_write(kiq_ring, 0);
3282 		amdgpu_ring_write(kiq_ring, 0);
3283 	}
3284 }
3285 
3286 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3287 				   struct amdgpu_ring *ring,
3288 				   u64 addr,
3289 				   u64 seq)
3290 {
3291 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3292 
3293 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3294 	amdgpu_ring_write(kiq_ring,
3295 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3296 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3297 			  PACKET3_QUERY_STATUS_COMMAND(2));
3298 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3299 			  PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3300 			  PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3301 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3302 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3303 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3304 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3305 }
3306 
3307 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3308 				uint16_t pasid, uint32_t flush_type,
3309 				bool all_hub)
3310 {
3311 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3312 	amdgpu_ring_write(kiq_ring,
3313 			PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3314 			PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3315 			PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3316 			PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3317 }
3318 
3319 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3320 	.kiq_set_resources = gfx10_kiq_set_resources,
3321 	.kiq_map_queues = gfx10_kiq_map_queues,
3322 	.kiq_unmap_queues = gfx10_kiq_unmap_queues,
3323 	.kiq_query_status = gfx10_kiq_query_status,
3324 	.kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3325 	.set_resources_size = 8,
3326 	.map_queues_size = 7,
3327 	.unmap_queues_size = 6,
3328 	.query_status_size = 7,
3329 	.invalidate_tlbs_size = 2,
3330 };
3331 
3332 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3333 {
3334 	adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3335 }
3336 
3337 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3338 {
3339 	switch (adev->asic_type) {
3340 	case CHIP_NAVI10:
3341 		soc15_program_register_sequence(adev,
3342 						golden_settings_gc_rlc_spm_10_0_nv10,
3343 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3344 		break;
3345 	case CHIP_NAVI14:
3346 		soc15_program_register_sequence(adev,
3347 						golden_settings_gc_rlc_spm_10_1_nv14,
3348 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3349 		break;
3350 	case CHIP_NAVI12:
3351 		soc15_program_register_sequence(adev,
3352 						golden_settings_gc_rlc_spm_10_1_2_nv12,
3353 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3354 		break;
3355 	default:
3356 		break;
3357 	}
3358 }
3359 
3360 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3361 {
3362 	switch (adev->asic_type) {
3363 	case CHIP_NAVI10:
3364 		soc15_program_register_sequence(adev,
3365 						golden_settings_gc_10_1,
3366 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3367 		soc15_program_register_sequence(adev,
3368 						golden_settings_gc_10_0_nv10,
3369 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3370 		break;
3371 	case CHIP_NAVI14:
3372 		soc15_program_register_sequence(adev,
3373 						golden_settings_gc_10_1_1,
3374 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3375 		soc15_program_register_sequence(adev,
3376 						golden_settings_gc_10_1_nv14,
3377 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3378 		break;
3379 	case CHIP_NAVI12:
3380 		soc15_program_register_sequence(adev,
3381 						golden_settings_gc_10_1_2,
3382 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3383 		soc15_program_register_sequence(adev,
3384 						golden_settings_gc_10_1_2_nv12,
3385 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3386 		break;
3387 	case CHIP_SIENNA_CICHLID:
3388 		soc15_program_register_sequence(adev,
3389 						golden_settings_gc_10_3,
3390 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3391 		soc15_program_register_sequence(adev,
3392 						golden_settings_gc_10_3_sienna_cichlid,
3393 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3394 		break;
3395 	case CHIP_NAVY_FLOUNDER:
3396 		soc15_program_register_sequence(adev,
3397 						golden_settings_gc_10_3_2,
3398 						(const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3399 		break;
3400 
3401 	default:
3402 		break;
3403 	}
3404 	gfx_v10_0_init_spm_golden_registers(adev);
3405 }
3406 
3407 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3408 {
3409 	adev->gfx.scratch.num_reg = 8;
3410 	adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3411 	adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3412 }
3413 
3414 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3415 				       bool wc, uint32_t reg, uint32_t val)
3416 {
3417 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3418 	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3419 			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3420 	amdgpu_ring_write(ring, reg);
3421 	amdgpu_ring_write(ring, 0);
3422 	amdgpu_ring_write(ring, val);
3423 }
3424 
3425 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3426 				  int mem_space, int opt, uint32_t addr0,
3427 				  uint32_t addr1, uint32_t ref, uint32_t mask,
3428 				  uint32_t inv)
3429 {
3430 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3431 	amdgpu_ring_write(ring,
3432 			  /* memory (1) or register (0) */
3433 			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3434 			   WAIT_REG_MEM_OPERATION(opt) | /* wait */
3435 			   WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3436 			   WAIT_REG_MEM_ENGINE(eng_sel)));
3437 
3438 	if (mem_space)
3439 		BUG_ON(addr0 & 0x3); /* Dword align */
3440 	amdgpu_ring_write(ring, addr0);
3441 	amdgpu_ring_write(ring, addr1);
3442 	amdgpu_ring_write(ring, ref);
3443 	amdgpu_ring_write(ring, mask);
3444 	amdgpu_ring_write(ring, inv); /* poll interval */
3445 }
3446 
3447 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3448 {
3449 	struct amdgpu_device *adev = ring->adev;
3450 	uint32_t scratch;
3451 	uint32_t tmp = 0;
3452 	unsigned i;
3453 	int r;
3454 
3455 	r = amdgpu_gfx_scratch_get(adev, &scratch);
3456 	if (r) {
3457 		DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3458 		return r;
3459 	}
3460 
3461 	WREG32(scratch, 0xCAFEDEAD);
3462 
3463 	r = amdgpu_ring_alloc(ring, 3);
3464 	if (r) {
3465 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3466 			  ring->idx, r);
3467 		amdgpu_gfx_scratch_free(adev, scratch);
3468 		return r;
3469 	}
3470 
3471 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3472 	amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3473 	amdgpu_ring_write(ring, 0xDEADBEEF);
3474 	amdgpu_ring_commit(ring);
3475 
3476 	for (i = 0; i < adev->usec_timeout; i++) {
3477 		tmp = RREG32(scratch);
3478 		if (tmp == 0xDEADBEEF)
3479 			break;
3480 		if (amdgpu_emu_mode == 1)
3481 			drm_msleep(1);
3482 		else
3483 			udelay(1);
3484 	}
3485 
3486 	if (i >= adev->usec_timeout)
3487 		r = -ETIMEDOUT;
3488 
3489 	amdgpu_gfx_scratch_free(adev, scratch);
3490 
3491 	return r;
3492 }
3493 
3494 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3495 {
3496 	struct amdgpu_device *adev = ring->adev;
3497 	struct amdgpu_ib ib;
3498 	struct dma_fence *f = NULL;
3499 	unsigned index;
3500 	uint64_t gpu_addr;
3501 	uint32_t tmp;
3502 	long r;
3503 
3504 	r = amdgpu_device_wb_get(adev, &index);
3505 	if (r)
3506 		return r;
3507 
3508 	gpu_addr = adev->wb.gpu_addr + (index * 4);
3509 	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3510 	memset(&ib, 0, sizeof(ib));
3511 	r = amdgpu_ib_get(adev, NULL, 16,
3512 					AMDGPU_IB_POOL_DIRECT, &ib);
3513 	if (r)
3514 		goto err1;
3515 
3516 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3517 	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3518 	ib.ptr[2] = lower_32_bits(gpu_addr);
3519 	ib.ptr[3] = upper_32_bits(gpu_addr);
3520 	ib.ptr[4] = 0xDEADBEEF;
3521 	ib.length_dw = 5;
3522 
3523 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3524 	if (r)
3525 		goto err2;
3526 
3527 	r = dma_fence_wait_timeout(f, false, timeout);
3528 	if (r == 0) {
3529 		r = -ETIMEDOUT;
3530 		goto err2;
3531 	} else if (r < 0) {
3532 		goto err2;
3533 	}
3534 
3535 	tmp = adev->wb.wb[index];
3536 	if (tmp == 0xDEADBEEF)
3537 		r = 0;
3538 	else
3539 		r = -EINVAL;
3540 err2:
3541 	amdgpu_ib_free(adev, &ib, NULL);
3542 	dma_fence_put(f);
3543 err1:
3544 	amdgpu_device_wb_free(adev, index);
3545 	return r;
3546 }
3547 
3548 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3549 {
3550 	release_firmware(adev->gfx.pfp_fw);
3551 	adev->gfx.pfp_fw = NULL;
3552 	release_firmware(adev->gfx.me_fw);
3553 	adev->gfx.me_fw = NULL;
3554 	release_firmware(adev->gfx.ce_fw);
3555 	adev->gfx.ce_fw = NULL;
3556 	release_firmware(adev->gfx.rlc_fw);
3557 	adev->gfx.rlc_fw = NULL;
3558 	release_firmware(adev->gfx.mec_fw);
3559 	adev->gfx.mec_fw = NULL;
3560 	release_firmware(adev->gfx.mec2_fw);
3561 	adev->gfx.mec2_fw = NULL;
3562 
3563 	kfree(adev->gfx.rlc.register_list_format);
3564 }
3565 
3566 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3567 {
3568 	adev->gfx.cp_fw_write_wait = false;
3569 
3570 	switch (adev->asic_type) {
3571 	case CHIP_NAVI10:
3572 	case CHIP_NAVI12:
3573 	case CHIP_NAVI14:
3574 		if ((adev->gfx.me_fw_version >= 0x00000046) &&
3575 		    (adev->gfx.me_feature_version >= 27) &&
3576 		    (adev->gfx.pfp_fw_version >= 0x00000068) &&
3577 		    (adev->gfx.pfp_feature_version >= 27) &&
3578 		    (adev->gfx.mec_fw_version >= 0x0000005b) &&
3579 		    (adev->gfx.mec_feature_version >= 27))
3580 			adev->gfx.cp_fw_write_wait = true;
3581 		break;
3582 	case CHIP_SIENNA_CICHLID:
3583 	case CHIP_NAVY_FLOUNDER:
3584 		adev->gfx.cp_fw_write_wait = true;
3585 		break;
3586 	default:
3587 		break;
3588 	}
3589 
3590 	if (!adev->gfx.cp_fw_write_wait)
3591 		DRM_WARN_ONCE("CP firmware version too old, please update!");
3592 }
3593 
3594 
3595 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3596 {
3597 	const struct rlc_firmware_header_v2_1 *rlc_hdr;
3598 
3599 	rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3600 	adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3601 	adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3602 	adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3603 	adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3604 	adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3605 	adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3606 	adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3607 	adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3608 	adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3609 	adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3610 	adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3611 	adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3612 	adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3613 			le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3614 }
3615 
3616 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3617 {
3618 	const struct rlc_firmware_header_v2_2 *rlc_hdr;
3619 
3620 	rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3621 	adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3622 	adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3623 	adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3624 	adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3625 }
3626 
3627 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3628 {
3629 	bool ret = false;
3630 
3631 	switch (adev->pdev->revision) {
3632 	case 0xc2:
3633 	case 0xc3:
3634 		ret = true;
3635 		break;
3636 	default:
3637 		ret = false;
3638 		break;
3639 	}
3640 
3641 	return ret ;
3642 }
3643 
3644 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3645 {
3646 	switch (adev->asic_type) {
3647 	case CHIP_NAVI10:
3648 		if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3649 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3650 		break;
3651 	case CHIP_NAVY_FLOUNDER:
3652 		adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3653 		break;
3654 	default:
3655 		break;
3656 	}
3657 }
3658 
3659 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3660 {
3661 	const char *chip_name;
3662 	char fw_name[40];
3663 	char wks[10];
3664 	int err;
3665 	struct amdgpu_firmware_info *info = NULL;
3666 	const struct common_firmware_header *header = NULL;
3667 	const struct gfx_firmware_header_v1_0 *cp_hdr;
3668 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
3669 	unsigned int *tmp = NULL;
3670 	unsigned int i = 0;
3671 	uint16_t version_major;
3672 	uint16_t version_minor;
3673 
3674 	DRM_DEBUG("\n");
3675 
3676 	memset(wks, 0, sizeof(wks));
3677 	switch (adev->asic_type) {
3678 	case CHIP_NAVI10:
3679 		chip_name = "navi10";
3680 		break;
3681 	case CHIP_NAVI14:
3682 		chip_name = "navi14";
3683 		if (!(adev->pdev->device == 0x7340 &&
3684 		      adev->pdev->revision != 0x00))
3685 			snprintf(wks, sizeof(wks), "_wks");
3686 		break;
3687 	case CHIP_NAVI12:
3688 		chip_name = "navi12";
3689 		break;
3690 	case CHIP_SIENNA_CICHLID:
3691 		chip_name = "sienna_cichlid";
3692 		break;
3693 	case CHIP_NAVY_FLOUNDER:
3694 		chip_name = "navy_flounder";
3695 		break;
3696 	default:
3697 		BUG();
3698 	}
3699 
3700 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3701 	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3702 	if (err)
3703 		goto out;
3704 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3705 	if (err)
3706 		goto out;
3707 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3708 	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3709 	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3710 
3711 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3712 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3713 	if (err)
3714 		goto out;
3715 	err = amdgpu_ucode_validate(adev->gfx.me_fw);
3716 	if (err)
3717 		goto out;
3718 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3719 	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3720 	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3721 
3722 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3723 	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3724 	if (err)
3725 		goto out;
3726 	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3727 	if (err)
3728 		goto out;
3729 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3730 	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3731 	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3732 
3733 	if (!amdgpu_sriov_vf(adev)) {
3734 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3735 		err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3736 		if (err)
3737 			goto out;
3738 		err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3739 		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3740 		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3741 		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3742 
3743 		adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3744 		adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3745 		adev->gfx.rlc.save_and_restore_offset =
3746 			le32_to_cpu(rlc_hdr->save_and_restore_offset);
3747 		adev->gfx.rlc.clear_state_descriptor_offset =
3748 			le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3749 		adev->gfx.rlc.avail_scratch_ram_locations =
3750 			le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3751 		adev->gfx.rlc.reg_restore_list_size =
3752 			le32_to_cpu(rlc_hdr->reg_restore_list_size);
3753 		adev->gfx.rlc.reg_list_format_start =
3754 			le32_to_cpu(rlc_hdr->reg_list_format_start);
3755 		adev->gfx.rlc.reg_list_format_separate_start =
3756 			le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3757 		adev->gfx.rlc.starting_offsets_start =
3758 			le32_to_cpu(rlc_hdr->starting_offsets_start);
3759 		adev->gfx.rlc.reg_list_format_size_bytes =
3760 			le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3761 		adev->gfx.rlc.reg_list_size_bytes =
3762 			le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3763 		adev->gfx.rlc.register_list_format =
3764 			kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3765 					adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3766 		if (!adev->gfx.rlc.register_list_format) {
3767 			err = -ENOMEM;
3768 			goto out;
3769 		}
3770 
3771 		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3772 							   le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3773 		for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3774 			adev->gfx.rlc.register_list_format[i] =	le32_to_cpu(tmp[i]);
3775 
3776 		adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3777 
3778 		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3779 							   le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3780 		for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3781 			adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3782 
3783 		if (version_major == 2) {
3784 			if (version_minor >= 1)
3785 				gfx_v10_0_init_rlc_ext_microcode(adev);
3786 			if (version_minor == 2)
3787 				gfx_v10_0_init_rlc_iram_dram_microcode(adev);
3788 		}
3789 	}
3790 
3791 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3792 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3793 	if (err)
3794 		goto out;
3795 	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3796 	if (err)
3797 		goto out;
3798 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3799 	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3800 	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3801 
3802 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3803 	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3804 	if (!err) {
3805 		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3806 		if (err)
3807 			goto out;
3808 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3809 		adev->gfx.mec2_fw->data;
3810 		adev->gfx.mec2_fw_version =
3811 		le32_to_cpu(cp_hdr->header.ucode_version);
3812 		adev->gfx.mec2_feature_version =
3813 		le32_to_cpu(cp_hdr->ucode_feature_version);
3814 	} else {
3815 		err = 0;
3816 		adev->gfx.mec2_fw = NULL;
3817 	}
3818 
3819 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3820 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3821 		info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3822 		info->fw = adev->gfx.pfp_fw;
3823 		header = (const struct common_firmware_header *)info->fw->data;
3824 		adev->firmware.fw_size +=
3825 			roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3826 
3827 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3828 		info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3829 		info->fw = adev->gfx.me_fw;
3830 		header = (const struct common_firmware_header *)info->fw->data;
3831 		adev->firmware.fw_size +=
3832 			roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3833 
3834 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3835 		info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3836 		info->fw = adev->gfx.ce_fw;
3837 		header = (const struct common_firmware_header *)info->fw->data;
3838 		adev->firmware.fw_size +=
3839 			roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3840 
3841 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3842 		info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3843 		info->fw = adev->gfx.rlc_fw;
3844 		if (info->fw) {
3845 			header = (const struct common_firmware_header *)info->fw->data;
3846 			adev->firmware.fw_size +=
3847 				roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3848 		}
3849 		if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3850 		    adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3851 		    adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3852 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3853 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3854 			info->fw = adev->gfx.rlc_fw;
3855 			adev->firmware.fw_size +=
3856 				roundup2(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3857 
3858 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3859 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3860 			info->fw = adev->gfx.rlc_fw;
3861 			adev->firmware.fw_size +=
3862 				roundup2(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3863 
3864 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3865 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3866 			info->fw = adev->gfx.rlc_fw;
3867 			adev->firmware.fw_size +=
3868 				roundup2(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3869 
3870 			if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
3871 			    adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
3872 				info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
3873 				info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
3874 				info->fw = adev->gfx.rlc_fw;
3875 				adev->firmware.fw_size +=
3876 					roundup2(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
3877 
3878 				info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
3879 				info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
3880 				info->fw = adev->gfx.rlc_fw;
3881 				adev->firmware.fw_size +=
3882 					roundup2(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
3883 			}
3884 		}
3885 
3886 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3887 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3888 		info->fw = adev->gfx.mec_fw;
3889 		header = (const struct common_firmware_header *)info->fw->data;
3890 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3891 		adev->firmware.fw_size +=
3892 			roundup2(le32_to_cpu(header->ucode_size_bytes) -
3893 			      le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3894 
3895 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3896 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3897 		info->fw = adev->gfx.mec_fw;
3898 		adev->firmware.fw_size +=
3899 			roundup2(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3900 
3901 		if (adev->gfx.mec2_fw) {
3902 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3903 			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3904 			info->fw = adev->gfx.mec2_fw;
3905 			header = (const struct common_firmware_header *)info->fw->data;
3906 			cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3907 			adev->firmware.fw_size +=
3908 				roundup2(le32_to_cpu(header->ucode_size_bytes) -
3909 				      le32_to_cpu(cp_hdr->jt_size) * 4,
3910 				      PAGE_SIZE);
3911 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3912 			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3913 			info->fw = adev->gfx.mec2_fw;
3914 			adev->firmware.fw_size +=
3915 				roundup2(le32_to_cpu(cp_hdr->jt_size) * 4,
3916 				      PAGE_SIZE);
3917 		}
3918 	}
3919 
3920 	gfx_v10_0_check_fw_write_wait(adev);
3921 out:
3922 	if (err) {
3923 		dev_err(adev->dev,
3924 			"gfx10: Failed to load firmware \"%s\"\n",
3925 			fw_name);
3926 		release_firmware(adev->gfx.pfp_fw);
3927 		adev->gfx.pfp_fw = NULL;
3928 		release_firmware(adev->gfx.me_fw);
3929 		adev->gfx.me_fw = NULL;
3930 		release_firmware(adev->gfx.ce_fw);
3931 		adev->gfx.ce_fw = NULL;
3932 		release_firmware(adev->gfx.rlc_fw);
3933 		adev->gfx.rlc_fw = NULL;
3934 		release_firmware(adev->gfx.mec_fw);
3935 		adev->gfx.mec_fw = NULL;
3936 		release_firmware(adev->gfx.mec2_fw);
3937 		adev->gfx.mec2_fw = NULL;
3938 	}
3939 
3940 	gfx_v10_0_check_gfxoff_flag(adev);
3941 
3942 	return err;
3943 }
3944 
3945 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3946 {
3947 	u32 count = 0;
3948 	const struct cs_section_def *sect = NULL;
3949 	const struct cs_extent_def *ext = NULL;
3950 
3951 	/* begin clear state */
3952 	count += 2;
3953 	/* context control state */
3954 	count += 3;
3955 
3956 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3957 		for (ext = sect->section; ext->extent != NULL; ++ext) {
3958 			if (sect->id == SECT_CONTEXT)
3959 				count += 2 + ext->reg_count;
3960 			else
3961 				return 0;
3962 		}
3963 	}
3964 
3965 	/* set PA_SC_TILE_STEERING_OVERRIDE */
3966 	count += 3;
3967 	/* end clear state */
3968 	count += 2;
3969 	/* clear state */
3970 	count += 2;
3971 
3972 	return count;
3973 }
3974 
3975 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3976 				    volatile u32 *buffer)
3977 {
3978 	u32 count = 0, i;
3979 	const struct cs_section_def *sect = NULL;
3980 	const struct cs_extent_def *ext = NULL;
3981 	int ctx_reg_offset;
3982 
3983 	if (adev->gfx.rlc.cs_data == NULL)
3984 		return;
3985 	if (buffer == NULL)
3986 		return;
3987 
3988 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3989 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3990 
3991 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3992 	buffer[count++] = cpu_to_le32(0x80000000);
3993 	buffer[count++] = cpu_to_le32(0x80000000);
3994 
3995 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3996 		for (ext = sect->section; ext->extent != NULL; ++ext) {
3997 			if (sect->id == SECT_CONTEXT) {
3998 				buffer[count++] =
3999 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4000 				buffer[count++] = cpu_to_le32(ext->reg_index -
4001 						PACKET3_SET_CONTEXT_REG_START);
4002 				for (i = 0; i < ext->reg_count; i++)
4003 					buffer[count++] = cpu_to_le32(ext->extent[i]);
4004 			} else {
4005 				return;
4006 			}
4007 		}
4008 	}
4009 
4010 	ctx_reg_offset =
4011 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4012 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4013 	buffer[count++] = cpu_to_le32(ctx_reg_offset);
4014 	buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4015 
4016 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4017 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4018 
4019 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4020 	buffer[count++] = cpu_to_le32(0);
4021 }
4022 
4023 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4024 {
4025 	/* clear state block */
4026 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4027 			&adev->gfx.rlc.clear_state_gpu_addr,
4028 			(void **)&adev->gfx.rlc.cs_ptr);
4029 
4030 	/* jump table block */
4031 	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4032 			&adev->gfx.rlc.cp_table_gpu_addr,
4033 			(void **)&adev->gfx.rlc.cp_table_ptr);
4034 }
4035 
4036 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4037 {
4038 	const struct cs_section_def *cs_data;
4039 	int r;
4040 
4041 	adev->gfx.rlc.cs_data = gfx10_cs_data;
4042 
4043 	cs_data = adev->gfx.rlc.cs_data;
4044 
4045 	if (cs_data) {
4046 		/* init clear state block */
4047 		r = amdgpu_gfx_rlc_init_csb(adev);
4048 		if (r)
4049 			return r;
4050 	}
4051 
4052 	/* init spm vmid with 0xf */
4053 	if (adev->gfx.rlc.funcs->update_spm_vmid)
4054 		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4055 
4056 	return 0;
4057 }
4058 
4059 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4060 {
4061 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4062 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4063 }
4064 
4065 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4066 {
4067 	int r;
4068 
4069 	bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4070 
4071 	amdgpu_gfx_graphics_queue_acquire(adev);
4072 
4073 	r = gfx_v10_0_init_microcode(adev);
4074 	if (r)
4075 		DRM_ERROR("Failed to load gfx firmware!\n");
4076 
4077 	return r;
4078 }
4079 
4080 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4081 {
4082 	int r;
4083 	u32 *hpd;
4084 	const __le32 *fw_data = NULL;
4085 	unsigned fw_size;
4086 	u32 *fw = NULL;
4087 	size_t mec_hpd_size;
4088 
4089 	const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4090 
4091 	bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4092 
4093 	/* take ownership of the relevant compute queues */
4094 	amdgpu_gfx_compute_queue_acquire(adev);
4095 	mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4096 
4097 	if (mec_hpd_size) {
4098 		r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4099 					      AMDGPU_GEM_DOMAIN_GTT,
4100 					      &adev->gfx.mec.hpd_eop_obj,
4101 					      &adev->gfx.mec.hpd_eop_gpu_addr,
4102 					      (void **)&hpd);
4103 		if (r) {
4104 			dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4105 			gfx_v10_0_mec_fini(adev);
4106 			return r;
4107 		}
4108 
4109 		memset(hpd, 0, mec_hpd_size);
4110 
4111 		amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4112 		amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4113 	}
4114 
4115 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4116 		mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4117 
4118 		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4119 			 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4120 		fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4121 
4122 		r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4123 					      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4124 					      &adev->gfx.mec.mec_fw_obj,
4125 					      &adev->gfx.mec.mec_fw_gpu_addr,
4126 					      (void **)&fw);
4127 		if (r) {
4128 			dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4129 			gfx_v10_0_mec_fini(adev);
4130 			return r;
4131 		}
4132 
4133 		memcpy(fw, fw_data, fw_size);
4134 
4135 		amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4136 		amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4137 	}
4138 
4139 	return 0;
4140 }
4141 
4142 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4143 {
4144 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4145 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4146 		(address << SQ_IND_INDEX__INDEX__SHIFT));
4147 	return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4148 }
4149 
4150 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4151 			   uint32_t thread, uint32_t regno,
4152 			   uint32_t num, uint32_t *out)
4153 {
4154 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4155 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4156 		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
4157 		(thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4158 		(SQ_IND_INDEX__AUTO_INCR_MASK));
4159 	while (num--)
4160 		*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4161 }
4162 
4163 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4164 {
4165 	/* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4166 	 * field when performing a select_se_sh so it should be
4167 	 * zero here */
4168 	WARN_ON(simd != 0);
4169 
4170 	/* type 2 wave data */
4171 	dst[(*no_fields)++] = 2;
4172 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4173 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4174 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4175 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4176 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4177 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4178 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4179 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4180 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4181 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4182 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4183 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4184 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4185 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4186 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4187 }
4188 
4189 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4190 				     uint32_t wave, uint32_t start,
4191 				     uint32_t size, uint32_t *dst)
4192 {
4193 	WARN_ON(simd != 0);
4194 
4195 	wave_read_regs(
4196 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4197 		dst);
4198 }
4199 
4200 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4201 				      uint32_t wave, uint32_t thread,
4202 				      uint32_t start, uint32_t size,
4203 				      uint32_t *dst)
4204 {
4205 	wave_read_regs(
4206 		adev, wave, thread,
4207 		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4208 }
4209 
4210 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4211 									  u32 me, u32 pipe, u32 q, u32 vm)
4212  {
4213        nv_grbm_select(adev, me, pipe, q, vm);
4214  }
4215 
4216 
4217 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4218 	.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4219 	.select_se_sh = &gfx_v10_0_select_se_sh,
4220 	.read_wave_data = &gfx_v10_0_read_wave_data,
4221 	.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4222 	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4223 	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4224 	.init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4225 };
4226 
4227 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4228 {
4229 	u32 gb_addr_config;
4230 
4231 	adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4232 
4233 	switch (adev->asic_type) {
4234 	case CHIP_NAVI10:
4235 	case CHIP_NAVI14:
4236 	case CHIP_NAVI12:
4237 		adev->gfx.config.max_hw_contexts = 8;
4238 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4239 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4240 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4241 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4242 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4243 		break;
4244 	case CHIP_SIENNA_CICHLID:
4245 	case CHIP_NAVY_FLOUNDER:
4246 		adev->gfx.config.max_hw_contexts = 8;
4247 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4248 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4249 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4250 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4251 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4252 		adev->gfx.config.gb_addr_config_fields.num_pkrs =
4253 			1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4254 		break;
4255 	default:
4256 		BUG();
4257 		break;
4258 	}
4259 
4260 	adev->gfx.config.gb_addr_config = gb_addr_config;
4261 
4262 	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4263 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4264 				      GB_ADDR_CONFIG, NUM_PIPES);
4265 
4266 	adev->gfx.config.max_tile_pipes =
4267 		adev->gfx.config.gb_addr_config_fields.num_pipes;
4268 
4269 	adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4270 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4271 				      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4272 	adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4273 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4274 				      GB_ADDR_CONFIG, NUM_RB_PER_SE);
4275 	adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4276 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4277 				      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4278 	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4279 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4280 				      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4281 }
4282 
4283 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4284 				   int me, int pipe, int queue)
4285 {
4286 	int r;
4287 	struct amdgpu_ring *ring;
4288 	unsigned int irq_type;
4289 
4290 	ring = &adev->gfx.gfx_ring[ring_id];
4291 
4292 	ring->me = me;
4293 	ring->pipe = pipe;
4294 	ring->queue = queue;
4295 
4296 	ring->ring_obj = NULL;
4297 	ring->use_doorbell = true;
4298 
4299 	if (!ring_id)
4300 		ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4301 	else
4302 		ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4303 	snprintf(ring->name, sizeof(ring->name), "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4304 
4305 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4306 	r = amdgpu_ring_init(adev, ring, 1024,
4307 			     &adev->gfx.eop_irq, irq_type,
4308 			     AMDGPU_RING_PRIO_DEFAULT);
4309 	if (r)
4310 		return r;
4311 	return 0;
4312 }
4313 
4314 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4315 				       int mec, int pipe, int queue)
4316 {
4317 	int r;
4318 	unsigned irq_type;
4319 	struct amdgpu_ring *ring;
4320 	unsigned int hw_prio;
4321 
4322 	ring = &adev->gfx.compute_ring[ring_id];
4323 
4324 	/* mec0 is me1 */
4325 	ring->me = mec + 1;
4326 	ring->pipe = pipe;
4327 	ring->queue = queue;
4328 
4329 	ring->ring_obj = NULL;
4330 	ring->use_doorbell = true;
4331 	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4332 	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4333 				+ (ring_id * GFX10_MEC_HPD_SIZE);
4334 	snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4335 
4336 	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4337 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4338 		+ ring->pipe;
4339 	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
4340 							    ring->queue) ?
4341 			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4342 	/* type-2 packets are deprecated on MEC, use type-3 instead */
4343 	r = amdgpu_ring_init(adev, ring, 1024,
4344 			     &adev->gfx.eop_irq, irq_type, hw_prio);
4345 	if (r)
4346 		return r;
4347 
4348 	return 0;
4349 }
4350 
4351 static int gfx_v10_0_sw_init(void *handle)
4352 {
4353 	int i, j, k, r, ring_id = 0;
4354 	struct amdgpu_kiq *kiq;
4355 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4356 
4357 	switch (adev->asic_type) {
4358 	case CHIP_NAVI10:
4359 	case CHIP_NAVI14:
4360 	case CHIP_NAVI12:
4361 		adev->gfx.me.num_me = 1;
4362 		adev->gfx.me.num_pipe_per_me = 1;
4363 		adev->gfx.me.num_queue_per_pipe = 1;
4364 		adev->gfx.mec.num_mec = 2;
4365 		adev->gfx.mec.num_pipe_per_mec = 4;
4366 		adev->gfx.mec.num_queue_per_pipe = 8;
4367 		break;
4368 	case CHIP_SIENNA_CICHLID:
4369 	case CHIP_NAVY_FLOUNDER:
4370 		adev->gfx.me.num_me = 1;
4371 		adev->gfx.me.num_pipe_per_me = 1;
4372 		adev->gfx.me.num_queue_per_pipe = 1;
4373 		adev->gfx.mec.num_mec = 2;
4374 		adev->gfx.mec.num_pipe_per_mec = 4;
4375 		adev->gfx.mec.num_queue_per_pipe = 4;
4376 		break;
4377 	default:
4378 		adev->gfx.me.num_me = 1;
4379 		adev->gfx.me.num_pipe_per_me = 1;
4380 		adev->gfx.me.num_queue_per_pipe = 1;
4381 		adev->gfx.mec.num_mec = 1;
4382 		adev->gfx.mec.num_pipe_per_mec = 4;
4383 		adev->gfx.mec.num_queue_per_pipe = 8;
4384 		break;
4385 	}
4386 
4387 	/* KIQ event */
4388 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4389 			      GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4390 			      &adev->gfx.kiq.irq);
4391 	if (r)
4392 		return r;
4393 
4394 	/* EOP Event */
4395 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4396 			      GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4397 			      &adev->gfx.eop_irq);
4398 	if (r)
4399 		return r;
4400 
4401 	/* Privileged reg */
4402 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4403 			      &adev->gfx.priv_reg_irq);
4404 	if (r)
4405 		return r;
4406 
4407 	/* Privileged inst */
4408 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4409 			      &adev->gfx.priv_inst_irq);
4410 	if (r)
4411 		return r;
4412 
4413 	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4414 
4415 	gfx_v10_0_scratch_init(adev);
4416 
4417 	r = gfx_v10_0_me_init(adev);
4418 	if (r)
4419 		return r;
4420 
4421 	r = gfx_v10_0_rlc_init(adev);
4422 	if (r) {
4423 		DRM_ERROR("Failed to init rlc BOs!\n");
4424 		return r;
4425 	}
4426 
4427 	r = gfx_v10_0_mec_init(adev);
4428 	if (r) {
4429 		DRM_ERROR("Failed to init MEC BOs!\n");
4430 		return r;
4431 	}
4432 
4433 	/* set up the gfx ring */
4434 	for (i = 0; i < adev->gfx.me.num_me; i++) {
4435 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4436 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4437 				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4438 					continue;
4439 
4440 				r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4441 							    i, k, j);
4442 				if (r)
4443 					return r;
4444 				ring_id++;
4445 			}
4446 		}
4447 	}
4448 
4449 	ring_id = 0;
4450 	/* set up the compute queues - allocate horizontally across pipes */
4451 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4452 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4453 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4454 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4455 								     j))
4456 					continue;
4457 
4458 				r = gfx_v10_0_compute_ring_init(adev, ring_id,
4459 								i, k, j);
4460 				if (r)
4461 					return r;
4462 
4463 				ring_id++;
4464 			}
4465 		}
4466 	}
4467 
4468 	r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4469 	if (r) {
4470 		DRM_ERROR("Failed to init KIQ BOs!\n");
4471 		return r;
4472 	}
4473 
4474 	kiq = &adev->gfx.kiq;
4475 	r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4476 	if (r)
4477 		return r;
4478 
4479 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4480 	if (r)
4481 		return r;
4482 
4483 	/* allocate visible FB for rlc auto-loading fw */
4484 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4485 		r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4486 		if (r)
4487 			return r;
4488 	}
4489 
4490 	adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4491 
4492 	gfx_v10_0_gpu_early_init(adev);
4493 
4494 	return 0;
4495 }
4496 
4497 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4498 {
4499 	amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4500 			      &adev->gfx.pfp.pfp_fw_gpu_addr,
4501 			      (void **)&adev->gfx.pfp.pfp_fw_ptr);
4502 }
4503 
4504 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4505 {
4506 	amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4507 			      &adev->gfx.ce.ce_fw_gpu_addr,
4508 			      (void **)&adev->gfx.ce.ce_fw_ptr);
4509 }
4510 
4511 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4512 {
4513 	amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4514 			      &adev->gfx.me.me_fw_gpu_addr,
4515 			      (void **)&adev->gfx.me.me_fw_ptr);
4516 }
4517 
4518 static int gfx_v10_0_sw_fini(void *handle)
4519 {
4520 	int i;
4521 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4522 
4523 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4524 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4525 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
4526 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4527 
4528 	amdgpu_gfx_mqd_sw_fini(adev);
4529 	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4530 	amdgpu_gfx_kiq_fini(adev);
4531 
4532 	gfx_v10_0_pfp_fini(adev);
4533 	gfx_v10_0_ce_fini(adev);
4534 	gfx_v10_0_me_fini(adev);
4535 	gfx_v10_0_rlc_fini(adev);
4536 	gfx_v10_0_mec_fini(adev);
4537 
4538 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4539 		gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4540 
4541 	gfx_v10_0_free_microcode(adev);
4542 
4543 	return 0;
4544 }
4545 
4546 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4547 				   u32 sh_num, u32 instance)
4548 {
4549 	u32 data;
4550 
4551 	if (instance == 0xffffffff)
4552 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4553 				     INSTANCE_BROADCAST_WRITES, 1);
4554 	else
4555 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4556 				     instance);
4557 
4558 	if (se_num == 0xffffffff)
4559 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4560 				     1);
4561 	else
4562 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4563 
4564 	if (sh_num == 0xffffffff)
4565 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4566 				     1);
4567 	else
4568 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4569 
4570 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4571 }
4572 
4573 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4574 {
4575 	u32 data, mask;
4576 
4577 	data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4578 	data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4579 
4580 	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4581 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4582 
4583 	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4584 					 adev->gfx.config.max_sh_per_se);
4585 
4586 	return (~data) & mask;
4587 }
4588 
4589 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4590 {
4591 	int i, j;
4592 	u32 data;
4593 	u32 active_rbs = 0;
4594 	u32 bitmap;
4595 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4596 					adev->gfx.config.max_sh_per_se;
4597 
4598 	mutex_lock(&adev->grbm_idx_mutex);
4599 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4600 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4601 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
4602 			if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4603 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4604 				continue;
4605 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4606 			data = gfx_v10_0_get_rb_active_bitmap(adev);
4607 			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4608 					       rb_bitmap_width_per_sh);
4609 		}
4610 	}
4611 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4612 	mutex_unlock(&adev->grbm_idx_mutex);
4613 
4614 	adev->gfx.config.backend_enable_mask = active_rbs;
4615 	adev->gfx.config.num_rbs = hweight32(active_rbs);
4616 }
4617 
4618 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4619 {
4620 	uint32_t num_sc;
4621 	uint32_t enabled_rb_per_sh;
4622 	uint32_t active_rb_bitmap;
4623 	uint32_t num_rb_per_sc;
4624 	uint32_t num_packer_per_sc;
4625 	uint32_t pa_sc_tile_steering_override;
4626 
4627 	/* for ASICs that integrates GFX v10.3
4628 	 * pa_sc_tile_steering_override should be set to 0 */
4629 	if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4630 	    adev->asic_type == CHIP_NAVY_FLOUNDER)
4631 		return 0;
4632 
4633 	/* init num_sc */
4634 	num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4635 			adev->gfx.config.num_sc_per_sh;
4636 	/* init num_rb_per_sc */
4637 	active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4638 	enabled_rb_per_sh = hweight32(active_rb_bitmap);
4639 	num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4640 	/* init num_packer_per_sc */
4641 	num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4642 
4643 	pa_sc_tile_steering_override = 0;
4644 	pa_sc_tile_steering_override |=
4645 		(order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4646 		PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4647 	pa_sc_tile_steering_override |=
4648 		(order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4649 		PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4650 	pa_sc_tile_steering_override |=
4651 		(order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4652 		PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4653 
4654 	return pa_sc_tile_steering_override;
4655 }
4656 
4657 #define DEFAULT_SH_MEM_BASES	(0x6000)
4658 
4659 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4660 {
4661 	int i;
4662 	uint32_t sh_mem_bases;
4663 
4664 	/*
4665 	 * Configure apertures:
4666 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4667 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4668 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4669 	 */
4670 	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4671 
4672 	mutex_lock(&adev->srbm_mutex);
4673 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4674 		nv_grbm_select(adev, 0, 0, 0, i);
4675 		/* CP and shaders */
4676 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4677 		WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4678 	}
4679 	nv_grbm_select(adev, 0, 0, 0, 0);
4680 	mutex_unlock(&adev->srbm_mutex);
4681 
4682 	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
4683 	   acccess. These should be enabled by FW for target VMIDs. */
4684 	for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4685 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4686 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4687 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4688 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4689 	}
4690 }
4691 
4692 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4693 {
4694 	int vmid;
4695 
4696 	/*
4697 	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4698 	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
4699 	 * the driver can enable them for graphics. VMID0 should maintain
4700 	 * access so that HWS firmware can save/restore entries.
4701 	 */
4702 	for (vmid = 1; vmid < 16; vmid++) {
4703 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4704 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4705 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4706 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4707 	}
4708 }
4709 
4710 
4711 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4712 {
4713 	int i, j, k;
4714 	int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4715 	u32 tmp, wgp_active_bitmap = 0;
4716 	u32 gcrd_targets_disable_tcp = 0;
4717 	u32 utcl_invreq_disable = 0;
4718 	/*
4719 	 * GCRD_TARGETS_DISABLE field contains
4720 	 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4721 	 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4722 	 */
4723 	u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4724 		2 * max_wgp_per_sh + /* TCP */
4725 		max_wgp_per_sh + /* SQC */
4726 		4); /* GL1C */
4727 	/*
4728 	 * UTCL1_UTCL0_INVREQ_DISABLE field contains
4729 	 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4730 	 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4731 	 */
4732 	u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4733 		2 * max_wgp_per_sh + /* TCP */
4734 		2 * max_wgp_per_sh + /* SQC */
4735 		4 + /* RMI */
4736 		1); /* SQG */
4737 
4738 	if (adev->asic_type == CHIP_NAVI10 ||
4739 	    adev->asic_type == CHIP_NAVI14 ||
4740 	    adev->asic_type == CHIP_NAVI12) {
4741 		mutex_lock(&adev->grbm_idx_mutex);
4742 		for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4743 			for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4744 				gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4745 				wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4746 				/*
4747 				 * Set corresponding TCP bits for the inactive WGPs in
4748 				 * GCRD_SA_TARGETS_DISABLE
4749 				 */
4750 				gcrd_targets_disable_tcp = 0;
4751 				/* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4752 				utcl_invreq_disable = 0;
4753 
4754 				for (k = 0; k < max_wgp_per_sh; k++) {
4755 					if (!(wgp_active_bitmap & (1 << k))) {
4756 						gcrd_targets_disable_tcp |= 3 << (2 * k);
4757 						utcl_invreq_disable |= (3 << (2 * k)) |
4758 							(3 << (2 * (max_wgp_per_sh + k)));
4759 					}
4760 				}
4761 
4762 				tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4763 				/* only override TCP & SQC bits */
4764 				tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4765 				tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4766 				WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4767 
4768 				tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4769 				/* only override TCP bits */
4770 				tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4771 				tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4772 				WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4773 			}
4774 		}
4775 
4776 		gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4777 		mutex_unlock(&adev->grbm_idx_mutex);
4778 	}
4779 }
4780 
4781 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4782 {
4783 	/* TCCs are global (not instanced). */
4784 	uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4785 			       RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4786 
4787 	adev->gfx.config.tcc_disabled_mask =
4788 		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4789 		(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4790 }
4791 
4792 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4793 {
4794 	u32 tmp;
4795 	int i;
4796 
4797 	WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4798 
4799 	gfx_v10_0_setup_rb(adev);
4800 	gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4801 	gfx_v10_0_get_tcc_info(adev);
4802 	adev->gfx.config.pa_sc_tile_steering_override =
4803 		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4804 
4805 	/* XXX SH_MEM regs */
4806 	/* where to put LDS, scratch, GPUVM in FSA64 space */
4807 	mutex_lock(&adev->srbm_mutex);
4808 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4809 		nv_grbm_select(adev, 0, 0, 0, i);
4810 		/* CP and shaders */
4811 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4812 		if (i != 0) {
4813 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4814 				(adev->gmc.private_aperture_start >> 48));
4815 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4816 				(adev->gmc.shared_aperture_start >> 48));
4817 			WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4818 		}
4819 	}
4820 	nv_grbm_select(adev, 0, 0, 0, 0);
4821 
4822 	mutex_unlock(&adev->srbm_mutex);
4823 
4824 	gfx_v10_0_init_compute_vmid(adev);
4825 	gfx_v10_0_init_gds_vmid(adev);
4826 
4827 }
4828 
4829 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4830 					       bool enable)
4831 {
4832 	u32 tmp;
4833 
4834 	if (amdgpu_sriov_vf(adev))
4835 		return;
4836 
4837 	tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4838 
4839 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4840 			    enable ? 1 : 0);
4841 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4842 			    enable ? 1 : 0);
4843 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4844 			    enable ? 1 : 0);
4845 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4846 			    enable ? 1 : 0);
4847 
4848 	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4849 }
4850 
4851 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4852 {
4853 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4854 
4855 	/* csib */
4856 	if (adev->asic_type == CHIP_NAVI12) {
4857 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4858 				adev->gfx.rlc.clear_state_gpu_addr >> 32);
4859 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4860 				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4861 		WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4862 	} else {
4863 		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
4864 				adev->gfx.rlc.clear_state_gpu_addr >> 32);
4865 		WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
4866 				adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4867 		WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4868 	}
4869 	return 0;
4870 }
4871 
4872 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4873 {
4874 	u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4875 
4876 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4877 	WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4878 }
4879 
4880 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4881 {
4882 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4883 	udelay(50);
4884 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4885 	udelay(50);
4886 }
4887 
4888 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4889 					     bool enable)
4890 {
4891 	uint32_t rlc_pg_cntl;
4892 
4893 	rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4894 
4895 	if (!enable) {
4896 		/* RLC_PG_CNTL[23] = 0 (default)
4897 		 * RLC will wait for handshake acks with SMU
4898 		 * GFXOFF will be enabled
4899 		 * RLC_PG_CNTL[23] = 1
4900 		 * RLC will not issue any message to SMU
4901 		 * hence no handshake between SMU & RLC
4902 		 * GFXOFF will be disabled
4903 		 */
4904 		rlc_pg_cntl |= 0x800000;
4905 	} else
4906 		rlc_pg_cntl &= ~0x800000;
4907 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4908 }
4909 
4910 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4911 {
4912 	/* TODO: enable rlc & smu handshake until smu
4913 	 * and gfxoff feature works as expected */
4914 	if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4915 		gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4916 
4917 	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4918 	udelay(50);
4919 }
4920 
4921 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4922 {
4923 	uint32_t tmp;
4924 
4925 	/* enable Save Restore Machine */
4926 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4927 	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4928 	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4929 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4930 }
4931 
4932 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4933 {
4934 	const struct rlc_firmware_header_v2_0 *hdr;
4935 	const __le32 *fw_data;
4936 	unsigned i, fw_size;
4937 
4938 	if (!adev->gfx.rlc_fw)
4939 		return -EINVAL;
4940 
4941 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4942 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
4943 
4944 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4945 			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4946 	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4947 
4948 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4949 		     RLCG_UCODE_LOADING_START_ADDRESS);
4950 
4951 	for (i = 0; i < fw_size; i++)
4952 		WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4953 			     le32_to_cpup(fw_data++));
4954 
4955 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4956 
4957 	return 0;
4958 }
4959 
4960 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4961 {
4962 	int r;
4963 
4964 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4965 
4966 		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4967 		if (r)
4968 			return r;
4969 
4970 		gfx_v10_0_init_csb(adev);
4971 
4972 		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4973 			gfx_v10_0_rlc_enable_srm(adev);
4974 	} else {
4975 		if (amdgpu_sriov_vf(adev)) {
4976 			gfx_v10_0_init_csb(adev);
4977 			return 0;
4978 		}
4979 
4980 		adev->gfx.rlc.funcs->stop(adev);
4981 
4982 		/* disable CG */
4983 		WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4984 
4985 		/* disable PG */
4986 		WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4987 
4988 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4989 			/* legacy rlc firmware loading */
4990 			r = gfx_v10_0_rlc_load_microcode(adev);
4991 			if (r)
4992 				return r;
4993 		} else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4994 			/* rlc backdoor autoload firmware */
4995 			r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4996 			if (r)
4997 				return r;
4998 		}
4999 
5000 		gfx_v10_0_init_csb(adev);
5001 
5002 		adev->gfx.rlc.funcs->start(adev);
5003 
5004 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5005 			r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5006 			if (r)
5007 				return r;
5008 		}
5009 	}
5010 	return 0;
5011 }
5012 
5013 static struct {
5014 	FIRMWARE_ID	id;
5015 	unsigned int	offset;
5016 	unsigned int	size;
5017 } rlc_autoload_info[FIRMWARE_ID_MAX];
5018 
5019 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5020 {
5021 	int ret;
5022 	RLC_TABLE_OF_CONTENT *rlc_toc;
5023 
5024 	ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5025 					AMDGPU_GEM_DOMAIN_GTT,
5026 					&adev->gfx.rlc.rlc_toc_bo,
5027 					&adev->gfx.rlc.rlc_toc_gpu_addr,
5028 					(void **)&adev->gfx.rlc.rlc_toc_buf);
5029 	if (ret) {
5030 		dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5031 		return ret;
5032 	}
5033 
5034 	/* Copy toc from psp sos fw to rlc toc buffer */
5035 	memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5036 
5037 	rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5038 	while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5039 		(rlc_toc->id < FIRMWARE_ID_MAX)) {
5040 		if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5041 		    (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5042 			/* Offset needs 4KB alignment */
5043 			rlc_toc->offset = roundup2(rlc_toc->offset * 4, PAGE_SIZE);
5044 		}
5045 
5046 		rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5047 		rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5048 		rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5049 
5050 		rlc_toc++;
5051 	}
5052 
5053 	return 0;
5054 }
5055 
5056 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5057 {
5058 	uint32_t total_size = 0;
5059 	FIRMWARE_ID id;
5060 	int ret;
5061 
5062 	ret = gfx_v10_0_parse_rlc_toc(adev);
5063 	if (ret) {
5064 		dev_err(adev->dev, "failed to parse rlc toc\n");
5065 		return 0;
5066 	}
5067 
5068 	for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5069 		total_size += rlc_autoload_info[id].size;
5070 
5071 	/* In case the offset in rlc toc ucode is aligned */
5072 	if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5073 		total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5074 				rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5075 
5076 	return total_size;
5077 }
5078 
5079 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5080 {
5081 	int r;
5082 	uint32_t total_size;
5083 
5084 	total_size = gfx_v10_0_calc_toc_total_size(adev);
5085 
5086 	r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5087 				      AMDGPU_GEM_DOMAIN_GTT,
5088 				      &adev->gfx.rlc.rlc_autoload_bo,
5089 				      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5090 				      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5091 	if (r) {
5092 		dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5093 		return r;
5094 	}
5095 
5096 	return 0;
5097 }
5098 
5099 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5100 {
5101 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5102 			      &adev->gfx.rlc.rlc_toc_gpu_addr,
5103 			      (void **)&adev->gfx.rlc.rlc_toc_buf);
5104 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5105 			      &adev->gfx.rlc.rlc_autoload_gpu_addr,
5106 			      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5107 }
5108 
5109 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5110 						       FIRMWARE_ID id,
5111 						       const void *fw_data,
5112 						       uint32_t fw_size)
5113 {
5114 	uint32_t toc_offset;
5115 	uint32_t toc_fw_size;
5116 	char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5117 
5118 	if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5119 		return;
5120 
5121 	toc_offset = rlc_autoload_info[id].offset;
5122 	toc_fw_size = rlc_autoload_info[id].size;
5123 
5124 	if (fw_size == 0)
5125 		fw_size = toc_fw_size;
5126 
5127 	if (fw_size > toc_fw_size)
5128 		fw_size = toc_fw_size;
5129 
5130 	memcpy(ptr + toc_offset, fw_data, fw_size);
5131 
5132 	if (fw_size < toc_fw_size)
5133 		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5134 }
5135 
5136 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5137 {
5138 	void *data;
5139 	uint32_t size;
5140 
5141 	data = adev->gfx.rlc.rlc_toc_buf;
5142 	size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5143 
5144 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5145 						   FIRMWARE_ID_RLC_TOC,
5146 						   data, size);
5147 }
5148 
5149 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5150 {
5151 	const __le32 *fw_data;
5152 	uint32_t fw_size;
5153 	const struct gfx_firmware_header_v1_0 *cp_hdr;
5154 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
5155 
5156 	/* pfp ucode */
5157 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5158 		adev->gfx.pfp_fw->data;
5159 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5160 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5161 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5162 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5163 						   FIRMWARE_ID_CP_PFP,
5164 						   fw_data, fw_size);
5165 
5166 	/* ce ucode */
5167 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5168 		adev->gfx.ce_fw->data;
5169 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5170 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5171 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5172 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5173 						   FIRMWARE_ID_CP_CE,
5174 						   fw_data, fw_size);
5175 
5176 	/* me ucode */
5177 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5178 		adev->gfx.me_fw->data;
5179 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5180 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5181 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5182 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5183 						   FIRMWARE_ID_CP_ME,
5184 						   fw_data, fw_size);
5185 
5186 	/* rlc ucode */
5187 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5188 		adev->gfx.rlc_fw->data;
5189 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5190 		le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5191 	fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5192 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5193 						   FIRMWARE_ID_RLC_G_UCODE,
5194 						   fw_data, fw_size);
5195 
5196 	/* mec1 ucode */
5197 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5198 		adev->gfx.mec_fw->data;
5199 	fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5200 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5201 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5202 		cp_hdr->jt_size * 4;
5203 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5204 						   FIRMWARE_ID_CP_MEC,
5205 						   fw_data, fw_size);
5206 	/* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5207 }
5208 
5209 /* Temporarily put sdma part here */
5210 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5211 {
5212 	const __le32 *fw_data;
5213 	uint32_t fw_size;
5214 	const struct sdma_firmware_header_v1_0 *sdma_hdr;
5215 	int i;
5216 
5217 	for (i = 0; i < adev->sdma.num_instances; i++) {
5218 		sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5219 			adev->sdma.instance[i].fw->data;
5220 		fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5221 			le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5222 		fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5223 
5224 		if (i == 0) {
5225 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5226 				FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5227 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5228 				FIRMWARE_ID_SDMA0_JT,
5229 				(uint32_t *)fw_data +
5230 				sdma_hdr->jt_offset,
5231 				sdma_hdr->jt_size * 4);
5232 		} else if (i == 1) {
5233 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5234 				FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5235 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5236 				FIRMWARE_ID_SDMA1_JT,
5237 				(uint32_t *)fw_data +
5238 				sdma_hdr->jt_offset,
5239 				sdma_hdr->jt_size * 4);
5240 		}
5241 	}
5242 }
5243 
5244 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5245 {
5246 	uint32_t rlc_g_offset, rlc_g_size, tmp;
5247 	uint64_t gpu_addr;
5248 
5249 	gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5250 	gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5251 	gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5252 
5253 	rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5254 	rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5255 	gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5256 
5257 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5258 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5259 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5260 
5261 	tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5262 	if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5263 		   RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5264 		DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5265 		return -EINVAL;
5266 	}
5267 
5268 	tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5269 	if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5270 		DRM_ERROR("RLC ROM should halt itself\n");
5271 		return -EINVAL;
5272 	}
5273 
5274 	return 0;
5275 }
5276 
5277 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5278 {
5279 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5280 	uint32_t tmp;
5281 	int i;
5282 	uint64_t addr;
5283 
5284 	/* Trigger an invalidation of the L1 instruction caches */
5285 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5286 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5287 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5288 
5289 	/* Wait for invalidation complete */
5290 	for (i = 0; i < usec_timeout; i++) {
5291 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5292 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5293 			INVALIDATE_CACHE_COMPLETE))
5294 			break;
5295 		udelay(1);
5296 	}
5297 
5298 	if (i >= usec_timeout) {
5299 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5300 		return -EINVAL;
5301 	}
5302 
5303 	/* Program me ucode address into intruction cache address register */
5304 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5305 		rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5306 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5307 			lower_32_bits(addr) & 0xFFFFF000);
5308 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5309 			upper_32_bits(addr));
5310 
5311 	return 0;
5312 }
5313 
5314 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5315 {
5316 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5317 	uint32_t tmp;
5318 	int i;
5319 	uint64_t addr;
5320 
5321 	/* Trigger an invalidation of the L1 instruction caches */
5322 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5323 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5324 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5325 
5326 	/* Wait for invalidation complete */
5327 	for (i = 0; i < usec_timeout; i++) {
5328 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5329 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5330 			INVALIDATE_CACHE_COMPLETE))
5331 			break;
5332 		udelay(1);
5333 	}
5334 
5335 	if (i >= usec_timeout) {
5336 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5337 		return -EINVAL;
5338 	}
5339 
5340 	/* Program ce ucode address into intruction cache address register */
5341 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5342 		rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5343 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5344 			lower_32_bits(addr) & 0xFFFFF000);
5345 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5346 			upper_32_bits(addr));
5347 
5348 	return 0;
5349 }
5350 
5351 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5352 {
5353 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5354 	uint32_t tmp;
5355 	int i;
5356 	uint64_t addr;
5357 
5358 	/* Trigger an invalidation of the L1 instruction caches */
5359 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5360 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5361 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5362 
5363 	/* Wait for invalidation complete */
5364 	for (i = 0; i < usec_timeout; i++) {
5365 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5366 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5367 			INVALIDATE_CACHE_COMPLETE))
5368 			break;
5369 		udelay(1);
5370 	}
5371 
5372 	if (i >= usec_timeout) {
5373 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5374 		return -EINVAL;
5375 	}
5376 
5377 	/* Program pfp ucode address into intruction cache address register */
5378 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5379 		rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5380 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5381 			lower_32_bits(addr) & 0xFFFFF000);
5382 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5383 			upper_32_bits(addr));
5384 
5385 	return 0;
5386 }
5387 
5388 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5389 {
5390 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5391 	uint32_t tmp;
5392 	int i;
5393 	uint64_t addr;
5394 
5395 	/* Trigger an invalidation of the L1 instruction caches */
5396 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5397 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5398 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5399 
5400 	/* Wait for invalidation complete */
5401 	for (i = 0; i < usec_timeout; i++) {
5402 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5403 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5404 			INVALIDATE_CACHE_COMPLETE))
5405 			break;
5406 		udelay(1);
5407 	}
5408 
5409 	if (i >= usec_timeout) {
5410 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5411 		return -EINVAL;
5412 	}
5413 
5414 	/* Program mec1 ucode address into intruction cache address register */
5415 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5416 		rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5417 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5418 			lower_32_bits(addr) & 0xFFFFF000);
5419 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5420 			upper_32_bits(addr));
5421 
5422 	return 0;
5423 }
5424 
5425 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5426 {
5427 	uint32_t cp_status;
5428 	uint32_t bootload_status;
5429 	int i, r;
5430 
5431 	for (i = 0; i < adev->usec_timeout; i++) {
5432 		cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5433 		bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5434 		if ((cp_status == 0) &&
5435 		    (REG_GET_FIELD(bootload_status,
5436 			RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5437 			break;
5438 		}
5439 		udelay(1);
5440 	}
5441 
5442 	if (i >= adev->usec_timeout) {
5443 		dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5444 		return -ETIMEDOUT;
5445 	}
5446 
5447 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5448 		r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5449 		if (r)
5450 			return r;
5451 
5452 		r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5453 		if (r)
5454 			return r;
5455 
5456 		r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5457 		if (r)
5458 			return r;
5459 
5460 		r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5461 		if (r)
5462 			return r;
5463 	}
5464 
5465 	return 0;
5466 }
5467 
5468 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5469 {
5470 	int i;
5471 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5472 
5473 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5474 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5475 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5476 
5477 	if (adev->asic_type == CHIP_NAVI12) {
5478 		WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5479 	} else {
5480 		WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5481 	}
5482 
5483 	for (i = 0; i < adev->usec_timeout; i++) {
5484 		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5485 			break;
5486 		udelay(1);
5487 	}
5488 
5489 	if (i >= adev->usec_timeout)
5490 		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5491 
5492 	return 0;
5493 }
5494 
5495 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5496 {
5497 	int r;
5498 	const struct gfx_firmware_header_v1_0 *pfp_hdr;
5499 	const __le32 *fw_data;
5500 	unsigned i, fw_size;
5501 	uint32_t tmp;
5502 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5503 
5504 	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5505 		adev->gfx.pfp_fw->data;
5506 
5507 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5508 
5509 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5510 		le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5511 	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5512 
5513 	r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5514 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5515 				      &adev->gfx.pfp.pfp_fw_obj,
5516 				      &adev->gfx.pfp.pfp_fw_gpu_addr,
5517 				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
5518 	if (r) {
5519 		dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5520 		gfx_v10_0_pfp_fini(adev);
5521 		return r;
5522 	}
5523 
5524 	memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5525 
5526 	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5527 	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5528 
5529 	/* Trigger an invalidation of the L1 instruction caches */
5530 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5531 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5532 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5533 
5534 	/* Wait for invalidation complete */
5535 	for (i = 0; i < usec_timeout; i++) {
5536 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5537 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5538 			INVALIDATE_CACHE_COMPLETE))
5539 			break;
5540 		udelay(1);
5541 	}
5542 
5543 	if (i >= usec_timeout) {
5544 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5545 		return -EINVAL;
5546 	}
5547 
5548 	if (amdgpu_emu_mode == 1)
5549 		adev->nbio.funcs->hdp_flush(adev, NULL);
5550 
5551 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5552 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5553 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5554 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5555 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5556 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5557 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5558 		adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5559 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5560 		upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5561 
5562 	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5563 
5564 	for (i = 0; i < pfp_hdr->jt_size; i++)
5565 		WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5566 			     le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5567 
5568 	WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5569 
5570 	return 0;
5571 }
5572 
5573 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5574 {
5575 	int r;
5576 	const struct gfx_firmware_header_v1_0 *ce_hdr;
5577 	const __le32 *fw_data;
5578 	unsigned i, fw_size;
5579 	uint32_t tmp;
5580 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5581 
5582 	ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5583 		adev->gfx.ce_fw->data;
5584 
5585 	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5586 
5587 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5588 		le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5589 	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5590 
5591 	r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5592 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5593 				      &adev->gfx.ce.ce_fw_obj,
5594 				      &adev->gfx.ce.ce_fw_gpu_addr,
5595 				      (void **)&adev->gfx.ce.ce_fw_ptr);
5596 	if (r) {
5597 		dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5598 		gfx_v10_0_ce_fini(adev);
5599 		return r;
5600 	}
5601 
5602 	memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5603 
5604 	amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5605 	amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5606 
5607 	/* Trigger an invalidation of the L1 instruction caches */
5608 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5609 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5610 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5611 
5612 	/* Wait for invalidation complete */
5613 	for (i = 0; i < usec_timeout; i++) {
5614 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5615 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5616 			INVALIDATE_CACHE_COMPLETE))
5617 			break;
5618 		udelay(1);
5619 	}
5620 
5621 	if (i >= usec_timeout) {
5622 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5623 		return -EINVAL;
5624 	}
5625 
5626 	if (amdgpu_emu_mode == 1)
5627 		adev->nbio.funcs->hdp_flush(adev, NULL);
5628 
5629 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5630 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5631 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5632 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5633 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5634 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5635 		adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5636 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5637 		upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5638 
5639 	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5640 
5641 	for (i = 0; i < ce_hdr->jt_size; i++)
5642 		WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5643 			     le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5644 
5645 	WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5646 
5647 	return 0;
5648 }
5649 
5650 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5651 {
5652 	int r;
5653 	const struct gfx_firmware_header_v1_0 *me_hdr;
5654 	const __le32 *fw_data;
5655 	unsigned i, fw_size;
5656 	uint32_t tmp;
5657 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5658 
5659 	me_hdr = (const struct gfx_firmware_header_v1_0 *)
5660 		adev->gfx.me_fw->data;
5661 
5662 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5663 
5664 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5665 		le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5666 	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5667 
5668 	r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5669 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5670 				      &adev->gfx.me.me_fw_obj,
5671 				      &adev->gfx.me.me_fw_gpu_addr,
5672 				      (void **)&adev->gfx.me.me_fw_ptr);
5673 	if (r) {
5674 		dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5675 		gfx_v10_0_me_fini(adev);
5676 		return r;
5677 	}
5678 
5679 	memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5680 
5681 	amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5682 	amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5683 
5684 	/* Trigger an invalidation of the L1 instruction caches */
5685 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5686 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5687 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5688 
5689 	/* Wait for invalidation complete */
5690 	for (i = 0; i < usec_timeout; i++) {
5691 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5692 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5693 			INVALIDATE_CACHE_COMPLETE))
5694 			break;
5695 		udelay(1);
5696 	}
5697 
5698 	if (i >= usec_timeout) {
5699 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5700 		return -EINVAL;
5701 	}
5702 
5703 	if (amdgpu_emu_mode == 1)
5704 		adev->nbio.funcs->hdp_flush(adev, NULL);
5705 
5706 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5707 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5708 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5709 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5710 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5711 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5712 		adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5713 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5714 		upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5715 
5716 	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5717 
5718 	for (i = 0; i < me_hdr->jt_size; i++)
5719 		WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5720 			     le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5721 
5722 	WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5723 
5724 	return 0;
5725 }
5726 
5727 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5728 {
5729 	int r;
5730 
5731 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5732 		return -EINVAL;
5733 
5734 	gfx_v10_0_cp_gfx_enable(adev, false);
5735 
5736 	r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5737 	if (r) {
5738 		dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5739 		return r;
5740 	}
5741 
5742 	r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5743 	if (r) {
5744 		dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5745 		return r;
5746 	}
5747 
5748 	r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5749 	if (r) {
5750 		dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5751 		return r;
5752 	}
5753 
5754 	return 0;
5755 }
5756 
5757 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5758 {
5759 	struct amdgpu_ring *ring;
5760 	const struct cs_section_def *sect = NULL;
5761 	const struct cs_extent_def *ext = NULL;
5762 	int r, i;
5763 	int ctx_reg_offset;
5764 
5765 	/* init the CP */
5766 	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5767 		     adev->gfx.config.max_hw_contexts - 1);
5768 	WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5769 
5770 	gfx_v10_0_cp_gfx_enable(adev, true);
5771 
5772 	ring = &adev->gfx.gfx_ring[0];
5773 	r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5774 	if (r) {
5775 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5776 		return r;
5777 	}
5778 
5779 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5780 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5781 
5782 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5783 	amdgpu_ring_write(ring, 0x80000000);
5784 	amdgpu_ring_write(ring, 0x80000000);
5785 
5786 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5787 		for (ext = sect->section; ext->extent != NULL; ++ext) {
5788 			if (sect->id == SECT_CONTEXT) {
5789 				amdgpu_ring_write(ring,
5790 						  PACKET3(PACKET3_SET_CONTEXT_REG,
5791 							  ext->reg_count));
5792 				amdgpu_ring_write(ring, ext->reg_index -
5793 						  PACKET3_SET_CONTEXT_REG_START);
5794 				for (i = 0; i < ext->reg_count; i++)
5795 					amdgpu_ring_write(ring, ext->extent[i]);
5796 			}
5797 		}
5798 	}
5799 
5800 	ctx_reg_offset =
5801 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5802 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5803 	amdgpu_ring_write(ring, ctx_reg_offset);
5804 	amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5805 
5806 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5807 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5808 
5809 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5810 	amdgpu_ring_write(ring, 0);
5811 
5812 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5813 	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5814 	amdgpu_ring_write(ring, 0x8000);
5815 	amdgpu_ring_write(ring, 0x8000);
5816 
5817 	amdgpu_ring_commit(ring);
5818 
5819 	/* submit cs packet to copy state 0 to next available state */
5820 	if (adev->gfx.num_gfx_rings > 1) {
5821 		/* maximum supported gfx ring is 2 */
5822 		ring = &adev->gfx.gfx_ring[1];
5823 		r = amdgpu_ring_alloc(ring, 2);
5824 		if (r) {
5825 			DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5826 			return r;
5827 		}
5828 
5829 		amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5830 		amdgpu_ring_write(ring, 0);
5831 
5832 		amdgpu_ring_commit(ring);
5833 	}
5834 	return 0;
5835 }
5836 
5837 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5838 					 CP_PIPE_ID pipe)
5839 {
5840 	u32 tmp;
5841 
5842 	tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5843 	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5844 
5845 	WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5846 }
5847 
5848 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5849 					  struct amdgpu_ring *ring)
5850 {
5851 	u32 tmp;
5852 
5853 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5854 	if (ring->use_doorbell) {
5855 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5856 				    DOORBELL_OFFSET, ring->doorbell_index);
5857 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5858 				    DOORBELL_EN, 1);
5859 	} else {
5860 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5861 				    DOORBELL_EN, 0);
5862 	}
5863 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5864 	switch (adev->asic_type) {
5865 	case CHIP_SIENNA_CICHLID:
5866 	case CHIP_NAVY_FLOUNDER:
5867 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5868 				    DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
5869 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5870 
5871 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5872 			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
5873 		break;
5874 	default:
5875 		tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5876 				    DOORBELL_RANGE_LOWER, ring->doorbell_index);
5877 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5878 
5879 		WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5880 			     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5881 		break;
5882 	}
5883 }
5884 
5885 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5886 {
5887 	struct amdgpu_ring *ring;
5888 	u32 tmp;
5889 	u32 rb_bufsz;
5890 	u64 rb_addr, rptr_addr, wptr_gpu_addr;
5891 	u32 i;
5892 
5893 	/* Set the write pointer delay */
5894 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5895 
5896 	/* set the RB to use vmid 0 */
5897 	WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5898 
5899 	/* Init gfx ring 0 for pipe 0 */
5900 	mutex_lock(&adev->srbm_mutex);
5901 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5902 
5903 	/* Set ring buffer size */
5904 	ring = &adev->gfx.gfx_ring[0];
5905 	rb_bufsz = order_base_2(ring->ring_size / 8);
5906 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5907 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5908 #ifdef __BIG_ENDIAN
5909 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5910 #endif
5911 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5912 
5913 	/* Initialize the ring buffer's write pointers */
5914 	ring->wptr = 0;
5915 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5916 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5917 
5918 	/* set the wb address wether it's enabled or not */
5919 	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5920 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5921 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5922 		     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5923 
5924 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5925 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5926 		     lower_32_bits(wptr_gpu_addr));
5927 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5928 		     upper_32_bits(wptr_gpu_addr));
5929 
5930 	mdelay(1);
5931 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5932 
5933 	rb_addr = ring->gpu_addr >> 8;
5934 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5935 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5936 
5937 	WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5938 
5939 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5940 	mutex_unlock(&adev->srbm_mutex);
5941 
5942 	/* Init gfx ring 1 for pipe 1 */
5943 	if (adev->gfx.num_gfx_rings > 1) {
5944 		mutex_lock(&adev->srbm_mutex);
5945 		gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5946 		/* maximum supported gfx ring is 2 */
5947 		ring = &adev->gfx.gfx_ring[1];
5948 		rb_bufsz = order_base_2(ring->ring_size / 8);
5949 		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5950 		tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5951 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5952 		/* Initialize the ring buffer's write pointers */
5953 		ring->wptr = 0;
5954 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5955 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5956 		/* Set the wb address wether it's enabled or not */
5957 		rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5958 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5959 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5960 			     CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5961 		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5962 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5963 			     lower_32_bits(wptr_gpu_addr));
5964 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5965 			     upper_32_bits(wptr_gpu_addr));
5966 
5967 		mdelay(1);
5968 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5969 
5970 		rb_addr = ring->gpu_addr >> 8;
5971 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5972 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5973 		WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5974 
5975 		gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5976 		mutex_unlock(&adev->srbm_mutex);
5977 	}
5978 	/* Switch to pipe 0 */
5979 	mutex_lock(&adev->srbm_mutex);
5980 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5981 	mutex_unlock(&adev->srbm_mutex);
5982 
5983 	/* start the ring */
5984 	gfx_v10_0_cp_gfx_start(adev);
5985 
5986 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5987 		ring = &adev->gfx.gfx_ring[i];
5988 		ring->sched.ready = true;
5989 	}
5990 
5991 	return 0;
5992 }
5993 
5994 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5995 {
5996 	if (enable) {
5997 		switch (adev->asic_type) {
5998 		case CHIP_SIENNA_CICHLID:
5999 		case CHIP_NAVY_FLOUNDER:
6000 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6001 			break;
6002 		default:
6003 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6004 			break;
6005 		}
6006 	} else {
6007 		switch (adev->asic_type) {
6008 		case CHIP_SIENNA_CICHLID:
6009 		case CHIP_NAVY_FLOUNDER:
6010 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6011 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6012 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6013 			break;
6014 		default:
6015 			WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6016 				     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6017 				      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6018 			break;
6019 		}
6020 		adev->gfx.kiq.ring.sched.ready = false;
6021 	}
6022 	udelay(50);
6023 }
6024 
6025 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6026 {
6027 	const struct gfx_firmware_header_v1_0 *mec_hdr;
6028 	const __le32 *fw_data;
6029 	unsigned i;
6030 	u32 tmp;
6031 	u32 usec_timeout = 50000; /* Wait for 50 ms */
6032 
6033 	if (!adev->gfx.mec_fw)
6034 		return -EINVAL;
6035 
6036 	gfx_v10_0_cp_compute_enable(adev, false);
6037 
6038 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6039 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6040 
6041 	fw_data = (const __le32 *)
6042 		(adev->gfx.mec_fw->data +
6043 		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6044 
6045 	/* Trigger an invalidation of the L1 instruction caches */
6046 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6047 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6048 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6049 
6050 	/* Wait for invalidation complete */
6051 	for (i = 0; i < usec_timeout; i++) {
6052 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6053 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6054 				       INVALIDATE_CACHE_COMPLETE))
6055 			break;
6056 		udelay(1);
6057 	}
6058 
6059 	if (i >= usec_timeout) {
6060 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
6061 		return -EINVAL;
6062 	}
6063 
6064 	if (amdgpu_emu_mode == 1)
6065 		adev->nbio.funcs->hdp_flush(adev, NULL);
6066 
6067 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6068 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6069 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6070 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6071 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6072 
6073 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6074 		     0xFFFFF000);
6075 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6076 		     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6077 
6078 	/* MEC1 */
6079 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6080 
6081 	for (i = 0; i < mec_hdr->jt_size; i++)
6082 		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6083 			     le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6084 
6085 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6086 
6087 	/*
6088 	 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6089 	 * different microcode than MEC1.
6090 	 */
6091 
6092 	return 0;
6093 }
6094 
6095 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6096 {
6097 	uint32_t tmp;
6098 	struct amdgpu_device *adev = ring->adev;
6099 
6100 	/* tell RLC which is KIQ queue */
6101 	switch (adev->asic_type) {
6102 	case CHIP_SIENNA_CICHLID:
6103 	case CHIP_NAVY_FLOUNDER:
6104 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6105 		tmp &= 0xffffff00;
6106 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6107 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6108 		tmp |= 0x80;
6109 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6110 		break;
6111 	default:
6112 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6113 		tmp &= 0xffffff00;
6114 		tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6115 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6116 		tmp |= 0x80;
6117 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6118 		break;
6119 	}
6120 }
6121 
6122 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6123 {
6124 	struct amdgpu_device *adev = ring->adev;
6125 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6126 	uint64_t hqd_gpu_addr, wb_gpu_addr;
6127 	uint32_t tmp;
6128 	uint32_t rb_bufsz;
6129 
6130 	/* set up gfx hqd wptr */
6131 	mqd->cp_gfx_hqd_wptr = 0;
6132 	mqd->cp_gfx_hqd_wptr_hi = 0;
6133 
6134 	/* set the pointer to the MQD */
6135 	mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6136 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6137 
6138 	/* set up mqd control */
6139 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6140 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6141 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6142 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6143 	mqd->cp_gfx_mqd_control = tmp;
6144 
6145 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6146 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6147 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6148 	mqd->cp_gfx_hqd_vmid = 0;
6149 
6150 	/* set up default queue priority level
6151 	 * 0x0 = low priority, 0x1 = high priority */
6152 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6153 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6154 	mqd->cp_gfx_hqd_queue_priority = tmp;
6155 
6156 	/* set up time quantum */
6157 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6158 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6159 	mqd->cp_gfx_hqd_quantum = tmp;
6160 
6161 	/* set up gfx hqd base. this is similar as CP_RB_BASE */
6162 	hqd_gpu_addr = ring->gpu_addr >> 8;
6163 	mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6164 	mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6165 
6166 	/* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6167 	wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6168 	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6169 	mqd->cp_gfx_hqd_rptr_addr_hi =
6170 		upper_32_bits(wb_gpu_addr) & 0xffff;
6171 
6172 	/* set up rb_wptr_poll addr */
6173 	wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6174 	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6175 	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6176 
6177 	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6178 	rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6179 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6180 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6181 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6182 #ifdef __BIG_ENDIAN
6183 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6184 #endif
6185 	mqd->cp_gfx_hqd_cntl = tmp;
6186 
6187 	/* set up cp_doorbell_control */
6188 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6189 	if (ring->use_doorbell) {
6190 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6191 				    DOORBELL_OFFSET, ring->doorbell_index);
6192 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6193 				    DOORBELL_EN, 1);
6194 	} else
6195 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6196 				    DOORBELL_EN, 0);
6197 	mqd->cp_rb_doorbell_control = tmp;
6198 
6199 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6200 	ring->wptr = 0;
6201 	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6202 
6203 	/* active the queue */
6204 	mqd->cp_gfx_hqd_active = 1;
6205 
6206 	return 0;
6207 }
6208 
6209 #ifdef BRING_UP_DEBUG
6210 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6211 {
6212 	struct amdgpu_device *adev = ring->adev;
6213 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6214 
6215 	/* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6216 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6217 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6218 
6219 	/* set GFX_MQD_BASE */
6220 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6221 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6222 
6223 	/* set GFX_MQD_CONTROL */
6224 	WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6225 
6226 	/* set GFX_HQD_VMID to 0 */
6227 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6228 
6229 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6230 			mqd->cp_gfx_hqd_queue_priority);
6231 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6232 
6233 	/* set GFX_HQD_BASE, similar as CP_RB_BASE */
6234 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6235 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6236 
6237 	/* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6238 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6239 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6240 
6241 	/* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6242 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6243 
6244 	/* set RB_WPTR_POLL_ADDR */
6245 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6246 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6247 
6248 	/* set RB_DOORBELL_CONTROL */
6249 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6250 
6251 	/* active the queue */
6252 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6253 
6254 	return 0;
6255 }
6256 #endif
6257 
6258 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6259 {
6260 	struct amdgpu_device *adev = ring->adev;
6261 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6262 	int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6263 
6264 	if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6265 		memset((void *)mqd, 0, sizeof(*mqd));
6266 		mutex_lock(&adev->srbm_mutex);
6267 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6268 		gfx_v10_0_gfx_mqd_init(ring);
6269 #ifdef BRING_UP_DEBUG
6270 		gfx_v10_0_gfx_queue_init_register(ring);
6271 #endif
6272 		nv_grbm_select(adev, 0, 0, 0, 0);
6273 		mutex_unlock(&adev->srbm_mutex);
6274 		if (adev->gfx.me.mqd_backup[mqd_idx])
6275 			memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6276 	} else if (amdgpu_in_reset(adev)) {
6277 		/* reset mqd with the backup copy */
6278 		if (adev->gfx.me.mqd_backup[mqd_idx])
6279 			memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6280 		/* reset the ring */
6281 		ring->wptr = 0;
6282 		adev->wb.wb[ring->wptr_offs] = 0;
6283 		amdgpu_ring_clear_ring(ring);
6284 #ifdef BRING_UP_DEBUG
6285 		mutex_lock(&adev->srbm_mutex);
6286 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6287 		gfx_v10_0_gfx_queue_init_register(ring);
6288 		nv_grbm_select(adev, 0, 0, 0, 0);
6289 		mutex_unlock(&adev->srbm_mutex);
6290 #endif
6291 	} else {
6292 		amdgpu_ring_clear_ring(ring);
6293 	}
6294 
6295 	return 0;
6296 }
6297 
6298 #ifndef BRING_UP_DEBUG
6299 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6300 {
6301 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6302 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6303 	int r, i;
6304 
6305 	if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6306 		return -EINVAL;
6307 
6308 	r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6309 					adev->gfx.num_gfx_rings);
6310 	if (r) {
6311 		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6312 		return r;
6313 	}
6314 
6315 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6316 		kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6317 
6318 	return amdgpu_ring_test_helper(kiq_ring);
6319 }
6320 #endif
6321 
6322 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6323 {
6324 	int r, i;
6325 	struct amdgpu_ring *ring;
6326 
6327 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6328 		ring = &adev->gfx.gfx_ring[i];
6329 
6330 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
6331 		if (unlikely(r != 0))
6332 			goto done;
6333 
6334 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6335 		if (!r) {
6336 			r = gfx_v10_0_gfx_init_queue(ring);
6337 			amdgpu_bo_kunmap(ring->mqd_obj);
6338 			ring->mqd_ptr = NULL;
6339 		}
6340 		amdgpu_bo_unreserve(ring->mqd_obj);
6341 		if (r)
6342 			goto done;
6343 	}
6344 #ifndef BRING_UP_DEBUG
6345 	r = gfx_v10_0_kiq_enable_kgq(adev);
6346 	if (r)
6347 		goto done;
6348 #endif
6349 	r = gfx_v10_0_cp_gfx_start(adev);
6350 	if (r)
6351 		goto done;
6352 
6353 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6354 		ring = &adev->gfx.gfx_ring[i];
6355 		ring->sched.ready = true;
6356 	}
6357 done:
6358 	return r;
6359 }
6360 
6361 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6362 {
6363 	struct amdgpu_device *adev = ring->adev;
6364 
6365 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6366 		if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
6367 							      ring->queue)) {
6368 			mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6369 			mqd->cp_hqd_queue_priority =
6370 				AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6371 		}
6372 	}
6373 }
6374 
6375 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6376 {
6377 	struct amdgpu_device *adev = ring->adev;
6378 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6379 	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6380 	uint32_t tmp;
6381 
6382 	mqd->header = 0xC0310800;
6383 	mqd->compute_pipelinestat_enable = 0x00000001;
6384 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6385 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6386 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6387 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6388 	mqd->compute_misc_reserved = 0x00000003;
6389 
6390 	eop_base_addr = ring->eop_gpu_addr >> 8;
6391 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6392 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6393 
6394 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6395 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6396 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6397 			(order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6398 
6399 	mqd->cp_hqd_eop_control = tmp;
6400 
6401 	/* enable doorbell? */
6402 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6403 
6404 	if (ring->use_doorbell) {
6405 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6406 				    DOORBELL_OFFSET, ring->doorbell_index);
6407 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6408 				    DOORBELL_EN, 1);
6409 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6410 				    DOORBELL_SOURCE, 0);
6411 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6412 				    DOORBELL_HIT, 0);
6413 	} else {
6414 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6415 				    DOORBELL_EN, 0);
6416 	}
6417 
6418 	mqd->cp_hqd_pq_doorbell_control = tmp;
6419 
6420 	/* disable the queue if it's active */
6421 	ring->wptr = 0;
6422 	mqd->cp_hqd_dequeue_request = 0;
6423 	mqd->cp_hqd_pq_rptr = 0;
6424 	mqd->cp_hqd_pq_wptr_lo = 0;
6425 	mqd->cp_hqd_pq_wptr_hi = 0;
6426 
6427 	/* set the pointer to the MQD */
6428 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6429 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6430 
6431 	/* set MQD vmid to 0 */
6432 	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6433 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6434 	mqd->cp_mqd_control = tmp;
6435 
6436 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6437 	hqd_gpu_addr = ring->gpu_addr >> 8;
6438 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6439 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6440 
6441 	/* set up the HQD, this is similar to CP_RB0_CNTL */
6442 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6443 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6444 			    (order_base_2(ring->ring_size / 4) - 1));
6445 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6446 			    ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6447 #ifdef __BIG_ENDIAN
6448 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6449 #endif
6450 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6451 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6452 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6453 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6454 	mqd->cp_hqd_pq_control = tmp;
6455 
6456 	/* set the wb address whether it's enabled or not */
6457 	wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6458 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6459 	mqd->cp_hqd_pq_rptr_report_addr_hi =
6460 		upper_32_bits(wb_gpu_addr) & 0xffff;
6461 
6462 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6463 	wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6464 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6465 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6466 
6467 	tmp = 0;
6468 	/* enable the doorbell if requested */
6469 	if (ring->use_doorbell) {
6470 		tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6471 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6472 				DOORBELL_OFFSET, ring->doorbell_index);
6473 
6474 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6475 				    DOORBELL_EN, 1);
6476 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6477 				    DOORBELL_SOURCE, 0);
6478 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6479 				    DOORBELL_HIT, 0);
6480 	}
6481 
6482 	mqd->cp_hqd_pq_doorbell_control = tmp;
6483 
6484 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6485 	ring->wptr = 0;
6486 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6487 
6488 	/* set the vmid for the queue */
6489 	mqd->cp_hqd_vmid = 0;
6490 
6491 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6492 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6493 	mqd->cp_hqd_persistent_state = tmp;
6494 
6495 	/* set MIN_IB_AVAIL_SIZE */
6496 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6497 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6498 	mqd->cp_hqd_ib_control = tmp;
6499 
6500 	/* set static priority for a compute queue/ring */
6501 	gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6502 
6503 	/* map_queues packet doesn't need activate the queue,
6504 	 * so only kiq need set this field.
6505 	 */
6506 	if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6507 		mqd->cp_hqd_active = 1;
6508 
6509 	return 0;
6510 }
6511 
6512 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6513 {
6514 	struct amdgpu_device *adev = ring->adev;
6515 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6516 	int j;
6517 
6518 	/* inactivate the queue */
6519 	if (amdgpu_sriov_vf(adev))
6520 		WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6521 
6522 	/* disable wptr polling */
6523 	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6524 
6525 	/* write the EOP addr */
6526 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6527 	       mqd->cp_hqd_eop_base_addr_lo);
6528 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6529 	       mqd->cp_hqd_eop_base_addr_hi);
6530 
6531 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6532 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6533 	       mqd->cp_hqd_eop_control);
6534 
6535 	/* enable doorbell? */
6536 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6537 	       mqd->cp_hqd_pq_doorbell_control);
6538 
6539 	/* disable the queue if it's active */
6540 	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6541 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6542 		for (j = 0; j < adev->usec_timeout; j++) {
6543 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6544 				break;
6545 			udelay(1);
6546 		}
6547 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6548 		       mqd->cp_hqd_dequeue_request);
6549 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6550 		       mqd->cp_hqd_pq_rptr);
6551 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6552 		       mqd->cp_hqd_pq_wptr_lo);
6553 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6554 		       mqd->cp_hqd_pq_wptr_hi);
6555 	}
6556 
6557 	/* set the pointer to the MQD */
6558 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6559 	       mqd->cp_mqd_base_addr_lo);
6560 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6561 	       mqd->cp_mqd_base_addr_hi);
6562 
6563 	/* set MQD vmid to 0 */
6564 	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6565 	       mqd->cp_mqd_control);
6566 
6567 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6568 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6569 	       mqd->cp_hqd_pq_base_lo);
6570 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6571 	       mqd->cp_hqd_pq_base_hi);
6572 
6573 	/* set up the HQD, this is similar to CP_RB0_CNTL */
6574 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6575 	       mqd->cp_hqd_pq_control);
6576 
6577 	/* set the wb address whether it's enabled or not */
6578 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6579 		mqd->cp_hqd_pq_rptr_report_addr_lo);
6580 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6581 		mqd->cp_hqd_pq_rptr_report_addr_hi);
6582 
6583 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6584 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6585 	       mqd->cp_hqd_pq_wptr_poll_addr_lo);
6586 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6587 	       mqd->cp_hqd_pq_wptr_poll_addr_hi);
6588 
6589 	/* enable the doorbell if requested */
6590 	if (ring->use_doorbell) {
6591 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6592 			(adev->doorbell_index.kiq * 2) << 2);
6593 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6594 			(adev->doorbell_index.userqueue_end * 2) << 2);
6595 	}
6596 
6597 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6598 	       mqd->cp_hqd_pq_doorbell_control);
6599 
6600 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6601 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6602 	       mqd->cp_hqd_pq_wptr_lo);
6603 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6604 	       mqd->cp_hqd_pq_wptr_hi);
6605 
6606 	/* set the vmid for the queue */
6607 	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6608 
6609 	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6610 	       mqd->cp_hqd_persistent_state);
6611 
6612 	/* activate the queue */
6613 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6614 	       mqd->cp_hqd_active);
6615 
6616 	if (ring->use_doorbell)
6617 		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6618 
6619 	return 0;
6620 }
6621 
6622 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6623 {
6624 	struct amdgpu_device *adev = ring->adev;
6625 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6626 	int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6627 
6628 	gfx_v10_0_kiq_setting(ring);
6629 
6630 	if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6631 		/* reset MQD to a clean status */
6632 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6633 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6634 
6635 		/* reset ring buffer */
6636 		ring->wptr = 0;
6637 		amdgpu_ring_clear_ring(ring);
6638 
6639 		mutex_lock(&adev->srbm_mutex);
6640 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6641 		gfx_v10_0_kiq_init_register(ring);
6642 		nv_grbm_select(adev, 0, 0, 0, 0);
6643 		mutex_unlock(&adev->srbm_mutex);
6644 	} else {
6645 		memset((void *)mqd, 0, sizeof(*mqd));
6646 		mutex_lock(&adev->srbm_mutex);
6647 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6648 		gfx_v10_0_compute_mqd_init(ring);
6649 		gfx_v10_0_kiq_init_register(ring);
6650 		nv_grbm_select(adev, 0, 0, 0, 0);
6651 		mutex_unlock(&adev->srbm_mutex);
6652 
6653 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6654 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6655 	}
6656 
6657 	return 0;
6658 }
6659 
6660 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6661 {
6662 	struct amdgpu_device *adev = ring->adev;
6663 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6664 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
6665 
6666 	if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6667 		memset((void *)mqd, 0, sizeof(*mqd));
6668 		mutex_lock(&adev->srbm_mutex);
6669 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6670 		gfx_v10_0_compute_mqd_init(ring);
6671 		nv_grbm_select(adev, 0, 0, 0, 0);
6672 		mutex_unlock(&adev->srbm_mutex);
6673 
6674 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6675 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6676 	} else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6677 		/* reset MQD to a clean status */
6678 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6679 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6680 
6681 		/* reset ring buffer */
6682 		ring->wptr = 0;
6683 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6684 		amdgpu_ring_clear_ring(ring);
6685 	} else {
6686 		amdgpu_ring_clear_ring(ring);
6687 	}
6688 
6689 	return 0;
6690 }
6691 
6692 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6693 {
6694 	struct amdgpu_ring *ring;
6695 	int r;
6696 
6697 	ring = &adev->gfx.kiq.ring;
6698 
6699 	r = amdgpu_bo_reserve(ring->mqd_obj, false);
6700 	if (unlikely(r != 0))
6701 		return r;
6702 
6703 	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6704 	if (unlikely(r != 0))
6705 		return r;
6706 
6707 	gfx_v10_0_kiq_init_queue(ring);
6708 	amdgpu_bo_kunmap(ring->mqd_obj);
6709 	ring->mqd_ptr = NULL;
6710 	amdgpu_bo_unreserve(ring->mqd_obj);
6711 	ring->sched.ready = true;
6712 	return 0;
6713 }
6714 
6715 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6716 {
6717 	struct amdgpu_ring *ring = NULL;
6718 	int r = 0, i;
6719 
6720 	gfx_v10_0_cp_compute_enable(adev, true);
6721 
6722 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6723 		ring = &adev->gfx.compute_ring[i];
6724 
6725 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
6726 		if (unlikely(r != 0))
6727 			goto done;
6728 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6729 		if (!r) {
6730 			r = gfx_v10_0_kcq_init_queue(ring);
6731 			amdgpu_bo_kunmap(ring->mqd_obj);
6732 			ring->mqd_ptr = NULL;
6733 		}
6734 		amdgpu_bo_unreserve(ring->mqd_obj);
6735 		if (r)
6736 			goto done;
6737 	}
6738 
6739 	r = amdgpu_gfx_enable_kcq(adev);
6740 done:
6741 	return r;
6742 }
6743 
6744 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6745 {
6746 	int r, i;
6747 	struct amdgpu_ring *ring;
6748 
6749 	if (!(adev->flags & AMD_IS_APU))
6750 		gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6751 
6752 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6753 		/* legacy firmware loading */
6754 		r = gfx_v10_0_cp_gfx_load_microcode(adev);
6755 		if (r)
6756 			return r;
6757 
6758 		r = gfx_v10_0_cp_compute_load_microcode(adev);
6759 		if (r)
6760 			return r;
6761 	}
6762 
6763 	r = gfx_v10_0_kiq_resume(adev);
6764 	if (r)
6765 		return r;
6766 
6767 	r = gfx_v10_0_kcq_resume(adev);
6768 	if (r)
6769 		return r;
6770 
6771 	if (!amdgpu_async_gfx_ring) {
6772 		r = gfx_v10_0_cp_gfx_resume(adev);
6773 		if (r)
6774 			return r;
6775 	} else {
6776 		r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6777 		if (r)
6778 			return r;
6779 	}
6780 
6781 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6782 		ring = &adev->gfx.gfx_ring[i];
6783 		r = amdgpu_ring_test_helper(ring);
6784 		if (r)
6785 			return r;
6786 	}
6787 
6788 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6789 		ring = &adev->gfx.compute_ring[i];
6790 		r = amdgpu_ring_test_helper(ring);
6791 		if (r)
6792 			return r;
6793 	}
6794 
6795 	return 0;
6796 }
6797 
6798 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6799 {
6800 	gfx_v10_0_cp_gfx_enable(adev, enable);
6801 	gfx_v10_0_cp_compute_enable(adev, enable);
6802 }
6803 
6804 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6805 {
6806 	uint32_t data, pattern = 0xDEADBEEF;
6807 
6808 	/* check if mmVGT_ESGS_RING_SIZE_UMD
6809 	 * has been remapped to mmVGT_ESGS_RING_SIZE */
6810 	switch (adev->asic_type) {
6811 	case CHIP_SIENNA_CICHLID:
6812 	case CHIP_NAVY_FLOUNDER:
6813 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6814 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6815 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6816 
6817 		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6818 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6819 			return true;
6820 		} else {
6821 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6822 			return false;
6823 		}
6824 		break;
6825 	default:
6826 		data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6827 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6828 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6829 
6830 		if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6831 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6832 			return true;
6833 		} else {
6834 			WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6835 			return false;
6836 		}
6837 		break;
6838 	}
6839 }
6840 
6841 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6842 {
6843 	uint32_t data;
6844 
6845 	/* initialize cam_index to 0
6846 	 * index will auto-inc after each data writting */
6847 	WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6848 
6849 	switch (adev->asic_type) {
6850 	case CHIP_SIENNA_CICHLID:
6851 	case CHIP_NAVY_FLOUNDER:
6852 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6853 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6854 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6855 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6856 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6857 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6858 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6859 
6860 		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6861 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6862 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6863 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
6864 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6865 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6866 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6867 
6868 		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6869 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6870 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6871 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
6872 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6873 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6874 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6875 
6876 		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6877 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6878 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6879 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
6880 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6881 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6882 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6883 
6884 		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6885 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6886 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6887 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
6888 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6889 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6890 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6891 
6892 		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6893 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6894 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6895 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
6896 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6897 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6898 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6899 
6900 		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6901 		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6902 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6903 		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
6904 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6905 		break;
6906 	default:
6907 		/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6908 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6909 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6910 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6911 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6912 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6913 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6914 
6915 		/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6916 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6917 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6918 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6919 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6920 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6921 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6922 
6923 		/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6924 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6925 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6926 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6927 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6928 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6929 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6930 
6931 		/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6932 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6933 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6934 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6935 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6936 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6937 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6938 
6939 		/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6940 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6941 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6942 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6943 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6944 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6945 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6946 
6947 		/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6948 		data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6949 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6950 		       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6951 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6952 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6953 		WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6954 
6955 		/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6956 		data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6957 			GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6958 		       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6959 			GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6960 		break;
6961 	}
6962 
6963 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6964 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6965 }
6966 
6967 static int gfx_v10_0_hw_init(void *handle)
6968 {
6969 	int r;
6970 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6971 
6972 	if (!amdgpu_emu_mode)
6973 		gfx_v10_0_init_golden_registers(adev);
6974 
6975 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6976 		/**
6977 		 * For gfx 10, rlc firmware loading relies on smu firmware is
6978 		 * loaded firstly, so in direct type, it has to load smc ucode
6979 		 * here before rlc.
6980 		 */
6981 		if (adev->smu.ppt_funcs != NULL) {
6982 			r = smu_load_microcode(&adev->smu);
6983 			if (r)
6984 				return r;
6985 
6986 			r = smu_check_fw_status(&adev->smu);
6987 			if (r) {
6988 				pr_err("SMC firmware status is not correct\n");
6989 				return r;
6990 			}
6991 		}
6992 	}
6993 
6994 	/* if GRBM CAM not remapped, set up the remapping */
6995 	if (!gfx_v10_0_check_grbm_cam_remapping(adev))
6996 		gfx_v10_0_setup_grbm_cam_remapping(adev);
6997 
6998 	gfx_v10_0_constants_init(adev);
6999 
7000 	r = gfx_v10_0_rlc_resume(adev);
7001 	if (r)
7002 		return r;
7003 
7004 	/*
7005 	 * init golden registers and rlc resume may override some registers,
7006 	 * reconfig them here
7007 	 */
7008 	gfx_v10_0_tcp_harvest(adev);
7009 
7010 	r = gfx_v10_0_cp_resume(adev);
7011 	if (r)
7012 		return r;
7013 
7014 	if (adev->asic_type == CHIP_SIENNA_CICHLID)
7015 		gfx_v10_3_program_pbb_mode(adev);
7016 
7017 	return r;
7018 }
7019 
7020 #ifndef BRING_UP_DEBUG
7021 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7022 {
7023 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7024 	struct amdgpu_ring *kiq_ring = &kiq->ring;
7025 	int i;
7026 
7027 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7028 		return -EINVAL;
7029 
7030 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7031 					adev->gfx.num_gfx_rings))
7032 		return -ENOMEM;
7033 
7034 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7035 		kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7036 					   PREEMPT_QUEUES, 0, 0);
7037 
7038 	return amdgpu_ring_test_helper(kiq_ring);
7039 }
7040 #endif
7041 
7042 static int gfx_v10_0_hw_fini(void *handle)
7043 {
7044 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7045 	int r;
7046 	uint32_t tmp;
7047 
7048 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7049 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7050 
7051 	if (!adev->in_pci_err_recovery) {
7052 #ifndef BRING_UP_DEBUG
7053 		if (amdgpu_async_gfx_ring) {
7054 			r = gfx_v10_0_kiq_disable_kgq(adev);
7055 			if (r)
7056 				DRM_ERROR("KGQ disable failed\n");
7057 		}
7058 #endif
7059 		if (amdgpu_gfx_disable_kcq(adev))
7060 			DRM_ERROR("KCQ disable failed\n");
7061 	}
7062 
7063 	if (amdgpu_sriov_vf(adev)) {
7064 		gfx_v10_0_cp_gfx_enable(adev, false);
7065 		/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7066 		tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7067 		tmp &= 0xffffff00;
7068 		WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7069 
7070 		return 0;
7071 	}
7072 	gfx_v10_0_cp_enable(adev, false);
7073 	gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7074 
7075 	return 0;
7076 }
7077 
7078 static int gfx_v10_0_suspend(void *handle)
7079 {
7080 	return gfx_v10_0_hw_fini(handle);
7081 }
7082 
7083 static int gfx_v10_0_resume(void *handle)
7084 {
7085 	return gfx_v10_0_hw_init(handle);
7086 }
7087 
7088 static bool gfx_v10_0_is_idle(void *handle)
7089 {
7090 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7091 
7092 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7093 				GRBM_STATUS, GUI_ACTIVE))
7094 		return false;
7095 	else
7096 		return true;
7097 }
7098 
7099 static int gfx_v10_0_wait_for_idle(void *handle)
7100 {
7101 	unsigned i;
7102 	u32 tmp;
7103 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7104 
7105 	for (i = 0; i < adev->usec_timeout; i++) {
7106 		/* read MC_STATUS */
7107 		tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7108 			GRBM_STATUS__GUI_ACTIVE_MASK;
7109 
7110 		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7111 			return 0;
7112 		udelay(1);
7113 	}
7114 	return -ETIMEDOUT;
7115 }
7116 
7117 static int gfx_v10_0_soft_reset(void *handle)
7118 {
7119 	u32 grbm_soft_reset = 0;
7120 	u32 tmp;
7121 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7122 
7123 	/* GRBM_STATUS */
7124 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7125 	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7126 		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7127 		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7128 		   GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7129 		   GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7130 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7131 						GRBM_SOFT_RESET, SOFT_RESET_CP,
7132 						1);
7133 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7134 						GRBM_SOFT_RESET, SOFT_RESET_GFX,
7135 						1);
7136 	}
7137 
7138 	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7139 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7140 						GRBM_SOFT_RESET, SOFT_RESET_CP,
7141 						1);
7142 	}
7143 
7144 	/* GRBM_STATUS2 */
7145 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7146 	switch (adev->asic_type) {
7147 	case CHIP_SIENNA_CICHLID:
7148 	case CHIP_NAVY_FLOUNDER:
7149 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7150 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7151 							GRBM_SOFT_RESET,
7152 							SOFT_RESET_RLC,
7153 							1);
7154 		break;
7155 	default:
7156 		if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7157 			grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7158 							GRBM_SOFT_RESET,
7159 							SOFT_RESET_RLC,
7160 							1);
7161 		break;
7162 	}
7163 
7164 	if (grbm_soft_reset) {
7165 		/* stop the rlc */
7166 		gfx_v10_0_rlc_stop(adev);
7167 
7168 		/* Disable GFX parsing/prefetching */
7169 		gfx_v10_0_cp_gfx_enable(adev, false);
7170 
7171 		/* Disable MEC parsing/prefetching */
7172 		gfx_v10_0_cp_compute_enable(adev, false);
7173 
7174 		if (grbm_soft_reset) {
7175 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7176 			tmp |= grbm_soft_reset;
7177 			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7178 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7179 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7180 
7181 			udelay(50);
7182 
7183 			tmp &= ~grbm_soft_reset;
7184 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7185 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7186 		}
7187 
7188 		/* Wait a little for things to settle down */
7189 		udelay(50);
7190 	}
7191 	return 0;
7192 }
7193 
7194 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7195 {
7196 	uint64_t clock;
7197 
7198 	amdgpu_gfx_off_ctrl(adev, false);
7199 	mutex_lock(&adev->gfx.gpu_clock_mutex);
7200 	clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7201 		((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7202 	mutex_unlock(&adev->gfx.gpu_clock_mutex);
7203 	amdgpu_gfx_off_ctrl(adev, true);
7204 	return clock;
7205 }
7206 
7207 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7208 					   uint32_t vmid,
7209 					   uint32_t gds_base, uint32_t gds_size,
7210 					   uint32_t gws_base, uint32_t gws_size,
7211 					   uint32_t oa_base, uint32_t oa_size)
7212 {
7213 	struct amdgpu_device *adev = ring->adev;
7214 
7215 	/* GDS Base */
7216 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7217 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7218 				    gds_base);
7219 
7220 	/* GDS Size */
7221 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7222 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7223 				    gds_size);
7224 
7225 	/* GWS */
7226 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7227 				    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7228 				    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7229 
7230 	/* OA */
7231 	gfx_v10_0_write_data_to_reg(ring, 0, false,
7232 				    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7233 				    (1 << (oa_size + oa_base)) - (1 << oa_base));
7234 }
7235 
7236 static int gfx_v10_0_early_init(void *handle)
7237 {
7238 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7239 
7240 	switch (adev->asic_type) {
7241 	case CHIP_NAVI10:
7242 	case CHIP_NAVI14:
7243 	case CHIP_NAVI12:
7244 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7245 		break;
7246 	case CHIP_SIENNA_CICHLID:
7247 	case CHIP_NAVY_FLOUNDER:
7248 		adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7249 		break;
7250 	default:
7251 		break;
7252 	}
7253 
7254 	adev->gfx.num_compute_rings = amdgpu_num_kcq;
7255 
7256 	gfx_v10_0_set_kiq_pm4_funcs(adev);
7257 	gfx_v10_0_set_ring_funcs(adev);
7258 	gfx_v10_0_set_irq_funcs(adev);
7259 	gfx_v10_0_set_gds_init(adev);
7260 	gfx_v10_0_set_rlc_funcs(adev);
7261 
7262 	return 0;
7263 }
7264 
7265 static int gfx_v10_0_late_init(void *handle)
7266 {
7267 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7268 	int r;
7269 
7270 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7271 	if (r)
7272 		return r;
7273 
7274 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7275 	if (r)
7276 		return r;
7277 
7278 	return 0;
7279 }
7280 
7281 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7282 {
7283 	uint32_t rlc_cntl;
7284 
7285 	/* if RLC is not enabled, do nothing */
7286 	rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7287 	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7288 }
7289 
7290 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7291 {
7292 	uint32_t data;
7293 	unsigned i;
7294 
7295 	data = RLC_SAFE_MODE__CMD_MASK;
7296 	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7297 
7298 	switch (adev->asic_type) {
7299 	case CHIP_SIENNA_CICHLID:
7300 	case CHIP_NAVY_FLOUNDER:
7301 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7302 
7303 		/* wait for RLC_SAFE_MODE */
7304 		for (i = 0; i < adev->usec_timeout; i++) {
7305 			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7306 					   RLC_SAFE_MODE, CMD))
7307 				break;
7308 			udelay(1);
7309 		}
7310 		break;
7311 	default:
7312 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7313 
7314 		/* wait for RLC_SAFE_MODE */
7315 		for (i = 0; i < adev->usec_timeout; i++) {
7316 			if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7317 					   RLC_SAFE_MODE, CMD))
7318 				break;
7319 			udelay(1);
7320 		}
7321 		break;
7322 	}
7323 }
7324 
7325 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7326 {
7327 	uint32_t data;
7328 
7329 	data = RLC_SAFE_MODE__CMD_MASK;
7330 	switch (adev->asic_type) {
7331 	case CHIP_SIENNA_CICHLID:
7332 	case CHIP_NAVY_FLOUNDER:
7333 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7334 		break;
7335 	default:
7336 		WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7337 		break;
7338 	}
7339 }
7340 
7341 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7342 						      bool enable)
7343 {
7344 	uint32_t data, def;
7345 
7346 	/* It is disabled by HW by default */
7347 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7348 		/* 0 - Disable some blocks' MGCG */
7349 		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7350 		WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7351 		WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7352 		WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7353 
7354 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
7355 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7356 		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7357 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7358 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7359 			  RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7360 
7361 		if (def != data)
7362 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7363 
7364 		/* MGLS is a global flag to control all MGLS in GFX */
7365 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7366 			/* 2 - RLC memory Light sleep */
7367 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7368 				def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7369 				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7370 				if (def != data)
7371 					WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7372 			}
7373 			/* 3 - CP memory Light sleep */
7374 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7375 				def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7376 				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7377 				if (def != data)
7378 					WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7379 			}
7380 		}
7381 	} else {
7382 		/* 1 - MGCG_OVERRIDE */
7383 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7384 		data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7385 			 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7386 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7387 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7388 		if (def != data)
7389 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7390 
7391 		/* 2 - disable MGLS in CP */
7392 		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7393 		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7394 			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7395 			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7396 		}
7397 
7398 		/* 3 - disable MGLS in RLC */
7399 		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7400 		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7401 			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7402 			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7403 		}
7404 
7405 	}
7406 }
7407 
7408 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7409 					   bool enable)
7410 {
7411 	uint32_t data, def;
7412 
7413 	/* Enable 3D CGCG/CGLS */
7414 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7415 		/* write cmd to clear cgcg/cgls ov */
7416 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7417 		/* unset CGCG override */
7418 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7419 		/* update CGCG and CGLS override bits */
7420 		if (def != data)
7421 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7422 		/* enable 3Dcgcg FSM(0x0000363f) */
7423 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7424 		data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7425 			RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7426 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7427 			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7428 				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7429 		if (def != data)
7430 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7431 
7432 		/* set IDLE_POLL_COUNT(0x00900100) */
7433 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7434 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7435 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7436 		if (def != data)
7437 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7438 	} else {
7439 		/* Disable CGCG/CGLS */
7440 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7441 		/* disable cgcg, cgls should be disabled */
7442 		data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7443 			  RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7444 		/* disable cgcg and cgls in FSM */
7445 		if (def != data)
7446 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7447 	}
7448 }
7449 
7450 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7451 						      bool enable)
7452 {
7453 	uint32_t def, data;
7454 
7455 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7456 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7457 		/* unset CGCG override */
7458 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7459 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7460 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7461 		else
7462 			data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7463 		/* update CGCG and CGLS override bits */
7464 		if (def != data)
7465 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7466 
7467 		/* enable cgcg FSM(0x0000363F) */
7468 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7469 		data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7470 			RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7471 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7472 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7473 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7474 		if (def != data)
7475 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7476 
7477 		/* set IDLE_POLL_COUNT(0x00900100) */
7478 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7479 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7480 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7481 		if (def != data)
7482 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7483 	} else {
7484 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7485 		/* reset CGCG/CGLS bits */
7486 		data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7487 		/* disable cgcg and cgls in FSM */
7488 		if (def != data)
7489 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7490 	}
7491 }
7492 
7493 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7494 					    bool enable)
7495 {
7496 	amdgpu_gfx_rlc_enter_safe_mode(adev);
7497 
7498 	if (enable) {
7499 		/* CGCG/CGLS should be enabled after MGCG/MGLS
7500 		 * ===  MGCG + MGLS ===
7501 		 */
7502 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7503 		/* ===  CGCG /CGLS for GFX 3D Only === */
7504 		gfx_v10_0_update_3d_clock_gating(adev, enable);
7505 		/* ===  CGCG + CGLS === */
7506 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7507 	} else {
7508 		/* CGCG/CGLS should be disabled before MGCG/MGLS
7509 		 * ===  CGCG + CGLS ===
7510 		 */
7511 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7512 		/* ===  CGCG /CGLS for GFX 3D Only === */
7513 		gfx_v10_0_update_3d_clock_gating(adev, enable);
7514 		/* ===  MGCG + MGLS === */
7515 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7516 	}
7517 
7518 	if (adev->cg_flags &
7519 	    (AMD_CG_SUPPORT_GFX_MGCG |
7520 	     AMD_CG_SUPPORT_GFX_CGLS |
7521 	     AMD_CG_SUPPORT_GFX_CGCG |
7522 	     AMD_CG_SUPPORT_GFX_3D_CGCG |
7523 	     AMD_CG_SUPPORT_GFX_3D_CGLS))
7524 		gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7525 
7526 	amdgpu_gfx_rlc_exit_safe_mode(adev);
7527 
7528 	return 0;
7529 }
7530 
7531 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7532 {
7533 	u32 reg, data;
7534 
7535 	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7536 	if (amdgpu_sriov_is_pp_one_vf(adev))
7537 		data = RREG32_NO_KIQ(reg);
7538 	else
7539 		data = RREG32(reg);
7540 
7541 	data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7542 	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7543 
7544 	if (amdgpu_sriov_is_pp_one_vf(adev))
7545 		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7546 	else
7547 		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7548 }
7549 
7550 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7551 					uint32_t offset,
7552 					struct soc15_reg_rlcg *entries, int arr_size)
7553 {
7554 	int i;
7555 	uint32_t reg;
7556 
7557 	if (!entries)
7558 		return false;
7559 
7560 	for (i = 0; i < arr_size; i++) {
7561 		const struct soc15_reg_rlcg *entry;
7562 
7563 		entry = &entries[i];
7564 		reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7565 		if (offset == reg)
7566 			return true;
7567 	}
7568 
7569 	return false;
7570 }
7571 
7572 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7573 {
7574 	return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7575 }
7576 
7577 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7578 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7579 	.set_safe_mode = gfx_v10_0_set_safe_mode,
7580 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
7581 	.init = gfx_v10_0_rlc_init,
7582 	.get_csb_size = gfx_v10_0_get_csb_size,
7583 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
7584 	.resume = gfx_v10_0_rlc_resume,
7585 	.stop = gfx_v10_0_rlc_stop,
7586 	.reset = gfx_v10_0_rlc_reset,
7587 	.start = gfx_v10_0_rlc_start,
7588 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
7589 };
7590 
7591 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7592 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7593 	.set_safe_mode = gfx_v10_0_set_safe_mode,
7594 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
7595 	.init = gfx_v10_0_rlc_init,
7596 	.get_csb_size = gfx_v10_0_get_csb_size,
7597 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
7598 	.resume = gfx_v10_0_rlc_resume,
7599 	.stop = gfx_v10_0_rlc_stop,
7600 	.reset = gfx_v10_0_rlc_reset,
7601 	.start = gfx_v10_0_rlc_start,
7602 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
7603 	.rlcg_wreg = gfx_v10_rlcg_wreg,
7604 	.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7605 };
7606 
7607 static int gfx_v10_0_set_powergating_state(void *handle,
7608 					  enum amd_powergating_state state)
7609 {
7610 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7611 	bool enable = (state == AMD_PG_STATE_GATE);
7612 
7613 	if (amdgpu_sriov_vf(adev))
7614 		return 0;
7615 
7616 	switch (adev->asic_type) {
7617 	case CHIP_NAVI10:
7618 	case CHIP_NAVI14:
7619 	case CHIP_NAVI12:
7620 	case CHIP_SIENNA_CICHLID:
7621 	case CHIP_NAVY_FLOUNDER:
7622 		amdgpu_gfx_off_ctrl(adev, enable);
7623 		break;
7624 	default:
7625 		break;
7626 	}
7627 	return 0;
7628 }
7629 
7630 static int gfx_v10_0_set_clockgating_state(void *handle,
7631 					  enum amd_clockgating_state state)
7632 {
7633 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7634 
7635 	if (amdgpu_sriov_vf(adev))
7636 		return 0;
7637 
7638 	switch (adev->asic_type) {
7639 	case CHIP_NAVI10:
7640 	case CHIP_NAVI14:
7641 	case CHIP_NAVI12:
7642 	case CHIP_SIENNA_CICHLID:
7643 	case CHIP_NAVY_FLOUNDER:
7644 		gfx_v10_0_update_gfx_clock_gating(adev,
7645 						 state == AMD_CG_STATE_GATE);
7646 		break;
7647 	default:
7648 		break;
7649 	}
7650 	return 0;
7651 }
7652 
7653 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7654 {
7655 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7656 	int data;
7657 
7658 	/* AMD_CG_SUPPORT_GFX_MGCG */
7659 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7660 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7661 		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
7662 
7663 	/* AMD_CG_SUPPORT_GFX_CGCG */
7664 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7665 	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7666 		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
7667 
7668 	/* AMD_CG_SUPPORT_GFX_CGLS */
7669 	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7670 		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
7671 
7672 	/* AMD_CG_SUPPORT_GFX_RLC_LS */
7673 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7674 	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7675 		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7676 
7677 	/* AMD_CG_SUPPORT_GFX_CP_LS */
7678 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7679 	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7680 		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7681 
7682 	/* AMD_CG_SUPPORT_GFX_3D_CGCG */
7683 	data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7684 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7685 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7686 
7687 	/* AMD_CG_SUPPORT_GFX_3D_CGLS */
7688 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7689 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7690 }
7691 
7692 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7693 {
7694 	return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7695 }
7696 
7697 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7698 {
7699 	struct amdgpu_device *adev = ring->adev;
7700 	u64 wptr;
7701 
7702 	/* XXX check if swapping is necessary on BE */
7703 	if (ring->use_doorbell) {
7704 		wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7705 	} else {
7706 		wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7707 		wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7708 	}
7709 
7710 	return wptr;
7711 }
7712 
7713 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7714 {
7715 	struct amdgpu_device *adev = ring->adev;
7716 
7717 	if (ring->use_doorbell) {
7718 		/* XXX check if swapping is necessary on BE */
7719 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7720 		WDOORBELL64(ring->doorbell_index, ring->wptr);
7721 	} else {
7722 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7723 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7724 	}
7725 }
7726 
7727 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7728 {
7729 	return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7730 }
7731 
7732 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7733 {
7734 	u64 wptr;
7735 
7736 	/* XXX check if swapping is necessary on BE */
7737 	if (ring->use_doorbell)
7738 		wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7739 	else
7740 		BUG();
7741 	return wptr;
7742 }
7743 
7744 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7745 {
7746 	struct amdgpu_device *adev = ring->adev;
7747 
7748 	/* XXX check if swapping is necessary on BE */
7749 	if (ring->use_doorbell) {
7750 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7751 		WDOORBELL64(ring->doorbell_index, ring->wptr);
7752 	} else {
7753 		BUG(); /* only DOORBELL method supported on gfx10 now */
7754 	}
7755 }
7756 
7757 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7758 {
7759 	struct amdgpu_device *adev = ring->adev;
7760 	u32 ref_and_mask, reg_mem_engine;
7761 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7762 
7763 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7764 		switch (ring->me) {
7765 		case 1:
7766 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7767 			break;
7768 		case 2:
7769 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7770 			break;
7771 		default:
7772 			return;
7773 		}
7774 		reg_mem_engine = 0;
7775 	} else {
7776 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7777 		reg_mem_engine = 1; /* pfp */
7778 	}
7779 
7780 	gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7781 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7782 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7783 			       ref_and_mask, ref_and_mask, 0x20);
7784 }
7785 
7786 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7787 				       struct amdgpu_job *job,
7788 				       struct amdgpu_ib *ib,
7789 				       uint32_t flags)
7790 {
7791 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7792 	u32 header, control = 0;
7793 
7794 	if (ib->flags & AMDGPU_IB_FLAG_CE)
7795 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7796 	else
7797 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7798 
7799 	control |= ib->length_dw | (vmid << 24);
7800 
7801 	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7802 		control |= INDIRECT_BUFFER_PRE_ENB(1);
7803 
7804 		if (flags & AMDGPU_IB_PREEMPTED)
7805 			control |= INDIRECT_BUFFER_PRE_RESUME(1);
7806 
7807 		if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7808 			gfx_v10_0_ring_emit_de_meta(ring,
7809 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7810 	}
7811 
7812 	amdgpu_ring_write(ring, header);
7813 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7814 	amdgpu_ring_write(ring,
7815 #ifdef __BIG_ENDIAN
7816 		(2 << 0) |
7817 #endif
7818 		lower_32_bits(ib->gpu_addr));
7819 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7820 	amdgpu_ring_write(ring, control);
7821 }
7822 
7823 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7824 					   struct amdgpu_job *job,
7825 					   struct amdgpu_ib *ib,
7826 					   uint32_t flags)
7827 {
7828 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7829 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7830 
7831 	/* Currently, there is a high possibility to get wave ID mismatch
7832 	 * between ME and GDS, leading to a hw deadlock, because ME generates
7833 	 * different wave IDs than the GDS expects. This situation happens
7834 	 * randomly when at least 5 compute pipes use GDS ordered append.
7835 	 * The wave IDs generated by ME are also wrong after suspend/resume.
7836 	 * Those are probably bugs somewhere else in the kernel driver.
7837 	 *
7838 	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7839 	 * GDS to 0 for this ring (me/pipe).
7840 	 */
7841 	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7842 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7843 		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7844 		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7845 	}
7846 
7847 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7848 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7849 	amdgpu_ring_write(ring,
7850 #ifdef __BIG_ENDIAN
7851 				(2 << 0) |
7852 #endif
7853 				lower_32_bits(ib->gpu_addr));
7854 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7855 	amdgpu_ring_write(ring, control);
7856 }
7857 
7858 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7859 				     u64 seq, unsigned flags)
7860 {
7861 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7862 	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7863 
7864 	/* RELEASE_MEM - flush caches, send int */
7865 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7866 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7867 				 PACKET3_RELEASE_MEM_GCR_GL2_WB |
7868 				 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7869 				 PACKET3_RELEASE_MEM_GCR_GLM_WB |
7870 				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7871 				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7872 				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7873 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7874 				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7875 
7876 	/*
7877 	 * the address should be Qword aligned if 64bit write, Dword
7878 	 * aligned if only send 32bit data low (discard data high)
7879 	 */
7880 	if (write64bit)
7881 		BUG_ON(addr & 0x7);
7882 	else
7883 		BUG_ON(addr & 0x3);
7884 	amdgpu_ring_write(ring, lower_32_bits(addr));
7885 	amdgpu_ring_write(ring, upper_32_bits(addr));
7886 	amdgpu_ring_write(ring, lower_32_bits(seq));
7887 	amdgpu_ring_write(ring, upper_32_bits(seq));
7888 	amdgpu_ring_write(ring, 0);
7889 }
7890 
7891 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7892 {
7893 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7894 	uint32_t seq = ring->fence_drv.sync_seq;
7895 	uint64_t addr = ring->fence_drv.gpu_addr;
7896 
7897 	gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7898 			       upper_32_bits(addr), seq, 0xffffffff, 4);
7899 }
7900 
7901 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7902 					 unsigned vmid, uint64_t pd_addr)
7903 {
7904 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7905 
7906 	/* compute doesn't have PFP */
7907 	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7908 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
7909 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7910 		amdgpu_ring_write(ring, 0x0);
7911 	}
7912 }
7913 
7914 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7915 					  u64 seq, unsigned int flags)
7916 {
7917 	struct amdgpu_device *adev = ring->adev;
7918 
7919 	/* we only allocate 32bit for each seq wb address */
7920 	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7921 
7922 	/* write fence seq to the "addr" */
7923 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7924 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7925 				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7926 	amdgpu_ring_write(ring, lower_32_bits(addr));
7927 	amdgpu_ring_write(ring, upper_32_bits(addr));
7928 	amdgpu_ring_write(ring, lower_32_bits(seq));
7929 
7930 	if (flags & AMDGPU_FENCE_FLAG_INT) {
7931 		/* set register to trigger INT */
7932 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7933 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7934 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7935 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7936 		amdgpu_ring_write(ring, 0);
7937 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7938 	}
7939 }
7940 
7941 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7942 {
7943 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7944 	amdgpu_ring_write(ring, 0);
7945 }
7946 
7947 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7948 					 uint32_t flags)
7949 {
7950 	uint32_t dw2 = 0;
7951 
7952 	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7953 		gfx_v10_0_ring_emit_ce_meta(ring,
7954 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7955 
7956 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7957 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7958 		/* set load_global_config & load_global_uconfig */
7959 		dw2 |= 0x8001;
7960 		/* set load_cs_sh_regs */
7961 		dw2 |= 0x01000000;
7962 		/* set load_per_context_state & load_gfx_sh_regs for GFX */
7963 		dw2 |= 0x10002;
7964 
7965 		/* set load_ce_ram if preamble presented */
7966 		if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
7967 			dw2 |= 0x10000000;
7968 	} else {
7969 		/* still load_ce_ram if this is the first time preamble presented
7970 		 * although there is no context switch happens.
7971 		 */
7972 		if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
7973 			dw2 |= 0x10000000;
7974 	}
7975 
7976 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7977 	amdgpu_ring_write(ring, dw2);
7978 	amdgpu_ring_write(ring, 0);
7979 }
7980 
7981 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7982 {
7983 	unsigned ret;
7984 
7985 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
7986 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
7987 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
7988 	amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7989 	ret = ring->wptr & ring->buf_mask;
7990 	amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
7991 
7992 	return ret;
7993 }
7994 
7995 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
7996 {
7997 	unsigned cur;
7998 	BUG_ON(offset > ring->buf_mask);
7999 	BUG_ON(ring->ring[offset] != 0x55aa55aa);
8000 
8001 	cur = (ring->wptr - 1) & ring->buf_mask;
8002 	if (likely(cur > offset))
8003 		ring->ring[offset] = cur - offset;
8004 	else
8005 		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8006 }
8007 
8008 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8009 {
8010 	int i, r = 0;
8011 	struct amdgpu_device *adev = ring->adev;
8012 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8013 	struct amdgpu_ring *kiq_ring = &kiq->ring;
8014 	unsigned long flags;
8015 
8016 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8017 		return -EINVAL;
8018 
8019 	spin_lock_irqsave(&kiq->ring_lock, flags);
8020 
8021 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8022 		spin_unlock_irqrestore(&kiq->ring_lock, flags);
8023 		return -ENOMEM;
8024 	}
8025 
8026 	/* assert preemption condition */
8027 	amdgpu_ring_set_preempt_cond_exec(ring, false);
8028 
8029 	/* assert IB preemption, emit the trailing fence */
8030 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8031 				   ring->trail_fence_gpu_addr,
8032 				   ++ring->trail_seq);
8033 	amdgpu_ring_commit(kiq_ring);
8034 
8035 	spin_unlock_irqrestore(&kiq->ring_lock, flags);
8036 
8037 	/* poll the trailing fence */
8038 	for (i = 0; i < adev->usec_timeout; i++) {
8039 		if (ring->trail_seq ==
8040 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8041 			break;
8042 		udelay(1);
8043 	}
8044 
8045 	if (i >= adev->usec_timeout) {
8046 		r = -EINVAL;
8047 		DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8048 	}
8049 
8050 	/* deassert preemption condition */
8051 	amdgpu_ring_set_preempt_cond_exec(ring, true);
8052 	return r;
8053 }
8054 
8055 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8056 {
8057 	struct amdgpu_device *adev = ring->adev;
8058 	struct v10_ce_ib_state ce_payload = {0};
8059 	uint64_t csa_addr;
8060 	int cnt;
8061 
8062 	cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8063 	csa_addr = amdgpu_csa_vaddr(ring->adev);
8064 
8065 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8066 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8067 				 WRITE_DATA_DST_SEL(8) |
8068 				 WR_CONFIRM) |
8069 				 WRITE_DATA_CACHE_POLICY(0));
8070 	amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8071 			      offsetof(struct v10_gfx_meta_data, ce_payload)));
8072 	amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8073 			      offsetof(struct v10_gfx_meta_data, ce_payload)));
8074 
8075 	if (resume)
8076 		amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8077 					   offsetof(struct v10_gfx_meta_data,
8078 						    ce_payload),
8079 					   sizeof(ce_payload) >> 2);
8080 	else
8081 		amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8082 					   sizeof(ce_payload) >> 2);
8083 }
8084 
8085 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8086 {
8087 	struct amdgpu_device *adev = ring->adev;
8088 	struct v10_de_ib_state de_payload = {0};
8089 	uint64_t csa_addr, gds_addr;
8090 	int cnt;
8091 
8092 	csa_addr = amdgpu_csa_vaddr(ring->adev);
8093 	gds_addr = roundup2(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8094 			 PAGE_SIZE);
8095 	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8096 	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8097 
8098 	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8099 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8100 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8101 				 WRITE_DATA_DST_SEL(8) |
8102 				 WR_CONFIRM) |
8103 				 WRITE_DATA_CACHE_POLICY(0));
8104 	amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8105 			      offsetof(struct v10_gfx_meta_data, de_payload)));
8106 	amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8107 			      offsetof(struct v10_gfx_meta_data, de_payload)));
8108 
8109 	if (resume)
8110 		amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8111 					   offsetof(struct v10_gfx_meta_data,
8112 						    de_payload),
8113 					   sizeof(de_payload) >> 2);
8114 	else
8115 		amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8116 					   sizeof(de_payload) >> 2);
8117 }
8118 
8119 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8120 				    bool secure)
8121 {
8122 	uint32_t v = secure ? FRAME_TMZ : 0;
8123 
8124 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8125 	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8126 }
8127 
8128 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8129 				     uint32_t reg_val_offs)
8130 {
8131 	struct amdgpu_device *adev = ring->adev;
8132 
8133 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8134 	amdgpu_ring_write(ring, 0 |	/* src: register*/
8135 				(5 << 8) |	/* dst: memory */
8136 				(1 << 20));	/* write confirm */
8137 	amdgpu_ring_write(ring, reg);
8138 	amdgpu_ring_write(ring, 0);
8139 	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8140 				reg_val_offs * 4));
8141 	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8142 				reg_val_offs * 4));
8143 }
8144 
8145 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8146 				   uint32_t val)
8147 {
8148 	uint32_t cmd = 0;
8149 
8150 	switch (ring->funcs->type) {
8151 	case AMDGPU_RING_TYPE_GFX:
8152 		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8153 		break;
8154 	case AMDGPU_RING_TYPE_KIQ:
8155 		cmd = (1 << 16); /* no inc addr */
8156 		break;
8157 	default:
8158 		cmd = WR_CONFIRM;
8159 		break;
8160 	}
8161 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8162 	amdgpu_ring_write(ring, cmd);
8163 	amdgpu_ring_write(ring, reg);
8164 	amdgpu_ring_write(ring, 0);
8165 	amdgpu_ring_write(ring, val);
8166 }
8167 
8168 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8169 					uint32_t val, uint32_t mask)
8170 {
8171 	gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8172 }
8173 
8174 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8175 						   uint32_t reg0, uint32_t reg1,
8176 						   uint32_t ref, uint32_t mask)
8177 {
8178 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8179 	struct amdgpu_device *adev = ring->adev;
8180 	bool fw_version_ok = false;
8181 
8182 	fw_version_ok = adev->gfx.cp_fw_write_wait;
8183 
8184 	if (fw_version_ok)
8185 		gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8186 				       ref, mask, 0x20);
8187 	else
8188 		amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8189 							   ref, mask);
8190 }
8191 
8192 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8193 					 unsigned vmid)
8194 {
8195 	struct amdgpu_device *adev = ring->adev;
8196 	uint32_t value = 0;
8197 
8198 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8199 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8200 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8201 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8202 	WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8203 }
8204 
8205 static void
8206 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8207 				      uint32_t me, uint32_t pipe,
8208 				      enum amdgpu_interrupt_state state)
8209 {
8210 	uint32_t cp_int_cntl, cp_int_cntl_reg;
8211 
8212 	if (!me) {
8213 		switch (pipe) {
8214 		case 0:
8215 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8216 			break;
8217 		case 1:
8218 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8219 			break;
8220 		default:
8221 			DRM_DEBUG("invalid pipe %d\n", pipe);
8222 			return;
8223 		}
8224 	} else {
8225 		DRM_DEBUG("invalid me %d\n", me);
8226 		return;
8227 	}
8228 
8229 	switch (state) {
8230 	case AMDGPU_IRQ_STATE_DISABLE:
8231 		cp_int_cntl = RREG32(cp_int_cntl_reg);
8232 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8233 					    TIME_STAMP_INT_ENABLE, 0);
8234 		WREG32(cp_int_cntl_reg, cp_int_cntl);
8235 		break;
8236 	case AMDGPU_IRQ_STATE_ENABLE:
8237 		cp_int_cntl = RREG32(cp_int_cntl_reg);
8238 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8239 					    TIME_STAMP_INT_ENABLE, 1);
8240 		WREG32(cp_int_cntl_reg, cp_int_cntl);
8241 		break;
8242 	default:
8243 		break;
8244 	}
8245 }
8246 
8247 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8248 						     int me, int pipe,
8249 						     enum amdgpu_interrupt_state state)
8250 {
8251 	u32 mec_int_cntl, mec_int_cntl_reg;
8252 
8253 	/*
8254 	 * amdgpu controls only the first MEC. That's why this function only
8255 	 * handles the setting of interrupts for this specific MEC. All other
8256 	 * pipes' interrupts are set by amdkfd.
8257 	 */
8258 
8259 	if (me == 1) {
8260 		switch (pipe) {
8261 		case 0:
8262 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8263 			break;
8264 		case 1:
8265 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8266 			break;
8267 		case 2:
8268 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8269 			break;
8270 		case 3:
8271 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8272 			break;
8273 		default:
8274 			DRM_DEBUG("invalid pipe %d\n", pipe);
8275 			return;
8276 		}
8277 	} else {
8278 		DRM_DEBUG("invalid me %d\n", me);
8279 		return;
8280 	}
8281 
8282 	switch (state) {
8283 	case AMDGPU_IRQ_STATE_DISABLE:
8284 		mec_int_cntl = RREG32(mec_int_cntl_reg);
8285 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8286 					     TIME_STAMP_INT_ENABLE, 0);
8287 		WREG32(mec_int_cntl_reg, mec_int_cntl);
8288 		break;
8289 	case AMDGPU_IRQ_STATE_ENABLE:
8290 		mec_int_cntl = RREG32(mec_int_cntl_reg);
8291 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8292 					     TIME_STAMP_INT_ENABLE, 1);
8293 		WREG32(mec_int_cntl_reg, mec_int_cntl);
8294 		break;
8295 	default:
8296 		break;
8297 	}
8298 }
8299 
8300 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8301 					    struct amdgpu_irq_src *src,
8302 					    unsigned type,
8303 					    enum amdgpu_interrupt_state state)
8304 {
8305 	switch (type) {
8306 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8307 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8308 		break;
8309 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8310 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8311 		break;
8312 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8313 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8314 		break;
8315 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8316 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8317 		break;
8318 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8319 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8320 		break;
8321 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8322 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8323 		break;
8324 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8325 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8326 		break;
8327 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8328 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8329 		break;
8330 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8331 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8332 		break;
8333 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8334 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8335 		break;
8336 	default:
8337 		break;
8338 	}
8339 	return 0;
8340 }
8341 
8342 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8343 			     struct amdgpu_irq_src *source,
8344 			     struct amdgpu_iv_entry *entry)
8345 {
8346 	int i;
8347 	u8 me_id, pipe_id, queue_id;
8348 	struct amdgpu_ring *ring;
8349 
8350 	DRM_DEBUG("IH: CP EOP\n");
8351 	me_id = (entry->ring_id & 0x0c) >> 2;
8352 	pipe_id = (entry->ring_id & 0x03) >> 0;
8353 	queue_id = (entry->ring_id & 0x70) >> 4;
8354 
8355 	switch (me_id) {
8356 	case 0:
8357 		if (pipe_id == 0)
8358 			amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8359 		else
8360 			amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8361 		break;
8362 	case 1:
8363 	case 2:
8364 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8365 			ring = &adev->gfx.compute_ring[i];
8366 			/* Per-queue interrupt is supported for MEC starting from VI.
8367 			  * The interrupt can only be enabled/disabled per pipe instead of per queue.
8368 			  */
8369 			if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8370 				amdgpu_fence_process(ring);
8371 		}
8372 		break;
8373 	}
8374 	return 0;
8375 }
8376 
8377 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8378 					      struct amdgpu_irq_src *source,
8379 					      unsigned type,
8380 					      enum amdgpu_interrupt_state state)
8381 {
8382 	switch (state) {
8383 	case AMDGPU_IRQ_STATE_DISABLE:
8384 	case AMDGPU_IRQ_STATE_ENABLE:
8385 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8386 			       PRIV_REG_INT_ENABLE,
8387 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8388 		break;
8389 	default:
8390 		break;
8391 	}
8392 
8393 	return 0;
8394 }
8395 
8396 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8397 					       struct amdgpu_irq_src *source,
8398 					       unsigned type,
8399 					       enum amdgpu_interrupt_state state)
8400 {
8401 	switch (state) {
8402 	case AMDGPU_IRQ_STATE_DISABLE:
8403 	case AMDGPU_IRQ_STATE_ENABLE:
8404 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8405 			       PRIV_INSTR_INT_ENABLE,
8406 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8407 	default:
8408 		break;
8409 	}
8410 
8411 	return 0;
8412 }
8413 
8414 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8415 					struct amdgpu_iv_entry *entry)
8416 {
8417 	u8 me_id, pipe_id, queue_id;
8418 	struct amdgpu_ring *ring;
8419 	int i;
8420 
8421 	me_id = (entry->ring_id & 0x0c) >> 2;
8422 	pipe_id = (entry->ring_id & 0x03) >> 0;
8423 	queue_id = (entry->ring_id & 0x70) >> 4;
8424 
8425 	switch (me_id) {
8426 	case 0:
8427 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8428 			ring = &adev->gfx.gfx_ring[i];
8429 			/* we only enabled 1 gfx queue per pipe for now */
8430 			if (ring->me == me_id && ring->pipe == pipe_id)
8431 				drm_sched_fault(&ring->sched);
8432 		}
8433 		break;
8434 	case 1:
8435 	case 2:
8436 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8437 			ring = &adev->gfx.compute_ring[i];
8438 			if (ring->me == me_id && ring->pipe == pipe_id &&
8439 			    ring->queue == queue_id)
8440 				drm_sched_fault(&ring->sched);
8441 		}
8442 		break;
8443 	default:
8444 		BUG();
8445 	}
8446 }
8447 
8448 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8449 				  struct amdgpu_irq_src *source,
8450 				  struct amdgpu_iv_entry *entry)
8451 {
8452 	DRM_ERROR("Illegal register access in command stream\n");
8453 	gfx_v10_0_handle_priv_fault(adev, entry);
8454 	return 0;
8455 }
8456 
8457 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8458 				   struct amdgpu_irq_src *source,
8459 				   struct amdgpu_iv_entry *entry)
8460 {
8461 	DRM_ERROR("Illegal instruction in command stream\n");
8462 	gfx_v10_0_handle_priv_fault(adev, entry);
8463 	return 0;
8464 }
8465 
8466 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8467 					     struct amdgpu_irq_src *src,
8468 					     unsigned int type,
8469 					     enum amdgpu_interrupt_state state)
8470 {
8471 	uint32_t tmp, target;
8472 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8473 
8474 	if (ring->me == 1)
8475 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8476 	else
8477 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8478 	target += ring->pipe;
8479 
8480 	switch (type) {
8481 	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8482 		if (state == AMDGPU_IRQ_STATE_DISABLE) {
8483 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8484 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8485 					    GENERIC2_INT_ENABLE, 0);
8486 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8487 
8488 			tmp = RREG32(target);
8489 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8490 					    GENERIC2_INT_ENABLE, 0);
8491 			WREG32(target, tmp);
8492 		} else {
8493 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8494 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8495 					    GENERIC2_INT_ENABLE, 1);
8496 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8497 
8498 			tmp = RREG32(target);
8499 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8500 					    GENERIC2_INT_ENABLE, 1);
8501 			WREG32(target, tmp);
8502 		}
8503 		break;
8504 	default:
8505 		BUG(); /* kiq only support GENERIC2_INT now */
8506 		break;
8507 	}
8508 	return 0;
8509 }
8510 
8511 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8512 			     struct amdgpu_irq_src *source,
8513 			     struct amdgpu_iv_entry *entry)
8514 {
8515 	u8 me_id, pipe_id, queue_id;
8516 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8517 
8518 	me_id = (entry->ring_id & 0x0c) >> 2;
8519 	pipe_id = (entry->ring_id & 0x03) >> 0;
8520 	queue_id = (entry->ring_id & 0x70) >> 4;
8521 	DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8522 		   me_id, pipe_id, queue_id);
8523 
8524 	amdgpu_fence_process(ring);
8525 	return 0;
8526 }
8527 
8528 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8529 {
8530 	const unsigned int gcr_cntl =
8531 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8532 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8533 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8534 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8535 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8536 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8537 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8538 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8539 
8540 	/* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8541 	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8542 	amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8543 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8544 	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8545 	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8546 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8547 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8548 	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8549 }
8550 
8551 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8552 	.name = "gfx_v10_0",
8553 	.early_init = gfx_v10_0_early_init,
8554 	.late_init = gfx_v10_0_late_init,
8555 	.sw_init = gfx_v10_0_sw_init,
8556 	.sw_fini = gfx_v10_0_sw_fini,
8557 	.hw_init = gfx_v10_0_hw_init,
8558 	.hw_fini = gfx_v10_0_hw_fini,
8559 	.suspend = gfx_v10_0_suspend,
8560 	.resume = gfx_v10_0_resume,
8561 	.is_idle = gfx_v10_0_is_idle,
8562 	.wait_for_idle = gfx_v10_0_wait_for_idle,
8563 	.soft_reset = gfx_v10_0_soft_reset,
8564 	.set_clockgating_state = gfx_v10_0_set_clockgating_state,
8565 	.set_powergating_state = gfx_v10_0_set_powergating_state,
8566 	.get_clockgating_state = gfx_v10_0_get_clockgating_state,
8567 };
8568 
8569 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8570 	.type = AMDGPU_RING_TYPE_GFX,
8571 	.align_mask = 0xff,
8572 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
8573 	.support_64bit_ptrs = true,
8574 	.vmhub = AMDGPU_GFXHUB_0,
8575 	.get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8576 	.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8577 	.set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8578 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
8579 		5 + /* COND_EXEC */
8580 		7 + /* PIPELINE_SYNC */
8581 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8582 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8583 		2 + /* VM_FLUSH */
8584 		8 + /* FENCE for VM_FLUSH */
8585 		20 + /* GDS switch */
8586 		4 + /* double SWITCH_BUFFER,
8587 		     * the first COND_EXEC jump to the place
8588 		     * just prior to this double SWITCH_BUFFER
8589 		     */
8590 		5 + /* COND_EXEC */
8591 		7 + /* HDP_flush */
8592 		4 + /* VGT_flush */
8593 		14 + /*	CE_META */
8594 		31 + /*	DE_META */
8595 		3 + /* CNTX_CTRL */
8596 		5 + /* HDP_INVL */
8597 		8 + 8 + /* FENCE x2 */
8598 		2 + /* SWITCH_BUFFER */
8599 		8, /* gfx_v10_0_emit_mem_sync */
8600 	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
8601 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8602 	.emit_fence = gfx_v10_0_ring_emit_fence,
8603 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8604 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8605 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8606 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8607 	.test_ring = gfx_v10_0_ring_test_ring,
8608 	.test_ib = gfx_v10_0_ring_test_ib,
8609 	.insert_nop = amdgpu_ring_insert_nop,
8610 	.pad_ib = amdgpu_ring_generic_pad_ib,
8611 	.emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8612 	.emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8613 	.init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8614 	.patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8615 	.preempt_ib = gfx_v10_0_ring_preempt_ib,
8616 	.emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8617 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
8618 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8619 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8620 	.soft_recovery = gfx_v10_0_ring_soft_recovery,
8621 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
8622 };
8623 
8624 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8625 	.type = AMDGPU_RING_TYPE_COMPUTE,
8626 	.align_mask = 0xff,
8627 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
8628 	.support_64bit_ptrs = true,
8629 	.vmhub = AMDGPU_GFXHUB_0,
8630 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
8631 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
8632 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
8633 	.emit_frame_size =
8634 		20 + /* gfx_v10_0_ring_emit_gds_switch */
8635 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
8636 		5 + /* hdp invalidate */
8637 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8638 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8639 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8640 		2 + /* gfx_v10_0_ring_emit_vm_flush */
8641 		8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8642 		8, /* gfx_v10_0_emit_mem_sync */
8643 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
8644 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
8645 	.emit_fence = gfx_v10_0_ring_emit_fence,
8646 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8647 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8648 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8649 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8650 	.test_ring = gfx_v10_0_ring_test_ring,
8651 	.test_ib = gfx_v10_0_ring_test_ib,
8652 	.insert_nop = amdgpu_ring_insert_nop,
8653 	.pad_ib = amdgpu_ring_generic_pad_ib,
8654 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
8655 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8656 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8657 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
8658 };
8659 
8660 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8661 	.type = AMDGPU_RING_TYPE_KIQ,
8662 	.align_mask = 0xff,
8663 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
8664 	.support_64bit_ptrs = true,
8665 	.vmhub = AMDGPU_GFXHUB_0,
8666 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
8667 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
8668 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
8669 	.emit_frame_size =
8670 		20 + /* gfx_v10_0_ring_emit_gds_switch */
8671 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
8672 		5 + /*hdp invalidate */
8673 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8674 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8675 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8676 		2 + /* gfx_v10_0_ring_emit_vm_flush */
8677 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8678 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
8679 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
8680 	.emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8681 	.test_ring = gfx_v10_0_ring_test_ring,
8682 	.test_ib = gfx_v10_0_ring_test_ib,
8683 	.insert_nop = amdgpu_ring_insert_nop,
8684 	.pad_ib = amdgpu_ring_generic_pad_ib,
8685 	.emit_rreg = gfx_v10_0_ring_emit_rreg,
8686 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
8687 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8688 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8689 };
8690 
8691 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8692 {
8693 	int i;
8694 
8695 	adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8696 
8697 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8698 		adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8699 
8700 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
8701 		adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8702 }
8703 
8704 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8705 	.set = gfx_v10_0_set_eop_interrupt_state,
8706 	.process = gfx_v10_0_eop_irq,
8707 };
8708 
8709 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8710 	.set = gfx_v10_0_set_priv_reg_fault_state,
8711 	.process = gfx_v10_0_priv_reg_irq,
8712 };
8713 
8714 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8715 	.set = gfx_v10_0_set_priv_inst_fault_state,
8716 	.process = gfx_v10_0_priv_inst_irq,
8717 };
8718 
8719 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8720 	.set = gfx_v10_0_kiq_set_interrupt_state,
8721 	.process = gfx_v10_0_kiq_irq,
8722 };
8723 
8724 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8725 {
8726 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8727 	adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8728 
8729 	adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8730 	adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8731 
8732 	adev->gfx.priv_reg_irq.num_types = 1;
8733 	adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8734 
8735 	adev->gfx.priv_inst_irq.num_types = 1;
8736 	adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8737 }
8738 
8739 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8740 {
8741 	switch (adev->asic_type) {
8742 	case CHIP_NAVI10:
8743 	case CHIP_NAVI14:
8744 	case CHIP_SIENNA_CICHLID:
8745 	case CHIP_NAVY_FLOUNDER:
8746 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8747 		break;
8748 	case CHIP_NAVI12:
8749 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8750 		break;
8751 	default:
8752 		break;
8753 	}
8754 }
8755 
8756 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8757 {
8758 	unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8759 			    adev->gfx.config.max_sh_per_se *
8760 			    adev->gfx.config.max_shader_engines;
8761 
8762 	adev->gds.gds_size = 0x10000;
8763 	adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8764 	adev->gds.gws_size = 64;
8765 	adev->gds.oa_size = 16;
8766 }
8767 
8768 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8769 							  u32 bitmap)
8770 {
8771 	u32 data;
8772 
8773 	if (!bitmap)
8774 		return;
8775 
8776 	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8777 	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8778 
8779 	WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8780 }
8781 
8782 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8783 {
8784 	u32 data, wgp_bitmask;
8785 	data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8786 	data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8787 
8788 	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8789 	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8790 
8791 	wgp_bitmask =
8792 		amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8793 
8794 	return (~data) & wgp_bitmask;
8795 }
8796 
8797 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8798 {
8799 	u32 wgp_idx, wgp_active_bitmap;
8800 	u32 cu_bitmap_per_wgp, cu_active_bitmap;
8801 
8802 	wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8803 	cu_active_bitmap = 0;
8804 
8805 	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8806 		/* if there is one WGP enabled, it means 2 CUs will be enabled */
8807 		cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8808 		if (wgp_active_bitmap & (1 << wgp_idx))
8809 			cu_active_bitmap |= cu_bitmap_per_wgp;
8810 	}
8811 
8812 	return cu_active_bitmap;
8813 }
8814 
8815 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8816 				 struct amdgpu_cu_info *cu_info)
8817 {
8818 	int i, j, k, counter, active_cu_number = 0;
8819 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8820 	unsigned disable_masks[4 * 2];
8821 
8822 	if (!adev || !cu_info)
8823 		return -EINVAL;
8824 
8825 	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8826 
8827 	mutex_lock(&adev->grbm_idx_mutex);
8828 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8829 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8830 			bitmap = i * adev->gfx.config.max_sh_per_se + j;
8831 			if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
8832 			    ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
8833 				continue;
8834 			mask = 1;
8835 			ao_bitmap = 0;
8836 			counter = 0;
8837 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8838 			if (i < 4 && j < 2)
8839 				gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8840 					adev, disable_masks[i * 2 + j]);
8841 			bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8842 			cu_info->bitmap[i][j] = bitmap;
8843 
8844 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8845 				if (bitmap & mask) {
8846 					if (counter < adev->gfx.config.max_cu_per_sh)
8847 						ao_bitmap |= mask;
8848 					counter++;
8849 				}
8850 				mask <<= 1;
8851 			}
8852 			active_cu_number += counter;
8853 			if (i < 2 && j < 2)
8854 				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8855 			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8856 		}
8857 	}
8858 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8859 	mutex_unlock(&adev->grbm_idx_mutex);
8860 
8861 	cu_info->number = active_cu_number;
8862 	cu_info->ao_cu_mask = ao_cu_mask;
8863 	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8864 
8865 	return 0;
8866 }
8867 
8868 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
8869 {
8870 	uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
8871 
8872 	efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
8873 	efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
8874 	efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
8875 
8876 	vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
8877 	vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
8878 	vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
8879 
8880 	max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
8881 						adev->gfx.config.max_shader_engines);
8882 	disabled_sa = efuse_setting | vbios_setting;
8883 	disabled_sa &= max_sa_mask;
8884 
8885 	return disabled_sa;
8886 }
8887 
8888 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
8889 {
8890 	uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
8891 	uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
8892 
8893 	disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
8894 
8895 	max_sa_per_se = adev->gfx.config.max_sh_per_se;
8896 	max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
8897 	max_shader_engines = adev->gfx.config.max_shader_engines;
8898 
8899 	for (se_index = 0; max_shader_engines > se_index; se_index++) {
8900 		disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
8901 		disabled_sa_per_se &= max_sa_per_se_mask;
8902 		if (disabled_sa_per_se == max_sa_per_se_mask) {
8903 			WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
8904 			break;
8905 		}
8906 	}
8907 }
8908 
8909 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8910 {
8911 	.type = AMD_IP_BLOCK_TYPE_GFX,
8912 	.major = 10,
8913 	.minor = 0,
8914 	.rev = 0,
8915 	.funcs = &gfx_v10_0_ip_funcs,
8916 };
8917