1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "smuio/smuio_11_0_0_offset.h" 39 #include "smuio/smuio_11_0_0_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "soc15_common.h" 47 #include "clearstate_gfx10.h" 48 #include "v10_structs.h" 49 #include "gfx_v10_0.h" 50 #include "nbio_v2_3.h" 51 52 /** 53 * Navi10 has two graphic rings to share each graphic pipe. 54 * 1. Primary ring 55 * 2. Async ring 56 */ 57 #define GFX10_NUM_GFX_RINGS_NV1X 1 58 #define GFX10_MEC_HPD_SIZE 2048 59 60 #define F32_CE_PROGRAM_RAM_SIZE 65536 61 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 62 63 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 65 66 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 67 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 68 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 69 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 70 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 71 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 72 73 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 74 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 75 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 76 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 77 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 78 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 79 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 80 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 81 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 82 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 83 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 84 85 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 86 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 87 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 88 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 89 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 90 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 91 92 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 93 { 94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 134 }; 135 136 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 137 { 138 /* Pending on emulation bring up */ 139 }; 140 141 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 142 { 143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 181 }; 182 183 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 184 { 185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 225 }; 226 227 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v) 228 { 229 #ifdef __linux__ 230 static void *scratch_reg0; 231 static void *scratch_reg1; 232 static void *scratch_reg2; 233 static void *scratch_reg3; 234 static void *spare_int; 235 #endif 236 static uint32_t grbm_cntl; 237 static uint32_t grbm_idx; 238 uint32_t i = 0; 239 uint32_t retries = 50000; 240 241 #ifdef __linux__ 242 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4; 243 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4; 244 scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4; 245 scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4; 246 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4; 247 #endif 248 249 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL; 250 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX; 251 252 if (amdgpu_sriov_runtime(adev)) { 253 pr_err("shouldn't call rlcg write register during runtime\n"); 254 return; 255 } 256 257 bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh, 258 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4, 259 v); 260 bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh, 261 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4, 262 offset | 0x80000000); 263 bus_space_write_4(adev->rmmio_bst, adev->rmmio_bsh, 264 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4, 265 1); 266 for (i = 0; i < retries; i++) { 267 u32 tmp; 268 269 tmp = bus_space_read_4(adev->rmmio_bst, adev->rmmio_bsh, 270 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4); 271 if (!(tmp & 0x80000000)) 272 break; 273 274 udelay(10); 275 } 276 277 if (i >= retries) 278 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset); 279 } 280 281 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 282 { 283 /* Pending on emulation bring up */ 284 }; 285 286 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 287 { 288 /* Pending on emulation bring up */ 289 }; 290 291 #define DEFAULT_SH_MEM_CONFIG \ 292 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 293 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 294 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 295 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 296 297 298 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 299 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 300 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 301 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 302 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 303 struct amdgpu_cu_info *cu_info); 304 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 305 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 306 u32 sh_num, u32 instance); 307 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 308 309 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 310 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 311 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 312 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 313 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 314 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 315 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start); 316 317 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 318 { 319 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 320 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 321 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 322 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 323 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 324 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 325 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 326 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 327 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 328 } 329 330 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 331 struct amdgpu_ring *ring) 332 { 333 struct amdgpu_device *adev = kiq_ring->adev; 334 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 335 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 336 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 337 338 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 339 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 340 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 341 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 342 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 343 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 344 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 345 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 346 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 347 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 348 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 349 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 350 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 351 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 352 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 353 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 354 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 355 } 356 357 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 358 struct amdgpu_ring *ring, 359 enum amdgpu_unmap_queues_action action, 360 u64 gpu_addr, u64 seq) 361 { 362 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 363 364 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 365 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 366 PACKET3_UNMAP_QUEUES_ACTION(action) | 367 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 368 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 369 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 370 amdgpu_ring_write(kiq_ring, 371 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 372 373 if (action == PREEMPT_QUEUES_NO_UNMAP) { 374 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 375 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 376 amdgpu_ring_write(kiq_ring, seq); 377 } else { 378 amdgpu_ring_write(kiq_ring, 0); 379 amdgpu_ring_write(kiq_ring, 0); 380 amdgpu_ring_write(kiq_ring, 0); 381 } 382 } 383 384 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 385 struct amdgpu_ring *ring, 386 u64 addr, 387 u64 seq) 388 { 389 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 390 391 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 392 amdgpu_ring_write(kiq_ring, 393 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 394 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 395 PACKET3_QUERY_STATUS_COMMAND(2)); 396 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 397 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 398 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 399 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 400 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 401 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 402 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 403 } 404 405 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 406 uint16_t pasid, uint32_t flush_type, 407 bool all_hub) 408 { 409 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 410 amdgpu_ring_write(kiq_ring, 411 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 412 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 413 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 414 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 415 } 416 417 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 418 .kiq_set_resources = gfx10_kiq_set_resources, 419 .kiq_map_queues = gfx10_kiq_map_queues, 420 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 421 .kiq_query_status = gfx10_kiq_query_status, 422 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 423 .set_resources_size = 8, 424 .map_queues_size = 7, 425 .unmap_queues_size = 6, 426 .query_status_size = 7, 427 .invalidate_tlbs_size = 2, 428 }; 429 430 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 431 { 432 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 433 } 434 435 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 436 { 437 switch (adev->asic_type) { 438 case CHIP_NAVI10: 439 soc15_program_register_sequence(adev, 440 golden_settings_gc_10_1, 441 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 442 soc15_program_register_sequence(adev, 443 golden_settings_gc_10_0_nv10, 444 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 445 break; 446 case CHIP_NAVI14: 447 soc15_program_register_sequence(adev, 448 golden_settings_gc_10_1_1, 449 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 450 soc15_program_register_sequence(adev, 451 golden_settings_gc_10_1_nv14, 452 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 453 break; 454 case CHIP_NAVI12: 455 soc15_program_register_sequence(adev, 456 golden_settings_gc_10_1_2, 457 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 458 soc15_program_register_sequence(adev, 459 golden_settings_gc_10_1_2_nv12, 460 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 461 break; 462 default: 463 break; 464 } 465 } 466 467 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 468 { 469 adev->gfx.scratch.num_reg = 8; 470 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 471 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 472 } 473 474 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 475 bool wc, uint32_t reg, uint32_t val) 476 { 477 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 478 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 479 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 480 amdgpu_ring_write(ring, reg); 481 amdgpu_ring_write(ring, 0); 482 amdgpu_ring_write(ring, val); 483 } 484 485 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 486 int mem_space, int opt, uint32_t addr0, 487 uint32_t addr1, uint32_t ref, uint32_t mask, 488 uint32_t inv) 489 { 490 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 491 amdgpu_ring_write(ring, 492 /* memory (1) or register (0) */ 493 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 494 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 495 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 496 WAIT_REG_MEM_ENGINE(eng_sel))); 497 498 if (mem_space) 499 BUG_ON(addr0 & 0x3); /* Dword align */ 500 amdgpu_ring_write(ring, addr0); 501 amdgpu_ring_write(ring, addr1); 502 amdgpu_ring_write(ring, ref); 503 amdgpu_ring_write(ring, mask); 504 amdgpu_ring_write(ring, inv); /* poll interval */ 505 } 506 507 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 508 { 509 struct amdgpu_device *adev = ring->adev; 510 uint32_t scratch; 511 uint32_t tmp = 0; 512 unsigned i; 513 int r; 514 515 r = amdgpu_gfx_scratch_get(adev, &scratch); 516 if (r) { 517 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 518 return r; 519 } 520 521 WREG32(scratch, 0xCAFEDEAD); 522 523 r = amdgpu_ring_alloc(ring, 3); 524 if (r) { 525 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 526 ring->idx, r); 527 amdgpu_gfx_scratch_free(adev, scratch); 528 return r; 529 } 530 531 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 532 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 533 amdgpu_ring_write(ring, 0xDEADBEEF); 534 amdgpu_ring_commit(ring); 535 536 for (i = 0; i < adev->usec_timeout; i++) { 537 tmp = RREG32(scratch); 538 if (tmp == 0xDEADBEEF) 539 break; 540 if (amdgpu_emu_mode == 1) 541 drm_msleep(1); 542 else 543 udelay(1); 544 } 545 546 if (i >= adev->usec_timeout) 547 r = -ETIMEDOUT; 548 549 amdgpu_gfx_scratch_free(adev, scratch); 550 551 return r; 552 } 553 554 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 555 { 556 struct amdgpu_device *adev = ring->adev; 557 struct amdgpu_ib ib; 558 struct dma_fence *f = NULL; 559 unsigned index; 560 uint64_t gpu_addr; 561 uint32_t tmp; 562 long r; 563 564 r = amdgpu_device_wb_get(adev, &index); 565 if (r) 566 return r; 567 568 gpu_addr = adev->wb.gpu_addr + (index * 4); 569 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 570 memset(&ib, 0, sizeof(ib)); 571 r = amdgpu_ib_get(adev, NULL, 16, &ib); 572 if (r) 573 goto err1; 574 575 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 576 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 577 ib.ptr[2] = lower_32_bits(gpu_addr); 578 ib.ptr[3] = upper_32_bits(gpu_addr); 579 ib.ptr[4] = 0xDEADBEEF; 580 ib.length_dw = 5; 581 582 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 583 if (r) 584 goto err2; 585 586 r = dma_fence_wait_timeout(f, false, timeout); 587 if (r == 0) { 588 r = -ETIMEDOUT; 589 goto err2; 590 } else if (r < 0) { 591 goto err2; 592 } 593 594 tmp = adev->wb.wb[index]; 595 if (tmp == 0xDEADBEEF) 596 r = 0; 597 else 598 r = -EINVAL; 599 err2: 600 amdgpu_ib_free(adev, &ib, NULL); 601 dma_fence_put(f); 602 err1: 603 amdgpu_device_wb_free(adev, index); 604 return r; 605 } 606 607 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 608 { 609 release_firmware(adev->gfx.pfp_fw); 610 adev->gfx.pfp_fw = NULL; 611 release_firmware(adev->gfx.me_fw); 612 adev->gfx.me_fw = NULL; 613 release_firmware(adev->gfx.ce_fw); 614 adev->gfx.ce_fw = NULL; 615 release_firmware(adev->gfx.rlc_fw); 616 adev->gfx.rlc_fw = NULL; 617 release_firmware(adev->gfx.mec_fw); 618 adev->gfx.mec_fw = NULL; 619 release_firmware(adev->gfx.mec2_fw); 620 adev->gfx.mec2_fw = NULL; 621 622 kfree(adev->gfx.rlc.register_list_format); 623 } 624 625 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 626 { 627 adev->gfx.cp_fw_write_wait = false; 628 629 switch (adev->asic_type) { 630 case CHIP_NAVI10: 631 case CHIP_NAVI12: 632 case CHIP_NAVI14: 633 if ((adev->gfx.me_fw_version >= 0x00000046) && 634 (adev->gfx.me_feature_version >= 27) && 635 (adev->gfx.pfp_fw_version >= 0x00000068) && 636 (adev->gfx.pfp_feature_version >= 27) && 637 (adev->gfx.mec_fw_version >= 0x0000005b) && 638 (adev->gfx.mec_feature_version >= 27)) 639 adev->gfx.cp_fw_write_wait = true; 640 break; 641 default: 642 break; 643 } 644 645 if (adev->gfx.cp_fw_write_wait == false) 646 DRM_WARN_ONCE("CP firmware version too old, please update!"); 647 } 648 649 650 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 651 { 652 const struct rlc_firmware_header_v2_1 *rlc_hdr; 653 654 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 655 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 656 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 657 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 658 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 659 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 660 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 661 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 662 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 663 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 664 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 665 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 666 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 667 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 668 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 669 } 670 671 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 672 { 673 bool ret = false; 674 675 switch (adev->pdev->revision) { 676 case 0xc2: 677 case 0xc3: 678 ret = true; 679 break; 680 default: 681 ret = false; 682 break; 683 } 684 685 return ret ; 686 } 687 688 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 689 { 690 switch (adev->asic_type) { 691 case CHIP_NAVI10: 692 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 693 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 694 break; 695 default: 696 break; 697 } 698 } 699 700 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 701 { 702 const char *chip_name; 703 char fw_name[40]; 704 char wks[10]; 705 int err; 706 struct amdgpu_firmware_info *info = NULL; 707 const struct common_firmware_header *header = NULL; 708 const struct gfx_firmware_header_v1_0 *cp_hdr; 709 const struct rlc_firmware_header_v2_0 *rlc_hdr; 710 unsigned int *tmp = NULL; 711 unsigned int i = 0; 712 uint16_t version_major; 713 uint16_t version_minor; 714 715 DRM_DEBUG("\n"); 716 717 memset(wks, 0, sizeof(wks)); 718 switch (adev->asic_type) { 719 case CHIP_NAVI10: 720 chip_name = "navi10"; 721 break; 722 case CHIP_NAVI14: 723 chip_name = "navi14"; 724 if (!(adev->pdev->device == 0x7340 && 725 adev->pdev->revision != 0x00)) 726 snprintf(wks, sizeof(wks), "_wks"); 727 break; 728 case CHIP_NAVI12: 729 chip_name = "navi12"; 730 break; 731 default: 732 BUG(); 733 } 734 735 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 736 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 737 if (err) 738 goto out; 739 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 740 if (err) 741 goto out; 742 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 743 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 744 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 745 746 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 747 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 748 if (err) 749 goto out; 750 err = amdgpu_ucode_validate(adev->gfx.me_fw); 751 if (err) 752 goto out; 753 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 754 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 755 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 756 757 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 758 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 759 if (err) 760 goto out; 761 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 762 if (err) 763 goto out; 764 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 765 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 766 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 767 768 if (!amdgpu_sriov_vf(adev)) { 769 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 770 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 771 if (err) 772 goto out; 773 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 774 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 775 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 776 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 777 if (version_major == 2 && version_minor == 1) 778 adev->gfx.rlc.is_rlc_v2_1 = true; 779 780 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 781 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 782 adev->gfx.rlc.save_and_restore_offset = 783 le32_to_cpu(rlc_hdr->save_and_restore_offset); 784 adev->gfx.rlc.clear_state_descriptor_offset = 785 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 786 adev->gfx.rlc.avail_scratch_ram_locations = 787 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 788 adev->gfx.rlc.reg_restore_list_size = 789 le32_to_cpu(rlc_hdr->reg_restore_list_size); 790 adev->gfx.rlc.reg_list_format_start = 791 le32_to_cpu(rlc_hdr->reg_list_format_start); 792 adev->gfx.rlc.reg_list_format_separate_start = 793 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 794 adev->gfx.rlc.starting_offsets_start = 795 le32_to_cpu(rlc_hdr->starting_offsets_start); 796 adev->gfx.rlc.reg_list_format_size_bytes = 797 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 798 adev->gfx.rlc.reg_list_size_bytes = 799 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 800 adev->gfx.rlc.register_list_format = 801 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 802 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 803 if (!adev->gfx.rlc.register_list_format) { 804 err = -ENOMEM; 805 goto out; 806 } 807 808 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 809 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 810 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 811 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 812 813 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 814 815 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 816 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 817 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 818 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 819 820 if (adev->gfx.rlc.is_rlc_v2_1) 821 gfx_v10_0_init_rlc_ext_microcode(adev); 822 } 823 824 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 825 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 826 if (err) 827 goto out; 828 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 829 if (err) 830 goto out; 831 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 832 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 833 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 834 835 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 836 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 837 if (!err) { 838 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 839 if (err) 840 goto out; 841 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 842 adev->gfx.mec2_fw->data; 843 adev->gfx.mec2_fw_version = 844 le32_to_cpu(cp_hdr->header.ucode_version); 845 adev->gfx.mec2_feature_version = 846 le32_to_cpu(cp_hdr->ucode_feature_version); 847 } else { 848 err = 0; 849 adev->gfx.mec2_fw = NULL; 850 } 851 852 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 853 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 854 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 855 info->fw = adev->gfx.pfp_fw; 856 header = (const struct common_firmware_header *)info->fw->data; 857 adev->firmware.fw_size += 858 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 859 860 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 861 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 862 info->fw = adev->gfx.me_fw; 863 header = (const struct common_firmware_header *)info->fw->data; 864 adev->firmware.fw_size += 865 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 866 867 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 868 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 869 info->fw = adev->gfx.ce_fw; 870 header = (const struct common_firmware_header *)info->fw->data; 871 adev->firmware.fw_size += 872 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 873 874 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 875 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 876 info->fw = adev->gfx.rlc_fw; 877 if (info->fw) { 878 header = (const struct common_firmware_header *)info->fw->data; 879 adev->firmware.fw_size += 880 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 881 } 882 if (adev->gfx.rlc.is_rlc_v2_1 && 883 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 884 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 885 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 886 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 887 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 888 info->fw = adev->gfx.rlc_fw; 889 adev->firmware.fw_size += 890 roundup2(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 891 892 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 893 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 894 info->fw = adev->gfx.rlc_fw; 895 adev->firmware.fw_size += 896 roundup2(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 897 898 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 899 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 900 info->fw = adev->gfx.rlc_fw; 901 adev->firmware.fw_size += 902 roundup2(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 903 } 904 905 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 906 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 907 info->fw = adev->gfx.mec_fw; 908 header = (const struct common_firmware_header *)info->fw->data; 909 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 910 adev->firmware.fw_size += 911 roundup2(le32_to_cpu(header->ucode_size_bytes) - 912 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 913 914 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 915 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 916 info->fw = adev->gfx.mec_fw; 917 adev->firmware.fw_size += 918 roundup2(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 919 920 if (adev->gfx.mec2_fw) { 921 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 922 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 923 info->fw = adev->gfx.mec2_fw; 924 header = (const struct common_firmware_header *)info->fw->data; 925 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 926 adev->firmware.fw_size += 927 roundup2(le32_to_cpu(header->ucode_size_bytes) - 928 le32_to_cpu(cp_hdr->jt_size) * 4, 929 PAGE_SIZE); 930 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 931 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 932 info->fw = adev->gfx.mec2_fw; 933 adev->firmware.fw_size += 934 roundup2(le32_to_cpu(cp_hdr->jt_size) * 4, 935 PAGE_SIZE); 936 } 937 } 938 939 gfx_v10_0_check_fw_write_wait(adev); 940 out: 941 if (err) { 942 dev_err(adev->dev, 943 "gfx10: Failed to load firmware \"%s\"\n", 944 fw_name); 945 release_firmware(adev->gfx.pfp_fw); 946 adev->gfx.pfp_fw = NULL; 947 release_firmware(adev->gfx.me_fw); 948 adev->gfx.me_fw = NULL; 949 release_firmware(adev->gfx.ce_fw); 950 adev->gfx.ce_fw = NULL; 951 release_firmware(adev->gfx.rlc_fw); 952 adev->gfx.rlc_fw = NULL; 953 release_firmware(adev->gfx.mec_fw); 954 adev->gfx.mec_fw = NULL; 955 release_firmware(adev->gfx.mec2_fw); 956 adev->gfx.mec2_fw = NULL; 957 } 958 959 gfx_v10_0_check_gfxoff_flag(adev); 960 961 return err; 962 } 963 964 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 965 { 966 u32 count = 0; 967 const struct cs_section_def *sect = NULL; 968 const struct cs_extent_def *ext = NULL; 969 970 /* begin clear state */ 971 count += 2; 972 /* context control state */ 973 count += 3; 974 975 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 976 for (ext = sect->section; ext->extent != NULL; ++ext) { 977 if (sect->id == SECT_CONTEXT) 978 count += 2 + ext->reg_count; 979 else 980 return 0; 981 } 982 } 983 984 /* set PA_SC_TILE_STEERING_OVERRIDE */ 985 count += 3; 986 /* end clear state */ 987 count += 2; 988 /* clear state */ 989 count += 2; 990 991 return count; 992 } 993 994 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 995 volatile u32 *buffer) 996 { 997 u32 count = 0, i; 998 const struct cs_section_def *sect = NULL; 999 const struct cs_extent_def *ext = NULL; 1000 int ctx_reg_offset; 1001 1002 if (adev->gfx.rlc.cs_data == NULL) 1003 return; 1004 if (buffer == NULL) 1005 return; 1006 1007 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1008 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1009 1010 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 1011 buffer[count++] = cpu_to_le32(0x80000000); 1012 buffer[count++] = cpu_to_le32(0x80000000); 1013 1014 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 1015 for (ext = sect->section; ext->extent != NULL; ++ext) { 1016 if (sect->id == SECT_CONTEXT) { 1017 buffer[count++] = 1018 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 1019 buffer[count++] = cpu_to_le32(ext->reg_index - 1020 PACKET3_SET_CONTEXT_REG_START); 1021 for (i = 0; i < ext->reg_count; i++) 1022 buffer[count++] = cpu_to_le32(ext->extent[i]); 1023 } else { 1024 return; 1025 } 1026 } 1027 } 1028 1029 ctx_reg_offset = 1030 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 1031 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 1032 buffer[count++] = cpu_to_le32(ctx_reg_offset); 1033 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 1034 1035 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1036 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 1037 1038 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 1039 buffer[count++] = cpu_to_le32(0); 1040 } 1041 1042 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 1043 { 1044 /* clear state block */ 1045 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 1046 &adev->gfx.rlc.clear_state_gpu_addr, 1047 (void **)&adev->gfx.rlc.cs_ptr); 1048 1049 /* jump table block */ 1050 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 1051 &adev->gfx.rlc.cp_table_gpu_addr, 1052 (void **)&adev->gfx.rlc.cp_table_ptr); 1053 } 1054 1055 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 1056 { 1057 const struct cs_section_def *cs_data; 1058 int r; 1059 1060 adev->gfx.rlc.cs_data = gfx10_cs_data; 1061 1062 cs_data = adev->gfx.rlc.cs_data; 1063 1064 if (cs_data) { 1065 /* init clear state block */ 1066 r = amdgpu_gfx_rlc_init_csb(adev); 1067 if (r) 1068 return r; 1069 } 1070 1071 /* init spm vmid with 0xf */ 1072 if (adev->gfx.rlc.funcs->update_spm_vmid) 1073 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1074 1075 return 0; 1076 } 1077 1078 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 1079 { 1080 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1081 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1082 } 1083 1084 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 1085 { 1086 int r; 1087 1088 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 1089 1090 amdgpu_gfx_graphics_queue_acquire(adev); 1091 1092 r = gfx_v10_0_init_microcode(adev); 1093 if (r) 1094 DRM_ERROR("Failed to load gfx firmware!\n"); 1095 1096 return r; 1097 } 1098 1099 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 1100 { 1101 int r; 1102 u32 *hpd; 1103 const __le32 *fw_data = NULL; 1104 unsigned fw_size; 1105 u32 *fw = NULL; 1106 size_t mec_hpd_size; 1107 1108 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 1109 1110 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1111 1112 /* take ownership of the relevant compute queues */ 1113 amdgpu_gfx_compute_queue_acquire(adev); 1114 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 1115 1116 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1117 AMDGPU_GEM_DOMAIN_GTT, 1118 &adev->gfx.mec.hpd_eop_obj, 1119 &adev->gfx.mec.hpd_eop_gpu_addr, 1120 (void **)&hpd); 1121 if (r) { 1122 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1123 gfx_v10_0_mec_fini(adev); 1124 return r; 1125 } 1126 1127 memset(hpd, 0, mec_hpd_size); 1128 1129 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1130 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1131 1132 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1133 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1134 1135 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1136 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1137 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 1138 1139 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1140 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1141 &adev->gfx.mec.mec_fw_obj, 1142 &adev->gfx.mec.mec_fw_gpu_addr, 1143 (void **)&fw); 1144 if (r) { 1145 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 1146 gfx_v10_0_mec_fini(adev); 1147 return r; 1148 } 1149 1150 memcpy(fw, fw_data, fw_size); 1151 1152 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1153 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1154 } 1155 1156 return 0; 1157 } 1158 1159 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1160 { 1161 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1162 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1163 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1164 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1165 } 1166 1167 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1168 uint32_t thread, uint32_t regno, 1169 uint32_t num, uint32_t *out) 1170 { 1171 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1172 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1173 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1174 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1175 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1176 while (num--) 1177 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1178 } 1179 1180 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1181 { 1182 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 1183 * field when performing a select_se_sh so it should be 1184 * zero here */ 1185 WARN_ON(simd != 0); 1186 1187 /* type 2 wave data */ 1188 dst[(*no_fields)++] = 2; 1189 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1190 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1191 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1192 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1193 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1194 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1195 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1196 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 1197 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1198 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1199 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1200 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1201 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1202 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1203 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1204 } 1205 1206 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1207 uint32_t wave, uint32_t start, 1208 uint32_t size, uint32_t *dst) 1209 { 1210 WARN_ON(simd != 0); 1211 1212 wave_read_regs( 1213 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1214 dst); 1215 } 1216 1217 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1218 uint32_t wave, uint32_t thread, 1219 uint32_t start, uint32_t size, 1220 uint32_t *dst) 1221 { 1222 wave_read_regs( 1223 adev, wave, thread, 1224 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1225 } 1226 1227 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 1228 u32 me, u32 pipe, u32 q, u32 vm) 1229 { 1230 nv_grbm_select(adev, me, pipe, q, vm); 1231 } 1232 1233 1234 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 1235 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 1236 .select_se_sh = &gfx_v10_0_select_se_sh, 1237 .read_wave_data = &gfx_v10_0_read_wave_data, 1238 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 1239 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 1240 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 1241 }; 1242 1243 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 1244 { 1245 u32 gb_addr_config; 1246 1247 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 1248 1249 switch (adev->asic_type) { 1250 case CHIP_NAVI10: 1251 case CHIP_NAVI14: 1252 case CHIP_NAVI12: 1253 adev->gfx.config.max_hw_contexts = 8; 1254 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1255 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1256 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1257 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1258 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1259 break; 1260 default: 1261 BUG(); 1262 break; 1263 } 1264 1265 adev->gfx.config.gb_addr_config = gb_addr_config; 1266 1267 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1268 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1269 GB_ADDR_CONFIG, NUM_PIPES); 1270 1271 adev->gfx.config.max_tile_pipes = 1272 adev->gfx.config.gb_addr_config_fields.num_pipes; 1273 1274 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1275 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1276 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 1277 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1278 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1279 GB_ADDR_CONFIG, NUM_RB_PER_SE); 1280 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1281 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1282 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 1283 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1284 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1285 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 1286 } 1287 1288 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1289 int me, int pipe, int queue) 1290 { 1291 int r; 1292 struct amdgpu_ring *ring; 1293 unsigned int irq_type; 1294 1295 ring = &adev->gfx.gfx_ring[ring_id]; 1296 1297 ring->me = me; 1298 ring->pipe = pipe; 1299 ring->queue = queue; 1300 1301 ring->ring_obj = NULL; 1302 ring->use_doorbell = true; 1303 1304 if (!ring_id) 1305 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1306 else 1307 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1308 snprintf(ring->name, sizeof(ring->name), "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1309 1310 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1311 r = amdgpu_ring_init(adev, ring, 1024, 1312 &adev->gfx.eop_irq, irq_type); 1313 if (r) 1314 return r; 1315 return 0; 1316 } 1317 1318 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1319 int mec, int pipe, int queue) 1320 { 1321 int r; 1322 unsigned irq_type; 1323 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1324 1325 ring = &adev->gfx.compute_ring[ring_id]; 1326 1327 /* mec0 is me1 */ 1328 ring->me = mec + 1; 1329 ring->pipe = pipe; 1330 ring->queue = queue; 1331 1332 ring->ring_obj = NULL; 1333 ring->use_doorbell = true; 1334 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1335 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1336 + (ring_id * GFX10_MEC_HPD_SIZE); 1337 snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1338 1339 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1340 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1341 + ring->pipe; 1342 1343 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1344 r = amdgpu_ring_init(adev, ring, 1024, 1345 &adev->gfx.eop_irq, irq_type); 1346 if (r) 1347 return r; 1348 1349 return 0; 1350 } 1351 1352 static int gfx_v10_0_sw_init(void *handle) 1353 { 1354 int i, j, k, r, ring_id = 0; 1355 struct amdgpu_kiq *kiq; 1356 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1357 1358 switch (adev->asic_type) { 1359 case CHIP_NAVI10: 1360 case CHIP_NAVI14: 1361 case CHIP_NAVI12: 1362 adev->gfx.me.num_me = 1; 1363 adev->gfx.me.num_pipe_per_me = 1; 1364 adev->gfx.me.num_queue_per_pipe = 1; 1365 adev->gfx.mec.num_mec = 2; 1366 adev->gfx.mec.num_pipe_per_mec = 4; 1367 adev->gfx.mec.num_queue_per_pipe = 8; 1368 break; 1369 default: 1370 adev->gfx.me.num_me = 1; 1371 adev->gfx.me.num_pipe_per_me = 1; 1372 adev->gfx.me.num_queue_per_pipe = 1; 1373 adev->gfx.mec.num_mec = 1; 1374 adev->gfx.mec.num_pipe_per_mec = 4; 1375 adev->gfx.mec.num_queue_per_pipe = 8; 1376 break; 1377 } 1378 1379 /* KIQ event */ 1380 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1381 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 1382 &adev->gfx.kiq.irq); 1383 if (r) 1384 return r; 1385 1386 /* EOP Event */ 1387 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1388 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 1389 &adev->gfx.eop_irq); 1390 if (r) 1391 return r; 1392 1393 /* Privileged reg */ 1394 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 1395 &adev->gfx.priv_reg_irq); 1396 if (r) 1397 return r; 1398 1399 /* Privileged inst */ 1400 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 1401 &adev->gfx.priv_inst_irq); 1402 if (r) 1403 return r; 1404 1405 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1406 1407 gfx_v10_0_scratch_init(adev); 1408 1409 r = gfx_v10_0_me_init(adev); 1410 if (r) 1411 return r; 1412 1413 r = gfx_v10_0_rlc_init(adev); 1414 if (r) { 1415 DRM_ERROR("Failed to init rlc BOs!\n"); 1416 return r; 1417 } 1418 1419 r = gfx_v10_0_mec_init(adev); 1420 if (r) { 1421 DRM_ERROR("Failed to init MEC BOs!\n"); 1422 return r; 1423 } 1424 1425 /* set up the gfx ring */ 1426 for (i = 0; i < adev->gfx.me.num_me; i++) { 1427 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1428 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1429 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1430 continue; 1431 1432 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 1433 i, k, j); 1434 if (r) 1435 return r; 1436 ring_id++; 1437 } 1438 } 1439 } 1440 1441 ring_id = 0; 1442 /* set up the compute queues - allocate horizontally across pipes */ 1443 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1444 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1445 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1446 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1447 j)) 1448 continue; 1449 1450 r = gfx_v10_0_compute_ring_init(adev, ring_id, 1451 i, k, j); 1452 if (r) 1453 return r; 1454 1455 ring_id++; 1456 } 1457 } 1458 } 1459 1460 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 1461 if (r) { 1462 DRM_ERROR("Failed to init KIQ BOs!\n"); 1463 return r; 1464 } 1465 1466 kiq = &adev->gfx.kiq; 1467 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1468 if (r) 1469 return r; 1470 1471 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 1472 if (r) 1473 return r; 1474 1475 /* allocate visible FB for rlc auto-loading fw */ 1476 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1477 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 1478 if (r) 1479 return r; 1480 } 1481 1482 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 1483 1484 gfx_v10_0_gpu_early_init(adev); 1485 1486 return 0; 1487 } 1488 1489 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 1490 { 1491 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1492 &adev->gfx.pfp.pfp_fw_gpu_addr, 1493 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1494 } 1495 1496 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 1497 { 1498 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 1499 &adev->gfx.ce.ce_fw_gpu_addr, 1500 (void **)&adev->gfx.ce.ce_fw_ptr); 1501 } 1502 1503 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 1504 { 1505 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1506 &adev->gfx.me.me_fw_gpu_addr, 1507 (void **)&adev->gfx.me.me_fw_ptr); 1508 } 1509 1510 static int gfx_v10_0_sw_fini(void *handle) 1511 { 1512 int i; 1513 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1514 1515 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1516 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1517 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1518 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1519 1520 amdgpu_gfx_mqd_sw_fini(adev); 1521 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 1522 amdgpu_gfx_kiq_fini(adev); 1523 1524 gfx_v10_0_pfp_fini(adev); 1525 gfx_v10_0_ce_fini(adev); 1526 gfx_v10_0_me_fini(adev); 1527 gfx_v10_0_rlc_fini(adev); 1528 gfx_v10_0_mec_fini(adev); 1529 1530 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1531 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 1532 1533 gfx_v10_0_free_microcode(adev); 1534 1535 return 0; 1536 } 1537 1538 1539 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev) 1540 { 1541 /* TODO */ 1542 } 1543 1544 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1545 u32 sh_num, u32 instance) 1546 { 1547 u32 data; 1548 1549 if (instance == 0xffffffff) 1550 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1551 INSTANCE_BROADCAST_WRITES, 1); 1552 else 1553 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1554 instance); 1555 1556 if (se_num == 0xffffffff) 1557 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1558 1); 1559 else 1560 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1561 1562 if (sh_num == 0xffffffff) 1563 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1564 1); 1565 else 1566 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1567 1568 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1569 } 1570 1571 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1572 { 1573 u32 data, mask; 1574 1575 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1576 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1577 1578 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1579 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1580 1581 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1582 adev->gfx.config.max_sh_per_se); 1583 1584 return (~data) & mask; 1585 } 1586 1587 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 1588 { 1589 int i, j; 1590 u32 data; 1591 u32 active_rbs = 0; 1592 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1593 adev->gfx.config.max_sh_per_se; 1594 1595 mutex_lock(&adev->grbm_idx_mutex); 1596 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1597 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1598 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1599 data = gfx_v10_0_get_rb_active_bitmap(adev); 1600 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1601 rb_bitmap_width_per_sh); 1602 } 1603 } 1604 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1605 mutex_unlock(&adev->grbm_idx_mutex); 1606 1607 adev->gfx.config.backend_enable_mask = active_rbs; 1608 adev->gfx.config.num_rbs = hweight32(active_rbs); 1609 } 1610 1611 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 1612 { 1613 uint32_t num_sc; 1614 uint32_t enabled_rb_per_sh; 1615 uint32_t active_rb_bitmap; 1616 uint32_t num_rb_per_sc; 1617 uint32_t num_packer_per_sc; 1618 uint32_t pa_sc_tile_steering_override; 1619 1620 /* init num_sc */ 1621 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 1622 adev->gfx.config.num_sc_per_sh; 1623 /* init num_rb_per_sc */ 1624 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 1625 enabled_rb_per_sh = hweight32(active_rb_bitmap); 1626 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 1627 /* init num_packer_per_sc */ 1628 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 1629 1630 pa_sc_tile_steering_override = 0; 1631 pa_sc_tile_steering_override |= 1632 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 1633 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 1634 pa_sc_tile_steering_override |= 1635 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 1636 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 1637 pa_sc_tile_steering_override |= 1638 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 1639 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 1640 1641 return pa_sc_tile_steering_override; 1642 } 1643 1644 #define DEFAULT_SH_MEM_BASES (0x6000) 1645 #define FIRST_COMPUTE_VMID (8) 1646 #define LAST_COMPUTE_VMID (16) 1647 1648 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 1649 { 1650 int i; 1651 uint32_t sh_mem_bases; 1652 1653 /* 1654 * Configure apertures: 1655 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1656 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1657 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1658 */ 1659 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1660 1661 mutex_lock(&adev->srbm_mutex); 1662 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1663 nv_grbm_select(adev, 0, 0, 0, i); 1664 /* CP and shaders */ 1665 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1666 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1667 } 1668 nv_grbm_select(adev, 0, 0, 0, 0); 1669 mutex_unlock(&adev->srbm_mutex); 1670 1671 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1672 acccess. These should be enabled by FW for target VMIDs. */ 1673 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1674 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 1675 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 1676 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 1677 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 1678 } 1679 } 1680 1681 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 1682 { 1683 int vmid; 1684 1685 /* 1686 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1687 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1688 * the driver can enable them for graphics. VMID0 should maintain 1689 * access so that HWS firmware can save/restore entries. 1690 */ 1691 for (vmid = 1; vmid < 16; vmid++) { 1692 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 1693 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 1694 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 1695 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 1696 } 1697 } 1698 1699 1700 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 1701 { 1702 int i, j, k; 1703 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 1704 u32 tmp, wgp_active_bitmap = 0; 1705 u32 gcrd_targets_disable_tcp = 0; 1706 u32 utcl_invreq_disable = 0; 1707 /* 1708 * GCRD_TARGETS_DISABLE field contains 1709 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 1710 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 1711 */ 1712 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 1713 2 * max_wgp_per_sh + /* TCP */ 1714 max_wgp_per_sh + /* SQC */ 1715 4); /* GL1C */ 1716 /* 1717 * UTCL1_UTCL0_INVREQ_DISABLE field contains 1718 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 1719 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 1720 */ 1721 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 1722 2 * max_wgp_per_sh + /* TCP */ 1723 2 * max_wgp_per_sh + /* SQC */ 1724 4 + /* RMI */ 1725 1); /* SQG */ 1726 1727 if (adev->asic_type == CHIP_NAVI10 || 1728 adev->asic_type == CHIP_NAVI14 || 1729 adev->asic_type == CHIP_NAVI12) { 1730 mutex_lock(&adev->grbm_idx_mutex); 1731 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1732 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1733 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1734 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 1735 /* 1736 * Set corresponding TCP bits for the inactive WGPs in 1737 * GCRD_SA_TARGETS_DISABLE 1738 */ 1739 gcrd_targets_disable_tcp = 0; 1740 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 1741 utcl_invreq_disable = 0; 1742 1743 for (k = 0; k < max_wgp_per_sh; k++) { 1744 if (!(wgp_active_bitmap & (1 << k))) { 1745 gcrd_targets_disable_tcp |= 3 << (2 * k); 1746 utcl_invreq_disable |= (3 << (2 * k)) | 1747 (3 << (2 * (max_wgp_per_sh + k))); 1748 } 1749 } 1750 1751 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 1752 /* only override TCP & SQC bits */ 1753 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 1754 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 1755 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 1756 1757 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 1758 /* only override TCP bits */ 1759 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 1760 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 1761 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 1762 } 1763 } 1764 1765 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1766 mutex_unlock(&adev->grbm_idx_mutex); 1767 } 1768 } 1769 1770 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 1771 { 1772 /* TCCs are global (not instanced). */ 1773 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 1774 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 1775 1776 adev->gfx.config.tcc_disabled_mask = 1777 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1778 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1779 } 1780 1781 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 1782 { 1783 u32 tmp; 1784 int i; 1785 1786 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1787 1788 gfx_v10_0_tiling_mode_table_init(adev); 1789 1790 gfx_v10_0_setup_rb(adev); 1791 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 1792 gfx_v10_0_get_tcc_info(adev); 1793 adev->gfx.config.pa_sc_tile_steering_override = 1794 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 1795 1796 /* XXX SH_MEM regs */ 1797 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1798 mutex_lock(&adev->srbm_mutex); 1799 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1800 nv_grbm_select(adev, 0, 0, 0, i); 1801 /* CP and shaders */ 1802 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1803 if (i != 0) { 1804 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1805 (adev->gmc.private_aperture_start >> 48)); 1806 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1807 (adev->gmc.shared_aperture_start >> 48)); 1808 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 1809 } 1810 } 1811 nv_grbm_select(adev, 0, 0, 0, 0); 1812 1813 mutex_unlock(&adev->srbm_mutex); 1814 1815 gfx_v10_0_init_compute_vmid(adev); 1816 gfx_v10_0_init_gds_vmid(adev); 1817 1818 } 1819 1820 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1821 bool enable) 1822 { 1823 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 1824 1825 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1826 enable ? 1 : 0); 1827 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1828 enable ? 1 : 0); 1829 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1830 enable ? 1 : 0); 1831 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1832 enable ? 1 : 0); 1833 1834 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 1835 } 1836 1837 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 1838 { 1839 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1840 1841 /* csib */ 1842 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 1843 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1844 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 1845 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1846 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1847 1848 return 0; 1849 } 1850 1851 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 1852 { 1853 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 1854 1855 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1856 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 1857 } 1858 1859 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 1860 { 1861 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1862 udelay(50); 1863 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1864 udelay(50); 1865 } 1866 1867 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1868 bool enable) 1869 { 1870 uint32_t rlc_pg_cntl; 1871 1872 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 1873 1874 if (!enable) { 1875 /* RLC_PG_CNTL[23] = 0 (default) 1876 * RLC will wait for handshake acks with SMU 1877 * GFXOFF will be enabled 1878 * RLC_PG_CNTL[23] = 1 1879 * RLC will not issue any message to SMU 1880 * hence no handshake between SMU & RLC 1881 * GFXOFF will be disabled 1882 */ 1883 rlc_pg_cntl |= 0x800000; 1884 } else 1885 rlc_pg_cntl &= ~0x800000; 1886 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 1887 } 1888 1889 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 1890 { 1891 /* TODO: enable rlc & smu handshake until smu 1892 * and gfxoff feature works as expected */ 1893 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1894 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 1895 1896 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1897 udelay(50); 1898 } 1899 1900 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 1901 { 1902 uint32_t tmp; 1903 1904 /* enable Save Restore Machine */ 1905 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 1906 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1907 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1908 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 1909 } 1910 1911 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 1912 { 1913 const struct rlc_firmware_header_v2_0 *hdr; 1914 const __le32 *fw_data; 1915 unsigned i, fw_size; 1916 1917 if (!adev->gfx.rlc_fw) 1918 return -EINVAL; 1919 1920 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1921 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1922 1923 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1924 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1925 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1926 1927 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 1928 RLCG_UCODE_LOADING_START_ADDRESS); 1929 1930 for (i = 0; i < fw_size; i++) 1931 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 1932 le32_to_cpup(fw_data++)); 1933 1934 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1935 1936 return 0; 1937 } 1938 1939 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 1940 { 1941 int r; 1942 1943 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1944 1945 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1946 if (r) 1947 return r; 1948 1949 gfx_v10_0_init_csb(adev); 1950 1951 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1952 gfx_v10_0_rlc_enable_srm(adev); 1953 } else { 1954 if (amdgpu_sriov_vf(adev)) { 1955 gfx_v10_0_init_csb(adev); 1956 return 0; 1957 } 1958 1959 adev->gfx.rlc.funcs->stop(adev); 1960 1961 /* disable CG */ 1962 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 1963 1964 /* disable PG */ 1965 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 1966 1967 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1968 /* legacy rlc firmware loading */ 1969 r = gfx_v10_0_rlc_load_microcode(adev); 1970 if (r) 1971 return r; 1972 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1973 /* rlc backdoor autoload firmware */ 1974 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 1975 if (r) 1976 return r; 1977 } 1978 1979 gfx_v10_0_init_csb(adev); 1980 1981 adev->gfx.rlc.funcs->start(adev); 1982 1983 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1984 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1985 if (r) 1986 return r; 1987 } 1988 } 1989 return 0; 1990 } 1991 1992 static struct { 1993 FIRMWARE_ID id; 1994 unsigned int offset; 1995 unsigned int size; 1996 } rlc_autoload_info[FIRMWARE_ID_MAX]; 1997 1998 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 1999 { 2000 int ret; 2001 RLC_TABLE_OF_CONTENT *rlc_toc; 2002 2003 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 2004 AMDGPU_GEM_DOMAIN_GTT, 2005 &adev->gfx.rlc.rlc_toc_bo, 2006 &adev->gfx.rlc.rlc_toc_gpu_addr, 2007 (void **)&adev->gfx.rlc.rlc_toc_buf); 2008 if (ret) { 2009 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 2010 return ret; 2011 } 2012 2013 /* Copy toc from psp sos fw to rlc toc buffer */ 2014 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 2015 2016 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 2017 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 2018 (rlc_toc->id < FIRMWARE_ID_MAX)) { 2019 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 2020 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 2021 /* Offset needs 4KB alignment */ 2022 rlc_toc->offset = roundup2(rlc_toc->offset * 4, PAGE_SIZE); 2023 } 2024 2025 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 2026 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 2027 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 2028 2029 rlc_toc++; 2030 } 2031 2032 return 0; 2033 } 2034 2035 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 2036 { 2037 uint32_t total_size = 0; 2038 FIRMWARE_ID id; 2039 int ret; 2040 2041 ret = gfx_v10_0_parse_rlc_toc(adev); 2042 if (ret) { 2043 dev_err(adev->dev, "failed to parse rlc toc\n"); 2044 return 0; 2045 } 2046 2047 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 2048 total_size += rlc_autoload_info[id].size; 2049 2050 /* In case the offset in rlc toc ucode is aligned */ 2051 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 2052 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 2053 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 2054 2055 return total_size; 2056 } 2057 2058 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 2059 { 2060 int r; 2061 uint32_t total_size; 2062 2063 total_size = gfx_v10_0_calc_toc_total_size(adev); 2064 2065 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 2066 AMDGPU_GEM_DOMAIN_GTT, 2067 &adev->gfx.rlc.rlc_autoload_bo, 2068 &adev->gfx.rlc.rlc_autoload_gpu_addr, 2069 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 2070 if (r) { 2071 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 2072 return r; 2073 } 2074 2075 return 0; 2076 } 2077 2078 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 2079 { 2080 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 2081 &adev->gfx.rlc.rlc_toc_gpu_addr, 2082 (void **)&adev->gfx.rlc.rlc_toc_buf); 2083 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 2084 &adev->gfx.rlc.rlc_autoload_gpu_addr, 2085 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 2086 } 2087 2088 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 2089 FIRMWARE_ID id, 2090 const void *fw_data, 2091 uint32_t fw_size) 2092 { 2093 uint32_t toc_offset; 2094 uint32_t toc_fw_size; 2095 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 2096 2097 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 2098 return; 2099 2100 toc_offset = rlc_autoload_info[id].offset; 2101 toc_fw_size = rlc_autoload_info[id].size; 2102 2103 if (fw_size == 0) 2104 fw_size = toc_fw_size; 2105 2106 if (fw_size > toc_fw_size) 2107 fw_size = toc_fw_size; 2108 2109 memcpy(ptr + toc_offset, fw_data, fw_size); 2110 2111 if (fw_size < toc_fw_size) 2112 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 2113 } 2114 2115 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 2116 { 2117 void *data; 2118 uint32_t size; 2119 2120 data = adev->gfx.rlc.rlc_toc_buf; 2121 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 2122 2123 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2124 FIRMWARE_ID_RLC_TOC, 2125 data, size); 2126 } 2127 2128 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 2129 { 2130 const __le32 *fw_data; 2131 uint32_t fw_size; 2132 const struct gfx_firmware_header_v1_0 *cp_hdr; 2133 const struct rlc_firmware_header_v2_0 *rlc_hdr; 2134 2135 /* pfp ucode */ 2136 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2137 adev->gfx.pfp_fw->data; 2138 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2139 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2140 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2141 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2142 FIRMWARE_ID_CP_PFP, 2143 fw_data, fw_size); 2144 2145 /* ce ucode */ 2146 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2147 adev->gfx.ce_fw->data; 2148 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 2149 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2150 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2151 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2152 FIRMWARE_ID_CP_CE, 2153 fw_data, fw_size); 2154 2155 /* me ucode */ 2156 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2157 adev->gfx.me_fw->data; 2158 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2159 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2160 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2161 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2162 FIRMWARE_ID_CP_ME, 2163 fw_data, fw_size); 2164 2165 /* rlc ucode */ 2166 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 2167 adev->gfx.rlc_fw->data; 2168 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2169 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 2170 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 2171 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2172 FIRMWARE_ID_RLC_G_UCODE, 2173 fw_data, fw_size); 2174 2175 /* mec1 ucode */ 2176 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2177 adev->gfx.mec_fw->data; 2178 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2179 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2180 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 2181 cp_hdr->jt_size * 4; 2182 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2183 FIRMWARE_ID_CP_MEC, 2184 fw_data, fw_size); 2185 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 2186 } 2187 2188 /* Temporarily put sdma part here */ 2189 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 2190 { 2191 const __le32 *fw_data; 2192 uint32_t fw_size; 2193 const struct sdma_firmware_header_v1_0 *sdma_hdr; 2194 int i; 2195 2196 for (i = 0; i < adev->sdma.num_instances; i++) { 2197 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 2198 adev->sdma.instance[i].fw->data; 2199 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 2200 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 2201 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 2202 2203 if (i == 0) { 2204 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2205 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 2206 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2207 FIRMWARE_ID_SDMA0_JT, 2208 (uint32_t *)fw_data + 2209 sdma_hdr->jt_offset, 2210 sdma_hdr->jt_size * 4); 2211 } else if (i == 1) { 2212 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2213 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 2214 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2215 FIRMWARE_ID_SDMA1_JT, 2216 (uint32_t *)fw_data + 2217 sdma_hdr->jt_offset, 2218 sdma_hdr->jt_size * 4); 2219 } 2220 } 2221 } 2222 2223 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 2224 { 2225 uint32_t rlc_g_offset, rlc_g_size, tmp; 2226 uint64_t gpu_addr; 2227 2228 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 2229 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 2230 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 2231 2232 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 2233 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 2234 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 2235 2236 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 2237 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 2238 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 2239 2240 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 2241 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 2242 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 2243 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 2244 return -EINVAL; 2245 } 2246 2247 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 2248 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2249 DRM_ERROR("RLC ROM should halt itself\n"); 2250 return -EINVAL; 2251 } 2252 2253 return 0; 2254 } 2255 2256 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 2257 { 2258 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2259 uint32_t tmp; 2260 int i; 2261 uint64_t addr; 2262 2263 /* Trigger an invalidation of the L1 instruction caches */ 2264 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2265 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2266 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2267 2268 /* Wait for invalidation complete */ 2269 for (i = 0; i < usec_timeout; i++) { 2270 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2271 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2272 INVALIDATE_CACHE_COMPLETE)) 2273 break; 2274 udelay(1); 2275 } 2276 2277 if (i >= usec_timeout) { 2278 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2279 return -EINVAL; 2280 } 2281 2282 /* Program me ucode address into intruction cache address register */ 2283 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2284 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 2285 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2286 lower_32_bits(addr) & 0xFFFFF000); 2287 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2288 upper_32_bits(addr)); 2289 2290 return 0; 2291 } 2292 2293 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 2294 { 2295 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2296 uint32_t tmp; 2297 int i; 2298 uint64_t addr; 2299 2300 /* Trigger an invalidation of the L1 instruction caches */ 2301 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2302 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2303 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2304 2305 /* Wait for invalidation complete */ 2306 for (i = 0; i < usec_timeout; i++) { 2307 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2308 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2309 INVALIDATE_CACHE_COMPLETE)) 2310 break; 2311 udelay(1); 2312 } 2313 2314 if (i >= usec_timeout) { 2315 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2316 return -EINVAL; 2317 } 2318 2319 /* Program ce ucode address into intruction cache address register */ 2320 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2321 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 2322 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2323 lower_32_bits(addr) & 0xFFFFF000); 2324 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2325 upper_32_bits(addr)); 2326 2327 return 0; 2328 } 2329 2330 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 2331 { 2332 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2333 uint32_t tmp; 2334 int i; 2335 uint64_t addr; 2336 2337 /* Trigger an invalidation of the L1 instruction caches */ 2338 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2339 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2340 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2341 2342 /* Wait for invalidation complete */ 2343 for (i = 0; i < usec_timeout; i++) { 2344 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2345 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2346 INVALIDATE_CACHE_COMPLETE)) 2347 break; 2348 udelay(1); 2349 } 2350 2351 if (i >= usec_timeout) { 2352 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2353 return -EINVAL; 2354 } 2355 2356 /* Program pfp ucode address into intruction cache address register */ 2357 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2358 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 2359 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2360 lower_32_bits(addr) & 0xFFFFF000); 2361 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2362 upper_32_bits(addr)); 2363 2364 return 0; 2365 } 2366 2367 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 2368 { 2369 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2370 uint32_t tmp; 2371 int i; 2372 uint64_t addr; 2373 2374 /* Trigger an invalidation of the L1 instruction caches */ 2375 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2376 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2377 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2378 2379 /* Wait for invalidation complete */ 2380 for (i = 0; i < usec_timeout; i++) { 2381 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2382 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2383 INVALIDATE_CACHE_COMPLETE)) 2384 break; 2385 udelay(1); 2386 } 2387 2388 if (i >= usec_timeout) { 2389 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2390 return -EINVAL; 2391 } 2392 2393 /* Program mec1 ucode address into intruction cache address register */ 2394 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2395 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 2396 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2397 lower_32_bits(addr) & 0xFFFFF000); 2398 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2399 upper_32_bits(addr)); 2400 2401 return 0; 2402 } 2403 2404 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2405 { 2406 uint32_t cp_status; 2407 uint32_t bootload_status; 2408 int i, r; 2409 2410 for (i = 0; i < adev->usec_timeout; i++) { 2411 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 2412 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 2413 if ((cp_status == 0) && 2414 (REG_GET_FIELD(bootload_status, 2415 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2416 break; 2417 } 2418 udelay(1); 2419 } 2420 2421 if (i >= adev->usec_timeout) { 2422 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2423 return -ETIMEDOUT; 2424 } 2425 2426 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2427 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 2428 if (r) 2429 return r; 2430 2431 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 2432 if (r) 2433 return r; 2434 2435 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 2436 if (r) 2437 return r; 2438 2439 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 2440 if (r) 2441 return r; 2442 } 2443 2444 return 0; 2445 } 2446 2447 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2448 { 2449 int i; 2450 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2451 2452 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2453 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2454 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2455 if (!enable) { 2456 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2457 adev->gfx.gfx_ring[i].sched.ready = false; 2458 } 2459 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 2460 2461 for (i = 0; i < adev->usec_timeout; i++) { 2462 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 2463 break; 2464 udelay(1); 2465 } 2466 2467 if (i >= adev->usec_timeout) 2468 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2469 2470 return 0; 2471 } 2472 2473 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2474 { 2475 int r; 2476 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2477 const __le32 *fw_data; 2478 unsigned i, fw_size; 2479 uint32_t tmp; 2480 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2481 2482 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2483 adev->gfx.pfp_fw->data; 2484 2485 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2486 2487 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2488 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2489 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2490 2491 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2492 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2493 &adev->gfx.pfp.pfp_fw_obj, 2494 &adev->gfx.pfp.pfp_fw_gpu_addr, 2495 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2496 if (r) { 2497 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2498 gfx_v10_0_pfp_fini(adev); 2499 return r; 2500 } 2501 2502 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2503 2504 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2505 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2506 2507 /* Trigger an invalidation of the L1 instruction caches */ 2508 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2509 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2510 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2511 2512 /* Wait for invalidation complete */ 2513 for (i = 0; i < usec_timeout; i++) { 2514 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2515 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2516 INVALIDATE_CACHE_COMPLETE)) 2517 break; 2518 udelay(1); 2519 } 2520 2521 if (i >= usec_timeout) { 2522 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2523 return -EINVAL; 2524 } 2525 2526 if (amdgpu_emu_mode == 1) 2527 adev->nbio.funcs->hdp_flush(adev, NULL); 2528 2529 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 2530 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2531 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2532 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2533 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2534 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 2535 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2536 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 2537 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2538 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2539 2540 return 0; 2541 } 2542 2543 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 2544 { 2545 int r; 2546 const struct gfx_firmware_header_v1_0 *ce_hdr; 2547 const __le32 *fw_data; 2548 unsigned i, fw_size; 2549 uint32_t tmp; 2550 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2551 2552 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2553 adev->gfx.ce_fw->data; 2554 2555 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2556 2557 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 2558 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2559 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 2560 2561 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 2562 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2563 &adev->gfx.ce.ce_fw_obj, 2564 &adev->gfx.ce.ce_fw_gpu_addr, 2565 (void **)&adev->gfx.ce.ce_fw_ptr); 2566 if (r) { 2567 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 2568 gfx_v10_0_ce_fini(adev); 2569 return r; 2570 } 2571 2572 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 2573 2574 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 2575 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 2576 2577 /* Trigger an invalidation of the L1 instruction caches */ 2578 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2579 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2580 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2581 2582 /* Wait for invalidation complete */ 2583 for (i = 0; i < usec_timeout; i++) { 2584 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2585 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2586 INVALIDATE_CACHE_COMPLETE)) 2587 break; 2588 udelay(1); 2589 } 2590 2591 if (i >= usec_timeout) { 2592 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2593 return -EINVAL; 2594 } 2595 2596 if (amdgpu_emu_mode == 1) 2597 adev->nbio.funcs->hdp_flush(adev, NULL); 2598 2599 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 2600 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 2601 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 2602 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 2603 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2604 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2605 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 2606 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2607 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 2608 2609 return 0; 2610 } 2611 2612 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2613 { 2614 int r; 2615 const struct gfx_firmware_header_v1_0 *me_hdr; 2616 const __le32 *fw_data; 2617 unsigned i, fw_size; 2618 uint32_t tmp; 2619 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2620 2621 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2622 adev->gfx.me_fw->data; 2623 2624 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2625 2626 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2627 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2628 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2629 2630 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2631 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2632 &adev->gfx.me.me_fw_obj, 2633 &adev->gfx.me.me_fw_gpu_addr, 2634 (void **)&adev->gfx.me.me_fw_ptr); 2635 if (r) { 2636 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2637 gfx_v10_0_me_fini(adev); 2638 return r; 2639 } 2640 2641 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2642 2643 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2644 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2645 2646 /* Trigger an invalidation of the L1 instruction caches */ 2647 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2648 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2649 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2650 2651 /* Wait for invalidation complete */ 2652 for (i = 0; i < usec_timeout; i++) { 2653 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2654 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2655 INVALIDATE_CACHE_COMPLETE)) 2656 break; 2657 udelay(1); 2658 } 2659 2660 if (i >= usec_timeout) { 2661 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2662 return -EINVAL; 2663 } 2664 2665 if (amdgpu_emu_mode == 1) 2666 adev->nbio.funcs->hdp_flush(adev, NULL); 2667 2668 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 2669 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2670 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2671 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2672 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2673 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2674 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 2675 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2676 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2677 2678 return 0; 2679 } 2680 2681 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2682 { 2683 int r; 2684 2685 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2686 return -EINVAL; 2687 2688 gfx_v10_0_cp_gfx_enable(adev, false); 2689 2690 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 2691 if (r) { 2692 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2693 return r; 2694 } 2695 2696 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 2697 if (r) { 2698 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 2699 return r; 2700 } 2701 2702 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 2703 if (r) { 2704 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2705 return r; 2706 } 2707 2708 return 0; 2709 } 2710 2711 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 2712 { 2713 struct amdgpu_ring *ring; 2714 const struct cs_section_def *sect = NULL; 2715 const struct cs_extent_def *ext = NULL; 2716 int r, i; 2717 int ctx_reg_offset; 2718 2719 /* init the CP */ 2720 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 2721 adev->gfx.config.max_hw_contexts - 1); 2722 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2723 2724 gfx_v10_0_cp_gfx_enable(adev, true); 2725 2726 ring = &adev->gfx.gfx_ring[0]; 2727 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 2728 if (r) { 2729 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2730 return r; 2731 } 2732 2733 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2734 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2735 2736 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2737 amdgpu_ring_write(ring, 0x80000000); 2738 amdgpu_ring_write(ring, 0x80000000); 2739 2740 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 2741 for (ext = sect->section; ext->extent != NULL; ++ext) { 2742 if (sect->id == SECT_CONTEXT) { 2743 amdgpu_ring_write(ring, 2744 PACKET3(PACKET3_SET_CONTEXT_REG, 2745 ext->reg_count)); 2746 amdgpu_ring_write(ring, ext->reg_index - 2747 PACKET3_SET_CONTEXT_REG_START); 2748 for (i = 0; i < ext->reg_count; i++) 2749 amdgpu_ring_write(ring, ext->extent[i]); 2750 } 2751 } 2752 } 2753 2754 ctx_reg_offset = 2755 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 2756 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2757 amdgpu_ring_write(ring, ctx_reg_offset); 2758 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 2759 2760 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2761 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2762 2763 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2764 amdgpu_ring_write(ring, 0); 2765 2766 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2767 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2768 amdgpu_ring_write(ring, 0x8000); 2769 amdgpu_ring_write(ring, 0x8000); 2770 2771 amdgpu_ring_commit(ring); 2772 2773 /* submit cs packet to copy state 0 to next available state */ 2774 if (adev->gfx.num_gfx_rings > 1) { 2775 /* maximum supported gfx ring is 2 */ 2776 ring = &adev->gfx.gfx_ring[1]; 2777 r = amdgpu_ring_alloc(ring, 2); 2778 if (r) { 2779 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2780 return r; 2781 } 2782 2783 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2784 amdgpu_ring_write(ring, 0); 2785 2786 amdgpu_ring_commit(ring); 2787 } 2788 return 0; 2789 } 2790 2791 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2792 CP_PIPE_ID pipe) 2793 { 2794 u32 tmp; 2795 2796 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 2797 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2798 2799 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 2800 } 2801 2802 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2803 struct amdgpu_ring *ring) 2804 { 2805 u32 tmp; 2806 2807 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2808 if (ring->use_doorbell) { 2809 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2810 DOORBELL_OFFSET, ring->doorbell_index); 2811 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2812 DOORBELL_EN, 1); 2813 } else { 2814 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2815 DOORBELL_EN, 0); 2816 } 2817 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2818 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2819 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2820 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2821 2822 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2823 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2824 } 2825 2826 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 2827 { 2828 struct amdgpu_ring *ring; 2829 u32 tmp; 2830 u32 rb_bufsz; 2831 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2832 u32 i; 2833 2834 /* Set the write pointer delay */ 2835 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2836 2837 /* set the RB to use vmid 0 */ 2838 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2839 2840 /* Init gfx ring 0 for pipe 0 */ 2841 mutex_lock(&adev->srbm_mutex); 2842 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2843 2844 /* Set ring buffer size */ 2845 ring = &adev->gfx.gfx_ring[0]; 2846 rb_bufsz = order_base_2(ring->ring_size / 8); 2847 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2848 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2849 #ifdef __BIG_ENDIAN 2850 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2851 #endif 2852 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2853 2854 /* Initialize the ring buffer's write pointers */ 2855 ring->wptr = 0; 2856 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2857 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2858 2859 /* set the wb address wether it's enabled or not */ 2860 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2861 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2862 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2863 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2864 2865 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2866 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2867 lower_32_bits(wptr_gpu_addr)); 2868 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2869 upper_32_bits(wptr_gpu_addr)); 2870 2871 mdelay(1); 2872 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2873 2874 rb_addr = ring->gpu_addr >> 8; 2875 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2876 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2877 2878 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 2879 2880 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2881 mutex_unlock(&adev->srbm_mutex); 2882 2883 /* Init gfx ring 1 for pipe 1 */ 2884 if (adev->gfx.num_gfx_rings > 1) { 2885 mutex_lock(&adev->srbm_mutex); 2886 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 2887 /* maximum supported gfx ring is 2 */ 2888 ring = &adev->gfx.gfx_ring[1]; 2889 rb_bufsz = order_base_2(ring->ring_size / 8); 2890 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 2891 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 2892 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2893 /* Initialize the ring buffer's write pointers */ 2894 ring->wptr = 0; 2895 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2896 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 2897 /* Set the wb address wether it's enabled or not */ 2898 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2899 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2900 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2901 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2902 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2903 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2904 lower_32_bits(wptr_gpu_addr)); 2905 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2906 upper_32_bits(wptr_gpu_addr)); 2907 2908 mdelay(1); 2909 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2910 2911 rb_addr = ring->gpu_addr >> 8; 2912 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 2913 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 2914 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 2915 2916 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2917 mutex_unlock(&adev->srbm_mutex); 2918 } 2919 /* Switch to pipe 0 */ 2920 mutex_lock(&adev->srbm_mutex); 2921 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2922 mutex_unlock(&adev->srbm_mutex); 2923 2924 /* start the ring */ 2925 gfx_v10_0_cp_gfx_start(adev); 2926 2927 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2928 ring = &adev->gfx.gfx_ring[i]; 2929 ring->sched.ready = true; 2930 } 2931 2932 return 0; 2933 } 2934 2935 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2936 { 2937 int i; 2938 2939 if (enable) { 2940 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2941 } else { 2942 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2943 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 2944 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2945 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2946 adev->gfx.compute_ring[i].sched.ready = false; 2947 adev->gfx.kiq.ring.sched.ready = false; 2948 } 2949 udelay(50); 2950 } 2951 2952 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2953 { 2954 const struct gfx_firmware_header_v1_0 *mec_hdr; 2955 const __le32 *fw_data; 2956 unsigned i; 2957 u32 tmp; 2958 u32 usec_timeout = 50000; /* Wait for 50 ms */ 2959 2960 if (!adev->gfx.mec_fw) 2961 return -EINVAL; 2962 2963 gfx_v10_0_cp_compute_enable(adev, false); 2964 2965 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2966 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2967 2968 fw_data = (const __le32 *) 2969 (adev->gfx.mec_fw->data + 2970 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2971 2972 /* Trigger an invalidation of the L1 instruction caches */ 2973 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2974 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2975 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2976 2977 /* Wait for invalidation complete */ 2978 for (i = 0; i < usec_timeout; i++) { 2979 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2980 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2981 INVALIDATE_CACHE_COMPLETE)) 2982 break; 2983 udelay(1); 2984 } 2985 2986 if (i >= usec_timeout) { 2987 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2988 return -EINVAL; 2989 } 2990 2991 if (amdgpu_emu_mode == 1) 2992 adev->nbio.funcs->hdp_flush(adev, NULL); 2993 2994 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 2995 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2996 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2997 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2998 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2999 3000 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 3001 0xFFFFF000); 3002 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 3003 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 3004 3005 /* MEC1 */ 3006 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 3007 3008 for (i = 0; i < mec_hdr->jt_size; i++) 3009 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 3010 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 3011 3012 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 3013 3014 /* 3015 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 3016 * different microcode than MEC1. 3017 */ 3018 3019 return 0; 3020 } 3021 3022 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 3023 { 3024 uint32_t tmp; 3025 struct amdgpu_device *adev = ring->adev; 3026 3027 /* tell RLC which is KIQ queue */ 3028 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 3029 tmp &= 0xffffff00; 3030 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 3031 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3032 tmp |= 0x80; 3033 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 3034 } 3035 3036 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 3037 { 3038 struct amdgpu_device *adev = ring->adev; 3039 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 3040 uint64_t hqd_gpu_addr, wb_gpu_addr; 3041 uint32_t tmp; 3042 uint32_t rb_bufsz; 3043 3044 /* set up gfx hqd wptr */ 3045 mqd->cp_gfx_hqd_wptr = 0; 3046 mqd->cp_gfx_hqd_wptr_hi = 0; 3047 3048 /* set the pointer to the MQD */ 3049 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 3050 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3051 3052 /* set up mqd control */ 3053 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 3054 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 3055 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 3056 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 3057 mqd->cp_gfx_mqd_control = tmp; 3058 3059 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3060 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 3061 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3062 mqd->cp_gfx_hqd_vmid = 0; 3063 3064 /* set up default queue priority level 3065 * 0x0 = low priority, 0x1 = high priority */ 3066 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 3067 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3068 mqd->cp_gfx_hqd_queue_priority = tmp; 3069 3070 /* set up time quantum */ 3071 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 3072 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3073 mqd->cp_gfx_hqd_quantum = tmp; 3074 3075 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3076 hqd_gpu_addr = ring->gpu_addr >> 8; 3077 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3078 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3079 3080 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3081 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3082 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3083 mqd->cp_gfx_hqd_rptr_addr_hi = 3084 upper_32_bits(wb_gpu_addr) & 0xffff; 3085 3086 /* set up rb_wptr_poll addr */ 3087 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3088 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3089 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3090 3091 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3092 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 3093 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 3094 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3095 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3096 #ifdef __BIG_ENDIAN 3097 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3098 #endif 3099 mqd->cp_gfx_hqd_cntl = tmp; 3100 3101 /* set up cp_doorbell_control */ 3102 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3103 if (ring->use_doorbell) { 3104 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3105 DOORBELL_OFFSET, ring->doorbell_index); 3106 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3107 DOORBELL_EN, 1); 3108 } else 3109 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3110 DOORBELL_EN, 0); 3111 mqd->cp_rb_doorbell_control = tmp; 3112 3113 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3114 ring->wptr = 0; 3115 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 3116 3117 /* active the queue */ 3118 mqd->cp_gfx_hqd_active = 1; 3119 3120 return 0; 3121 } 3122 3123 #ifdef BRING_UP_DEBUG 3124 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3125 { 3126 struct amdgpu_device *adev = ring->adev; 3127 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 3128 3129 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3130 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3131 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3132 3133 /* set GFX_MQD_BASE */ 3134 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3135 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3136 3137 /* set GFX_MQD_CONTROL */ 3138 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3139 3140 /* set GFX_HQD_VMID to 0 */ 3141 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3142 3143 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 3144 mqd->cp_gfx_hqd_queue_priority); 3145 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3146 3147 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3148 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3149 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3150 3151 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3152 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3153 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3154 3155 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3156 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3157 3158 /* set RB_WPTR_POLL_ADDR */ 3159 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3160 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3161 3162 /* set RB_DOORBELL_CONTROL */ 3163 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3164 3165 /* active the queue */ 3166 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3167 3168 return 0; 3169 } 3170 #endif 3171 3172 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 3173 { 3174 struct amdgpu_device *adev = ring->adev; 3175 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 3176 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3177 3178 if (!adev->in_gpu_reset && !adev->in_suspend) { 3179 memset((void *)mqd, 0, sizeof(*mqd)); 3180 mutex_lock(&adev->srbm_mutex); 3181 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3182 gfx_v10_0_gfx_mqd_init(ring); 3183 #ifdef BRING_UP_DEBUG 3184 gfx_v10_0_gfx_queue_init_register(ring); 3185 #endif 3186 nv_grbm_select(adev, 0, 0, 0, 0); 3187 mutex_unlock(&adev->srbm_mutex); 3188 if (adev->gfx.me.mqd_backup[mqd_idx]) 3189 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3190 } else if (adev->in_gpu_reset) { 3191 /* reset mqd with the backup copy */ 3192 if (adev->gfx.me.mqd_backup[mqd_idx]) 3193 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3194 /* reset the ring */ 3195 ring->wptr = 0; 3196 adev->wb.wb[ring->wptr_offs] = 0; 3197 amdgpu_ring_clear_ring(ring); 3198 #ifdef BRING_UP_DEBUG 3199 mutex_lock(&adev->srbm_mutex); 3200 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3201 gfx_v10_0_gfx_queue_init_register(ring); 3202 nv_grbm_select(adev, 0, 0, 0, 0); 3203 mutex_unlock(&adev->srbm_mutex); 3204 #endif 3205 } else { 3206 amdgpu_ring_clear_ring(ring); 3207 } 3208 3209 return 0; 3210 } 3211 3212 #ifndef BRING_UP_DEBUG 3213 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 3214 { 3215 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3216 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3217 int r, i; 3218 3219 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3220 return -EINVAL; 3221 3222 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3223 adev->gfx.num_gfx_rings); 3224 if (r) { 3225 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3226 return r; 3227 } 3228 3229 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3230 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3231 3232 return amdgpu_ring_test_helper(kiq_ring); 3233 } 3234 #endif 3235 3236 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3237 { 3238 int r, i; 3239 struct amdgpu_ring *ring; 3240 3241 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3242 ring = &adev->gfx.gfx_ring[i]; 3243 3244 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3245 if (unlikely(r != 0)) 3246 goto done; 3247 3248 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3249 if (!r) { 3250 r = gfx_v10_0_gfx_init_queue(ring); 3251 amdgpu_bo_kunmap(ring->mqd_obj); 3252 ring->mqd_ptr = NULL; 3253 } 3254 amdgpu_bo_unreserve(ring->mqd_obj); 3255 if (r) 3256 goto done; 3257 } 3258 #ifndef BRING_UP_DEBUG 3259 r = gfx_v10_0_kiq_enable_kgq(adev); 3260 if (r) 3261 goto done; 3262 #endif 3263 r = gfx_v10_0_cp_gfx_start(adev); 3264 if (r) 3265 goto done; 3266 3267 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3268 ring = &adev->gfx.gfx_ring[i]; 3269 ring->sched.ready = true; 3270 } 3271 done: 3272 return r; 3273 } 3274 3275 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd) 3276 { 3277 struct amdgpu_device *adev = ring->adev; 3278 3279 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 3280 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) { 3281 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; 3282 ring->has_high_prio = true; 3283 mqd->cp_hqd_queue_priority = 3284 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; 3285 } else { 3286 ring->has_high_prio = false; 3287 } 3288 } 3289 } 3290 3291 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 3292 { 3293 struct amdgpu_device *adev = ring->adev; 3294 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3295 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3296 uint32_t tmp; 3297 3298 mqd->header = 0xC0310800; 3299 mqd->compute_pipelinestat_enable = 0x00000001; 3300 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3301 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3302 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3303 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3304 mqd->compute_misc_reserved = 0x00000003; 3305 3306 eop_base_addr = ring->eop_gpu_addr >> 8; 3307 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3308 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3309 3310 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3311 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3312 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3313 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 3314 3315 mqd->cp_hqd_eop_control = tmp; 3316 3317 /* enable doorbell? */ 3318 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3319 3320 if (ring->use_doorbell) { 3321 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3322 DOORBELL_OFFSET, ring->doorbell_index); 3323 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3324 DOORBELL_EN, 1); 3325 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3326 DOORBELL_SOURCE, 0); 3327 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3328 DOORBELL_HIT, 0); 3329 } else { 3330 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3331 DOORBELL_EN, 0); 3332 } 3333 3334 mqd->cp_hqd_pq_doorbell_control = tmp; 3335 3336 /* disable the queue if it's active */ 3337 ring->wptr = 0; 3338 mqd->cp_hqd_dequeue_request = 0; 3339 mqd->cp_hqd_pq_rptr = 0; 3340 mqd->cp_hqd_pq_wptr_lo = 0; 3341 mqd->cp_hqd_pq_wptr_hi = 0; 3342 3343 /* set the pointer to the MQD */ 3344 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3345 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3346 3347 /* set MQD vmid to 0 */ 3348 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3349 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3350 mqd->cp_mqd_control = tmp; 3351 3352 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3353 hqd_gpu_addr = ring->gpu_addr >> 8; 3354 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3355 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3356 3357 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3358 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3359 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3360 (order_base_2(ring->ring_size / 4) - 1)); 3361 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3362 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3363 #ifdef __BIG_ENDIAN 3364 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3365 #endif 3366 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3367 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3368 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3369 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3370 mqd->cp_hqd_pq_control = tmp; 3371 3372 /* set the wb address whether it's enabled or not */ 3373 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3374 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3375 mqd->cp_hqd_pq_rptr_report_addr_hi = 3376 upper_32_bits(wb_gpu_addr) & 0xffff; 3377 3378 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3379 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3380 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3381 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3382 3383 tmp = 0; 3384 /* enable the doorbell if requested */ 3385 if (ring->use_doorbell) { 3386 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3387 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3388 DOORBELL_OFFSET, ring->doorbell_index); 3389 3390 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3391 DOORBELL_EN, 1); 3392 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3393 DOORBELL_SOURCE, 0); 3394 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3395 DOORBELL_HIT, 0); 3396 } 3397 3398 mqd->cp_hqd_pq_doorbell_control = tmp; 3399 3400 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3401 ring->wptr = 0; 3402 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3403 3404 /* set the vmid for the queue */ 3405 mqd->cp_hqd_vmid = 0; 3406 3407 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3408 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3409 mqd->cp_hqd_persistent_state = tmp; 3410 3411 /* set MIN_IB_AVAIL_SIZE */ 3412 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3413 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3414 mqd->cp_hqd_ib_control = tmp; 3415 3416 /* set static priority for a compute queue/ring */ 3417 gfx_v10_0_compute_mqd_set_priority(ring, mqd); 3418 3419 /* map_queues packet doesn't need activate the queue, 3420 * so only kiq need set this field. 3421 */ 3422 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 3423 mqd->cp_hqd_active = 1; 3424 3425 return 0; 3426 } 3427 3428 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 3429 { 3430 struct amdgpu_device *adev = ring->adev; 3431 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3432 int j; 3433 3434 /* disable wptr polling */ 3435 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3436 3437 /* write the EOP addr */ 3438 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3439 mqd->cp_hqd_eop_base_addr_lo); 3440 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3441 mqd->cp_hqd_eop_base_addr_hi); 3442 3443 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3444 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 3445 mqd->cp_hqd_eop_control); 3446 3447 /* enable doorbell? */ 3448 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3449 mqd->cp_hqd_pq_doorbell_control); 3450 3451 /* disable the queue if it's active */ 3452 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3453 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3454 for (j = 0; j < adev->usec_timeout; j++) { 3455 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3456 break; 3457 udelay(1); 3458 } 3459 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3460 mqd->cp_hqd_dequeue_request); 3461 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 3462 mqd->cp_hqd_pq_rptr); 3463 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3464 mqd->cp_hqd_pq_wptr_lo); 3465 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3466 mqd->cp_hqd_pq_wptr_hi); 3467 } 3468 3469 /* set the pointer to the MQD */ 3470 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 3471 mqd->cp_mqd_base_addr_lo); 3472 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3473 mqd->cp_mqd_base_addr_hi); 3474 3475 /* set MQD vmid to 0 */ 3476 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 3477 mqd->cp_mqd_control); 3478 3479 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3480 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 3481 mqd->cp_hqd_pq_base_lo); 3482 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 3483 mqd->cp_hqd_pq_base_hi); 3484 3485 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3486 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 3487 mqd->cp_hqd_pq_control); 3488 3489 /* set the wb address whether it's enabled or not */ 3490 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3491 mqd->cp_hqd_pq_rptr_report_addr_lo); 3492 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3493 mqd->cp_hqd_pq_rptr_report_addr_hi); 3494 3495 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3496 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3497 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3498 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3499 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3500 3501 /* enable the doorbell if requested */ 3502 if (ring->use_doorbell) { 3503 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3504 (adev->doorbell_index.kiq * 2) << 2); 3505 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3506 (adev->doorbell_index.userqueue_end * 2) << 2); 3507 } 3508 3509 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3510 mqd->cp_hqd_pq_doorbell_control); 3511 3512 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3513 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3514 mqd->cp_hqd_pq_wptr_lo); 3515 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3516 mqd->cp_hqd_pq_wptr_hi); 3517 3518 /* set the vmid for the queue */ 3519 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3520 3521 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3522 mqd->cp_hqd_persistent_state); 3523 3524 /* activate the queue */ 3525 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 3526 mqd->cp_hqd_active); 3527 3528 if (ring->use_doorbell) 3529 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3530 3531 return 0; 3532 } 3533 3534 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 3535 { 3536 struct amdgpu_device *adev = ring->adev; 3537 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3538 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3539 3540 gfx_v10_0_kiq_setting(ring); 3541 3542 if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3543 /* reset MQD to a clean status */ 3544 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3545 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3546 3547 /* reset ring buffer */ 3548 ring->wptr = 0; 3549 amdgpu_ring_clear_ring(ring); 3550 3551 mutex_lock(&adev->srbm_mutex); 3552 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3553 gfx_v10_0_kiq_init_register(ring); 3554 nv_grbm_select(adev, 0, 0, 0, 0); 3555 mutex_unlock(&adev->srbm_mutex); 3556 } else { 3557 memset((void *)mqd, 0, sizeof(*mqd)); 3558 mutex_lock(&adev->srbm_mutex); 3559 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3560 gfx_v10_0_compute_mqd_init(ring); 3561 gfx_v10_0_kiq_init_register(ring); 3562 nv_grbm_select(adev, 0, 0, 0, 0); 3563 mutex_unlock(&adev->srbm_mutex); 3564 3565 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3566 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3567 } 3568 3569 return 0; 3570 } 3571 3572 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 3573 { 3574 struct amdgpu_device *adev = ring->adev; 3575 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3576 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3577 3578 if (!adev->in_gpu_reset && !adev->in_suspend) { 3579 memset((void *)mqd, 0, sizeof(*mqd)); 3580 mutex_lock(&adev->srbm_mutex); 3581 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3582 gfx_v10_0_compute_mqd_init(ring); 3583 nv_grbm_select(adev, 0, 0, 0, 0); 3584 mutex_unlock(&adev->srbm_mutex); 3585 3586 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3587 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3588 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3589 /* reset MQD to a clean status */ 3590 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3591 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3592 3593 /* reset ring buffer */ 3594 ring->wptr = 0; 3595 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 3596 amdgpu_ring_clear_ring(ring); 3597 } else { 3598 amdgpu_ring_clear_ring(ring); 3599 } 3600 3601 return 0; 3602 } 3603 3604 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 3605 { 3606 struct amdgpu_ring *ring; 3607 int r; 3608 3609 ring = &adev->gfx.kiq.ring; 3610 3611 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3612 if (unlikely(r != 0)) 3613 return r; 3614 3615 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3616 if (unlikely(r != 0)) 3617 return r; 3618 3619 gfx_v10_0_kiq_init_queue(ring); 3620 amdgpu_bo_kunmap(ring->mqd_obj); 3621 ring->mqd_ptr = NULL; 3622 amdgpu_bo_unreserve(ring->mqd_obj); 3623 ring->sched.ready = true; 3624 return 0; 3625 } 3626 3627 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 3628 { 3629 struct amdgpu_ring *ring = NULL; 3630 int r = 0, i; 3631 3632 gfx_v10_0_cp_compute_enable(adev, true); 3633 3634 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3635 ring = &adev->gfx.compute_ring[i]; 3636 3637 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3638 if (unlikely(r != 0)) 3639 goto done; 3640 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3641 if (!r) { 3642 r = gfx_v10_0_kcq_init_queue(ring); 3643 amdgpu_bo_kunmap(ring->mqd_obj); 3644 ring->mqd_ptr = NULL; 3645 } 3646 amdgpu_bo_unreserve(ring->mqd_obj); 3647 if (r) 3648 goto done; 3649 } 3650 3651 r = amdgpu_gfx_enable_kcq(adev); 3652 done: 3653 return r; 3654 } 3655 3656 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 3657 { 3658 int r, i; 3659 struct amdgpu_ring *ring; 3660 3661 if (!(adev->flags & AMD_IS_APU)) 3662 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3663 3664 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3665 /* legacy firmware loading */ 3666 r = gfx_v10_0_cp_gfx_load_microcode(adev); 3667 if (r) 3668 return r; 3669 3670 r = gfx_v10_0_cp_compute_load_microcode(adev); 3671 if (r) 3672 return r; 3673 } 3674 3675 r = gfx_v10_0_kiq_resume(adev); 3676 if (r) 3677 return r; 3678 3679 r = gfx_v10_0_kcq_resume(adev); 3680 if (r) 3681 return r; 3682 3683 if (!amdgpu_async_gfx_ring) { 3684 r = gfx_v10_0_cp_gfx_resume(adev); 3685 if (r) 3686 return r; 3687 } else { 3688 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 3689 if (r) 3690 return r; 3691 } 3692 3693 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3694 ring = &adev->gfx.gfx_ring[i]; 3695 r = amdgpu_ring_test_helper(ring); 3696 if (r) 3697 return r; 3698 } 3699 3700 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3701 ring = &adev->gfx.compute_ring[i]; 3702 r = amdgpu_ring_test_helper(ring); 3703 if (r) 3704 return r; 3705 } 3706 3707 return 0; 3708 } 3709 3710 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 3711 { 3712 gfx_v10_0_cp_gfx_enable(adev, enable); 3713 gfx_v10_0_cp_compute_enable(adev, enable); 3714 } 3715 3716 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 3717 { 3718 uint32_t data, pattern = 0xDEADBEEF; 3719 3720 /* check if mmVGT_ESGS_RING_SIZE_UMD 3721 * has been remapped to mmVGT_ESGS_RING_SIZE */ 3722 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 3723 3724 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 3725 3726 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 3727 3728 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 3729 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 3730 return true; 3731 } else { 3732 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 3733 return false; 3734 } 3735 } 3736 3737 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 3738 { 3739 uint32_t data; 3740 3741 /* initialize cam_index to 0 3742 * index will auto-inc after each data writting */ 3743 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 3744 3745 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 3746 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 3747 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3748 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 3749 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3750 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3751 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3752 3753 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 3754 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 3755 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3756 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 3757 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3758 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3759 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3760 3761 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 3762 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 3763 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3764 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 3765 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3766 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3767 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3768 3769 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 3770 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 3771 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3772 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 3773 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3774 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3775 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3776 3777 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 3778 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 3779 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3780 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 3781 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3782 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3783 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3784 3785 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 3786 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 3787 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3788 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 3789 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3790 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3791 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3792 3793 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 3794 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 3795 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3796 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 3797 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3798 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3799 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3800 } 3801 3802 static int gfx_v10_0_hw_init(void *handle) 3803 { 3804 int r; 3805 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3806 3807 if (!amdgpu_emu_mode) 3808 gfx_v10_0_init_golden_registers(adev); 3809 3810 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3811 /** 3812 * For gfx 10, rlc firmware loading relies on smu firmware is 3813 * loaded firstly, so in direct type, it has to load smc ucode 3814 * here before rlc. 3815 */ 3816 r = smu_load_microcode(&adev->smu); 3817 if (r) 3818 return r; 3819 3820 r = smu_check_fw_status(&adev->smu); 3821 if (r) { 3822 pr_err("SMC firmware status is not correct\n"); 3823 return r; 3824 } 3825 } 3826 3827 /* if GRBM CAM not remapped, set up the remapping */ 3828 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 3829 gfx_v10_0_setup_grbm_cam_remapping(adev); 3830 3831 gfx_v10_0_constants_init(adev); 3832 3833 r = gfx_v10_0_rlc_resume(adev); 3834 if (r) 3835 return r; 3836 3837 /* 3838 * init golden registers and rlc resume may override some registers, 3839 * reconfig them here 3840 */ 3841 gfx_v10_0_tcp_harvest(adev); 3842 3843 r = gfx_v10_0_cp_resume(adev); 3844 if (r) 3845 return r; 3846 3847 return r; 3848 } 3849 3850 #ifndef BRING_UP_DEBUG 3851 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 3852 { 3853 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3854 struct amdgpu_ring *kiq_ring = &kiq->ring; 3855 int i; 3856 3857 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3858 return -EINVAL; 3859 3860 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 3861 adev->gfx.num_gfx_rings)) 3862 return -ENOMEM; 3863 3864 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3865 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 3866 PREEMPT_QUEUES, 0, 0); 3867 3868 return amdgpu_ring_test_helper(kiq_ring); 3869 } 3870 #endif 3871 3872 static int gfx_v10_0_hw_fini(void *handle) 3873 { 3874 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3875 int r; 3876 3877 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3878 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3879 #ifndef BRING_UP_DEBUG 3880 if (amdgpu_async_gfx_ring) { 3881 r = gfx_v10_0_kiq_disable_kgq(adev); 3882 if (r) 3883 DRM_ERROR("KGQ disable failed\n"); 3884 } 3885 #endif 3886 if (amdgpu_gfx_disable_kcq(adev)) 3887 DRM_ERROR("KCQ disable failed\n"); 3888 if (amdgpu_sriov_vf(adev)) { 3889 gfx_v10_0_cp_gfx_enable(adev, false); 3890 return 0; 3891 } 3892 gfx_v10_0_cp_enable(adev, false); 3893 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3894 3895 return 0; 3896 } 3897 3898 static int gfx_v10_0_suspend(void *handle) 3899 { 3900 return gfx_v10_0_hw_fini(handle); 3901 } 3902 3903 static int gfx_v10_0_resume(void *handle) 3904 { 3905 return gfx_v10_0_hw_init(handle); 3906 } 3907 3908 static bool gfx_v10_0_is_idle(void *handle) 3909 { 3910 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3911 3912 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3913 GRBM_STATUS, GUI_ACTIVE)) 3914 return false; 3915 else 3916 return true; 3917 } 3918 3919 static int gfx_v10_0_wait_for_idle(void *handle) 3920 { 3921 unsigned i; 3922 u32 tmp; 3923 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3924 3925 for (i = 0; i < adev->usec_timeout; i++) { 3926 /* read MC_STATUS */ 3927 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 3928 GRBM_STATUS__GUI_ACTIVE_MASK; 3929 3930 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3931 return 0; 3932 udelay(1); 3933 } 3934 return -ETIMEDOUT; 3935 } 3936 3937 static int gfx_v10_0_soft_reset(void *handle) 3938 { 3939 u32 grbm_soft_reset = 0; 3940 u32 tmp; 3941 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3942 3943 /* GRBM_STATUS */ 3944 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3945 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3946 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3947 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 3948 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 3949 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK 3950 | GRBM_STATUS__BCI_BUSY_MASK)) { 3951 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3952 GRBM_SOFT_RESET, SOFT_RESET_CP, 3953 1); 3954 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3955 GRBM_SOFT_RESET, SOFT_RESET_GFX, 3956 1); 3957 } 3958 3959 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3960 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3961 GRBM_SOFT_RESET, SOFT_RESET_CP, 3962 1); 3963 } 3964 3965 /* GRBM_STATUS2 */ 3966 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3967 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3968 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3969 GRBM_SOFT_RESET, SOFT_RESET_RLC, 3970 1); 3971 3972 if (grbm_soft_reset) { 3973 /* stop the rlc */ 3974 gfx_v10_0_rlc_stop(adev); 3975 3976 /* Disable GFX parsing/prefetching */ 3977 gfx_v10_0_cp_gfx_enable(adev, false); 3978 3979 /* Disable MEC parsing/prefetching */ 3980 gfx_v10_0_cp_compute_enable(adev, false); 3981 3982 if (grbm_soft_reset) { 3983 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3984 tmp |= grbm_soft_reset; 3985 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3986 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3987 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3988 3989 udelay(50); 3990 3991 tmp &= ~grbm_soft_reset; 3992 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3993 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3994 } 3995 3996 /* Wait a little for things to settle down */ 3997 udelay(50); 3998 } 3999 return 0; 4000 } 4001 4002 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 4003 { 4004 uint64_t clock; 4005 4006 amdgpu_gfx_off_ctrl(adev, false); 4007 mutex_lock(&adev->gfx.gpu_clock_mutex); 4008 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) | 4009 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL); 4010 mutex_unlock(&adev->gfx.gpu_clock_mutex); 4011 amdgpu_gfx_off_ctrl(adev, true); 4012 return clock; 4013 } 4014 4015 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 4016 uint32_t vmid, 4017 uint32_t gds_base, uint32_t gds_size, 4018 uint32_t gws_base, uint32_t gws_size, 4019 uint32_t oa_base, uint32_t oa_size) 4020 { 4021 struct amdgpu_device *adev = ring->adev; 4022 4023 /* GDS Base */ 4024 gfx_v10_0_write_data_to_reg(ring, 0, false, 4025 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 4026 gds_base); 4027 4028 /* GDS Size */ 4029 gfx_v10_0_write_data_to_reg(ring, 0, false, 4030 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 4031 gds_size); 4032 4033 /* GWS */ 4034 gfx_v10_0_write_data_to_reg(ring, 0, false, 4035 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 4036 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 4037 4038 /* OA */ 4039 gfx_v10_0_write_data_to_reg(ring, 0, false, 4040 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 4041 (1 << (oa_size + oa_base)) - (1 << oa_base)); 4042 } 4043 4044 static int gfx_v10_0_early_init(void *handle) 4045 { 4046 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4047 4048 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 4049 4050 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 4051 4052 gfx_v10_0_set_kiq_pm4_funcs(adev); 4053 gfx_v10_0_set_ring_funcs(adev); 4054 gfx_v10_0_set_irq_funcs(adev); 4055 gfx_v10_0_set_gds_init(adev); 4056 gfx_v10_0_set_rlc_funcs(adev); 4057 4058 return 0; 4059 } 4060 4061 static int gfx_v10_0_late_init(void *handle) 4062 { 4063 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4064 int r; 4065 4066 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 4067 if (r) 4068 return r; 4069 4070 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 4071 if (r) 4072 return r; 4073 4074 return 0; 4075 } 4076 4077 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 4078 { 4079 uint32_t rlc_cntl; 4080 4081 /* if RLC is not enabled, do nothing */ 4082 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4083 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4084 } 4085 4086 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 4087 { 4088 uint32_t data; 4089 unsigned i; 4090 4091 data = RLC_SAFE_MODE__CMD_MASK; 4092 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4093 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4094 4095 /* wait for RLC_SAFE_MODE */ 4096 for (i = 0; i < adev->usec_timeout; i++) { 4097 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4098 break; 4099 udelay(1); 4100 } 4101 } 4102 4103 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 4104 { 4105 uint32_t data; 4106 4107 data = RLC_SAFE_MODE__CMD_MASK; 4108 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4109 } 4110 4111 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4112 bool enable) 4113 { 4114 uint32_t data, def; 4115 4116 /* It is disabled by HW by default */ 4117 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4118 /* 0 - Disable some blocks' MGCG */ 4119 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 4120 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 4121 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 4122 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 4123 4124 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4125 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4126 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4127 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4128 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4129 4130 /* only for Vega10 & Raven1 */ 4131 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4132 4133 if (def != data) 4134 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4135 4136 /* MGLS is a global flag to control all MGLS in GFX */ 4137 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4138 /* 2 - RLC memory Light sleep */ 4139 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4140 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4141 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4142 if (def != data) 4143 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4144 } 4145 /* 3 - CP memory Light sleep */ 4146 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4147 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4148 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4149 if (def != data) 4150 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4151 } 4152 } 4153 } else { 4154 /* 1 - MGCG_OVERRIDE */ 4155 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4156 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4157 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4158 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4159 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4160 if (def != data) 4161 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4162 4163 /* 2 - disable MGLS in CP */ 4164 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4165 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4166 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4167 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4168 } 4169 4170 /* 3 - disable MGLS in RLC */ 4171 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4172 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4173 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4174 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4175 } 4176 4177 } 4178 } 4179 4180 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 4181 bool enable) 4182 { 4183 uint32_t data, def; 4184 4185 /* Enable 3D CGCG/CGLS */ 4186 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 4187 /* write cmd to clear cgcg/cgls ov */ 4188 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4189 /* unset CGCG override */ 4190 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4191 /* update CGCG and CGLS override bits */ 4192 if (def != data) 4193 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4194 /* enable 3Dcgcg FSM(0x0000363f) */ 4195 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4196 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4197 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4198 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4199 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4200 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4201 if (def != data) 4202 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4203 4204 /* set IDLE_POLL_COUNT(0x00900100) */ 4205 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4206 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4207 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4208 if (def != data) 4209 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4210 } else { 4211 /* Disable CGCG/CGLS */ 4212 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4213 /* disable cgcg, cgls should be disabled */ 4214 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4215 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4216 /* disable cgcg and cgls in FSM */ 4217 if (def != data) 4218 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4219 } 4220 } 4221 4222 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4223 bool enable) 4224 { 4225 uint32_t def, data; 4226 4227 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4228 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4229 /* unset CGCG override */ 4230 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4231 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4232 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4233 else 4234 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4235 /* update CGCG and CGLS override bits */ 4236 if (def != data) 4237 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4238 4239 /* enable cgcg FSM(0x0000363F) */ 4240 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4241 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4242 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4243 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4244 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4245 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4246 if (def != data) 4247 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4248 4249 /* set IDLE_POLL_COUNT(0x00900100) */ 4250 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4251 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4252 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4253 if (def != data) 4254 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4255 } else { 4256 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4257 /* reset CGCG/CGLS bits */ 4258 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4259 /* disable cgcg and cgls in FSM */ 4260 if (def != data) 4261 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4262 } 4263 } 4264 4265 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4266 bool enable) 4267 { 4268 amdgpu_gfx_rlc_enter_safe_mode(adev); 4269 4270 if (enable) { 4271 /* CGCG/CGLS should be enabled after MGCG/MGLS 4272 * === MGCG + MGLS === 4273 */ 4274 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4275 /* === CGCG /CGLS for GFX 3D Only === */ 4276 gfx_v10_0_update_3d_clock_gating(adev, enable); 4277 /* === CGCG + CGLS === */ 4278 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4279 } else { 4280 /* CGCG/CGLS should be disabled before MGCG/MGLS 4281 * === CGCG + CGLS === 4282 */ 4283 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4284 /* === CGCG /CGLS for GFX 3D Only === */ 4285 gfx_v10_0_update_3d_clock_gating(adev, enable); 4286 /* === MGCG + MGLS === */ 4287 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4288 } 4289 4290 if (adev->cg_flags & 4291 (AMD_CG_SUPPORT_GFX_MGCG | 4292 AMD_CG_SUPPORT_GFX_CGLS | 4293 AMD_CG_SUPPORT_GFX_CGCG | 4294 AMD_CG_SUPPORT_GFX_CGLS | 4295 AMD_CG_SUPPORT_GFX_3D_CGCG | 4296 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4297 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 4298 4299 amdgpu_gfx_rlc_exit_safe_mode(adev); 4300 4301 return 0; 4302 } 4303 4304 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 4305 { 4306 u32 data; 4307 4308 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 4309 4310 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4311 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4312 4313 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 4314 } 4315 4316 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 4317 uint32_t offset, 4318 struct soc15_reg_rlcg *entries, int arr_size) 4319 { 4320 int i; 4321 uint32_t reg; 4322 4323 if (!entries) 4324 return false; 4325 4326 for (i = 0; i < arr_size; i++) { 4327 const struct soc15_reg_rlcg *entry; 4328 4329 entry = &entries[i]; 4330 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 4331 if (offset == reg) 4332 return true; 4333 } 4334 4335 return false; 4336 } 4337 4338 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 4339 { 4340 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 4341 } 4342 4343 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 4344 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 4345 .set_safe_mode = gfx_v10_0_set_safe_mode, 4346 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 4347 .init = gfx_v10_0_rlc_init, 4348 .get_csb_size = gfx_v10_0_get_csb_size, 4349 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 4350 .resume = gfx_v10_0_rlc_resume, 4351 .stop = gfx_v10_0_rlc_stop, 4352 .reset = gfx_v10_0_rlc_reset, 4353 .start = gfx_v10_0_rlc_start, 4354 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 4355 .rlcg_wreg = gfx_v10_rlcg_wreg, 4356 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 4357 }; 4358 4359 static int gfx_v10_0_set_powergating_state(void *handle, 4360 enum amd_powergating_state state) 4361 { 4362 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4363 bool enable = (state == AMD_PG_STATE_GATE); 4364 switch (adev->asic_type) { 4365 case CHIP_NAVI10: 4366 case CHIP_NAVI14: 4367 amdgpu_gfx_off_ctrl(adev, enable); 4368 break; 4369 default: 4370 break; 4371 } 4372 return 0; 4373 } 4374 4375 static int gfx_v10_0_set_clockgating_state(void *handle, 4376 enum amd_clockgating_state state) 4377 { 4378 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4379 4380 switch (adev->asic_type) { 4381 case CHIP_NAVI10: 4382 case CHIP_NAVI14: 4383 case CHIP_NAVI12: 4384 gfx_v10_0_update_gfx_clock_gating(adev, 4385 state == AMD_CG_STATE_GATE); 4386 break; 4387 default: 4388 break; 4389 } 4390 return 0; 4391 } 4392 4393 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 4394 { 4395 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4396 int data; 4397 4398 /* AMD_CG_SUPPORT_GFX_MGCG */ 4399 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4400 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4401 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4402 4403 /* AMD_CG_SUPPORT_GFX_CGCG */ 4404 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4405 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4406 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4407 4408 /* AMD_CG_SUPPORT_GFX_CGLS */ 4409 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4410 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4411 4412 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 4413 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4414 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 4415 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 4416 4417 /* AMD_CG_SUPPORT_GFX_CP_LS */ 4418 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4419 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 4420 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 4421 4422 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4423 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4424 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4425 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4426 4427 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4428 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4429 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4430 } 4431 4432 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4433 { 4434 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 4435 } 4436 4437 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4438 { 4439 struct amdgpu_device *adev = ring->adev; 4440 u64 wptr; 4441 4442 /* XXX check if swapping is necessary on BE */ 4443 if (ring->use_doorbell) { 4444 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 4445 } else { 4446 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 4447 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 4448 } 4449 4450 return wptr; 4451 } 4452 4453 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4454 { 4455 struct amdgpu_device *adev = ring->adev; 4456 4457 if (ring->use_doorbell) { 4458 /* XXX check if swapping is necessary on BE */ 4459 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4460 WDOORBELL64(ring->doorbell_index, ring->wptr); 4461 } else { 4462 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 4463 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 4464 } 4465 } 4466 4467 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4468 { 4469 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 4470 } 4471 4472 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4473 { 4474 u64 wptr; 4475 4476 /* XXX check if swapping is necessary on BE */ 4477 if (ring->use_doorbell) 4478 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 4479 else 4480 BUG(); 4481 return wptr; 4482 } 4483 4484 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4485 { 4486 struct amdgpu_device *adev = ring->adev; 4487 4488 /* XXX check if swapping is necessary on BE */ 4489 if (ring->use_doorbell) { 4490 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4491 WDOORBELL64(ring->doorbell_index, ring->wptr); 4492 } else { 4493 BUG(); /* only DOORBELL method supported on gfx10 now */ 4494 } 4495 } 4496 4497 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4498 { 4499 struct amdgpu_device *adev = ring->adev; 4500 u32 ref_and_mask, reg_mem_engine; 4501 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4502 4503 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4504 switch (ring->me) { 4505 case 1: 4506 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4507 break; 4508 case 2: 4509 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4510 break; 4511 default: 4512 return; 4513 } 4514 reg_mem_engine = 0; 4515 } else { 4516 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4517 reg_mem_engine = 1; /* pfp */ 4518 } 4519 4520 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4521 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4522 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4523 ref_and_mask, ref_and_mask, 0x20); 4524 } 4525 4526 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4527 struct amdgpu_job *job, 4528 struct amdgpu_ib *ib, 4529 uint32_t flags) 4530 { 4531 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4532 u32 header, control = 0; 4533 4534 if (ib->flags & AMDGPU_IB_FLAG_CE) 4535 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 4536 else 4537 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4538 4539 control |= ib->length_dw | (vmid << 24); 4540 4541 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 4542 control |= INDIRECT_BUFFER_PRE_ENB(1); 4543 4544 if (flags & AMDGPU_IB_PREEMPTED) 4545 control |= INDIRECT_BUFFER_PRE_RESUME(1); 4546 4547 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 4548 gfx_v10_0_ring_emit_de_meta(ring, 4549 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 4550 } 4551 4552 amdgpu_ring_write(ring, header); 4553 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4554 amdgpu_ring_write(ring, 4555 #ifdef __BIG_ENDIAN 4556 (2 << 0) | 4557 #endif 4558 lower_32_bits(ib->gpu_addr)); 4559 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4560 amdgpu_ring_write(ring, control); 4561 } 4562 4563 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4564 struct amdgpu_job *job, 4565 struct amdgpu_ib *ib, 4566 uint32_t flags) 4567 { 4568 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4569 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4570 4571 /* Currently, there is a high possibility to get wave ID mismatch 4572 * between ME and GDS, leading to a hw deadlock, because ME generates 4573 * different wave IDs than the GDS expects. This situation happens 4574 * randomly when at least 5 compute pipes use GDS ordered append. 4575 * The wave IDs generated by ME are also wrong after suspend/resume. 4576 * Those are probably bugs somewhere else in the kernel driver. 4577 * 4578 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 4579 * GDS to 0 for this ring (me/pipe). 4580 */ 4581 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 4582 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 4583 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 4584 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 4585 } 4586 4587 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4588 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4589 amdgpu_ring_write(ring, 4590 #ifdef __BIG_ENDIAN 4591 (2 << 0) | 4592 #endif 4593 lower_32_bits(ib->gpu_addr)); 4594 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4595 amdgpu_ring_write(ring, control); 4596 } 4597 4598 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4599 u64 seq, unsigned flags) 4600 { 4601 struct amdgpu_device *adev = ring->adev; 4602 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4603 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4604 4605 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 4606 if (adev->pdev->device == 0x50) 4607 int_sel = false; 4608 4609 /* RELEASE_MEM - flush caches, send int */ 4610 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4611 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4612 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4613 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 4614 PACKET3_RELEASE_MEM_GCR_GLM_WB | 4615 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4616 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4617 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4618 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4619 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4620 4621 /* 4622 * the address should be Qword aligned if 64bit write, Dword 4623 * aligned if only send 32bit data low (discard data high) 4624 */ 4625 if (write64bit) 4626 BUG_ON(addr & 0x7); 4627 else 4628 BUG_ON(addr & 0x3); 4629 amdgpu_ring_write(ring, lower_32_bits(addr)); 4630 amdgpu_ring_write(ring, upper_32_bits(addr)); 4631 amdgpu_ring_write(ring, lower_32_bits(seq)); 4632 amdgpu_ring_write(ring, upper_32_bits(seq)); 4633 amdgpu_ring_write(ring, 0); 4634 } 4635 4636 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4637 { 4638 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4639 uint32_t seq = ring->fence_drv.sync_seq; 4640 uint64_t addr = ring->fence_drv.gpu_addr; 4641 4642 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4643 upper_32_bits(addr), seq, 0xffffffff, 4); 4644 } 4645 4646 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4647 unsigned vmid, uint64_t pd_addr) 4648 { 4649 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4650 4651 /* compute doesn't have PFP */ 4652 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4653 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4654 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4655 amdgpu_ring_write(ring, 0x0); 4656 } 4657 } 4658 4659 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4660 u64 seq, unsigned int flags) 4661 { 4662 struct amdgpu_device *adev = ring->adev; 4663 4664 /* we only allocate 32bit for each seq wb address */ 4665 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4666 4667 /* write fence seq to the "addr" */ 4668 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4669 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4670 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4671 amdgpu_ring_write(ring, lower_32_bits(addr)); 4672 amdgpu_ring_write(ring, upper_32_bits(addr)); 4673 amdgpu_ring_write(ring, lower_32_bits(seq)); 4674 4675 if (flags & AMDGPU_FENCE_FLAG_INT) { 4676 /* set register to trigger INT */ 4677 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4678 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4679 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4680 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 4681 amdgpu_ring_write(ring, 0); 4682 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4683 } 4684 } 4685 4686 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 4687 { 4688 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4689 amdgpu_ring_write(ring, 0); 4690 } 4691 4692 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 4693 { 4694 uint32_t dw2 = 0; 4695 4696 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 4697 gfx_v10_0_ring_emit_ce_meta(ring, 4698 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 4699 4700 gfx_v10_0_ring_emit_tmz(ring, true); 4701 4702 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4703 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4704 /* set load_global_config & load_global_uconfig */ 4705 dw2 |= 0x8001; 4706 /* set load_cs_sh_regs */ 4707 dw2 |= 0x01000000; 4708 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4709 dw2 |= 0x10002; 4710 4711 /* set load_ce_ram if preamble presented */ 4712 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 4713 dw2 |= 0x10000000; 4714 } else { 4715 /* still load_ce_ram if this is the first time preamble presented 4716 * although there is no context switch happens. 4717 */ 4718 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 4719 dw2 |= 0x10000000; 4720 } 4721 4722 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4723 amdgpu_ring_write(ring, dw2); 4724 amdgpu_ring_write(ring, 0); 4725 } 4726 4727 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 4728 { 4729 unsigned ret; 4730 4731 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4732 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 4733 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 4734 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 4735 ret = ring->wptr & ring->buf_mask; 4736 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 4737 4738 return ret; 4739 } 4740 4741 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 4742 { 4743 unsigned cur; 4744 BUG_ON(offset > ring->buf_mask); 4745 BUG_ON(ring->ring[offset] != 0x55aa55aa); 4746 4747 cur = (ring->wptr - 1) & ring->buf_mask; 4748 if (likely(cur > offset)) 4749 ring->ring[offset] = cur - offset; 4750 else 4751 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 4752 } 4753 4754 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 4755 { 4756 int i, r = 0; 4757 struct amdgpu_device *adev = ring->adev; 4758 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4759 struct amdgpu_ring *kiq_ring = &kiq->ring; 4760 unsigned long flags; 4761 4762 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4763 return -EINVAL; 4764 4765 spin_lock_irqsave(&kiq->ring_lock, flags); 4766 4767 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 4768 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4769 return -ENOMEM; 4770 } 4771 4772 /* assert preemption condition */ 4773 amdgpu_ring_set_preempt_cond_exec(ring, false); 4774 4775 /* assert IB preemption, emit the trailing fence */ 4776 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4777 ring->trail_fence_gpu_addr, 4778 ++ring->trail_seq); 4779 amdgpu_ring_commit(kiq_ring); 4780 4781 spin_unlock_irqrestore(&kiq->ring_lock, flags); 4782 4783 /* poll the trailing fence */ 4784 for (i = 0; i < adev->usec_timeout; i++) { 4785 if (ring->trail_seq == 4786 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4787 break; 4788 udelay(1); 4789 } 4790 4791 if (i >= adev->usec_timeout) { 4792 r = -EINVAL; 4793 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4794 } 4795 4796 /* deassert preemption condition */ 4797 amdgpu_ring_set_preempt_cond_exec(ring, true); 4798 return r; 4799 } 4800 4801 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 4802 { 4803 struct amdgpu_device *adev = ring->adev; 4804 struct v10_ce_ib_state ce_payload = {0}; 4805 uint64_t csa_addr; 4806 int cnt; 4807 4808 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 4809 csa_addr = amdgpu_csa_vaddr(ring->adev); 4810 4811 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4812 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 4813 WRITE_DATA_DST_SEL(8) | 4814 WR_CONFIRM) | 4815 WRITE_DATA_CACHE_POLICY(0)); 4816 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4817 offsetof(struct v10_gfx_meta_data, ce_payload))); 4818 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4819 offsetof(struct v10_gfx_meta_data, ce_payload))); 4820 4821 if (resume) 4822 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4823 offsetof(struct v10_gfx_meta_data, 4824 ce_payload), 4825 sizeof(ce_payload) >> 2); 4826 else 4827 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 4828 sizeof(ce_payload) >> 2); 4829 } 4830 4831 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 4832 { 4833 struct amdgpu_device *adev = ring->adev; 4834 struct v10_de_ib_state de_payload = {0}; 4835 uint64_t csa_addr, gds_addr; 4836 int cnt; 4837 4838 csa_addr = amdgpu_csa_vaddr(ring->adev); 4839 gds_addr = roundup2(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 4840 PAGE_SIZE); 4841 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 4842 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 4843 4844 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 4845 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4846 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 4847 WRITE_DATA_DST_SEL(8) | 4848 WR_CONFIRM) | 4849 WRITE_DATA_CACHE_POLICY(0)); 4850 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4851 offsetof(struct v10_gfx_meta_data, de_payload))); 4852 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4853 offsetof(struct v10_gfx_meta_data, de_payload))); 4854 4855 if (resume) 4856 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4857 offsetof(struct v10_gfx_meta_data, 4858 de_payload), 4859 sizeof(de_payload) >> 2); 4860 else 4861 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 4862 sizeof(de_payload) >> 2); 4863 } 4864 4865 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 4866 { 4867 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4868 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 4869 } 4870 4871 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 4872 { 4873 struct amdgpu_device *adev = ring->adev; 4874 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4875 4876 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4877 amdgpu_ring_write(ring, 0 | /* src: register*/ 4878 (5 << 8) | /* dst: memory */ 4879 (1 << 20)); /* write confirm */ 4880 amdgpu_ring_write(ring, reg); 4881 amdgpu_ring_write(ring, 0); 4882 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4883 kiq->reg_val_offs * 4)); 4884 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4885 kiq->reg_val_offs * 4)); 4886 } 4887 4888 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 4889 uint32_t val) 4890 { 4891 uint32_t cmd = 0; 4892 4893 switch (ring->funcs->type) { 4894 case AMDGPU_RING_TYPE_GFX: 4895 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4896 break; 4897 case AMDGPU_RING_TYPE_KIQ: 4898 cmd = (1 << 16); /* no inc addr */ 4899 break; 4900 default: 4901 cmd = WR_CONFIRM; 4902 break; 4903 } 4904 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4905 amdgpu_ring_write(ring, cmd); 4906 amdgpu_ring_write(ring, reg); 4907 amdgpu_ring_write(ring, 0); 4908 amdgpu_ring_write(ring, val); 4909 } 4910 4911 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4912 uint32_t val, uint32_t mask) 4913 { 4914 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4915 } 4916 4917 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4918 uint32_t reg0, uint32_t reg1, 4919 uint32_t ref, uint32_t mask) 4920 { 4921 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4922 struct amdgpu_device *adev = ring->adev; 4923 bool fw_version_ok = false; 4924 4925 fw_version_ok = adev->gfx.cp_fw_write_wait; 4926 4927 if (fw_version_ok) 4928 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4929 ref, mask, 0x20); 4930 else 4931 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 4932 ref, mask); 4933 } 4934 4935 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 4936 unsigned vmid) 4937 { 4938 struct amdgpu_device *adev = ring->adev; 4939 uint32_t value = 0; 4940 4941 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 4942 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 4943 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 4944 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 4945 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 4946 } 4947 4948 static void 4949 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4950 uint32_t me, uint32_t pipe, 4951 enum amdgpu_interrupt_state state) 4952 { 4953 uint32_t cp_int_cntl, cp_int_cntl_reg; 4954 4955 if (!me) { 4956 switch (pipe) { 4957 case 0: 4958 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 4959 break; 4960 case 1: 4961 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 4962 break; 4963 default: 4964 DRM_DEBUG("invalid pipe %d\n", pipe); 4965 return; 4966 } 4967 } else { 4968 DRM_DEBUG("invalid me %d\n", me); 4969 return; 4970 } 4971 4972 switch (state) { 4973 case AMDGPU_IRQ_STATE_DISABLE: 4974 cp_int_cntl = RREG32(cp_int_cntl_reg); 4975 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4976 TIME_STAMP_INT_ENABLE, 0); 4977 WREG32(cp_int_cntl_reg, cp_int_cntl); 4978 break; 4979 case AMDGPU_IRQ_STATE_ENABLE: 4980 cp_int_cntl = RREG32(cp_int_cntl_reg); 4981 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4982 TIME_STAMP_INT_ENABLE, 1); 4983 WREG32(cp_int_cntl_reg, cp_int_cntl); 4984 break; 4985 default: 4986 break; 4987 } 4988 } 4989 4990 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4991 int me, int pipe, 4992 enum amdgpu_interrupt_state state) 4993 { 4994 u32 mec_int_cntl, mec_int_cntl_reg; 4995 4996 /* 4997 * amdgpu controls only the first MEC. That's why this function only 4998 * handles the setting of interrupts for this specific MEC. All other 4999 * pipes' interrupts are set by amdkfd. 5000 */ 5001 5002 if (me == 1) { 5003 switch (pipe) { 5004 case 0: 5005 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5006 break; 5007 case 1: 5008 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 5009 break; 5010 case 2: 5011 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 5012 break; 5013 case 3: 5014 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 5015 break; 5016 default: 5017 DRM_DEBUG("invalid pipe %d\n", pipe); 5018 return; 5019 } 5020 } else { 5021 DRM_DEBUG("invalid me %d\n", me); 5022 return; 5023 } 5024 5025 switch (state) { 5026 case AMDGPU_IRQ_STATE_DISABLE: 5027 mec_int_cntl = RREG32(mec_int_cntl_reg); 5028 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5029 TIME_STAMP_INT_ENABLE, 0); 5030 WREG32(mec_int_cntl_reg, mec_int_cntl); 5031 break; 5032 case AMDGPU_IRQ_STATE_ENABLE: 5033 mec_int_cntl = RREG32(mec_int_cntl_reg); 5034 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 5035 TIME_STAMP_INT_ENABLE, 1); 5036 WREG32(mec_int_cntl_reg, mec_int_cntl); 5037 break; 5038 default: 5039 break; 5040 } 5041 } 5042 5043 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 5044 struct amdgpu_irq_src *src, 5045 unsigned type, 5046 enum amdgpu_interrupt_state state) 5047 { 5048 switch (type) { 5049 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 5050 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 5051 break; 5052 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 5053 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 5054 break; 5055 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 5056 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 5057 break; 5058 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 5059 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 5060 break; 5061 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 5062 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 5063 break; 5064 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 5065 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 5066 break; 5067 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 5068 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 5069 break; 5070 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 5071 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 5072 break; 5073 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 5074 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 5075 break; 5076 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 5077 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 5078 break; 5079 default: 5080 break; 5081 } 5082 return 0; 5083 } 5084 5085 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 5086 struct amdgpu_irq_src *source, 5087 struct amdgpu_iv_entry *entry) 5088 { 5089 int i; 5090 u8 me_id, pipe_id, queue_id; 5091 struct amdgpu_ring *ring; 5092 5093 DRM_DEBUG("IH: CP EOP\n"); 5094 me_id = (entry->ring_id & 0x0c) >> 2; 5095 pipe_id = (entry->ring_id & 0x03) >> 0; 5096 queue_id = (entry->ring_id & 0x70) >> 4; 5097 5098 switch (me_id) { 5099 case 0: 5100 if (pipe_id == 0) 5101 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 5102 else 5103 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 5104 break; 5105 case 1: 5106 case 2: 5107 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5108 ring = &adev->gfx.compute_ring[i]; 5109 /* Per-queue interrupt is supported for MEC starting from VI. 5110 * The interrupt can only be enabled/disabled per pipe instead of per queue. 5111 */ 5112 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 5113 amdgpu_fence_process(ring); 5114 } 5115 break; 5116 } 5117 return 0; 5118 } 5119 5120 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 5121 struct amdgpu_irq_src *source, 5122 unsigned type, 5123 enum amdgpu_interrupt_state state) 5124 { 5125 switch (state) { 5126 case AMDGPU_IRQ_STATE_DISABLE: 5127 case AMDGPU_IRQ_STATE_ENABLE: 5128 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5129 PRIV_REG_INT_ENABLE, 5130 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5131 break; 5132 default: 5133 break; 5134 } 5135 5136 return 0; 5137 } 5138 5139 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5140 struct amdgpu_irq_src *source, 5141 unsigned type, 5142 enum amdgpu_interrupt_state state) 5143 { 5144 switch (state) { 5145 case AMDGPU_IRQ_STATE_DISABLE: 5146 case AMDGPU_IRQ_STATE_ENABLE: 5147 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5148 PRIV_INSTR_INT_ENABLE, 5149 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5150 default: 5151 break; 5152 } 5153 5154 return 0; 5155 } 5156 5157 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 5158 struct amdgpu_iv_entry *entry) 5159 { 5160 u8 me_id, pipe_id, queue_id; 5161 struct amdgpu_ring *ring; 5162 int i; 5163 5164 me_id = (entry->ring_id & 0x0c) >> 2; 5165 pipe_id = (entry->ring_id & 0x03) >> 0; 5166 queue_id = (entry->ring_id & 0x70) >> 4; 5167 5168 switch (me_id) { 5169 case 0: 5170 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5171 ring = &adev->gfx.gfx_ring[i]; 5172 /* we only enabled 1 gfx queue per pipe for now */ 5173 if (ring->me == me_id && ring->pipe == pipe_id) 5174 drm_sched_fault(&ring->sched); 5175 } 5176 break; 5177 case 1: 5178 case 2: 5179 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5180 ring = &adev->gfx.compute_ring[i]; 5181 if (ring->me == me_id && ring->pipe == pipe_id && 5182 ring->queue == queue_id) 5183 drm_sched_fault(&ring->sched); 5184 } 5185 break; 5186 default: 5187 BUG(); 5188 } 5189 } 5190 5191 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 5192 struct amdgpu_irq_src *source, 5193 struct amdgpu_iv_entry *entry) 5194 { 5195 DRM_ERROR("Illegal register access in command stream\n"); 5196 gfx_v10_0_handle_priv_fault(adev, entry); 5197 return 0; 5198 } 5199 5200 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 5201 struct amdgpu_irq_src *source, 5202 struct amdgpu_iv_entry *entry) 5203 { 5204 DRM_ERROR("Illegal instruction in command stream\n"); 5205 gfx_v10_0_handle_priv_fault(adev, entry); 5206 return 0; 5207 } 5208 5209 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 5210 struct amdgpu_irq_src *src, 5211 unsigned int type, 5212 enum amdgpu_interrupt_state state) 5213 { 5214 uint32_t tmp, target; 5215 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 5216 5217 if (ring->me == 1) 5218 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5219 else 5220 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 5221 target += ring->pipe; 5222 5223 switch (type) { 5224 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 5225 if (state == AMDGPU_IRQ_STATE_DISABLE) { 5226 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 5227 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 5228 GENERIC2_INT_ENABLE, 0); 5229 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 5230 5231 tmp = RREG32(target); 5232 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 5233 GENERIC2_INT_ENABLE, 0); 5234 WREG32(target, tmp); 5235 } else { 5236 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 5237 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 5238 GENERIC2_INT_ENABLE, 1); 5239 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 5240 5241 tmp = RREG32(target); 5242 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 5243 GENERIC2_INT_ENABLE, 1); 5244 WREG32(target, tmp); 5245 } 5246 break; 5247 default: 5248 BUG(); /* kiq only support GENERIC2_INT now */ 5249 break; 5250 } 5251 return 0; 5252 } 5253 5254 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 5255 struct amdgpu_irq_src *source, 5256 struct amdgpu_iv_entry *entry) 5257 { 5258 u8 me_id, pipe_id, queue_id; 5259 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 5260 5261 me_id = (entry->ring_id & 0x0c) >> 2; 5262 pipe_id = (entry->ring_id & 0x03) >> 0; 5263 queue_id = (entry->ring_id & 0x70) >> 4; 5264 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 5265 me_id, pipe_id, queue_id); 5266 5267 amdgpu_fence_process(ring); 5268 return 0; 5269 } 5270 5271 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 5272 .name = "gfx_v10_0", 5273 .early_init = gfx_v10_0_early_init, 5274 .late_init = gfx_v10_0_late_init, 5275 .sw_init = gfx_v10_0_sw_init, 5276 .sw_fini = gfx_v10_0_sw_fini, 5277 .hw_init = gfx_v10_0_hw_init, 5278 .hw_fini = gfx_v10_0_hw_fini, 5279 .suspend = gfx_v10_0_suspend, 5280 .resume = gfx_v10_0_resume, 5281 .is_idle = gfx_v10_0_is_idle, 5282 .wait_for_idle = gfx_v10_0_wait_for_idle, 5283 .soft_reset = gfx_v10_0_soft_reset, 5284 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 5285 .set_powergating_state = gfx_v10_0_set_powergating_state, 5286 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 5287 }; 5288 5289 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 5290 .type = AMDGPU_RING_TYPE_GFX, 5291 .align_mask = 0xff, 5292 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5293 .support_64bit_ptrs = true, 5294 .vmhub = AMDGPU_GFXHUB_0, 5295 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 5296 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 5297 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 5298 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5299 5 + /* COND_EXEC */ 5300 7 + /* PIPELINE_SYNC */ 5301 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5302 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5303 2 + /* VM_FLUSH */ 5304 8 + /* FENCE for VM_FLUSH */ 5305 20 + /* GDS switch */ 5306 4 + /* double SWITCH_BUFFER, 5307 * the first COND_EXEC jump to the place 5308 * just prior to this double SWITCH_BUFFER 5309 */ 5310 5 + /* COND_EXEC */ 5311 7 + /* HDP_flush */ 5312 4 + /* VGT_flush */ 5313 14 + /* CE_META */ 5314 31 + /* DE_META */ 5315 3 + /* CNTX_CTRL */ 5316 5 + /* HDP_INVL */ 5317 8 + 8 + /* FENCE x2 */ 5318 2, /* SWITCH_BUFFER */ 5319 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 5320 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 5321 .emit_fence = gfx_v10_0_ring_emit_fence, 5322 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5323 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5324 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5325 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5326 .test_ring = gfx_v10_0_ring_test_ring, 5327 .test_ib = gfx_v10_0_ring_test_ib, 5328 .insert_nop = amdgpu_ring_insert_nop, 5329 .pad_ib = amdgpu_ring_generic_pad_ib, 5330 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 5331 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 5332 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 5333 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 5334 .preempt_ib = gfx_v10_0_ring_preempt_ib, 5335 .emit_tmz = gfx_v10_0_ring_emit_tmz, 5336 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5337 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5338 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5339 .soft_recovery = gfx_v10_0_ring_soft_recovery, 5340 }; 5341 5342 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 5343 .type = AMDGPU_RING_TYPE_COMPUTE, 5344 .align_mask = 0xff, 5345 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5346 .support_64bit_ptrs = true, 5347 .vmhub = AMDGPU_GFXHUB_0, 5348 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5349 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5350 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5351 .emit_frame_size = 5352 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5353 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5354 5 + /* hdp invalidate */ 5355 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5356 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5357 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5358 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5359 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 5360 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5361 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5362 .emit_fence = gfx_v10_0_ring_emit_fence, 5363 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5364 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5365 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5366 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5367 .test_ring = gfx_v10_0_ring_test_ring, 5368 .test_ib = gfx_v10_0_ring_test_ib, 5369 .insert_nop = amdgpu_ring_insert_nop, 5370 .pad_ib = amdgpu_ring_generic_pad_ib, 5371 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5372 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5373 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5374 }; 5375 5376 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 5377 .type = AMDGPU_RING_TYPE_KIQ, 5378 .align_mask = 0xff, 5379 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5380 .support_64bit_ptrs = true, 5381 .vmhub = AMDGPU_GFXHUB_0, 5382 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5383 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5384 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5385 .emit_frame_size = 5386 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5387 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5388 5 + /*hdp invalidate */ 5389 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5390 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5391 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5392 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5393 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5394 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5395 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5396 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 5397 .test_ring = gfx_v10_0_ring_test_ring, 5398 .test_ib = gfx_v10_0_ring_test_ib, 5399 .insert_nop = amdgpu_ring_insert_nop, 5400 .pad_ib = amdgpu_ring_generic_pad_ib, 5401 .emit_rreg = gfx_v10_0_ring_emit_rreg, 5402 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5403 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5404 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5405 }; 5406 5407 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 5408 { 5409 int i; 5410 5411 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 5412 5413 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5414 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 5415 5416 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5417 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 5418 } 5419 5420 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 5421 .set = gfx_v10_0_set_eop_interrupt_state, 5422 .process = gfx_v10_0_eop_irq, 5423 }; 5424 5425 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 5426 .set = gfx_v10_0_set_priv_reg_fault_state, 5427 .process = gfx_v10_0_priv_reg_irq, 5428 }; 5429 5430 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 5431 .set = gfx_v10_0_set_priv_inst_fault_state, 5432 .process = gfx_v10_0_priv_inst_irq, 5433 }; 5434 5435 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 5436 .set = gfx_v10_0_kiq_set_interrupt_state, 5437 .process = gfx_v10_0_kiq_irq, 5438 }; 5439 5440 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 5441 { 5442 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5443 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 5444 5445 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 5446 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 5447 5448 adev->gfx.priv_reg_irq.num_types = 1; 5449 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 5450 5451 adev->gfx.priv_inst_irq.num_types = 1; 5452 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 5453 } 5454 5455 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 5456 { 5457 switch (adev->asic_type) { 5458 case CHIP_NAVI10: 5459 case CHIP_NAVI14: 5460 case CHIP_NAVI12: 5461 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 5462 break; 5463 default: 5464 break; 5465 } 5466 } 5467 5468 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 5469 { 5470 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 5471 adev->gfx.config.max_sh_per_se * 5472 adev->gfx.config.max_shader_engines; 5473 5474 adev->gds.gds_size = 0x10000; 5475 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 5476 adev->gds.gws_size = 64; 5477 adev->gds.oa_size = 16; 5478 } 5479 5480 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5481 u32 bitmap) 5482 { 5483 u32 data; 5484 5485 if (!bitmap) 5486 return; 5487 5488 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5489 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5490 5491 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 5492 } 5493 5494 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5495 { 5496 u32 data, wgp_bitmask; 5497 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 5498 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 5499 5500 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5501 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5502 5503 wgp_bitmask = 5504 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5505 5506 return (~data) & wgp_bitmask; 5507 } 5508 5509 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5510 { 5511 u32 wgp_idx, wgp_active_bitmap; 5512 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5513 5514 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5515 cu_active_bitmap = 0; 5516 5517 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5518 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5519 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5520 if (wgp_active_bitmap & (1 << wgp_idx)) 5521 cu_active_bitmap |= cu_bitmap_per_wgp; 5522 } 5523 5524 return cu_active_bitmap; 5525 } 5526 5527 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 5528 struct amdgpu_cu_info *cu_info) 5529 { 5530 int i, j, k, counter, active_cu_number = 0; 5531 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5532 unsigned disable_masks[4 * 2]; 5533 5534 if (!adev || !cu_info) 5535 return -EINVAL; 5536 5537 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5538 5539 mutex_lock(&adev->grbm_idx_mutex); 5540 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5541 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5542 mask = 1; 5543 ao_bitmap = 0; 5544 counter = 0; 5545 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5546 if (i < 4 && j < 2) 5547 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 5548 adev, disable_masks[i * 2 + j]); 5549 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 5550 cu_info->bitmap[i][j] = bitmap; 5551 5552 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5553 if (bitmap & mask) { 5554 if (counter < adev->gfx.config.max_cu_per_sh) 5555 ao_bitmap |= mask; 5556 counter++; 5557 } 5558 mask <<= 1; 5559 } 5560 active_cu_number += counter; 5561 if (i < 2 && j < 2) 5562 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5563 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5564 } 5565 } 5566 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5567 mutex_unlock(&adev->grbm_idx_mutex); 5568 5569 cu_info->number = active_cu_number; 5570 cu_info->ao_cu_mask = ao_cu_mask; 5571 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5572 5573 return 0; 5574 } 5575 5576 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 5577 { 5578 .type = AMD_IP_BLOCK_TYPE_GFX, 5579 .major = 10, 5580 .minor = 0, 5581 .rev = 0, 5582 .funcs = &gfx_v10_0_ip_funcs, 5583 }; 5584