1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/list.h> 25 #include "amdgpu.h" 26 #include "amdgpu_xgmi.h" 27 #include "amdgpu_ras.h" 28 #include "soc15.h" 29 #include "df/df_3_6_offset.h" 30 #include "xgmi/xgmi_4_0_0_smn.h" 31 #include "xgmi/xgmi_4_0_0_sh_mask.h" 32 #include "wafl/wafl2_4_0_0_smn.h" 33 #include "wafl/wafl2_4_0_0_sh_mask.h" 34 35 #define smnPCS_XGMI23_PCS_ERROR_STATUS 0x11a01210 36 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c 37 #define smnPCS_GOPX1_PCS_ERROR_STATUS 0x12200210 38 39 static DEFINE_MUTEX(xgmi_mutex); 40 41 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE 4 42 43 static DRM_LIST_HEAD(xgmi_hive_list); 44 45 static const int xgmi_pcs_err_status_reg_vg20[] = { 46 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 47 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 48 }; 49 50 static const int wafl_pcs_err_status_reg_vg20[] = { 51 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 52 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 53 }; 54 55 static const int xgmi_pcs_err_status_reg_arct[] = { 56 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 57 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 58 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000, 59 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000, 60 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000, 61 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000, 62 }; 63 64 /* same as vg20*/ 65 static const int wafl_pcs_err_status_reg_arct[] = { 66 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 67 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 68 }; 69 70 static const int xgmi23_pcs_err_status_reg_aldebaran[] = { 71 smnPCS_XGMI23_PCS_ERROR_STATUS, 72 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x100000, 73 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x200000, 74 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x300000, 75 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x400000, 76 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x500000, 77 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x600000, 78 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x700000 79 }; 80 81 static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = { 82 smnPCS_XGMI3X16_PCS_ERROR_STATUS, 83 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000, 84 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x200000, 85 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x300000, 86 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x400000, 87 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x500000, 88 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x600000, 89 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x700000 90 }; 91 92 static const int walf_pcs_err_status_reg_aldebaran[] = { 93 smnPCS_GOPX1_PCS_ERROR_STATUS, 94 smnPCS_GOPX1_PCS_ERROR_STATUS + 0x100000 95 }; 96 97 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = { 98 {"XGMI PCS DataLossErr", 99 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)}, 100 {"XGMI PCS TrainingErr", 101 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)}, 102 {"XGMI PCS CRCErr", 103 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)}, 104 {"XGMI PCS BERExceededErr", 105 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)}, 106 {"XGMI PCS TxMetaDataErr", 107 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)}, 108 {"XGMI PCS ReplayBufParityErr", 109 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)}, 110 {"XGMI PCS DataParityErr", 111 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)}, 112 {"XGMI PCS ReplayFifoOverflowErr", 113 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 114 {"XGMI PCS ReplayFifoUnderflowErr", 115 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 116 {"XGMI PCS ElasticFifoOverflowErr", 117 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 118 {"XGMI PCS DeskewErr", 119 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)}, 120 {"XGMI PCS DataStartupLimitErr", 121 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)}, 122 {"XGMI PCS FCInitTimeoutErr", 123 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 124 {"XGMI PCS RecoveryTimeoutErr", 125 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 126 {"XGMI PCS ReadySerialTimeoutErr", 127 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 128 {"XGMI PCS ReadySerialAttemptErr", 129 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 130 {"XGMI PCS RecoveryAttemptErr", 131 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 132 {"XGMI PCS RecoveryRelockAttemptErr", 133 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 134 }; 135 136 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = { 137 {"WAFL PCS DataLossErr", 138 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)}, 139 {"WAFL PCS TrainingErr", 140 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)}, 141 {"WAFL PCS CRCErr", 142 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)}, 143 {"WAFL PCS BERExceededErr", 144 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)}, 145 {"WAFL PCS TxMetaDataErr", 146 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)}, 147 {"WAFL PCS ReplayBufParityErr", 148 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)}, 149 {"WAFL PCS DataParityErr", 150 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)}, 151 {"WAFL PCS ReplayFifoOverflowErr", 152 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 153 {"WAFL PCS ReplayFifoUnderflowErr", 154 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 155 {"WAFL PCS ElasticFifoOverflowErr", 156 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 157 {"WAFL PCS DeskewErr", 158 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)}, 159 {"WAFL PCS DataStartupLimitErr", 160 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)}, 161 {"WAFL PCS FCInitTimeoutErr", 162 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 163 {"WAFL PCS RecoveryTimeoutErr", 164 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 165 {"WAFL PCS ReadySerialTimeoutErr", 166 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 167 {"WAFL PCS ReadySerialAttemptErr", 168 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 169 {"WAFL PCS RecoveryAttemptErr", 170 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 171 {"WAFL PCS RecoveryRelockAttemptErr", 172 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 173 }; 174 175 /** 176 * DOC: AMDGPU XGMI Support 177 * 178 * XGMI is a high speed interconnect that joins multiple GPU cards 179 * into a homogeneous memory space that is organized by a collective 180 * hive ID and individual node IDs, both of which are 64-bit numbers. 181 * 182 * The file xgmi_device_id contains the unique per GPU device ID and 183 * is stored in the /sys/class/drm/card${cardno}/device/ directory. 184 * 185 * Inside the device directory a sub-directory 'xgmi_hive_info' is 186 * created which contains the hive ID and the list of nodes. 187 * 188 * The hive ID is stored in: 189 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id 190 * 191 * The node information is stored in numbered directories: 192 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id 193 * 194 * Each device has their own xgmi_hive_info direction with a mirror 195 * set of node sub-directories. 196 * 197 * The XGMI memory space is built by contiguously adding the power of 198 * two padded VRAM space from each node to each other. 199 * 200 */ 201 202 static struct attribute amdgpu_xgmi_hive_id = { 203 .name = "xgmi_hive_id", 204 #ifdef notyet 205 .mode = S_IRUGO 206 #endif 207 }; 208 209 static struct attribute *amdgpu_xgmi_hive_attrs[] = { 210 &amdgpu_xgmi_hive_id, 211 NULL 212 }; 213 214 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj, 215 struct attribute *attr, char *buf) 216 { 217 struct amdgpu_hive_info *hive = container_of( 218 kobj, struct amdgpu_hive_info, kobj); 219 220 if (attr == &amdgpu_xgmi_hive_id) 221 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id); 222 223 return 0; 224 } 225 226 static void amdgpu_xgmi_hive_release(struct kobject *kobj) 227 { 228 struct amdgpu_hive_info *hive = container_of( 229 kobj, struct amdgpu_hive_info, kobj); 230 231 mutex_destroy(&hive->hive_lock); 232 kfree(hive); 233 } 234 235 #ifdef notyet 236 static const struct sysfs_ops amdgpu_xgmi_hive_ops = { 237 .show = amdgpu_xgmi_show_attrs, 238 }; 239 #endif 240 241 struct kobj_type amdgpu_xgmi_hive_type = { 242 .release = amdgpu_xgmi_hive_release, 243 #ifdef notyet 244 .sysfs_ops = &amdgpu_xgmi_hive_ops, 245 .default_attrs = amdgpu_xgmi_hive_attrs, 246 #endif 247 }; 248 249 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, 250 struct device_attribute *attr, 251 char *buf) 252 { 253 struct drm_device *ddev = dev_get_drvdata(dev); 254 struct amdgpu_device *adev = drm_to_adev(ddev); 255 256 return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id); 257 258 } 259 260 #define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801) 261 static ssize_t amdgpu_xgmi_show_error(struct device *dev, 262 struct device_attribute *attr, 263 char *buf) 264 { 265 struct drm_device *ddev = dev_get_drvdata(dev); 266 struct amdgpu_device *adev = drm_to_adev(ddev); 267 uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in; 268 uint64_t fica_out; 269 unsigned int error_count = 0; 270 271 ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200); 272 ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208); 273 274 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in); 275 if (fica_out != 0x1f) 276 pr_err("xGMI error counters not enabled!\n"); 277 278 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in); 279 280 if ((fica_out & 0xffff) == 2) 281 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63); 282 283 adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0); 284 285 return sysfs_emit(buf, "%u\n", error_count); 286 } 287 288 289 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL); 290 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL); 291 292 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev, 293 struct amdgpu_hive_info *hive) 294 { 295 STUB(); 296 return -ENOSYS; 297 #ifdef notyet 298 int ret = 0; 299 char node[10] = { 0 }; 300 301 /* Create xgmi device id file */ 302 ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id); 303 if (ret) { 304 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n"); 305 return ret; 306 } 307 308 /* Create xgmi error file */ 309 ret = device_create_file(adev->dev, &dev_attr_xgmi_error); 310 if (ret) 311 pr_err("failed to create xgmi_error\n"); 312 313 314 /* Create sysfs link to hive info folder on the first device */ 315 if (hive->kobj.parent != (&adev->dev->kobj)) { 316 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj, 317 "xgmi_hive_info"); 318 if (ret) { 319 dev_err(adev->dev, "XGMI: Failed to create link to hive info"); 320 goto remove_file; 321 } 322 } 323 324 snprintf(node, sizeof(node), "node%d", atomic_read(&hive->number_devices)); 325 /* Create sysfs link form the hive folder to yourself */ 326 ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node); 327 if (ret) { 328 dev_err(adev->dev, "XGMI: Failed to create link from hive info"); 329 goto remove_link; 330 } 331 332 goto success; 333 334 335 remove_link: 336 sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique); 337 338 remove_file: 339 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 340 341 success: 342 return ret; 343 #endif 344 } 345 346 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev, 347 struct amdgpu_hive_info *hive) 348 { 349 #ifdef __linux__ 350 char node[10]; 351 memset(node, 0, sizeof(node)); 352 353 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 354 device_remove_file(adev->dev, &dev_attr_xgmi_error); 355 356 if (hive->kobj.parent != (&adev->dev->kobj)) 357 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info"); 358 359 sprintf(node, "node%d", atomic_read(&hive->number_devices)); 360 sysfs_remove_link(&hive->kobj, node); 361 #endif 362 } 363 364 365 366 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) 367 { 368 struct amdgpu_hive_info *hive = NULL; 369 int ret; 370 371 if (!adev->gmc.xgmi.hive_id) 372 return NULL; 373 374 STUB(); 375 return NULL; 376 #ifdef notyet 377 378 if (adev->hive) { 379 kobject_get(&adev->hive->kobj); 380 return adev->hive; 381 } 382 383 mutex_lock(&xgmi_mutex); 384 385 list_for_each_entry(hive, &xgmi_hive_list, node) { 386 if (hive->hive_id == adev->gmc.xgmi.hive_id) 387 goto pro_end; 388 } 389 390 hive = kzalloc(sizeof(*hive), GFP_KERNEL); 391 if (!hive) { 392 dev_err(adev->dev, "XGMI: allocation failed\n"); 393 hive = NULL; 394 goto pro_end; 395 } 396 397 /* initialize new hive if not exist */ 398 ret = kobject_init_and_add(&hive->kobj, 399 &amdgpu_xgmi_hive_type, 400 &adev->dev->kobj, 401 "%s", "xgmi_hive_info"); 402 if (ret) { 403 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n"); 404 kobject_put(&hive->kobj); 405 kfree(hive); 406 hive = NULL; 407 goto pro_end; 408 } 409 410 hive->hive_id = adev->gmc.xgmi.hive_id; 411 INIT_LIST_HEAD(&hive->device_list); 412 INIT_LIST_HEAD(&hive->node); 413 rw_init(&hive->hive_lock, "aghive"); 414 atomic_set(&hive->in_reset, 0); 415 atomic_set(&hive->number_devices, 0); 416 task_barrier_init(&hive->tb); 417 hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN; 418 hive->hi_req_gpu = NULL; 419 /* 420 * hive pstate on boot is high in vega20 so we have to go to low 421 * pstate on after boot. 422 */ 423 hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE; 424 list_add_tail(&hive->node, &xgmi_hive_list); 425 426 pro_end: 427 if (hive) 428 kobject_get(&hive->kobj); 429 mutex_unlock(&xgmi_mutex); 430 return hive; 431 #endif 432 } 433 434 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive) 435 { 436 if (hive) 437 kobject_put(&hive->kobj); 438 } 439 440 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate) 441 { 442 int ret = 0; 443 struct amdgpu_hive_info *hive; 444 struct amdgpu_device *request_adev; 445 bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20; 446 bool init_low; 447 448 hive = amdgpu_get_xgmi_hive(adev); 449 if (!hive) 450 return 0; 451 452 request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev; 453 init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN; 454 amdgpu_put_xgmi_hive(hive); 455 /* fw bug so temporarily disable pstate switching */ 456 return 0; 457 458 if (!hive || adev->asic_type != CHIP_VEGA20) 459 return 0; 460 461 mutex_lock(&hive->hive_lock); 462 463 if (is_hi_req) 464 hive->hi_req_count++; 465 else 466 hive->hi_req_count--; 467 468 /* 469 * Vega20 only needs single peer to request pstate high for the hive to 470 * go high but all peers must request pstate low for the hive to go low 471 */ 472 if (hive->pstate == pstate || 473 (!is_hi_req && hive->hi_req_count && !init_low)) 474 goto out; 475 476 dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate); 477 478 ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate); 479 if (ret) { 480 dev_err(request_adev->dev, 481 "XGMI: Set pstate failure on device %llx, hive %llx, ret %d", 482 request_adev->gmc.xgmi.node_id, 483 request_adev->gmc.xgmi.hive_id, ret); 484 goto out; 485 } 486 487 if (init_low) 488 hive->pstate = hive->hi_req_count ? 489 hive->pstate : AMDGPU_XGMI_PSTATE_MIN; 490 else { 491 hive->pstate = pstate; 492 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ? 493 adev : NULL; 494 } 495 out: 496 mutex_unlock(&hive->hive_lock); 497 return ret; 498 } 499 500 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev) 501 { 502 int ret; 503 504 /* Each psp need to set the latest topology */ 505 ret = psp_xgmi_set_topology_info(&adev->psp, 506 atomic_read(&hive->number_devices), 507 &adev->psp.xgmi_context.top_info); 508 if (ret) 509 dev_err(adev->dev, 510 "XGMI: Set topology failure on device %llx, hive %llx, ret %d", 511 adev->gmc.xgmi.node_id, 512 adev->gmc.xgmi.hive_id, ret); 513 514 return ret; 515 } 516 517 518 /* 519 * NOTE psp_xgmi_node_info.num_hops layout is as follows: 520 * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved) 521 * num_hops[5:3] = reserved 522 * num_hops[2:0] = number of hops 523 */ 524 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, 525 struct amdgpu_device *peer_adev) 526 { 527 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 528 uint8_t num_hops_mask = 0x7; 529 int i; 530 531 for (i = 0 ; i < top->num_nodes; ++i) 532 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 533 return top->nodes[i].num_hops & num_hops_mask; 534 return -EINVAL; 535 } 536 537 int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev, 538 struct amdgpu_device *peer_adev) 539 { 540 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 541 int i; 542 543 for (i = 0 ; i < top->num_nodes; ++i) 544 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 545 return top->nodes[i].num_links; 546 return -EINVAL; 547 } 548 549 /* 550 * Devices that support extended data require the entire hive to initialize with 551 * the shared memory buffer flag set. 552 * 553 * Hive locks and conditions apply - see amdgpu_xgmi_add_device 554 */ 555 static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info *hive, 556 bool set_extended_data) 557 { 558 struct amdgpu_device *tmp_adev; 559 int ret; 560 561 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 562 ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false); 563 if (ret) { 564 dev_err(tmp_adev->dev, 565 "XGMI: Failed to initialize xgmi session for data partition %i\n", 566 set_extended_data); 567 return ret; 568 } 569 570 } 571 572 return 0; 573 } 574 575 int amdgpu_xgmi_add_device(struct amdgpu_device *adev) 576 { 577 struct psp_xgmi_topology_info *top_info; 578 struct amdgpu_hive_info *hive; 579 struct amdgpu_xgmi *entry; 580 struct amdgpu_device *tmp_adev = NULL; 581 582 int count = 0, ret = 0; 583 584 if (!adev->gmc.xgmi.supported) 585 return 0; 586 587 if (!adev->gmc.xgmi.pending_reset && 588 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 589 ret = psp_xgmi_initialize(&adev->psp, false, true); 590 if (ret) { 591 dev_err(adev->dev, 592 "XGMI: Failed to initialize xgmi session\n"); 593 return ret; 594 } 595 596 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id); 597 if (ret) { 598 dev_err(adev->dev, 599 "XGMI: Failed to get hive id\n"); 600 return ret; 601 } 602 603 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id); 604 if (ret) { 605 dev_err(adev->dev, 606 "XGMI: Failed to get node id\n"); 607 return ret; 608 } 609 } else { 610 adev->gmc.xgmi.hive_id = 16; 611 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16; 612 } 613 614 hive = amdgpu_get_xgmi_hive(adev); 615 if (!hive) { 616 ret = -EINVAL; 617 dev_err(adev->dev, 618 "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n", 619 adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id); 620 goto exit; 621 } 622 mutex_lock(&hive->hive_lock); 623 624 top_info = &adev->psp.xgmi_context.top_info; 625 626 list_add_tail(&adev->gmc.xgmi.head, &hive->device_list); 627 list_for_each_entry(entry, &hive->device_list, head) 628 top_info->nodes[count++].node_id = entry->node_id; 629 top_info->num_nodes = count; 630 atomic_set(&hive->number_devices, count); 631 632 task_barrier_add_task(&hive->tb); 633 634 if (!adev->gmc.xgmi.pending_reset && 635 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 636 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 637 /* update node list for other device in the hive */ 638 if (tmp_adev != adev) { 639 top_info = &tmp_adev->psp.xgmi_context.top_info; 640 top_info->nodes[count - 1].node_id = 641 adev->gmc.xgmi.node_id; 642 top_info->num_nodes = count; 643 } 644 ret = amdgpu_xgmi_update_topology(hive, tmp_adev); 645 if (ret) 646 goto exit_unlock; 647 } 648 649 /* get latest topology info for each device from psp */ 650 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 651 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 652 &tmp_adev->psp.xgmi_context.top_info, false); 653 if (ret) { 654 dev_err(tmp_adev->dev, 655 "XGMI: Get topology failure on device %llx, hive %llx, ret %d", 656 tmp_adev->gmc.xgmi.node_id, 657 tmp_adev->gmc.xgmi.hive_id, ret); 658 /* To do : continue with some node failed or disable the whole hive */ 659 goto exit_unlock; 660 } 661 } 662 663 /* get topology again for hives that support extended data */ 664 if (adev->psp.xgmi_context.supports_extended_data) { 665 666 /* initialize the hive to get extended data. */ 667 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true); 668 if (ret) 669 goto exit_unlock; 670 671 /* get the extended data. */ 672 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 673 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 674 &tmp_adev->psp.xgmi_context.top_info, true); 675 if (ret) { 676 dev_err(tmp_adev->dev, 677 "XGMI: Get topology for extended data failure on device %llx, hive %llx, ret %d", 678 tmp_adev->gmc.xgmi.node_id, 679 tmp_adev->gmc.xgmi.hive_id, ret); 680 goto exit_unlock; 681 } 682 } 683 684 /* initialize the hive to get non-extended data for the next round. */ 685 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false); 686 if (ret) 687 goto exit_unlock; 688 689 } 690 } 691 692 if (!ret && !adev->gmc.xgmi.pending_reset) 693 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive); 694 695 exit_unlock: 696 mutex_unlock(&hive->hive_lock); 697 exit: 698 if (!ret) { 699 adev->hive = hive; 700 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n", 701 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id); 702 } else { 703 amdgpu_put_xgmi_hive(hive); 704 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n", 705 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id, 706 ret); 707 } 708 709 return ret; 710 } 711 712 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev) 713 { 714 struct amdgpu_hive_info *hive = adev->hive; 715 716 if (!adev->gmc.xgmi.supported) 717 return -EINVAL; 718 719 if (!hive) 720 return -EINVAL; 721 722 mutex_lock(&hive->hive_lock); 723 task_barrier_rem_task(&hive->tb); 724 amdgpu_xgmi_sysfs_rem_dev_info(adev, hive); 725 if (hive->hi_req_gpu == adev) 726 hive->hi_req_gpu = NULL; 727 list_del(&adev->gmc.xgmi.head); 728 mutex_unlock(&hive->hive_lock); 729 730 amdgpu_put_xgmi_hive(hive); 731 adev->hive = NULL; 732 733 if (atomic_dec_return(&hive->number_devices) == 0) { 734 /* Remove the hive from global hive list */ 735 mutex_lock(&xgmi_mutex); 736 list_del(&hive->node); 737 mutex_unlock(&xgmi_mutex); 738 739 amdgpu_put_xgmi_hive(hive); 740 } 741 742 return psp_xgmi_terminate(&adev->psp); 743 } 744 745 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev) 746 { 747 int r; 748 struct ras_ih_if ih_info = { 749 .cb = NULL, 750 }; 751 struct ras_fs_if fs_info = { 752 .sysfs_name = "xgmi_wafl_err_count", 753 }; 754 755 if (!adev->gmc.xgmi.supported || 756 adev->gmc.xgmi.num_physical_nodes == 0) 757 return 0; 758 759 adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev); 760 761 if (!adev->gmc.xgmi.ras_if) { 762 adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); 763 if (!adev->gmc.xgmi.ras_if) 764 return -ENOMEM; 765 adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL; 766 adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 767 adev->gmc.xgmi.ras_if->sub_block_index = 0; 768 } 769 ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if; 770 r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if, 771 &fs_info, &ih_info); 772 if (r || !amdgpu_ras_is_supported(adev, adev->gmc.xgmi.ras_if->block)) { 773 kfree(adev->gmc.xgmi.ras_if); 774 adev->gmc.xgmi.ras_if = NULL; 775 } 776 777 return r; 778 } 779 780 static void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev) 781 { 782 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) && 783 adev->gmc.xgmi.ras_if) { 784 struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if; 785 struct ras_ih_if ih_info = { 786 .cb = NULL, 787 }; 788 789 amdgpu_ras_late_fini(adev, ras_if, &ih_info); 790 kfree(ras_if); 791 } 792 } 793 794 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev, 795 uint64_t addr) 796 { 797 struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi; 798 return (addr + xgmi->physical_node_id * xgmi->node_segment_size); 799 } 800 801 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg) 802 { 803 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); 804 WREG32_PCIE(pcs_status_reg, 0); 805 } 806 807 static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev) 808 { 809 uint32_t i; 810 811 switch (adev->asic_type) { 812 case CHIP_ARCTURUS: 813 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) 814 pcs_clear_status(adev, 815 xgmi_pcs_err_status_reg_arct[i]); 816 break; 817 case CHIP_VEGA20: 818 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) 819 pcs_clear_status(adev, 820 xgmi_pcs_err_status_reg_vg20[i]); 821 break; 822 case CHIP_ALDEBARAN: 823 for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++) 824 pcs_clear_status(adev, 825 xgmi23_pcs_err_status_reg_aldebaran[i]); 826 for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++) 827 pcs_clear_status(adev, 828 xgmi23_pcs_err_status_reg_aldebaran[i]); 829 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) 830 pcs_clear_status(adev, 831 walf_pcs_err_status_reg_aldebaran[i]); 832 break; 833 default: 834 break; 835 } 836 } 837 838 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev, 839 uint32_t value, 840 uint32_t *ue_count, 841 uint32_t *ce_count, 842 bool is_xgmi_pcs) 843 { 844 int i; 845 int ue_cnt; 846 847 if (is_xgmi_pcs) { 848 /* query xgmi pcs error status, 849 * only ue is supported */ 850 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_ras_fields); i ++) { 851 ue_cnt = (value & 852 xgmi_pcs_ras_fields[i].pcs_err_mask) >> 853 xgmi_pcs_ras_fields[i].pcs_err_shift; 854 if (ue_cnt) { 855 dev_info(adev->dev, "%s detected\n", 856 xgmi_pcs_ras_fields[i].err_name); 857 *ue_count += ue_cnt; 858 } 859 } 860 } else { 861 /* query wafl pcs error status, 862 * only ue is supported */ 863 for (i = 0; i < ARRAY_SIZE(wafl_pcs_ras_fields); i++) { 864 ue_cnt = (value & 865 wafl_pcs_ras_fields[i].pcs_err_mask) >> 866 wafl_pcs_ras_fields[i].pcs_err_shift; 867 if (ue_cnt) { 868 dev_info(adev->dev, "%s detected\n", 869 wafl_pcs_ras_fields[i].err_name); 870 *ue_count += ue_cnt; 871 } 872 } 873 } 874 875 return 0; 876 } 877 878 static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, 879 void *ras_error_status) 880 { 881 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 882 int i; 883 uint32_t data; 884 uint32_t ue_cnt = 0, ce_cnt = 0; 885 886 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL)) 887 return -EINVAL; 888 889 err_data->ue_count = 0; 890 err_data->ce_count = 0; 891 892 switch (adev->asic_type) { 893 case CHIP_ARCTURUS: 894 /* check xgmi pcs error */ 895 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) { 896 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); 897 if (data) 898 amdgpu_xgmi_query_pcs_error_status(adev, 899 data, &ue_cnt, &ce_cnt, true); 900 } 901 /* check wafl pcs error */ 902 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) { 903 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); 904 if (data) 905 amdgpu_xgmi_query_pcs_error_status(adev, 906 data, &ue_cnt, &ce_cnt, false); 907 } 908 break; 909 case CHIP_VEGA20: 910 /* check xgmi pcs error */ 911 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) { 912 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); 913 if (data) 914 amdgpu_xgmi_query_pcs_error_status(adev, 915 data, &ue_cnt, &ce_cnt, true); 916 } 917 /* check wafl pcs error */ 918 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) { 919 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); 920 if (data) 921 amdgpu_xgmi_query_pcs_error_status(adev, 922 data, &ue_cnt, &ce_cnt, false); 923 } 924 break; 925 case CHIP_ALDEBARAN: 926 /* check xgmi23 pcs error */ 927 for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++) { 928 data = RREG32_PCIE(xgmi23_pcs_err_status_reg_aldebaran[i]); 929 if (data) 930 amdgpu_xgmi_query_pcs_error_status(adev, 931 data, &ue_cnt, &ce_cnt, true); 932 } 933 /* check xgmi3x16 pcs error */ 934 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) { 935 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); 936 if (data) 937 amdgpu_xgmi_query_pcs_error_status(adev, 938 data, &ue_cnt, &ce_cnt, true); 939 } 940 /* check wafl pcs error */ 941 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) { 942 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); 943 if (data) 944 amdgpu_xgmi_query_pcs_error_status(adev, 945 data, &ue_cnt, &ce_cnt, false); 946 } 947 break; 948 default: 949 dev_warn(adev->dev, "XGMI RAS error query not supported"); 950 break; 951 } 952 953 adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev); 954 955 err_data->ue_count += ue_cnt; 956 err_data->ce_count += ce_cnt; 957 958 return 0; 959 } 960 961 const struct amdgpu_xgmi_ras_funcs xgmi_ras_funcs = { 962 .ras_late_init = amdgpu_xgmi_ras_late_init, 963 .ras_fini = amdgpu_xgmi_ras_fini, 964 .query_ras_error_count = amdgpu_xgmi_query_ras_error_count, 965 .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count, 966 }; 967