1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/list.h> 25 #include "amdgpu.h" 26 #include "amdgpu_xgmi.h" 27 #include "amdgpu_ras.h" 28 #include "soc15.h" 29 #include "df/df_3_6_offset.h" 30 #include "xgmi/xgmi_4_0_0_smn.h" 31 #include "xgmi/xgmi_4_0_0_sh_mask.h" 32 #include "xgmi/xgmi_6_1_0_sh_mask.h" 33 #include "wafl/wafl2_4_0_0_smn.h" 34 #include "wafl/wafl2_4_0_0_sh_mask.h" 35 36 #include "amdgpu_reset.h" 37 38 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c 39 #define smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK 0x11a00218 40 #define smnPCS_GOPX1_PCS_ERROR_STATUS 0x12200210 41 #define smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK 0x12200218 42 43 static DEFINE_MUTEX(xgmi_mutex); 44 45 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE 4 46 47 static DRM_LIST_HEAD(xgmi_hive_list); 48 49 static const int xgmi_pcs_err_status_reg_vg20[] = { 50 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 51 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 52 }; 53 54 static const int wafl_pcs_err_status_reg_vg20[] = { 55 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 56 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 57 }; 58 59 static const int xgmi_pcs_err_status_reg_arct[] = { 60 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 61 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 62 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000, 63 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000, 64 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000, 65 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000, 66 }; 67 68 /* same as vg20*/ 69 static const int wafl_pcs_err_status_reg_arct[] = { 70 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 71 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 72 }; 73 74 static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = { 75 smnPCS_XGMI3X16_PCS_ERROR_STATUS, 76 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000, 77 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x200000, 78 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x300000, 79 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x400000, 80 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x500000, 81 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x600000, 82 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x700000 83 }; 84 85 static const int xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[] = { 86 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK, 87 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000, 88 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x200000, 89 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x300000, 90 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x400000, 91 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x500000, 92 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x600000, 93 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x700000 94 }; 95 96 static const int walf_pcs_err_status_reg_aldebaran[] = { 97 smnPCS_GOPX1_PCS_ERROR_STATUS, 98 smnPCS_GOPX1_PCS_ERROR_STATUS + 0x100000 99 }; 100 101 static const int walf_pcs_err_noncorrectable_mask_reg_aldebaran[] = { 102 smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK, 103 smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000 104 }; 105 106 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = { 107 {"XGMI PCS DataLossErr", 108 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)}, 109 {"XGMI PCS TrainingErr", 110 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)}, 111 {"XGMI PCS CRCErr", 112 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)}, 113 {"XGMI PCS BERExceededErr", 114 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)}, 115 {"XGMI PCS TxMetaDataErr", 116 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)}, 117 {"XGMI PCS ReplayBufParityErr", 118 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)}, 119 {"XGMI PCS DataParityErr", 120 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)}, 121 {"XGMI PCS ReplayFifoOverflowErr", 122 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 123 {"XGMI PCS ReplayFifoUnderflowErr", 124 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 125 {"XGMI PCS ElasticFifoOverflowErr", 126 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 127 {"XGMI PCS DeskewErr", 128 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)}, 129 {"XGMI PCS DataStartupLimitErr", 130 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)}, 131 {"XGMI PCS FCInitTimeoutErr", 132 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 133 {"XGMI PCS RecoveryTimeoutErr", 134 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 135 {"XGMI PCS ReadySerialTimeoutErr", 136 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 137 {"XGMI PCS ReadySerialAttemptErr", 138 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 139 {"XGMI PCS RecoveryAttemptErr", 140 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 141 {"XGMI PCS RecoveryRelockAttemptErr", 142 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 143 }; 144 145 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = { 146 {"WAFL PCS DataLossErr", 147 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)}, 148 {"WAFL PCS TrainingErr", 149 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)}, 150 {"WAFL PCS CRCErr", 151 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)}, 152 {"WAFL PCS BERExceededErr", 153 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)}, 154 {"WAFL PCS TxMetaDataErr", 155 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)}, 156 {"WAFL PCS ReplayBufParityErr", 157 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)}, 158 {"WAFL PCS DataParityErr", 159 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)}, 160 {"WAFL PCS ReplayFifoOverflowErr", 161 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 162 {"WAFL PCS ReplayFifoUnderflowErr", 163 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 164 {"WAFL PCS ElasticFifoOverflowErr", 165 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 166 {"WAFL PCS DeskewErr", 167 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)}, 168 {"WAFL PCS DataStartupLimitErr", 169 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)}, 170 {"WAFL PCS FCInitTimeoutErr", 171 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 172 {"WAFL PCS RecoveryTimeoutErr", 173 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 174 {"WAFL PCS ReadySerialTimeoutErr", 175 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 176 {"WAFL PCS ReadySerialAttemptErr", 177 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 178 {"WAFL PCS RecoveryAttemptErr", 179 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 180 {"WAFL PCS RecoveryRelockAttemptErr", 181 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 182 }; 183 184 static const struct amdgpu_pcs_ras_field xgmi3x16_pcs_ras_fields[] = { 185 {"XGMI3X16 PCS DataLossErr", 186 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataLossErr)}, 187 {"XGMI3X16 PCS TrainingErr", 188 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TrainingErr)}, 189 {"XGMI3X16 PCS FlowCtrlAckErr", 190 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FlowCtrlAckErr)}, 191 {"XGMI3X16 PCS RxFifoUnderflowErr", 192 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxFifoUnderflowErr)}, 193 {"XGMI3X16 PCS RxFifoOverflowErr", 194 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxFifoOverflowErr)}, 195 {"XGMI3X16 PCS CRCErr", 196 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, CRCErr)}, 197 {"XGMI3X16 PCS BERExceededErr", 198 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, BERExceededErr)}, 199 {"XGMI3X16 PCS TxVcidDataErr", 200 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TxVcidDataErr)}, 201 {"XGMI3X16 PCS ReplayBufParityErr", 202 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayBufParityErr)}, 203 {"XGMI3X16 PCS DataParityErr", 204 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataParityErr)}, 205 {"XGMI3X16 PCS ReplayFifoOverflowErr", 206 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 207 {"XGMI3X16 PCS ReplayFifoUnderflowErr", 208 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 209 {"XGMI3X16 PCS ElasticFifoOverflowErr", 210 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 211 {"XGMI3X16 PCS DeskewErr", 212 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DeskewErr)}, 213 {"XGMI3X16 PCS FlowCtrlCRCErr", 214 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FlowCtrlCRCErr)}, 215 {"XGMI3X16 PCS DataStartupLimitErr", 216 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataStartupLimitErr)}, 217 {"XGMI3X16 PCS FCInitTimeoutErr", 218 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 219 {"XGMI3X16 PCS RecoveryTimeoutErr", 220 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 221 {"XGMI3X16 PCS ReadySerialTimeoutErr", 222 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 223 {"XGMI3X16 PCS ReadySerialAttemptErr", 224 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 225 {"XGMI3X16 PCS RecoveryAttemptErr", 226 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 227 {"XGMI3X16 PCS RecoveryRelockAttemptErr", 228 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 229 {"XGMI3X16 PCS ReplayAttemptErr", 230 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayAttemptErr)}, 231 {"XGMI3X16 PCS SyncHdrErr", 232 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, SyncHdrErr)}, 233 {"XGMI3X16 PCS TxReplayTimeoutErr", 234 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TxReplayTimeoutErr)}, 235 {"XGMI3X16 PCS RxReplayTimeoutErr", 236 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxReplayTimeoutErr)}, 237 {"XGMI3X16 PCS LinkSubTxTimeoutErr", 238 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, LinkSubTxTimeoutErr)}, 239 {"XGMI3X16 PCS LinkSubRxTimeoutErr", 240 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, LinkSubRxTimeoutErr)}, 241 {"XGMI3X16 PCS RxCMDPktErr", 242 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxCMDPktErr)}, 243 }; 244 245 /** 246 * DOC: AMDGPU XGMI Support 247 * 248 * XGMI is a high speed interconnect that joins multiple GPU cards 249 * into a homogeneous memory space that is organized by a collective 250 * hive ID and individual node IDs, both of which are 64-bit numbers. 251 * 252 * The file xgmi_device_id contains the unique per GPU device ID and 253 * is stored in the /sys/class/drm/card${cardno}/device/ directory. 254 * 255 * Inside the device directory a sub-directory 'xgmi_hive_info' is 256 * created which contains the hive ID and the list of nodes. 257 * 258 * The hive ID is stored in: 259 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id 260 * 261 * The node information is stored in numbered directories: 262 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id 263 * 264 * Each device has their own xgmi_hive_info direction with a mirror 265 * set of node sub-directories. 266 * 267 * The XGMI memory space is built by contiguously adding the power of 268 * two padded VRAM space from each node to each other. 269 * 270 */ 271 272 static struct attribute amdgpu_xgmi_hive_id = { 273 .name = "xgmi_hive_id", 274 #ifdef notyet 275 .mode = S_IRUGO 276 #endif 277 }; 278 279 static struct attribute *amdgpu_xgmi_hive_attrs[] = { 280 &amdgpu_xgmi_hive_id, 281 NULL 282 }; 283 ATTRIBUTE_GROUPS(amdgpu_xgmi_hive); 284 285 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj, 286 struct attribute *attr, char *buf) 287 { 288 struct amdgpu_hive_info *hive = container_of( 289 kobj, struct amdgpu_hive_info, kobj); 290 291 if (attr == &amdgpu_xgmi_hive_id) 292 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id); 293 294 return 0; 295 } 296 297 static void amdgpu_xgmi_hive_release(struct kobject *kobj) 298 { 299 struct amdgpu_hive_info *hive = container_of( 300 kobj, struct amdgpu_hive_info, kobj); 301 302 amdgpu_reset_put_reset_domain(hive->reset_domain); 303 hive->reset_domain = NULL; 304 305 mutex_destroy(&hive->hive_lock); 306 kfree(hive); 307 } 308 309 #ifdef notyet 310 static const struct sysfs_ops amdgpu_xgmi_hive_ops = { 311 .show = amdgpu_xgmi_show_attrs, 312 }; 313 #endif 314 315 static const struct kobj_type amdgpu_xgmi_hive_type = { 316 .release = amdgpu_xgmi_hive_release, 317 #ifdef notyet 318 .sysfs_ops = &amdgpu_xgmi_hive_ops, 319 .default_groups = amdgpu_xgmi_hive_groups, 320 #endif 321 }; 322 323 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, 324 struct device_attribute *attr, 325 char *buf) 326 { 327 struct drm_device *ddev = dev_get_drvdata(dev); 328 struct amdgpu_device *adev = drm_to_adev(ddev); 329 330 return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id); 331 332 } 333 334 static ssize_t amdgpu_xgmi_show_num_hops(struct device *dev, 335 struct device_attribute *attr, 336 char *buf) 337 { 338 STUB(); 339 return -ENOSYS; 340 #ifdef __linux__ 341 struct drm_device *ddev = dev_get_drvdata(dev); 342 struct amdgpu_device *adev = drm_to_adev(ddev); 343 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 344 int i; 345 346 for (i = 0; i < top->num_nodes; i++) 347 sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_hops); 348 349 return sysfs_emit(buf, "%s\n", buf); 350 #endif 351 } 352 353 static ssize_t amdgpu_xgmi_show_num_links(struct device *dev, 354 struct device_attribute *attr, 355 char *buf) 356 { 357 STUB(); 358 return -ENOSYS; 359 #ifdef __linux__ 360 struct drm_device *ddev = dev_get_drvdata(dev); 361 struct amdgpu_device *adev = drm_to_adev(ddev); 362 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 363 int i; 364 365 for (i = 0; i < top->num_nodes; i++) 366 sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_links); 367 368 return sysfs_emit(buf, "%s\n", buf); 369 #endif 370 } 371 372 #define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801) 373 static ssize_t amdgpu_xgmi_show_error(struct device *dev, 374 struct device_attribute *attr, 375 char *buf) 376 { 377 struct drm_device *ddev = dev_get_drvdata(dev); 378 struct amdgpu_device *adev = drm_to_adev(ddev); 379 uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in; 380 uint64_t fica_out; 381 unsigned int error_count = 0; 382 383 ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200); 384 ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208); 385 386 if ((!adev->df.funcs) || 387 (!adev->df.funcs->get_fica) || 388 (!adev->df.funcs->set_fica)) 389 return -EINVAL; 390 391 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in); 392 if (fica_out != 0x1f) 393 pr_err("xGMI error counters not enabled!\n"); 394 395 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in); 396 397 if ((fica_out & 0xffff) == 2) 398 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63); 399 400 adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0); 401 402 return sysfs_emit(buf, "%u\n", error_count); 403 } 404 405 406 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL); 407 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL); 408 static DEVICE_ATTR(xgmi_num_hops, S_IRUGO, amdgpu_xgmi_show_num_hops, NULL); 409 static DEVICE_ATTR(xgmi_num_links, S_IRUGO, amdgpu_xgmi_show_num_links, NULL); 410 411 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev, 412 struct amdgpu_hive_info *hive) 413 { 414 STUB(); 415 return -ENOSYS; 416 #ifdef notyet 417 int ret = 0; 418 char node[10] = { 0 }; 419 420 /* Create xgmi device id file */ 421 ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id); 422 if (ret) { 423 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n"); 424 return ret; 425 } 426 427 /* Create xgmi error file */ 428 ret = device_create_file(adev->dev, &dev_attr_xgmi_error); 429 if (ret) 430 pr_err("failed to create xgmi_error\n"); 431 432 /* Create xgmi num hops file */ 433 ret = device_create_file(adev->dev, &dev_attr_xgmi_num_hops); 434 if (ret) 435 pr_err("failed to create xgmi_num_hops\n"); 436 437 /* Create xgmi num links file */ 438 ret = device_create_file(adev->dev, &dev_attr_xgmi_num_links); 439 if (ret) 440 pr_err("failed to create xgmi_num_links\n"); 441 442 /* Create sysfs link to hive info folder on the first device */ 443 if (hive->kobj.parent != (&adev->dev->kobj)) { 444 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj, 445 "xgmi_hive_info"); 446 if (ret) { 447 dev_err(adev->dev, "XGMI: Failed to create link to hive info"); 448 goto remove_file; 449 } 450 } 451 452 snprintf(node, sizeof(node), "node%d", atomic_read(&hive->number_devices)); 453 /* Create sysfs link form the hive folder to yourself */ 454 ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node); 455 if (ret) { 456 dev_err(adev->dev, "XGMI: Failed to create link from hive info"); 457 goto remove_link; 458 } 459 460 goto success; 461 462 463 remove_link: 464 sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique); 465 466 remove_file: 467 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 468 device_remove_file(adev->dev, &dev_attr_xgmi_error); 469 device_remove_file(adev->dev, &dev_attr_xgmi_num_hops); 470 device_remove_file(adev->dev, &dev_attr_xgmi_num_links); 471 472 success: 473 return ret; 474 #endif 475 } 476 477 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev, 478 struct amdgpu_hive_info *hive) 479 { 480 #ifdef __linux__ 481 char node[10]; 482 memset(node, 0, sizeof(node)); 483 484 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 485 device_remove_file(adev->dev, &dev_attr_xgmi_error); 486 device_remove_file(adev->dev, &dev_attr_xgmi_num_hops); 487 device_remove_file(adev->dev, &dev_attr_xgmi_num_links); 488 489 if (hive->kobj.parent != (&adev->dev->kobj)) 490 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info"); 491 492 sprintf(node, "node%d", atomic_read(&hive->number_devices)); 493 sysfs_remove_link(&hive->kobj, node); 494 #endif 495 } 496 497 498 499 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) 500 { 501 struct amdgpu_hive_info *hive = NULL; 502 int ret; 503 504 if (!adev->gmc.xgmi.hive_id) 505 return NULL; 506 507 STUB(); 508 return NULL; 509 #ifdef notyet 510 511 if (adev->hive) { 512 kobject_get(&adev->hive->kobj); 513 return adev->hive; 514 } 515 516 mutex_lock(&xgmi_mutex); 517 518 list_for_each_entry(hive, &xgmi_hive_list, node) { 519 if (hive->hive_id == adev->gmc.xgmi.hive_id) 520 goto pro_end; 521 } 522 523 hive = kzalloc(sizeof(*hive), GFP_KERNEL); 524 if (!hive) { 525 dev_err(adev->dev, "XGMI: allocation failed\n"); 526 ret = -ENOMEM; 527 hive = NULL; 528 goto pro_end; 529 } 530 531 /* initialize new hive if not exist */ 532 ret = kobject_init_and_add(&hive->kobj, 533 &amdgpu_xgmi_hive_type, 534 &adev->dev->kobj, 535 "%s", "xgmi_hive_info"); 536 if (ret) { 537 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n"); 538 kobject_put(&hive->kobj); 539 hive = NULL; 540 goto pro_end; 541 } 542 543 /** 544 * Only init hive->reset_domain for none SRIOV configuration. For SRIOV, 545 * Host driver decide how to reset the GPU either through FLR or chain reset. 546 * Guest side will get individual notifications from the host for the FLR 547 * if necessary. 548 */ 549 if (!amdgpu_sriov_vf(adev)) { 550 /** 551 * Avoid recreating reset domain when hive is reconstructed for the case 552 * of reset the devices in the XGMI hive during probe for passthrough GPU 553 * See https://www.spinics.net/lists/amd-gfx/msg58836.html 554 */ 555 if (adev->reset_domain->type != XGMI_HIVE) { 556 hive->reset_domain = 557 amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive"); 558 if (!hive->reset_domain) { 559 dev_err(adev->dev, "XGMI: failed initializing reset domain for xgmi hive\n"); 560 ret = -ENOMEM; 561 kobject_put(&hive->kobj); 562 hive = NULL; 563 goto pro_end; 564 } 565 } else { 566 amdgpu_reset_get_reset_domain(adev->reset_domain); 567 hive->reset_domain = adev->reset_domain; 568 } 569 } 570 571 hive->hive_id = adev->gmc.xgmi.hive_id; 572 INIT_LIST_HEAD(&hive->device_list); 573 INIT_LIST_HEAD(&hive->node); 574 rw_init(&hive->hive_lock, "aghive"); 575 atomic_set(&hive->number_devices, 0); 576 task_barrier_init(&hive->tb); 577 hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN; 578 hive->hi_req_gpu = NULL; 579 580 /* 581 * hive pstate on boot is high in vega20 so we have to go to low 582 * pstate on after boot. 583 */ 584 hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE; 585 list_add_tail(&hive->node, &xgmi_hive_list); 586 587 pro_end: 588 if (hive) 589 kobject_get(&hive->kobj); 590 mutex_unlock(&xgmi_mutex); 591 return hive; 592 #endif 593 } 594 595 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive) 596 { 597 if (hive) 598 kobject_put(&hive->kobj); 599 } 600 601 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate) 602 { 603 int ret = 0; 604 struct amdgpu_hive_info *hive; 605 struct amdgpu_device *request_adev; 606 bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20; 607 bool init_low; 608 609 hive = amdgpu_get_xgmi_hive(adev); 610 if (!hive) 611 return 0; 612 613 request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev; 614 init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN; 615 amdgpu_put_xgmi_hive(hive); 616 /* fw bug so temporarily disable pstate switching */ 617 return 0; 618 619 if (!hive || adev->asic_type != CHIP_VEGA20) 620 return 0; 621 622 mutex_lock(&hive->hive_lock); 623 624 if (is_hi_req) 625 hive->hi_req_count++; 626 else 627 hive->hi_req_count--; 628 629 /* 630 * Vega20 only needs single peer to request pstate high for the hive to 631 * go high but all peers must request pstate low for the hive to go low 632 */ 633 if (hive->pstate == pstate || 634 (!is_hi_req && hive->hi_req_count && !init_low)) 635 goto out; 636 637 dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate); 638 639 ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate); 640 if (ret) { 641 dev_err(request_adev->dev, 642 "XGMI: Set pstate failure on device %llx, hive %llx, ret %d", 643 request_adev->gmc.xgmi.node_id, 644 request_adev->gmc.xgmi.hive_id, ret); 645 goto out; 646 } 647 648 if (init_low) 649 hive->pstate = hive->hi_req_count ? 650 hive->pstate : AMDGPU_XGMI_PSTATE_MIN; 651 else { 652 hive->pstate = pstate; 653 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ? 654 adev : NULL; 655 } 656 out: 657 mutex_unlock(&hive->hive_lock); 658 return ret; 659 } 660 661 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev) 662 { 663 int ret; 664 665 if (amdgpu_sriov_vf(adev)) 666 return 0; 667 668 /* Each psp need to set the latest topology */ 669 ret = psp_xgmi_set_topology_info(&adev->psp, 670 atomic_read(&hive->number_devices), 671 &adev->psp.xgmi_context.top_info); 672 if (ret) 673 dev_err(adev->dev, 674 "XGMI: Set topology failure on device %llx, hive %llx, ret %d", 675 adev->gmc.xgmi.node_id, 676 adev->gmc.xgmi.hive_id, ret); 677 678 return ret; 679 } 680 681 682 /* 683 * NOTE psp_xgmi_node_info.num_hops layout is as follows: 684 * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved) 685 * num_hops[5:3] = reserved 686 * num_hops[2:0] = number of hops 687 */ 688 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, 689 struct amdgpu_device *peer_adev) 690 { 691 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 692 uint8_t num_hops_mask = 0x7; 693 int i; 694 695 for (i = 0 ; i < top->num_nodes; ++i) 696 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 697 return top->nodes[i].num_hops & num_hops_mask; 698 return -EINVAL; 699 } 700 701 int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev, 702 struct amdgpu_device *peer_adev) 703 { 704 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 705 int i; 706 707 for (i = 0 ; i < top->num_nodes; ++i) 708 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 709 return top->nodes[i].num_links; 710 return -EINVAL; 711 } 712 713 /* 714 * Devices that support extended data require the entire hive to initialize with 715 * the shared memory buffer flag set. 716 * 717 * Hive locks and conditions apply - see amdgpu_xgmi_add_device 718 */ 719 static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info *hive, 720 bool set_extended_data) 721 { 722 struct amdgpu_device *tmp_adev; 723 int ret; 724 725 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 726 ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false); 727 if (ret) { 728 dev_err(tmp_adev->dev, 729 "XGMI: Failed to initialize xgmi session for data partition %i\n", 730 set_extended_data); 731 return ret; 732 } 733 734 } 735 736 return 0; 737 } 738 739 int amdgpu_xgmi_add_device(struct amdgpu_device *adev) 740 { 741 struct psp_xgmi_topology_info *top_info; 742 struct amdgpu_hive_info *hive; 743 struct amdgpu_xgmi *entry; 744 struct amdgpu_device *tmp_adev = NULL; 745 746 int count = 0, ret = 0; 747 748 if (!adev->gmc.xgmi.supported) 749 return 0; 750 751 if (!adev->gmc.xgmi.pending_reset && 752 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 753 ret = psp_xgmi_initialize(&adev->psp, false, true); 754 if (ret) { 755 dev_err(adev->dev, 756 "XGMI: Failed to initialize xgmi session\n"); 757 return ret; 758 } 759 760 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id); 761 if (ret) { 762 dev_err(adev->dev, 763 "XGMI: Failed to get hive id\n"); 764 return ret; 765 } 766 767 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id); 768 if (ret) { 769 dev_err(adev->dev, 770 "XGMI: Failed to get node id\n"); 771 return ret; 772 } 773 } else { 774 adev->gmc.xgmi.hive_id = 16; 775 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16; 776 } 777 778 hive = amdgpu_get_xgmi_hive(adev); 779 if (!hive) { 780 ret = -EINVAL; 781 dev_err(adev->dev, 782 "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n", 783 adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id); 784 goto exit; 785 } 786 mutex_lock(&hive->hive_lock); 787 788 top_info = &adev->psp.xgmi_context.top_info; 789 790 list_add_tail(&adev->gmc.xgmi.head, &hive->device_list); 791 list_for_each_entry(entry, &hive->device_list, head) 792 top_info->nodes[count++].node_id = entry->node_id; 793 top_info->num_nodes = count; 794 atomic_set(&hive->number_devices, count); 795 796 task_barrier_add_task(&hive->tb); 797 798 if (!adev->gmc.xgmi.pending_reset && 799 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 800 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 801 /* update node list for other device in the hive */ 802 if (tmp_adev != adev) { 803 top_info = &tmp_adev->psp.xgmi_context.top_info; 804 top_info->nodes[count - 1].node_id = 805 adev->gmc.xgmi.node_id; 806 top_info->num_nodes = count; 807 } 808 ret = amdgpu_xgmi_update_topology(hive, tmp_adev); 809 if (ret) 810 goto exit_unlock; 811 } 812 813 /* get latest topology info for each device from psp */ 814 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 815 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 816 &tmp_adev->psp.xgmi_context.top_info, false); 817 if (ret) { 818 dev_err(tmp_adev->dev, 819 "XGMI: Get topology failure on device %llx, hive %llx, ret %d", 820 tmp_adev->gmc.xgmi.node_id, 821 tmp_adev->gmc.xgmi.hive_id, ret); 822 /* To do : continue with some node failed or disable the whole hive */ 823 goto exit_unlock; 824 } 825 } 826 827 /* get topology again for hives that support extended data */ 828 if (adev->psp.xgmi_context.supports_extended_data) { 829 830 /* initialize the hive to get extended data. */ 831 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true); 832 if (ret) 833 goto exit_unlock; 834 835 /* get the extended data. */ 836 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 837 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 838 &tmp_adev->psp.xgmi_context.top_info, true); 839 if (ret) { 840 dev_err(tmp_adev->dev, 841 "XGMI: Get topology for extended data failure on device %llx, hive %llx, ret %d", 842 tmp_adev->gmc.xgmi.node_id, 843 tmp_adev->gmc.xgmi.hive_id, ret); 844 goto exit_unlock; 845 } 846 } 847 848 /* initialize the hive to get non-extended data for the next round. */ 849 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false); 850 if (ret) 851 goto exit_unlock; 852 853 } 854 } 855 856 if (!ret && !adev->gmc.xgmi.pending_reset) 857 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive); 858 859 exit_unlock: 860 mutex_unlock(&hive->hive_lock); 861 exit: 862 if (!ret) { 863 adev->hive = hive; 864 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n", 865 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id); 866 } else { 867 amdgpu_put_xgmi_hive(hive); 868 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n", 869 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id, 870 ret); 871 } 872 873 return ret; 874 } 875 876 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev) 877 { 878 struct amdgpu_hive_info *hive = adev->hive; 879 880 if (!adev->gmc.xgmi.supported) 881 return -EINVAL; 882 883 if (!hive) 884 return -EINVAL; 885 886 mutex_lock(&hive->hive_lock); 887 task_barrier_rem_task(&hive->tb); 888 amdgpu_xgmi_sysfs_rem_dev_info(adev, hive); 889 if (hive->hi_req_gpu == adev) 890 hive->hi_req_gpu = NULL; 891 list_del(&adev->gmc.xgmi.head); 892 mutex_unlock(&hive->hive_lock); 893 894 amdgpu_put_xgmi_hive(hive); 895 adev->hive = NULL; 896 897 if (atomic_dec_return(&hive->number_devices) == 0) { 898 /* Remove the hive from global hive list */ 899 mutex_lock(&xgmi_mutex); 900 list_del(&hive->node); 901 mutex_unlock(&xgmi_mutex); 902 903 amdgpu_put_xgmi_hive(hive); 904 } 905 906 return 0; 907 } 908 909 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 910 { 911 if (!adev->gmc.xgmi.supported || 912 adev->gmc.xgmi.num_physical_nodes == 0) 913 return 0; 914 915 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); 916 917 return amdgpu_ras_block_late_init(adev, ras_block); 918 } 919 920 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev, 921 uint64_t addr) 922 { 923 struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi; 924 return (addr + xgmi->physical_node_id * xgmi->node_segment_size); 925 } 926 927 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg) 928 { 929 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); 930 WREG32_PCIE(pcs_status_reg, 0); 931 } 932 933 static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev) 934 { 935 uint32_t i; 936 937 switch (adev->asic_type) { 938 case CHIP_ARCTURUS: 939 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) 940 pcs_clear_status(adev, 941 xgmi_pcs_err_status_reg_arct[i]); 942 break; 943 case CHIP_VEGA20: 944 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) 945 pcs_clear_status(adev, 946 xgmi_pcs_err_status_reg_vg20[i]); 947 break; 948 case CHIP_ALDEBARAN: 949 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) 950 pcs_clear_status(adev, 951 xgmi3x16_pcs_err_status_reg_aldebaran[i]); 952 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) 953 pcs_clear_status(adev, 954 walf_pcs_err_status_reg_aldebaran[i]); 955 break; 956 default: 957 break; 958 } 959 } 960 961 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev, 962 uint32_t value, 963 uint32_t mask_value, 964 uint32_t *ue_count, 965 uint32_t *ce_count, 966 bool is_xgmi_pcs, 967 bool check_mask) 968 { 969 int i; 970 int ue_cnt = 0; 971 const struct amdgpu_pcs_ras_field *pcs_ras_fields = NULL; 972 uint32_t field_array_size = 0; 973 974 if (is_xgmi_pcs) { 975 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) { 976 pcs_ras_fields = &xgmi3x16_pcs_ras_fields[0]; 977 field_array_size = ARRAY_SIZE(xgmi3x16_pcs_ras_fields); 978 } else { 979 pcs_ras_fields = &xgmi_pcs_ras_fields[0]; 980 field_array_size = ARRAY_SIZE(xgmi_pcs_ras_fields); 981 } 982 } else { 983 pcs_ras_fields = &wafl_pcs_ras_fields[0]; 984 field_array_size = ARRAY_SIZE(wafl_pcs_ras_fields); 985 } 986 987 if (check_mask) 988 value = value & ~mask_value; 989 990 /* query xgmi/walf pcs error status, 991 * only ue is supported */ 992 for (i = 0; value && i < field_array_size; i++) { 993 ue_cnt = (value & 994 pcs_ras_fields[i].pcs_err_mask) >> 995 pcs_ras_fields[i].pcs_err_shift; 996 if (ue_cnt) { 997 dev_info(adev->dev, "%s detected\n", 998 pcs_ras_fields[i].err_name); 999 *ue_count += ue_cnt; 1000 } 1001 1002 /* reset bit value if the bit is checked */ 1003 value &= ~(pcs_ras_fields[i].pcs_err_mask); 1004 } 1005 1006 return 0; 1007 } 1008 1009 static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, 1010 void *ras_error_status) 1011 { 1012 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 1013 int i; 1014 uint32_t data, mask_data = 0; 1015 uint32_t ue_cnt = 0, ce_cnt = 0; 1016 1017 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL)) 1018 return ; 1019 1020 err_data->ue_count = 0; 1021 err_data->ce_count = 0; 1022 1023 switch (adev->asic_type) { 1024 case CHIP_ARCTURUS: 1025 /* check xgmi pcs error */ 1026 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) { 1027 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); 1028 if (data) 1029 amdgpu_xgmi_query_pcs_error_status(adev, data, 1030 mask_data, &ue_cnt, &ce_cnt, true, false); 1031 } 1032 /* check wafl pcs error */ 1033 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) { 1034 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); 1035 if (data) 1036 amdgpu_xgmi_query_pcs_error_status(adev, data, 1037 mask_data, &ue_cnt, &ce_cnt, false, false); 1038 } 1039 break; 1040 case CHIP_VEGA20: 1041 /* check xgmi pcs error */ 1042 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) { 1043 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); 1044 if (data) 1045 amdgpu_xgmi_query_pcs_error_status(adev, data, 1046 mask_data, &ue_cnt, &ce_cnt, true, false); 1047 } 1048 /* check wafl pcs error */ 1049 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) { 1050 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); 1051 if (data) 1052 amdgpu_xgmi_query_pcs_error_status(adev, data, 1053 mask_data, &ue_cnt, &ce_cnt, false, false); 1054 } 1055 break; 1056 case CHIP_ALDEBARAN: 1057 /* check xgmi3x16 pcs error */ 1058 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) { 1059 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); 1060 mask_data = 1061 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[i]); 1062 if (data) 1063 amdgpu_xgmi_query_pcs_error_status(adev, data, 1064 mask_data, &ue_cnt, &ce_cnt, true, true); 1065 } 1066 /* check wafl pcs error */ 1067 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) { 1068 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); 1069 mask_data = 1070 RREG32_PCIE(walf_pcs_err_noncorrectable_mask_reg_aldebaran[i]); 1071 if (data) 1072 amdgpu_xgmi_query_pcs_error_status(adev, data, 1073 mask_data, &ue_cnt, &ce_cnt, false, true); 1074 } 1075 break; 1076 default: 1077 dev_warn(adev->dev, "XGMI RAS error query not supported"); 1078 break; 1079 } 1080 1081 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1082 1083 err_data->ue_count += ue_cnt; 1084 err_data->ce_count += ce_cnt; 1085 } 1086 1087 /* Trigger XGMI/WAFL error */ 1088 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, 1089 void *inject_if, uint32_t instance_mask) 1090 { 1091 int ret = 0; 1092 struct ta_ras_trigger_error_input *block_info = 1093 (struct ta_ras_trigger_error_input *)inject_if; 1094 1095 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) 1096 dev_warn(adev->dev, "Failed to disallow df cstate"); 1097 1098 if (amdgpu_dpm_allow_xgmi_power_down(adev, false)) 1099 dev_warn(adev->dev, "Failed to disallow XGMI power down"); 1100 1101 ret = psp_ras_trigger_error(&adev->psp, block_info, instance_mask); 1102 1103 if (amdgpu_ras_intr_triggered()) 1104 return ret; 1105 1106 if (amdgpu_dpm_allow_xgmi_power_down(adev, true)) 1107 dev_warn(adev->dev, "Failed to allow XGMI power down"); 1108 1109 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW)) 1110 dev_warn(adev->dev, "Failed to allow df cstate"); 1111 1112 return ret; 1113 } 1114 1115 struct amdgpu_ras_block_hw_ops xgmi_ras_hw_ops = { 1116 .query_ras_error_count = amdgpu_xgmi_query_ras_error_count, 1117 .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count, 1118 .ras_error_inject = amdgpu_ras_error_inject_xgmi, 1119 }; 1120 1121 struct amdgpu_xgmi_ras xgmi_ras = { 1122 .ras_block = { 1123 .hw_ops = &xgmi_ras_hw_ops, 1124 .ras_late_init = amdgpu_xgmi_ras_late_init, 1125 }, 1126 }; 1127 1128 int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev) 1129 { 1130 int err; 1131 struct amdgpu_xgmi_ras *ras; 1132 1133 if (!adev->gmc.xgmi.ras) 1134 return 0; 1135 1136 ras = adev->gmc.xgmi.ras; 1137 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1138 if (err) { 1139 dev_err(adev->dev, "Failed to register xgmi_wafl_pcs ras block!\n"); 1140 return err; 1141 } 1142 1143 strlcpy(ras->ras_block.ras_comm.name, "xgmi_wafl", 1144 sizeof(ras->ras_block.ras_comm.name)); 1145 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__XGMI_WAFL; 1146 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 1147 adev->gmc.xgmi.ras_if = &ras->ras_block.ras_comm; 1148 1149 return 0; 1150 } 1151