1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 26 #include <drm/drm_drv.h> 27 #include <xen/xen.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ras.h" 31 #include "vi.h" 32 #include "soc15.h" 33 #include "nv.h" 34 35 #define POPULATE_UCODE_INFO(vf2pf_info, ucode, ver) \ 36 do { \ 37 vf2pf_info->ucode_info[ucode].id = ucode; \ 38 vf2pf_info->ucode_info[ucode].version = ver; \ 39 } while (0) 40 41 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) 42 { 43 /* By now all MMIO pages except mailbox are blocked */ 44 /* if blocking is enabled in hypervisor. Choose the */ 45 /* SCRATCH_REG0 to test. */ 46 return RREG32_NO_KIQ(0xc040) == 0xffffffff; 47 } 48 49 void amdgpu_virt_init_setting(struct amdgpu_device *adev) 50 { 51 struct drm_device *ddev = adev_to_drm(adev); 52 53 /* enable virtual display */ 54 if (adev->asic_type != CHIP_ALDEBARAN && 55 adev->asic_type != CHIP_ARCTURUS) { 56 if (adev->mode_info.num_crtc == 0) 57 adev->mode_info.num_crtc = 1; 58 adev->enable_virtual_display = true; 59 } 60 ddev->driver_features &= ~DRIVER_ATOMIC; 61 adev->cg_flags = 0; 62 adev->pg_flags = 0; 63 } 64 65 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 66 uint32_t reg0, uint32_t reg1, 67 uint32_t ref, uint32_t mask) 68 { 69 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 70 struct amdgpu_ring *ring = &kiq->ring; 71 signed long r, cnt = 0; 72 unsigned long flags; 73 uint32_t seq; 74 75 spin_lock_irqsave(&kiq->ring_lock, flags); 76 amdgpu_ring_alloc(ring, 32); 77 amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1, 78 ref, mask); 79 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 80 if (r) 81 goto failed_undo; 82 83 amdgpu_ring_commit(ring); 84 spin_unlock_irqrestore(&kiq->ring_lock, flags); 85 86 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 87 88 /* don't wait anymore for IRQ context */ 89 if (r < 1 && in_interrupt()) 90 goto failed_kiq; 91 92 might_sleep(); 93 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 94 95 drm_msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 96 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 97 } 98 99 if (cnt > MAX_KIQ_REG_TRY) 100 goto failed_kiq; 101 102 return; 103 104 failed_undo: 105 amdgpu_ring_undo(ring); 106 spin_unlock_irqrestore(&kiq->ring_lock, flags); 107 failed_kiq: 108 dev_err(adev->dev, "failed to write reg %x wait reg %x\n", reg0, reg1); 109 } 110 111 /** 112 * amdgpu_virt_request_full_gpu() - request full gpu access 113 * @adev: amdgpu device. 114 * @init: is driver init time. 115 * When start to init/fini driver, first need to request full gpu access. 116 * Return: Zero if request success, otherwise will return error. 117 */ 118 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) 119 { 120 struct amdgpu_virt *virt = &adev->virt; 121 int r; 122 123 if (virt->ops && virt->ops->req_full_gpu) { 124 r = virt->ops->req_full_gpu(adev, init); 125 if (r) 126 return r; 127 128 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 129 } 130 131 return 0; 132 } 133 134 /** 135 * amdgpu_virt_release_full_gpu() - release full gpu access 136 * @adev: amdgpu device. 137 * @init: is driver init time. 138 * When finishing driver init/fini, need to release full gpu access. 139 * Return: Zero if release success, otherwise will returen error. 140 */ 141 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) 142 { 143 struct amdgpu_virt *virt = &adev->virt; 144 int r; 145 146 if (virt->ops && virt->ops->rel_full_gpu) { 147 r = virt->ops->rel_full_gpu(adev, init); 148 if (r) 149 return r; 150 151 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 152 } 153 return 0; 154 } 155 156 /** 157 * amdgpu_virt_reset_gpu() - reset gpu 158 * @adev: amdgpu device. 159 * Send reset command to GPU hypervisor to reset GPU that VM is using 160 * Return: Zero if reset success, otherwise will return error. 161 */ 162 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) 163 { 164 struct amdgpu_virt *virt = &adev->virt; 165 int r; 166 167 if (virt->ops && virt->ops->reset_gpu) { 168 r = virt->ops->reset_gpu(adev); 169 if (r) 170 return r; 171 172 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 173 } 174 175 return 0; 176 } 177 178 void amdgpu_virt_request_init_data(struct amdgpu_device *adev) 179 { 180 struct amdgpu_virt *virt = &adev->virt; 181 182 if (virt->ops && virt->ops->req_init_data) 183 virt->ops->req_init_data(adev); 184 185 if (adev->virt.req_init_data_ver > 0) 186 DRM_INFO("host supports REQ_INIT_DATA handshake\n"); 187 else 188 DRM_WARN("host doesn't support REQ_INIT_DATA handshake\n"); 189 } 190 191 /** 192 * amdgpu_virt_wait_reset() - wait for reset gpu completed 193 * @adev: amdgpu device. 194 * Wait for GPU reset completed. 195 * Return: Zero if reset success, otherwise will return error. 196 */ 197 int amdgpu_virt_wait_reset(struct amdgpu_device *adev) 198 { 199 struct amdgpu_virt *virt = &adev->virt; 200 201 if (!virt->ops || !virt->ops->wait_reset) 202 return -EINVAL; 203 204 return virt->ops->wait_reset(adev); 205 } 206 207 /** 208 * amdgpu_virt_alloc_mm_table() - alloc memory for mm table 209 * @adev: amdgpu device. 210 * MM table is used by UVD and VCE for its initialization 211 * Return: Zero if allocate success. 212 */ 213 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) 214 { 215 int r; 216 217 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 218 return 0; 219 220 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, 221 AMDGPU_GEM_DOMAIN_VRAM, 222 &adev->virt.mm_table.bo, 223 &adev->virt.mm_table.gpu_addr, 224 (void *)&adev->virt.mm_table.cpu_addr); 225 if (r) { 226 DRM_ERROR("failed to alloc mm table and error = %d.\n", r); 227 return r; 228 } 229 230 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); 231 DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n", 232 adev->virt.mm_table.gpu_addr, 233 adev->virt.mm_table.cpu_addr); 234 return 0; 235 } 236 237 /** 238 * amdgpu_virt_free_mm_table() - free mm table memory 239 * @adev: amdgpu device. 240 * Free MM table memory 241 */ 242 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) 243 { 244 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 245 return; 246 247 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, 248 &adev->virt.mm_table.gpu_addr, 249 (void *)&adev->virt.mm_table.cpu_addr); 250 adev->virt.mm_table.gpu_addr = 0; 251 } 252 253 254 unsigned int amd_sriov_msg_checksum(void *obj, 255 unsigned long obj_size, 256 unsigned int key, 257 unsigned int checksum) 258 { 259 unsigned int ret = key; 260 unsigned long i = 0; 261 unsigned char *pos; 262 263 pos = (char *)obj; 264 /* calculate checksum */ 265 for (i = 0; i < obj_size; ++i) 266 ret += *(pos + i); 267 /* minus the checksum itself */ 268 pos = (char *)&checksum; 269 for (i = 0; i < sizeof(checksum); ++i) 270 ret -= *(pos + i); 271 return ret; 272 } 273 274 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) 275 { 276 struct amdgpu_virt *virt = &adev->virt; 277 struct amdgpu_virt_ras_err_handler_data **data = &virt->virt_eh_data; 278 /* GPU will be marked bad on host if bp count more then 10, 279 * so alloc 512 is enough. 280 */ 281 unsigned int align_space = 512; 282 void *bps = NULL; 283 struct amdgpu_bo **bps_bo = NULL; 284 285 *data = kmalloc(sizeof(struct amdgpu_virt_ras_err_handler_data), GFP_KERNEL); 286 if (!*data) 287 return -ENOMEM; 288 289 bps = kmalloc_array(align_space, sizeof((*data)->bps), GFP_KERNEL); 290 bps_bo = kmalloc_array(align_space, sizeof((*data)->bps_bo), GFP_KERNEL); 291 292 if (!bps || !bps_bo) { 293 kfree(bps); 294 kfree(bps_bo); 295 kfree(*data); 296 return -ENOMEM; 297 } 298 299 (*data)->bps = bps; 300 (*data)->bps_bo = bps_bo; 301 (*data)->count = 0; 302 (*data)->last_reserved = 0; 303 304 virt->ras_init_done = true; 305 306 return 0; 307 } 308 309 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) 310 { 311 struct amdgpu_virt *virt = &adev->virt; 312 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 313 struct amdgpu_bo *bo; 314 int i; 315 316 if (!data) 317 return; 318 319 for (i = data->last_reserved - 1; i >= 0; i--) { 320 bo = data->bps_bo[i]; 321 amdgpu_bo_free_kernel(&bo, NULL, NULL); 322 data->bps_bo[i] = bo; 323 data->last_reserved = i; 324 } 325 } 326 327 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) 328 { 329 struct amdgpu_virt *virt = &adev->virt; 330 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 331 332 virt->ras_init_done = false; 333 334 if (!data) 335 return; 336 337 amdgpu_virt_ras_release_bp(adev); 338 339 kfree(data->bps); 340 kfree(data->bps_bo); 341 kfree(data); 342 virt->virt_eh_data = NULL; 343 } 344 345 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, 346 struct eeprom_table_record *bps, int pages) 347 { 348 struct amdgpu_virt *virt = &adev->virt; 349 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 350 351 if (!data) 352 return; 353 354 memcpy(&data->bps[data->count], bps, pages * sizeof(*data->bps)); 355 data->count += pages; 356 } 357 358 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) 359 { 360 struct amdgpu_virt *virt = &adev->virt; 361 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 362 struct amdgpu_bo *bo = NULL; 363 uint64_t bp; 364 int i; 365 366 if (!data) 367 return; 368 369 for (i = data->last_reserved; i < data->count; i++) { 370 bp = data->bps[i].retired_page; 371 372 /* There are two cases of reserve error should be ignored: 373 * 1) a ras bad page has been allocated (used by someone); 374 * 2) a ras bad page has been reserved (duplicate error injection 375 * for one page); 376 */ 377 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, 378 AMDGPU_GPU_PAGE_SIZE, 379 AMDGPU_GEM_DOMAIN_VRAM, 380 &bo, NULL)) 381 DRM_DEBUG("RAS WARN: reserve vram for retired page %llx fail\n", bp); 382 383 data->bps_bo[i] = bo; 384 data->last_reserved = i + 1; 385 bo = NULL; 386 } 387 } 388 389 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, 390 uint64_t retired_page) 391 { 392 struct amdgpu_virt *virt = &adev->virt; 393 struct amdgpu_virt_ras_err_handler_data *data = virt->virt_eh_data; 394 int i; 395 396 if (!data) 397 return true; 398 399 for (i = 0; i < data->count; i++) 400 if (retired_page == data->bps[i].retired_page) 401 return true; 402 403 return false; 404 } 405 406 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, 407 uint64_t bp_block_offset, uint32_t bp_block_size) 408 { 409 struct eeprom_table_record bp; 410 uint64_t retired_page; 411 uint32_t bp_idx, bp_cnt; 412 413 if (bp_block_size) { 414 bp_cnt = bp_block_size / sizeof(uint64_t); 415 for (bp_idx = 0; bp_idx < bp_cnt; bp_idx++) { 416 retired_page = *(uint64_t *)(adev->mman.fw_vram_usage_va + 417 bp_block_offset + bp_idx * sizeof(uint64_t)); 418 bp.retired_page = retired_page; 419 420 if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) 421 continue; 422 423 amdgpu_virt_ras_add_bps(adev, &bp, 1); 424 425 amdgpu_virt_ras_reserve_bps(adev); 426 } 427 } 428 } 429 430 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 431 { 432 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; 433 uint32_t checksum; 434 uint32_t checkval; 435 436 uint32_t i; 437 uint32_t tmp; 438 439 if (adev->virt.fw_reserve.p_pf2vf == NULL) 440 return -EINVAL; 441 442 if (pf2vf_info->size > 1024) { 443 DRM_ERROR("invalid pf2vf message size\n"); 444 return -EINVAL; 445 } 446 447 switch (pf2vf_info->version) { 448 case 1: 449 checksum = ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->checksum; 450 checkval = amd_sriov_msg_checksum( 451 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 452 adev->virt.fw_reserve.checksum_key, checksum); 453 if (checksum != checkval) { 454 DRM_ERROR("invalid pf2vf message\n"); 455 return -EINVAL; 456 } 457 458 adev->virt.gim_feature = 459 ((struct amdgim_pf2vf_info_v1 *)pf2vf_info)->feature_flags; 460 break; 461 case 2: 462 /* TODO: missing key, need to add it later */ 463 checksum = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->checksum; 464 checkval = amd_sriov_msg_checksum( 465 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, 466 0, checksum); 467 if (checksum != checkval) { 468 DRM_ERROR("invalid pf2vf message\n"); 469 return -EINVAL; 470 } 471 472 adev->virt.vf2pf_update_interval_ms = 473 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->vf2pf_update_interval_ms; 474 adev->virt.gim_feature = 475 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->feature_flags.all; 476 adev->virt.reg_access = 477 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->reg_access_flags.all; 478 479 adev->virt.decode_max_dimension_pixels = 0; 480 adev->virt.decode_max_frame_pixels = 0; 481 adev->virt.encode_max_dimension_pixels = 0; 482 adev->virt.encode_max_frame_pixels = 0; 483 adev->virt.is_mm_bw_enabled = false; 484 for (i = 0; i < AMD_SRIOV_MSG_RESERVE_VCN_INST; i++) { 485 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_dimension_pixels; 486 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); 487 488 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].decode_max_frame_pixels; 489 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); 490 491 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_dimension_pixels; 492 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); 493 494 tmp = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->mm_bw_management[i].encode_max_frame_pixels; 495 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); 496 } 497 if((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) 498 adev->virt.is_mm_bw_enabled = true; 499 500 adev->unique_id = 501 ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; 502 break; 503 default: 504 DRM_ERROR("invalid pf2vf version\n"); 505 return -EINVAL; 506 } 507 508 /* correct too large or too little interval value */ 509 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) 510 adev->virt.vf2pf_update_interval_ms = 2000; 511 512 return 0; 513 } 514 515 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) 516 { 517 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 518 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 519 520 if (adev->virt.fw_reserve.p_vf2pf == NULL) 521 return; 522 523 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); 524 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); 525 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); 526 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); 527 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); 528 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); 529 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); 530 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); 531 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); 532 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); 533 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); 534 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); 535 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); 536 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ASD, adev->psp.asd.fw_version); 537 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_RAS, adev->psp.ras.feature_version); 538 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_TA_XGMI, adev->psp.xgmi.feature_version); 539 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); 540 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); 541 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); 542 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); 543 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); 544 } 545 546 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) 547 { 548 struct amd_sriov_msg_vf2pf_info *vf2pf_info; 549 struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 550 551 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; 552 553 if (adev->virt.fw_reserve.p_vf2pf == NULL) 554 return -EINVAL; 555 556 memset(vf2pf_info, 0, sizeof(struct amd_sriov_msg_vf2pf_info)); 557 558 vf2pf_info->header.size = sizeof(struct amd_sriov_msg_vf2pf_info); 559 vf2pf_info->header.version = AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER; 560 561 #ifdef MODULE 562 if (THIS_MODULE->version != NULL) 563 strcpy(vf2pf_info->driver_version, THIS_MODULE->version); 564 else 565 #endif 566 strlcpy(vf2pf_info->driver_version, "N/A", 567 sizeof(vf2pf_info->driver_version)); 568 569 vf2pf_info->pf2vf_version_required = 0; // no requirement, guest understands all 570 vf2pf_info->driver_cert = 0; 571 vf2pf_info->os_info.all = 0; 572 573 vf2pf_info->fb_usage = amdgpu_vram_mgr_usage(vram_man) >> 20; 574 vf2pf_info->fb_vis_usage = amdgpu_vram_mgr_vis_usage(vram_man) >> 20; 575 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; 576 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; 577 578 amdgpu_virt_populate_vf2pf_ucode_info(adev); 579 580 /* TODO: read dynamic info */ 581 vf2pf_info->gfx_usage = 0; 582 vf2pf_info->compute_usage = 0; 583 vf2pf_info->encode_usage = 0; 584 vf2pf_info->decode_usage = 0; 585 586 vf2pf_info->checksum = 587 amd_sriov_msg_checksum( 588 vf2pf_info, vf2pf_info->header.size, 0, 0); 589 590 return 0; 591 } 592 593 static void amdgpu_virt_update_vf2pf_work_item(struct work_struct *work) 594 { 595 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); 596 int ret; 597 598 ret = amdgpu_virt_read_pf2vf_data(adev); 599 if (ret) 600 goto out; 601 amdgpu_virt_write_vf2pf_data(adev); 602 603 out: 604 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); 605 } 606 607 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) 608 { 609 if (adev->virt.vf2pf_update_interval_ms != 0) { 610 DRM_INFO("clean up the vf2pf work item\n"); 611 cancel_delayed_work_sync(&adev->virt.vf2pf_work); 612 adev->virt.vf2pf_update_interval_ms = 0; 613 } 614 } 615 616 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) 617 { 618 adev->virt.fw_reserve.p_pf2vf = NULL; 619 adev->virt.fw_reserve.p_vf2pf = NULL; 620 adev->virt.vf2pf_update_interval_ms = 0; 621 622 if (adev->mman.fw_vram_usage_va != NULL) { 623 /* go through this logic in ip_init and reset to init workqueue*/ 624 amdgpu_virt_exchange_data(adev); 625 626 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); 627 schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_ms)); 628 } else if (adev->bios != NULL) { 629 /* got through this logic in early init stage to get necessary flags, e.g. rlcg_acc related*/ 630 adev->virt.fw_reserve.p_pf2vf = 631 (struct amd_sriov_msg_pf2vf_info_header *) 632 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 633 634 amdgpu_virt_read_pf2vf_data(adev); 635 } 636 } 637 638 639 void amdgpu_virt_exchange_data(struct amdgpu_device *adev) 640 { 641 uint64_t bp_block_offset = 0; 642 uint32_t bp_block_size = 0; 643 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 644 645 if (adev->mman.fw_vram_usage_va != NULL) { 646 647 adev->virt.fw_reserve.p_pf2vf = 648 (struct amd_sriov_msg_pf2vf_info_header *) 649 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); 650 adev->virt.fw_reserve.p_vf2pf = 651 (struct amd_sriov_msg_vf2pf_info_header *) 652 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); 653 654 amdgpu_virt_read_pf2vf_data(adev); 655 amdgpu_virt_write_vf2pf_data(adev); 656 657 /* bad page handling for version 2 */ 658 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { 659 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; 660 661 bp_block_offset = ((uint64_t)pf2vf_v2->bp_block_offset_low & 0xFFFFFFFF) | 662 ((((uint64_t)pf2vf_v2->bp_block_offset_high) << 32) & 0xFFFFFFFF00000000); 663 bp_block_size = pf2vf_v2->bp_block_size; 664 665 if (bp_block_size && !adev->virt.ras_init_done) 666 amdgpu_virt_init_ras_err_handler_data(adev); 667 668 if (adev->virt.ras_init_done) 669 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); 670 } 671 } 672 } 673 674 675 void amdgpu_detect_virtualization(struct amdgpu_device *adev) 676 { 677 uint32_t reg; 678 679 switch (adev->asic_type) { 680 case CHIP_TONGA: 681 case CHIP_FIJI: 682 reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER); 683 break; 684 case CHIP_VEGA10: 685 case CHIP_VEGA20: 686 case CHIP_NAVI10: 687 case CHIP_NAVI12: 688 case CHIP_SIENNA_CICHLID: 689 case CHIP_ARCTURUS: 690 case CHIP_ALDEBARAN: 691 reg = RREG32(mmRCC_IOV_FUNC_IDENTIFIER); 692 break; 693 default: /* other chip doesn't support SRIOV */ 694 reg = 0; 695 break; 696 } 697 698 if (reg & 1) 699 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; 700 701 if (reg & 0x80000000) 702 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; 703 704 if (!reg) { 705 /* passthrough mode exclus sriov mod */ 706 if (is_virtual_machine() && !xen_initial_domain()) 707 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 708 } 709 710 /* we have the ability to check now */ 711 if (amdgpu_sriov_vf(adev)) { 712 switch (adev->asic_type) { 713 case CHIP_TONGA: 714 case CHIP_FIJI: 715 vi_set_virt_ops(adev); 716 break; 717 case CHIP_VEGA10: 718 case CHIP_VEGA20: 719 case CHIP_ARCTURUS: 720 case CHIP_ALDEBARAN: 721 soc15_set_virt_ops(adev); 722 break; 723 case CHIP_NAVI10: 724 case CHIP_NAVI12: 725 case CHIP_SIENNA_CICHLID: 726 nv_set_virt_ops(adev); 727 /* try send GPU_INIT_DATA request to host */ 728 amdgpu_virt_request_init_data(adev); 729 break; 730 default: /* other chip doesn't support SRIOV */ 731 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); 732 break; 733 } 734 } 735 } 736 737 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) 738 { 739 return amdgpu_sriov_is_debug(adev) ? true : false; 740 } 741 742 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) 743 { 744 return amdgpu_sriov_is_normal(adev) ? true : false; 745 } 746 747 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) 748 { 749 if (!amdgpu_sriov_vf(adev) || 750 amdgpu_virt_access_debugfs_is_kiq(adev)) 751 return 0; 752 753 if (amdgpu_virt_access_debugfs_is_mmio(adev)) 754 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; 755 else 756 return -EPERM; 757 758 return 0; 759 } 760 761 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) 762 { 763 if (amdgpu_sriov_vf(adev)) 764 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; 765 } 766 767 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) 768 { 769 enum amdgpu_sriov_vf_mode mode; 770 771 if (amdgpu_sriov_vf(adev)) { 772 if (amdgpu_sriov_is_pp_one_vf(adev)) 773 mode = SRIOV_VF_MODE_ONE_VF; 774 else 775 mode = SRIOV_VF_MODE_MULTI_VF; 776 } else { 777 mode = SRIOV_VF_MODE_BARE_METAL; 778 } 779 780 return mode; 781 } 782 783 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 784 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 785 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size) 786 { 787 uint32_t i; 788 789 if (!adev->virt.is_mm_bw_enabled) 790 return; 791 792 if (encode) { 793 for (i = 0; i < encode_array_size; i++) { 794 encode[i].max_width = adev->virt.encode_max_dimension_pixels; 795 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; 796 if (encode[i].max_width > 0) 797 encode[i].max_height = encode[i].max_pixels_per_frame / encode[i].max_width; 798 else 799 encode[i].max_height = 0; 800 } 801 } 802 803 if (decode) { 804 for (i = 0; i < decode_array_size; i++) { 805 decode[i].max_width = adev->virt.decode_max_dimension_pixels; 806 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; 807 if (decode[i].max_width > 0) 808 decode[i].max_height = decode[i].max_pixels_per_frame / decode[i].max_width; 809 else 810 decode[i].max_height = 0; 811 } 812 } 813 } 814