1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_TTM_H__ 25 #define __AMDGPU_TTM_H__ 26 27 #include <linux/dma-direction.h> 28 #include <drm/gpu_scheduler.h> 29 #include "amdgpu_vram_mgr.h" 30 #include "amdgpu.h" 31 32 #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0) 33 #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1) 34 #define AMDGPU_PL_OA (TTM_PL_PRIV + 2) 35 #define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) 36 37 #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 38 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 39 40 #define AMDGPU_POISON 0xd0bed0be 41 42 struct hmm_range; 43 44 struct amdgpu_gtt_mgr { 45 struct ttm_resource_manager manager; 46 struct drm_mm mm; 47 spinlock_t lock; 48 }; 49 50 struct amdgpu_mman { 51 struct ttm_device bdev; 52 bool initialized; 53 void __iomem *aper_base_kaddr; 54 bus_space_handle_t aper_bsh; 55 56 /* buffer handling */ 57 const struct amdgpu_buffer_funcs *buffer_funcs; 58 struct amdgpu_ring *buffer_funcs_ring; 59 bool buffer_funcs_enabled; 60 61 struct rwlock gtt_window_lock; 62 /* Scheduler entity for buffer moves */ 63 struct drm_sched_entity entity; 64 65 struct amdgpu_vram_mgr vram_mgr; 66 struct amdgpu_gtt_mgr gtt_mgr; 67 struct ttm_resource_manager preempt_mgr; 68 69 uint64_t stolen_vga_size; 70 struct amdgpu_bo *stolen_vga_memory; 71 uint64_t stolen_extended_size; 72 struct amdgpu_bo *stolen_extended_memory; 73 bool keep_stolen_vga_memory; 74 75 struct amdgpu_bo *stolen_reserved_memory; 76 uint64_t stolen_reserved_offset; 77 uint64_t stolen_reserved_size; 78 79 /* discovery */ 80 uint8_t *discovery_bin; 81 uint32_t discovery_tmr_size; 82 struct amdgpu_bo *discovery_memory; 83 84 /* firmware VRAM reservation */ 85 u64 fw_vram_usage_start_offset; 86 u64 fw_vram_usage_size; 87 struct amdgpu_bo *fw_vram_usage_reserved_bo; 88 void *fw_vram_usage_va; 89 90 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */ 91 struct amdgpu_bo *sdma_access_bo; 92 void *sdma_access_ptr; 93 }; 94 95 struct amdgpu_copy_mem { 96 struct ttm_buffer_object *bo; 97 struct ttm_resource *mem; 98 unsigned long offset; 99 }; 100 101 int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size); 102 void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev); 103 int amdgpu_preempt_mgr_init(struct amdgpu_device *adev); 104 void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev); 105 int amdgpu_vram_mgr_init(struct amdgpu_device *adev); 106 void amdgpu_vram_mgr_fini(struct amdgpu_device *adev); 107 108 bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem); 109 void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr); 110 111 uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man); 112 113 u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo); 114 int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, 115 struct ttm_resource *mem, 116 u64 offset, u64 size, 117 struct device *dev, 118 enum dma_data_direction dir, 119 struct sg_table **sgt); 120 void amdgpu_vram_mgr_free_sgt(struct device *dev, 121 enum dma_data_direction dir, 122 struct sg_table *sgt); 123 uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr); 124 int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr, 125 uint64_t start, uint64_t size); 126 int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr, 127 uint64_t start); 128 129 int amdgpu_ttm_init(struct amdgpu_device *adev); 130 void amdgpu_ttm_fini(struct amdgpu_device *adev); 131 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, 132 bool enable); 133 134 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 135 uint64_t dst_offset, uint32_t byte_count, 136 struct dma_resv *resv, 137 struct dma_fence **fence, bool direct_submit, 138 bool vm_needs_flush, bool tmz); 139 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 140 const struct amdgpu_copy_mem *src, 141 const struct amdgpu_copy_mem *dst, 142 uint64_t size, bool tmz, 143 struct dma_resv *resv, 144 struct dma_fence **f); 145 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 146 uint32_t src_data, 147 struct dma_resv *resv, 148 struct dma_fence **fence); 149 150 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); 151 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); 152 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); 153 154 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 155 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, 156 struct hmm_range **range); 157 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, 158 struct hmm_range *range); 159 #else 160 static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, 161 struct vm_page **pages, 162 struct hmm_range **range) 163 { 164 return -EPERM; 165 } 166 static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, 167 struct hmm_range *range) 168 { 169 return false; 170 } 171 #endif 172 173 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct vm_page **pages); 174 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo, 175 uint64_t *user_addr); 176 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 177 uint64_t addr, uint32_t flags); 178 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 179 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 180 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 181 unsigned long end, unsigned long *userptr); 182 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 183 int *last_invalidated); 184 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); 185 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 186 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); 187 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 188 struct ttm_resource *mem); 189 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type); 190 191 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev); 192 193 #endif 194