1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/dma-mapping.h> 34 #include <linux/iommu.h> 35 #include <linux/pagemap.h> 36 #include <linux/sched/task.h> 37 #include <linux/sched/mm.h> 38 #include <linux/seq_file.h> 39 #include <linux/slab.h> 40 #include <linux/swap.h> 41 #include <linux/swiotlb.h> 42 #include <linux/dma-buf.h> 43 #include <linux/sizes.h> 44 45 #include <drm/ttm/ttm_bo_api.h> 46 #include <drm/ttm/ttm_bo_driver.h> 47 #include <drm/ttm/ttm_placement.h> 48 #include <drm/ttm/ttm_range_manager.h> 49 50 #include <drm/amdgpu_drm.h> 51 52 #include "amdgpu.h" 53 #include "amdgpu_object.h" 54 #include "amdgpu_trace.h" 55 #include "amdgpu_amdkfd.h" 56 #include "amdgpu_sdma.h" 57 #include "amdgpu_ras.h" 58 #include "amdgpu_atomfirmware.h" 59 #include "amdgpu_res_cursor.h" 60 #include "bif/bif_4_1_d.h" 61 62 #define AMDGPU_TTM_VRAM_MAX_DW_READ (size_t)128 63 64 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 65 struct ttm_tt *ttm, 66 struct ttm_resource *bo_mem); 67 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 68 struct ttm_tt *ttm); 69 70 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev, 71 unsigned int type, 72 uint64_t size_in_page) 73 { 74 return ttm_range_man_init(&adev->mman.bdev, type, 75 false, size_in_page); 76 } 77 78 /** 79 * amdgpu_evict_flags - Compute placement flags 80 * 81 * @bo: The buffer object to evict 82 * @placement: Possible destination(s) for evicted BO 83 * 84 * Fill in placement data when ttm_bo_evict() is called 85 */ 86 static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 87 struct ttm_placement *placement) 88 { 89 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 90 struct amdgpu_bo *abo; 91 static const struct ttm_place placements = { 92 .fpfn = 0, 93 .lpfn = 0, 94 .mem_type = TTM_PL_SYSTEM, 95 .flags = 0 96 }; 97 98 /* Don't handle scatter gather BOs */ 99 if (bo->type == ttm_bo_type_sg) { 100 placement->num_placement = 0; 101 placement->num_busy_placement = 0; 102 return; 103 } 104 105 /* Object isn't an AMDGPU object so ignore */ 106 if (!amdgpu_bo_is_amdgpu_bo(bo)) { 107 placement->placement = &placements; 108 placement->busy_placement = &placements; 109 placement->num_placement = 1; 110 placement->num_busy_placement = 1; 111 return; 112 } 113 114 abo = ttm_to_amdgpu_bo(bo); 115 if (abo->flags & AMDGPU_AMDKFD_CREATE_SVM_BO) { 116 struct dma_fence *fence; 117 struct dma_resv *resv = &bo->base._resv; 118 119 rcu_read_lock(); 120 fence = rcu_dereference(resv->fence_excl); 121 if (fence && !fence->ops->signaled) 122 dma_fence_enable_sw_signaling(fence); 123 124 placement->num_placement = 0; 125 placement->num_busy_placement = 0; 126 rcu_read_unlock(); 127 return; 128 } 129 130 switch (bo->resource->mem_type) { 131 case AMDGPU_PL_GDS: 132 case AMDGPU_PL_GWS: 133 case AMDGPU_PL_OA: 134 placement->num_placement = 0; 135 placement->num_busy_placement = 0; 136 return; 137 138 case TTM_PL_VRAM: 139 if (!adev->mman.buffer_funcs_enabled) { 140 /* Move to system memory */ 141 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 142 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 143 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 144 amdgpu_bo_in_cpu_visible_vram(abo)) { 145 146 /* Try evicting to the CPU inaccessible part of VRAM 147 * first, but only set GTT as busy placement, so this 148 * BO will be evicted to GTT rather than causing other 149 * BOs to be evicted from VRAM 150 */ 151 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 152 AMDGPU_GEM_DOMAIN_GTT | 153 AMDGPU_GEM_DOMAIN_CPU); 154 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 155 abo->placements[0].lpfn = 0; 156 abo->placement.busy_placement = &abo->placements[1]; 157 abo->placement.num_busy_placement = 1; 158 } else { 159 /* Move to GTT memory */ 160 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT | 161 AMDGPU_GEM_DOMAIN_CPU); 162 } 163 break; 164 case TTM_PL_TT: 165 case AMDGPU_PL_PREEMPT: 166 default: 167 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); 168 break; 169 } 170 *placement = abo->placement; 171 } 172 173 /** 174 * amdgpu_ttm_map_buffer - Map memory into the GART windows 175 * @bo: buffer object to map 176 * @mem: memory object to map 177 * @mm_cur: range to map 178 * @num_pages: number of pages to map 179 * @window: which GART window to use 180 * @ring: DMA ring to use for the copy 181 * @tmz: if we should setup a TMZ enabled mapping 182 * @addr: resulting address inside the MC address space 183 * 184 * Setup one of the GART windows to access a specific piece of memory or return 185 * the physical address for local memory. 186 */ 187 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo, 188 struct ttm_resource *mem, 189 struct amdgpu_res_cursor *mm_cur, 190 unsigned num_pages, unsigned window, 191 struct amdgpu_ring *ring, bool tmz, 192 uint64_t *addr) 193 { 194 struct amdgpu_device *adev = ring->adev; 195 struct amdgpu_job *job; 196 unsigned num_dw, num_bytes; 197 struct dma_fence *fence; 198 uint64_t src_addr, dst_addr; 199 void *cpu_addr; 200 uint64_t flags; 201 unsigned int i; 202 int r; 203 204 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < 205 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); 206 BUG_ON(mem->mem_type == AMDGPU_PL_PREEMPT); 207 208 /* Map only what can't be accessed directly */ 209 if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) { 210 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) + 211 mm_cur->start; 212 return 0; 213 } 214 215 *addr = adev->gmc.gart_start; 216 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 217 AMDGPU_GPU_PAGE_SIZE; 218 *addr += mm_cur->start & ~LINUX_PAGE_MASK; 219 220 num_dw = roundup2(adev->mman.buffer_funcs->copy_num_dw, 8); 221 num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE; 222 223 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, 224 AMDGPU_IB_POOL_DELAYED, &job); 225 if (r) 226 return r; 227 228 src_addr = num_dw * 4; 229 src_addr += job->ibs[0].gpu_addr; 230 231 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo); 232 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8; 233 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, 234 dst_addr, num_bytes, false); 235 236 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 237 WARN_ON(job->ibs[0].length_dw > num_dw); 238 239 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem); 240 if (tmz) 241 flags |= AMDGPU_PTE_TMZ; 242 243 cpu_addr = &job->ibs[0].ptr[num_dw]; 244 245 if (mem->mem_type == TTM_PL_TT) { 246 dma_addr_t *dma_addr; 247 248 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT]; 249 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags, 250 cpu_addr); 251 if (r) 252 goto error_free; 253 } else { 254 dma_addr_t dma_address; 255 256 dma_address = mm_cur->start; 257 dma_address += adev->vm_manager.vram_base_offset; 258 259 for (i = 0; i < num_pages; ++i) { 260 r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1, 261 &dma_address, flags, cpu_addr); 262 if (r) 263 goto error_free; 264 265 dma_address += PAGE_SIZE; 266 } 267 } 268 269 r = amdgpu_job_submit(job, &adev->mman.entity, 270 AMDGPU_FENCE_OWNER_UNDEFINED, &fence); 271 if (r) 272 goto error_free; 273 274 dma_fence_put(fence); 275 276 return r; 277 278 error_free: 279 amdgpu_job_free(job); 280 return r; 281 } 282 283 /** 284 * amdgpu_ttm_copy_mem_to_mem - Helper function for copy 285 * @adev: amdgpu device 286 * @src: buffer/address where to read from 287 * @dst: buffer/address where to write to 288 * @size: number of bytes to copy 289 * @tmz: if a secure copy should be used 290 * @resv: resv object to sync to 291 * @f: Returns the last fence if multiple jobs are submitted. 292 * 293 * The function copies @size bytes from {src->mem + src->offset} to 294 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a 295 * move and different for a BO to BO copy. 296 * 297 */ 298 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev, 299 const struct amdgpu_copy_mem *src, 300 const struct amdgpu_copy_mem *dst, 301 uint64_t size, bool tmz, 302 struct dma_resv *resv, 303 struct dma_fence **f) 304 { 305 const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE * 306 AMDGPU_GPU_PAGE_SIZE); 307 308 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 309 struct amdgpu_res_cursor src_mm, dst_mm; 310 struct dma_fence *fence = NULL; 311 int r = 0; 312 313 if (!adev->mman.buffer_funcs_enabled) { 314 DRM_ERROR("Trying to move memory with ring turned off.\n"); 315 return -EINVAL; 316 } 317 318 amdgpu_res_first(src->mem, src->offset, size, &src_mm); 319 amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm); 320 321 mutex_lock(&adev->mman.gtt_window_lock); 322 while (src_mm.remaining) { 323 uint32_t src_page_offset = src_mm.start & ~LINUX_PAGE_MASK; 324 uint32_t dst_page_offset = dst_mm.start & ~LINUX_PAGE_MASK; 325 struct dma_fence *next; 326 uint32_t cur_size; 327 uint64_t from, to; 328 329 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst 330 * begins at an offset, then adjust the size accordingly 331 */ 332 cur_size = max(src_page_offset, dst_page_offset); 333 cur_size = min(min3(src_mm.size, dst_mm.size, size), 334 (uint64_t)(GTT_MAX_BYTES - cur_size)); 335 336 /* Map src to window 0 and dst to window 1. */ 337 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm, 338 PFN_UP(cur_size + src_page_offset), 339 0, ring, tmz, &from); 340 if (r) 341 goto error; 342 343 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm, 344 PFN_UP(cur_size + dst_page_offset), 345 1, ring, tmz, &to); 346 if (r) 347 goto error; 348 349 r = amdgpu_copy_buffer(ring, from, to, cur_size, 350 resv, &next, false, true, tmz); 351 if (r) 352 goto error; 353 354 dma_fence_put(fence); 355 fence = next; 356 357 amdgpu_res_next(&src_mm, cur_size); 358 amdgpu_res_next(&dst_mm, cur_size); 359 } 360 error: 361 mutex_unlock(&adev->mman.gtt_window_lock); 362 if (f) 363 *f = dma_fence_get(fence); 364 dma_fence_put(fence); 365 return r; 366 } 367 368 /* 369 * amdgpu_move_blit - Copy an entire buffer to another buffer 370 * 371 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to 372 * help move buffers to and from VRAM. 373 */ 374 static int amdgpu_move_blit(struct ttm_buffer_object *bo, 375 bool evict, 376 struct ttm_resource *new_mem, 377 struct ttm_resource *old_mem) 378 { 379 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 380 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 381 struct amdgpu_copy_mem src, dst; 382 struct dma_fence *fence = NULL; 383 int r; 384 385 src.bo = bo; 386 dst.bo = bo; 387 src.mem = old_mem; 388 dst.mem = new_mem; 389 src.offset = 0; 390 dst.offset = 0; 391 392 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, 393 new_mem->num_pages << PAGE_SHIFT, 394 amdgpu_bo_encrypted(abo), 395 bo->base.resv, &fence); 396 if (r) 397 goto error; 398 399 /* clear the space being freed */ 400 if (old_mem->mem_type == TTM_PL_VRAM && 401 (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) { 402 struct dma_fence *wipe_fence = NULL; 403 404 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON, 405 NULL, &wipe_fence); 406 if (r) { 407 goto error; 408 } else if (wipe_fence) { 409 dma_fence_put(fence); 410 fence = wipe_fence; 411 } 412 } 413 414 /* Always block for VM page tables before committing the new location */ 415 if (bo->type == ttm_bo_type_kernel) 416 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem); 417 else 418 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem); 419 dma_fence_put(fence); 420 return r; 421 422 error: 423 if (fence) 424 dma_fence_wait(fence, false); 425 dma_fence_put(fence); 426 return r; 427 } 428 429 /* 430 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy 431 * 432 * Called by amdgpu_bo_move() 433 */ 434 static bool amdgpu_mem_visible(struct amdgpu_device *adev, 435 struct ttm_resource *mem) 436 { 437 uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT; 438 struct amdgpu_res_cursor cursor; 439 440 if (mem->mem_type == TTM_PL_SYSTEM || 441 mem->mem_type == TTM_PL_TT) 442 return true; 443 if (mem->mem_type != TTM_PL_VRAM) 444 return false; 445 446 amdgpu_res_first(mem, 0, mem_size, &cursor); 447 448 /* ttm_resource_ioremap only supports contiguous memory */ 449 if (cursor.size != mem_size) 450 return false; 451 452 return cursor.start + cursor.size <= adev->gmc.visible_vram_size; 453 } 454 455 /* 456 * amdgpu_bo_move - Move a buffer object to a new memory location 457 * 458 * Called by ttm_bo_handle_move_mem() 459 */ 460 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 461 struct ttm_operation_ctx *ctx, 462 struct ttm_resource *new_mem, 463 struct ttm_place *hop) 464 { 465 struct amdgpu_device *adev; 466 struct amdgpu_bo *abo; 467 struct ttm_resource *old_mem = bo->resource; 468 int r; 469 470 if (new_mem->mem_type == TTM_PL_TT || 471 new_mem->mem_type == AMDGPU_PL_PREEMPT) { 472 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem); 473 if (r) 474 return r; 475 } 476 477 /* Can't move a pinned BO */ 478 abo = ttm_to_amdgpu_bo(bo); 479 if (WARN_ON_ONCE(abo->tbo.pin_count > 0)) 480 return -EINVAL; 481 482 adev = amdgpu_ttm_adev(bo->bdev); 483 484 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 485 ttm_bo_move_null(bo, new_mem); 486 goto out; 487 } 488 if (old_mem->mem_type == TTM_PL_SYSTEM && 489 (new_mem->mem_type == TTM_PL_TT || 490 new_mem->mem_type == AMDGPU_PL_PREEMPT)) { 491 ttm_bo_move_null(bo, new_mem); 492 goto out; 493 } 494 if ((old_mem->mem_type == TTM_PL_TT || 495 old_mem->mem_type == AMDGPU_PL_PREEMPT) && 496 new_mem->mem_type == TTM_PL_SYSTEM) { 497 r = ttm_bo_wait_ctx(bo, ctx); 498 if (r) 499 return r; 500 501 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm); 502 ttm_resource_free(bo, &bo->resource); 503 ttm_bo_assign_mem(bo, new_mem); 504 goto out; 505 } 506 507 if (old_mem->mem_type == AMDGPU_PL_GDS || 508 old_mem->mem_type == AMDGPU_PL_GWS || 509 old_mem->mem_type == AMDGPU_PL_OA || 510 new_mem->mem_type == AMDGPU_PL_GDS || 511 new_mem->mem_type == AMDGPU_PL_GWS || 512 new_mem->mem_type == AMDGPU_PL_OA) { 513 /* Nothing to save here */ 514 ttm_bo_move_null(bo, new_mem); 515 goto out; 516 } 517 518 if (bo->type == ttm_bo_type_device && 519 new_mem->mem_type == TTM_PL_VRAM && 520 old_mem->mem_type != TTM_PL_VRAM) { 521 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU 522 * accesses the BO after it's moved. 523 */ 524 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 525 } 526 527 if (adev->mman.buffer_funcs_enabled) { 528 if (((old_mem->mem_type == TTM_PL_SYSTEM && 529 new_mem->mem_type == TTM_PL_VRAM) || 530 (old_mem->mem_type == TTM_PL_VRAM && 531 new_mem->mem_type == TTM_PL_SYSTEM))) { 532 hop->fpfn = 0; 533 hop->lpfn = 0; 534 hop->mem_type = TTM_PL_TT; 535 hop->flags = TTM_PL_FLAG_TEMPORARY; 536 return -EMULTIHOP; 537 } 538 539 r = amdgpu_move_blit(bo, evict, new_mem, old_mem); 540 } else { 541 r = -ENODEV; 542 } 543 544 if (r) { 545 /* Check that all memory is CPU accessible */ 546 if (!amdgpu_mem_visible(adev, old_mem) || 547 !amdgpu_mem_visible(adev, new_mem)) { 548 pr_err("Move buffer fallback to memcpy unavailable\n"); 549 return r; 550 } 551 552 r = ttm_bo_move_memcpy(bo, ctx, new_mem); 553 if (r) 554 return r; 555 } 556 557 out: 558 /* update statistics */ 559 atomic64_add(bo->base.size, &adev->num_bytes_moved); 560 amdgpu_bo_move_notify(bo, evict, new_mem); 561 return 0; 562 } 563 564 /* 565 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault 566 * 567 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault() 568 */ 569 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 570 struct ttm_resource *mem) 571 { 572 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 573 size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT; 574 575 switch (mem->mem_type) { 576 case TTM_PL_SYSTEM: 577 /* system memory */ 578 return 0; 579 case TTM_PL_TT: 580 case AMDGPU_PL_PREEMPT: 581 break; 582 case TTM_PL_VRAM: 583 mem->bus.offset = mem->start << PAGE_SHIFT; 584 /* check if it's visible */ 585 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size) 586 return -EINVAL; 587 588 if (adev->mman.aper_base_kaddr && 589 mem->placement & TTM_PL_FLAG_CONTIGUOUS) 590 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr + 591 mem->bus.offset; 592 593 mem->bus.offset += adev->gmc.aper_base; 594 mem->bus.is_iomem = true; 595 break; 596 default: 597 return -EINVAL; 598 } 599 return 0; 600 } 601 602 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 603 unsigned long page_offset) 604 { 605 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 606 struct amdgpu_res_cursor cursor; 607 608 amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, 609 &cursor); 610 return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT; 611 } 612 613 /** 614 * amdgpu_ttm_domain_start - Returns GPU start address 615 * @adev: amdgpu device object 616 * @type: type of the memory 617 * 618 * Returns: 619 * GPU start address of a memory domain 620 */ 621 622 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) 623 { 624 switch (type) { 625 case TTM_PL_TT: 626 return adev->gmc.gart_start; 627 case TTM_PL_VRAM: 628 return adev->gmc.vram_start; 629 } 630 631 return 0; 632 } 633 634 /* 635 * TTM backend functions. 636 */ 637 struct amdgpu_ttm_tt { 638 struct ttm_tt ttm; 639 struct drm_gem_object *gobj; 640 u64 offset; 641 uint64_t userptr; 642 struct task_struct *usertask; 643 uint32_t userflags; 644 bool bound; 645 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 646 struct hmm_range *range; 647 #endif 648 }; 649 650 #ifdef CONFIG_DRM_AMDGPU_USERPTR 651 /* 652 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user 653 * memory and start HMM tracking CPU page table update 654 * 655 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only 656 * once afterwards to stop HMM tracking 657 */ 658 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct vm_page **pages) 659 { 660 struct ttm_tt *ttm = bo->tbo.ttm; 661 struct amdgpu_ttm_tt *gtt = (void *)ttm; 662 unsigned long start = gtt->userptr; 663 struct vm_area_struct *vma; 664 struct mm_struct *mm; 665 bool readonly; 666 int r = 0; 667 668 mm = bo->notifier.mm; 669 if (unlikely(!mm)) { 670 DRM_DEBUG_DRIVER("BO is not registered?\n"); 671 return -EFAULT; 672 } 673 674 /* Another get_user_pages is running at the same time?? */ 675 if (WARN_ON(gtt->range)) 676 return -EFAULT; 677 678 if (!mmget_not_zero(mm)) /* Happens during process shutdown */ 679 return -ESRCH; 680 681 mmap_read_lock(mm); 682 vma = vma_lookup(mm, start); 683 if (unlikely(!vma)) { 684 r = -EFAULT; 685 goto out_unlock; 686 } 687 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) && 688 vma->vm_file)) { 689 r = -EPERM; 690 goto out_unlock; 691 } 692 693 readonly = amdgpu_ttm_tt_is_readonly(ttm); 694 r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start, 695 ttm->num_pages, >t->range, readonly, 696 true, NULL); 697 out_unlock: 698 mmap_read_unlock(mm); 699 mmput(mm); 700 701 return r; 702 } 703 704 /* 705 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change 706 * Check if the pages backing this ttm range have been invalidated 707 * 708 * Returns: true if pages are still valid 709 */ 710 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm) 711 { 712 struct amdgpu_ttm_tt *gtt = (void *)ttm; 713 bool r = false; 714 715 if (!gtt || !gtt->userptr) 716 return false; 717 718 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", 719 gtt->userptr, ttm->num_pages); 720 721 WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns, 722 "No user pages to check\n"); 723 724 if (gtt->range) { 725 /* 726 * FIXME: Must always hold notifier_lock for this, and must 727 * not ignore the return code. 728 */ 729 r = amdgpu_hmm_range_get_pages_done(gtt->range); 730 gtt->range = NULL; 731 } 732 733 return !r; 734 } 735 #endif 736 737 /* 738 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. 739 * 740 * Called by amdgpu_cs_list_validate(). This creates the page list 741 * that backs user memory and will ultimately be mapped into the device 742 * address space. 743 */ 744 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct vm_page **pages) 745 { 746 unsigned long i; 747 748 for (i = 0; i < ttm->num_pages; ++i) 749 ttm->pages[i] = pages ? pages[i] : NULL; 750 } 751 752 /* 753 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages 754 * 755 * Called by amdgpu_ttm_backend_bind() 756 **/ 757 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev, 758 struct ttm_tt *ttm) 759 { 760 STUB(); 761 return -ENOSYS; 762 #ifdef notyet 763 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 764 struct amdgpu_ttm_tt *gtt = (void *)ttm; 765 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 766 enum dma_data_direction direction = write ? 767 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 768 int r; 769 770 /* Allocate an SG array and squash pages into it */ 771 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0, 772 (u64)ttm->num_pages << PAGE_SHIFT, 773 GFP_KERNEL); 774 if (r) 775 goto release_sg; 776 777 /* Map SG to device */ 778 r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 779 if (r) 780 goto release_sg; 781 782 /* convert SG to linear array of pages and dma addresses */ 783 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 784 ttm->num_pages); 785 786 return 0; 787 788 release_sg: 789 kfree(ttm->sg); 790 ttm->sg = NULL; 791 return r; 792 #endif 793 } 794 795 /* 796 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages 797 */ 798 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, 799 struct ttm_tt *ttm) 800 { 801 STUB(); 802 #ifdef notyet 803 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 804 struct amdgpu_ttm_tt *gtt = (void *)ttm; 805 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 806 enum dma_data_direction direction = write ? 807 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 808 809 /* double check that we don't free the table twice */ 810 if (!ttm->sg || !ttm->sg->sgl) 811 return; 812 813 /* unmap the pages mapped to the device */ 814 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 815 sg_free_table(ttm->sg); 816 817 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR) 818 if (gtt->range) { 819 unsigned long i; 820 821 for (i = 0; i < ttm->num_pages; i++) { 822 if (ttm->pages[i] != 823 hmm_pfn_to_page(gtt->range->hmm_pfns[i])) 824 break; 825 } 826 827 WARN((i == ttm->num_pages), "Missing get_user_page_done\n"); 828 } 829 #endif 830 #endif 831 } 832 833 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev, 834 struct ttm_buffer_object *tbo, 835 uint64_t flags) 836 { 837 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo); 838 struct ttm_tt *ttm = tbo->ttm; 839 struct amdgpu_ttm_tt *gtt = (void *)ttm; 840 int r; 841 842 if (amdgpu_bo_encrypted(abo)) 843 flags |= AMDGPU_PTE_TMZ; 844 845 if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) { 846 uint64_t page_idx = 1; 847 848 r = amdgpu_gart_bind(adev, gtt->offset, page_idx, 849 gtt->ttm.dma_address, flags); 850 if (r) 851 goto gart_bind_fail; 852 853 /* The memory type of the first page defaults to UC. Now 854 * modify the memory type to NC from the second page of 855 * the BO onward. 856 */ 857 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK; 858 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC); 859 860 r = amdgpu_gart_bind(adev, 861 gtt->offset + (page_idx << PAGE_SHIFT), 862 ttm->num_pages - page_idx, 863 &(gtt->ttm.dma_address[page_idx]), flags); 864 } else { 865 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 866 gtt->ttm.dma_address, flags); 867 } 868 869 gart_bind_fail: 870 if (r) 871 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 872 ttm->num_pages, gtt->offset); 873 874 return r; 875 } 876 877 /* 878 * amdgpu_ttm_backend_bind - Bind GTT memory 879 * 880 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem(). 881 * This handles binding GTT memory to the device address space. 882 */ 883 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, 884 struct ttm_tt *ttm, 885 struct ttm_resource *bo_mem) 886 { 887 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 888 struct amdgpu_ttm_tt *gtt = (void*)ttm; 889 uint64_t flags; 890 int r = 0; 891 892 if (!bo_mem) 893 return -EINVAL; 894 895 if (gtt->bound) 896 return 0; 897 898 if (gtt->userptr) { 899 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm); 900 if (r) { 901 DRM_ERROR("failed to pin userptr\n"); 902 return r; 903 } 904 } else if (ttm->page_flags & TTM_PAGE_FLAG_SG) { 905 if (!ttm->sg) { 906 struct dma_buf_attachment *attach; 907 struct sg_table *sgt; 908 909 attach = gtt->gobj->import_attach; 910 #ifdef notyet 911 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); 912 if (IS_ERR(sgt)) 913 return PTR_ERR(sgt); 914 #else 915 STUB(); 916 return -ENOSYS; 917 #endif 918 919 ttm->sg = sgt; 920 } 921 922 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, 923 ttm->num_pages); 924 } 925 926 if (!ttm->num_pages) { 927 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n", 928 ttm->num_pages, bo_mem, ttm); 929 } 930 931 if (bo_mem->mem_type == AMDGPU_PL_GDS || 932 bo_mem->mem_type == AMDGPU_PL_GWS || 933 bo_mem->mem_type == AMDGPU_PL_OA) 934 return -EINVAL; 935 936 if (bo_mem->mem_type != TTM_PL_TT || 937 !amdgpu_gtt_mgr_has_gart_addr(bo_mem)) { 938 gtt->offset = AMDGPU_BO_INVALID_OFFSET; 939 return 0; 940 } 941 942 /* compute PTE flags relevant to this BO memory */ 943 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem); 944 945 /* bind pages into GART page tables */ 946 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT; 947 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages, 948 gtt->ttm.dma_address, flags); 949 950 if (r) 951 DRM_ERROR("failed to bind %u pages at 0x%08llX\n", 952 ttm->num_pages, gtt->offset); 953 gtt->bound = true; 954 return r; 955 } 956 957 /* 958 * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either 959 * through AGP or GART aperture. 960 * 961 * If bo is accessible through AGP aperture, then use AGP aperture 962 * to access bo; otherwise allocate logical space in GART aperture 963 * and map bo to GART aperture. 964 */ 965 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) 966 { 967 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 968 struct ttm_operation_ctx ctx = { false, false }; 969 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm; 970 struct ttm_placement placement; 971 struct ttm_place placements; 972 struct ttm_resource *tmp; 973 uint64_t addr, flags; 974 int r; 975 976 if (bo->resource->start != AMDGPU_BO_INVALID_OFFSET) 977 return 0; 978 979 addr = amdgpu_gmc_agp_addr(bo); 980 if (addr != AMDGPU_BO_INVALID_OFFSET) { 981 bo->resource->start = addr >> PAGE_SHIFT; 982 return 0; 983 } 984 985 /* allocate GART space */ 986 placement.num_placement = 1; 987 placement.placement = &placements; 988 placement.num_busy_placement = 1; 989 placement.busy_placement = &placements; 990 placements.fpfn = 0; 991 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; 992 placements.mem_type = TTM_PL_TT; 993 placements.flags = bo->resource->placement; 994 995 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx); 996 if (unlikely(r)) 997 return r; 998 999 /* compute PTE flags for this buffer object */ 1000 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, tmp); 1001 1002 /* Bind pages */ 1003 gtt->offset = (u64)tmp->start << PAGE_SHIFT; 1004 r = amdgpu_ttm_gart_bind(adev, bo, flags); 1005 if (unlikely(r)) { 1006 ttm_resource_free(bo, &tmp); 1007 return r; 1008 } 1009 1010 amdgpu_gart_invalidate_tlb(adev); 1011 ttm_resource_free(bo, &bo->resource); 1012 ttm_bo_assign_mem(bo, tmp); 1013 1014 return 0; 1015 } 1016 1017 /* 1018 * amdgpu_ttm_recover_gart - Rebind GTT pages 1019 * 1020 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to 1021 * rebind GTT pages during a GPU reset. 1022 */ 1023 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo) 1024 { 1025 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 1026 uint64_t flags; 1027 int r; 1028 1029 if (!tbo->ttm) 1030 return 0; 1031 1032 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, tbo->resource); 1033 r = amdgpu_ttm_gart_bind(adev, tbo, flags); 1034 1035 return r; 1036 } 1037 1038 /* 1039 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages 1040 * 1041 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and 1042 * ttm_tt_destroy(). 1043 */ 1044 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, 1045 struct ttm_tt *ttm) 1046 { 1047 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1048 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1049 int r; 1050 1051 /* if the pages have userptr pinning then clear that first */ 1052 if (gtt->userptr) { 1053 amdgpu_ttm_tt_unpin_userptr(bdev, ttm); 1054 } else if (ttm->sg && gtt->gobj->import_attach) { 1055 struct dma_buf_attachment *attach; 1056 1057 attach = gtt->gobj->import_attach; 1058 #ifdef notyet 1059 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); 1060 #else 1061 STUB(); 1062 #endif 1063 ttm->sg = NULL; 1064 } 1065 1066 if (!gtt->bound) 1067 return; 1068 1069 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET) 1070 return; 1071 1072 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */ 1073 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages); 1074 if (r) 1075 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n", 1076 gtt->ttm.num_pages, gtt->offset); 1077 gtt->bound = false; 1078 } 1079 1080 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev, 1081 struct ttm_tt *ttm) 1082 { 1083 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1084 1085 amdgpu_ttm_backend_unbind(bdev, ttm); 1086 ttm_tt_destroy_common(bdev, ttm); 1087 #ifdef notyet 1088 if (gtt->usertask) 1089 put_task_struct(gtt->usertask); 1090 #endif 1091 1092 ttm_tt_fini(>t->ttm); 1093 kfree(gtt); 1094 } 1095 1096 /** 1097 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO 1098 * 1099 * @bo: The buffer object to create a GTT ttm_tt object around 1100 * @page_flags: Page flags to be added to the ttm_tt object 1101 * 1102 * Called by ttm_tt_create(). 1103 */ 1104 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo, 1105 uint32_t page_flags) 1106 { 1107 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1108 struct amdgpu_ttm_tt *gtt; 1109 enum ttm_caching caching; 1110 1111 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL); 1112 if (gtt == NULL) { 1113 return NULL; 1114 } 1115 gtt->gobj = &bo->base; 1116 1117 if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 1118 caching = ttm_write_combined; 1119 else 1120 caching = ttm_cached; 1121 1122 /* allocate space for the uninitialized page entries */ 1123 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) { 1124 kfree(gtt); 1125 return NULL; 1126 } 1127 return >t->ttm; 1128 } 1129 1130 /* 1131 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device 1132 * 1133 * Map the pages of a ttm_tt object to an address space visible 1134 * to the underlying device. 1135 */ 1136 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev, 1137 struct ttm_tt *ttm, 1138 struct ttm_operation_ctx *ctx) 1139 { 1140 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev); 1141 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1142 1143 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */ 1144 if (gtt->userptr) { 1145 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL); 1146 if (!ttm->sg) 1147 return -ENOMEM; 1148 return 0; 1149 } 1150 1151 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1152 return 0; 1153 1154 return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx); 1155 } 1156 1157 /* 1158 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays 1159 * 1160 * Unmaps pages of a ttm_tt object from the device address space and 1161 * unpopulates the page array backing it. 1162 */ 1163 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev, 1164 struct ttm_tt *ttm) 1165 { 1166 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1167 struct amdgpu_device *adev; 1168 1169 if (gtt->userptr) { 1170 amdgpu_ttm_tt_set_user_pages(ttm, NULL); 1171 kfree(ttm->sg); 1172 ttm->sg = NULL; 1173 return; 1174 } 1175 1176 if (ttm->page_flags & TTM_PAGE_FLAG_SG) 1177 return; 1178 1179 adev = amdgpu_ttm_adev(bdev); 1180 return ttm_pool_free(&adev->mman.bdev.pool, ttm); 1181 } 1182 1183 /** 1184 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current 1185 * task 1186 * 1187 * @bo: The ttm_buffer_object to bind this userptr to 1188 * @addr: The address in the current tasks VM space to use 1189 * @flags: Requirements of userptr object. 1190 * 1191 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages 1192 * to current task 1193 */ 1194 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, 1195 uint64_t addr, uint32_t flags) 1196 { 1197 struct amdgpu_ttm_tt *gtt; 1198 1199 if (!bo->ttm) { 1200 /* TODO: We want a separate TTM object type for userptrs */ 1201 bo->ttm = amdgpu_ttm_tt_create(bo, 0); 1202 if (bo->ttm == NULL) 1203 return -ENOMEM; 1204 } 1205 1206 /* Set TTM_PAGE_FLAG_SG before populate but after create. */ 1207 bo->ttm->page_flags |= TTM_PAGE_FLAG_SG; 1208 1209 gtt = (void *)bo->ttm; 1210 gtt->userptr = addr; 1211 gtt->userflags = flags; 1212 1213 #ifdef notyet 1214 if (gtt->usertask) 1215 put_task_struct(gtt->usertask); 1216 gtt->usertask = current->group_leader; 1217 get_task_struct(gtt->usertask); 1218 #endif 1219 1220 return 0; 1221 } 1222 1223 /* 1224 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object 1225 */ 1226 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) 1227 { 1228 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1229 1230 if (gtt == NULL) 1231 return NULL; 1232 1233 if (gtt->usertask == NULL) 1234 return NULL; 1235 1236 #ifdef notyet 1237 return gtt->usertask->mm; 1238 #else 1239 STUB(); 1240 return NULL; 1241 #endif 1242 } 1243 1244 /* 1245 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an 1246 * address range for the current task. 1247 * 1248 */ 1249 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1250 unsigned long end) 1251 { 1252 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1253 unsigned long size; 1254 1255 if (gtt == NULL || !gtt->userptr) 1256 return false; 1257 1258 /* Return false if no part of the ttm_tt object lies within 1259 * the range 1260 */ 1261 size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; 1262 if (gtt->userptr > end || gtt->userptr + size <= start) 1263 return false; 1264 1265 return true; 1266 } 1267 1268 /* 1269 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr? 1270 */ 1271 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) 1272 { 1273 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1274 1275 if (gtt == NULL || !gtt->userptr) 1276 return false; 1277 1278 return true; 1279 } 1280 1281 /* 1282 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? 1283 */ 1284 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm) 1285 { 1286 struct amdgpu_ttm_tt *gtt = (void *)ttm; 1287 1288 if (gtt == NULL) 1289 return false; 1290 1291 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY); 1292 } 1293 1294 /** 1295 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object 1296 * 1297 * @ttm: The ttm_tt object to compute the flags for 1298 * @mem: The memory registry backing this ttm_tt object 1299 * 1300 * Figure out the flags to use for a VM PDE (Page Directory Entry). 1301 */ 1302 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 1303 { 1304 uint64_t flags = 0; 1305 1306 if (mem && mem->mem_type != TTM_PL_SYSTEM) 1307 flags |= AMDGPU_PTE_VALID; 1308 1309 if (mem && (mem->mem_type == TTM_PL_TT || 1310 mem->mem_type == AMDGPU_PL_PREEMPT)) { 1311 flags |= AMDGPU_PTE_SYSTEM; 1312 1313 if (ttm->caching == ttm_cached) 1314 flags |= AMDGPU_PTE_SNOOPED; 1315 } 1316 1317 if (mem && mem->mem_type == TTM_PL_VRAM && 1318 mem->bus.caching == ttm_cached) 1319 flags |= AMDGPU_PTE_SNOOPED; 1320 1321 return flags; 1322 } 1323 1324 /** 1325 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object 1326 * 1327 * @adev: amdgpu_device pointer 1328 * @ttm: The ttm_tt object to compute the flags for 1329 * @mem: The memory registry backing this ttm_tt object 1330 * 1331 * Figure out the flags to use for a VM PTE (Page Table Entry). 1332 */ 1333 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1334 struct ttm_resource *mem) 1335 { 1336 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); 1337 1338 flags |= adev->gart.gart_pte_flags; 1339 flags |= AMDGPU_PTE_READABLE; 1340 1341 if (!amdgpu_ttm_tt_is_readonly(ttm)) 1342 flags |= AMDGPU_PTE_WRITEABLE; 1343 1344 return flags; 1345 } 1346 1347 /* 1348 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer 1349 * object. 1350 * 1351 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on 1352 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until 1353 * it can find space for a new object and by ttm_bo_force_list_clean() which is 1354 * used to clean out a memory space. 1355 */ 1356 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, 1357 const struct ttm_place *place) 1358 { 1359 unsigned long num_pages = bo->resource->num_pages; 1360 struct amdgpu_res_cursor cursor; 1361 struct dma_resv_list *flist; 1362 struct dma_fence *f; 1363 int i; 1364 1365 /* Swapout? */ 1366 if (bo->resource->mem_type == TTM_PL_SYSTEM) 1367 return true; 1368 1369 if (bo->type == ttm_bo_type_kernel && 1370 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo))) 1371 return false; 1372 1373 /* If bo is a KFD BO, check if the bo belongs to the current process. 1374 * If true, then return false as any KFD process needs all its BOs to 1375 * be resident to run successfully 1376 */ 1377 flist = dma_resv_shared_list(bo->base.resv); 1378 if (flist) { 1379 for (i = 0; i < flist->shared_count; ++i) { 1380 f = rcu_dereference_protected(flist->shared[i], 1381 dma_resv_held(bo->base.resv)); 1382 #ifdef notyet 1383 if (amdkfd_fence_check_mm(f, current->mm)) 1384 return false; 1385 #endif 1386 } 1387 } 1388 1389 switch (bo->resource->mem_type) { 1390 case AMDGPU_PL_PREEMPT: 1391 /* Preemptible BOs don't own system resources managed by the 1392 * driver (pages, VRAM, GART space). They point to resources 1393 * owned by someone else (e.g. pageable memory in user mode 1394 * or a DMABuf). They are used in a preemptible context so we 1395 * can guarantee no deadlocks and good QoS in case of MMU 1396 * notifiers or DMABuf move notifiers from the resource owner. 1397 */ 1398 return false; 1399 case TTM_PL_TT: 1400 if (amdgpu_bo_is_amdgpu_bo(bo) && 1401 amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo))) 1402 return false; 1403 return true; 1404 1405 case TTM_PL_VRAM: 1406 /* Check each drm MM node individually */ 1407 amdgpu_res_first(bo->resource, 0, (u64)num_pages << PAGE_SHIFT, 1408 &cursor); 1409 while (cursor.remaining) { 1410 if (place->fpfn < PFN_DOWN(cursor.start + cursor.size) 1411 && !(place->lpfn && 1412 place->lpfn <= PFN_DOWN(cursor.start))) 1413 return true; 1414 1415 amdgpu_res_next(&cursor, cursor.size); 1416 } 1417 return false; 1418 1419 default: 1420 break; 1421 } 1422 1423 return ttm_bo_eviction_valuable(bo, place); 1424 } 1425 1426 static void amdgpu_ttm_vram_mm_access(struct amdgpu_device *adev, loff_t pos, 1427 void *buf, size_t size, bool write) 1428 { 1429 STUB(); 1430 #ifdef notyet 1431 while (size) { 1432 uint64_t aligned_pos = ALIGN_DOWN(pos, 4); 1433 uint64_t bytes = 4 - (pos & 0x3); 1434 uint32_t shift = (pos & 0x3) * 8; 1435 uint32_t mask = 0xffffffff << shift; 1436 uint32_t value = 0; 1437 1438 if (size < bytes) { 1439 mask &= 0xffffffff >> (bytes - size) * 8; 1440 bytes = size; 1441 } 1442 1443 if (mask != 0xffffffff) { 1444 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, false); 1445 if (write) { 1446 value &= ~mask; 1447 value |= (*(uint32_t *)buf << shift) & mask; 1448 amdgpu_device_mm_access(adev, aligned_pos, &value, 4, true); 1449 } else { 1450 value = (value & mask) >> shift; 1451 memcpy(buf, &value, bytes); 1452 } 1453 } else { 1454 amdgpu_device_mm_access(adev, aligned_pos, buf, 4, write); 1455 } 1456 1457 pos += bytes; 1458 buf += bytes; 1459 size -= bytes; 1460 } 1461 #endif 1462 } 1463 1464 /** 1465 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object. 1466 * 1467 * @bo: The buffer object to read/write 1468 * @offset: Offset into buffer object 1469 * @buf: Secondary buffer to write/read from 1470 * @len: Length in bytes of access 1471 * @write: true if writing 1472 * 1473 * This is used to access VRAM that backs a buffer object via MMIO 1474 * access for debugging purposes. 1475 */ 1476 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, 1477 unsigned long offset, void *buf, int len, 1478 int write) 1479 { 1480 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1481 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 1482 struct amdgpu_res_cursor cursor; 1483 int ret = 0; 1484 1485 if (bo->resource->mem_type != TTM_PL_VRAM) 1486 return -EIO; 1487 1488 amdgpu_res_first(bo->resource, offset, len, &cursor); 1489 while (cursor.remaining) { 1490 size_t count, size = cursor.size; 1491 loff_t pos = cursor.start; 1492 1493 count = amdgpu_device_aper_access(adev, pos, buf, size, write); 1494 size -= count; 1495 if (size) { 1496 /* using MM to access rest vram and handle un-aligned address */ 1497 pos += count; 1498 buf += count; 1499 amdgpu_ttm_vram_mm_access(adev, pos, buf, size, write); 1500 } 1501 1502 ret += cursor.size; 1503 buf += cursor.size; 1504 amdgpu_res_next(&cursor, cursor.size); 1505 } 1506 1507 return ret; 1508 } 1509 1510 static void 1511 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo) 1512 { 1513 amdgpu_bo_move_notify(bo, false, NULL); 1514 } 1515 1516 static struct ttm_device_funcs amdgpu_bo_driver = { 1517 .ttm_tt_create = &amdgpu_ttm_tt_create, 1518 .ttm_tt_populate = &amdgpu_ttm_tt_populate, 1519 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate, 1520 .ttm_tt_destroy = &amdgpu_ttm_backend_destroy, 1521 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, 1522 .evict_flags = &amdgpu_evict_flags, 1523 .move = &amdgpu_bo_move, 1524 .delete_mem_notify = &amdgpu_bo_delete_mem_notify, 1525 .release_notify = &amdgpu_bo_release_notify, 1526 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, 1527 .io_mem_pfn = amdgpu_ttm_io_mem_pfn, 1528 .access_memory = &amdgpu_ttm_access_memory, 1529 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify 1530 }; 1531 1532 /* 1533 * Firmware Reservation functions 1534 */ 1535 /** 1536 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram 1537 * 1538 * @adev: amdgpu_device pointer 1539 * 1540 * free fw reserved vram if it has been reserved. 1541 */ 1542 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev) 1543 { 1544 amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo, 1545 NULL, &adev->mman.fw_vram_usage_va); 1546 } 1547 1548 /** 1549 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw 1550 * 1551 * @adev: amdgpu_device pointer 1552 * 1553 * create bo vram reservation from fw. 1554 */ 1555 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) 1556 { 1557 uint64_t vram_size = adev->gmc.visible_vram_size; 1558 1559 adev->mman.fw_vram_usage_va = NULL; 1560 adev->mman.fw_vram_usage_reserved_bo = NULL; 1561 1562 if (adev->mman.fw_vram_usage_size == 0 || 1563 adev->mman.fw_vram_usage_size > vram_size) 1564 return 0; 1565 1566 return amdgpu_bo_create_kernel_at(adev, 1567 adev->mman.fw_vram_usage_start_offset, 1568 adev->mman.fw_vram_usage_size, 1569 AMDGPU_GEM_DOMAIN_VRAM, 1570 &adev->mman.fw_vram_usage_reserved_bo, 1571 &adev->mman.fw_vram_usage_va); 1572 } 1573 1574 /* 1575 * Memoy training reservation functions 1576 */ 1577 1578 /** 1579 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram 1580 * 1581 * @adev: amdgpu_device pointer 1582 * 1583 * free memory training reserved vram if it has been reserved. 1584 */ 1585 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev) 1586 { 1587 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1588 1589 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 1590 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL); 1591 ctx->c2p_bo = NULL; 1592 1593 return 0; 1594 } 1595 1596 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev) 1597 { 1598 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1599 1600 memset(ctx, 0, sizeof(*ctx)); 1601 1602 ctx->c2p_train_data_offset = 1603 roundup2((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M); 1604 ctx->p2c_train_data_offset = 1605 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET); 1606 ctx->train_data_size = 1607 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES; 1608 1609 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 1610 ctx->train_data_size, 1611 ctx->p2c_train_data_offset, 1612 ctx->c2p_train_data_offset); 1613 } 1614 1615 /* 1616 * reserve TMR memory at the top of VRAM which holds 1617 * IP Discovery data and is protected by PSP. 1618 */ 1619 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) 1620 { 1621 int ret; 1622 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx; 1623 bool mem_train_support = false; 1624 1625 if (!amdgpu_sriov_vf(adev)) { 1626 if (amdgpu_atomfirmware_mem_training_supported(adev)) 1627 mem_train_support = true; 1628 else 1629 DRM_DEBUG("memory training does not support!\n"); 1630 } 1631 1632 /* 1633 * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all 1634 * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc) 1635 * 1636 * Otherwise, fallback to legacy approach to check and reserve tmr block for ip 1637 * discovery data and G6 memory training data respectively 1638 */ 1639 adev->mman.discovery_tmr_size = 1640 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev); 1641 if (!adev->mman.discovery_tmr_size) 1642 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET; 1643 1644 if (mem_train_support) { 1645 /* reserve vram for mem train according to TMR location */ 1646 amdgpu_ttm_training_data_block_init(adev); 1647 ret = amdgpu_bo_create_kernel_at(adev, 1648 ctx->c2p_train_data_offset, 1649 ctx->train_data_size, 1650 AMDGPU_GEM_DOMAIN_VRAM, 1651 &ctx->c2p_bo, 1652 NULL); 1653 if (ret) { 1654 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret); 1655 amdgpu_ttm_training_reserve_vram_fini(adev); 1656 return ret; 1657 } 1658 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS; 1659 } 1660 1661 ret = amdgpu_bo_create_kernel_at(adev, 1662 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size, 1663 adev->mman.discovery_tmr_size, 1664 AMDGPU_GEM_DOMAIN_VRAM, 1665 &adev->mman.discovery_memory, 1666 NULL); 1667 if (ret) { 1668 DRM_ERROR("alloc tmr failed(%d)!\n", ret); 1669 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1670 return ret; 1671 } 1672 1673 return 0; 1674 } 1675 1676 /* 1677 * amdgpu_ttm_init - Init the memory management (ttm) as well as various 1678 * gtt/vram related fields. 1679 * 1680 * This initializes all of the memory space pools that the TTM layer 1681 * will need such as the GTT space (system memory mapped to the device), 1682 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which 1683 * can be mapped per VMID. 1684 */ 1685 int amdgpu_ttm_init(struct amdgpu_device *adev) 1686 { 1687 uint64_t gtt_size; 1688 int r; 1689 u64 vis_vram_limit; 1690 1691 rw_init(&adev->mman.gtt_window_lock, "gttwin"); 1692 1693 /* No others user of address space so set it to 0 */ 1694 #ifdef notyet 1695 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1696 adev_to_drm(adev)->anon_inode->i_mapping, 1697 adev_to_drm(adev)->vma_offset_manager, 1698 adev->need_swiotlb, 1699 dma_addressing_limited(adev->dev)); 1700 #else 1701 r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev, 1702 /*adev_to_drm(adev)->anon_inode->i_mapping*/NULL, 1703 adev_to_drm(adev)->vma_offset_manager, 1704 adev->need_swiotlb, 1705 dma_addressing_limited(adev->dev)); 1706 #endif 1707 if (r) { 1708 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 1709 return r; 1710 } 1711 adev->mman.bdev.iot = adev->iot; 1712 adev->mman.bdev.memt = adev->memt; 1713 adev->mman.bdev.dmat = adev->dmat; 1714 adev->mman.initialized = true; 1715 1716 /* Initialize VRAM pool with all of VRAM divided into pages */ 1717 r = amdgpu_vram_mgr_init(adev); 1718 if (r) { 1719 DRM_ERROR("Failed initializing VRAM heap.\n"); 1720 return r; 1721 } 1722 1723 /* Reduce size of CPU-visible VRAM if requested */ 1724 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; 1725 if (amdgpu_vis_vram_limit > 0 && 1726 vis_vram_limit <= adev->gmc.visible_vram_size) 1727 adev->gmc.visible_vram_size = vis_vram_limit; 1728 1729 /* Change the size here instead of the init above so only lpfn is affected */ 1730 amdgpu_ttm_set_buffer_funcs_status(adev, false); 1731 #if defined(CONFIG_64BIT) && defined(__linux__) 1732 #ifdef CONFIG_X86 1733 if (adev->gmc.xgmi.connected_to_cpu) 1734 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base, 1735 adev->gmc.visible_vram_size); 1736 1737 else 1738 #endif 1739 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base, 1740 adev->gmc.visible_vram_size); 1741 #else 1742 if (bus_space_map(adev->memt, adev->gmc.aper_base, 1743 adev->gmc.visible_vram_size, 1744 BUS_SPACE_MAP_LINEAR | BUS_SPACE_MAP_PREFETCHABLE, 1745 &adev->mman.aper_bsh)) { 1746 adev->mman.aper_base_kaddr = NULL; 1747 } else { 1748 adev->mman.aper_base_kaddr = bus_space_vaddr(adev->memt, 1749 adev->mman.aper_bsh); 1750 } 1751 #endif 1752 1753 /* 1754 *The reserved vram for firmware must be pinned to the specified 1755 *place on the VRAM, so reserve it early. 1756 */ 1757 r = amdgpu_ttm_fw_reserve_vram_init(adev); 1758 if (r) { 1759 return r; 1760 } 1761 1762 /* 1763 * only NAVI10 and onwards ASIC support for IP discovery. 1764 * If IP discovery enabled, a block of memory should be 1765 * reserved for IP discovey. 1766 */ 1767 if (adev->mman.discovery_bin) { 1768 r = amdgpu_ttm_reserve_tmr(adev); 1769 if (r) 1770 return r; 1771 } 1772 1773 /* allocate memory as required for VGA 1774 * This is used for VGA emulation and pre-OS scanout buffers to 1775 * avoid display artifacts while transitioning between pre-OS 1776 * and driver. */ 1777 r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size, 1778 AMDGPU_GEM_DOMAIN_VRAM, 1779 &adev->mman.stolen_vga_memory, 1780 NULL); 1781 if (r) 1782 return r; 1783 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size, 1784 adev->mman.stolen_extended_size, 1785 AMDGPU_GEM_DOMAIN_VRAM, 1786 &adev->mman.stolen_extended_memory, 1787 NULL); 1788 if (r) 1789 return r; 1790 r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_reserved_offset, 1791 adev->mman.stolen_reserved_size, 1792 AMDGPU_GEM_DOMAIN_VRAM, 1793 &adev->mman.stolen_reserved_memory, 1794 NULL); 1795 if (r) 1796 return r; 1797 1798 DRM_INFO("amdgpu: %uM of VRAM memory ready\n", 1799 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); 1800 1801 /* Compute GTT size, either bsaed on 3/4th the size of RAM size 1802 * or whatever the user passed on module init */ 1803 if (amdgpu_gtt_size == -1) { 1804 #ifdef __linux__ 1805 struct sysinfo si; 1806 1807 si_meminfo(&si); 1808 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1809 adev->gmc.mc_vram_size), 1810 ((uint64_t)si.totalram * si.mem_unit * 3/4)); 1811 #else 1812 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), 1813 adev->gmc.mc_vram_size), 1814 ((uint64_t)ptoa(physmem) * 3/4)); 1815 #endif 1816 } 1817 else 1818 gtt_size = (uint64_t)amdgpu_gtt_size << 20; 1819 1820 /* Initialize GTT memory pool */ 1821 r = amdgpu_gtt_mgr_init(adev, gtt_size); 1822 if (r) { 1823 DRM_ERROR("Failed initializing GTT heap.\n"); 1824 return r; 1825 } 1826 DRM_INFO("amdgpu: %uM of GTT memory ready.\n", 1827 (unsigned)(gtt_size / (1024 * 1024))); 1828 1829 /* Initialize preemptible memory pool */ 1830 r = amdgpu_preempt_mgr_init(adev); 1831 if (r) { 1832 DRM_ERROR("Failed initializing PREEMPT heap.\n"); 1833 return r; 1834 } 1835 1836 /* Initialize various on-chip memory pools */ 1837 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size); 1838 if (r) { 1839 DRM_ERROR("Failed initializing GDS heap.\n"); 1840 return r; 1841 } 1842 1843 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size); 1844 if (r) { 1845 DRM_ERROR("Failed initializing gws heap.\n"); 1846 return r; 1847 } 1848 1849 r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size); 1850 if (r) { 1851 DRM_ERROR("Failed initializing oa heap.\n"); 1852 return r; 1853 } 1854 1855 return 0; 1856 } 1857 1858 /* 1859 * amdgpu_ttm_fini - De-initialize the TTM memory pools 1860 */ 1861 void amdgpu_ttm_fini(struct amdgpu_device *adev) 1862 { 1863 if (!adev->mman.initialized) 1864 return; 1865 1866 amdgpu_ttm_training_reserve_vram_fini(adev); 1867 /* return the stolen vga memory back to VRAM */ 1868 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL); 1869 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL); 1870 /* return the IP Discovery TMR memory back to VRAM */ 1871 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL); 1872 if (adev->mman.stolen_reserved_size) 1873 amdgpu_bo_free_kernel(&adev->mman.stolen_reserved_memory, 1874 NULL, NULL); 1875 amdgpu_ttm_fw_reserve_vram_fini(adev); 1876 1877 amdgpu_vram_mgr_fini(adev); 1878 amdgpu_gtt_mgr_fini(adev); 1879 amdgpu_preempt_mgr_fini(adev); 1880 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS); 1881 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS); 1882 ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA); 1883 ttm_device_fini(&adev->mman.bdev); 1884 adev->mman.initialized = false; 1885 DRM_INFO("amdgpu: ttm finalized\n"); 1886 } 1887 1888 /** 1889 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions 1890 * 1891 * @adev: amdgpu_device pointer 1892 * @enable: true when we can use buffer functions. 1893 * 1894 * Enable/disable use of buffer functions during suspend/resume. This should 1895 * only be called at bootup or when userspace isn't running. 1896 */ 1897 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable) 1898 { 1899 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 1900 uint64_t size; 1901 int r; 1902 1903 if (!adev->mman.initialized || amdgpu_in_reset(adev) || 1904 adev->mman.buffer_funcs_enabled == enable) 1905 return; 1906 1907 if (enable) { 1908 struct amdgpu_ring *ring; 1909 struct drm_gpu_scheduler *sched; 1910 1911 ring = adev->mman.buffer_funcs_ring; 1912 sched = &ring->sched; 1913 r = drm_sched_entity_init(&adev->mman.entity, 1914 DRM_SCHED_PRIORITY_KERNEL, &sched, 1915 1, NULL); 1916 if (r) { 1917 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n", 1918 r); 1919 return; 1920 } 1921 } else { 1922 drm_sched_entity_destroy(&adev->mman.entity); 1923 dma_fence_put(man->move); 1924 man->move = NULL; 1925 } 1926 1927 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 1928 if (enable) 1929 size = adev->gmc.real_vram_size; 1930 else 1931 size = adev->gmc.visible_vram_size; 1932 man->size = size >> PAGE_SHIFT; 1933 adev->mman.buffer_funcs_enabled = enable; 1934 } 1935 1936 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, 1937 uint64_t dst_offset, uint32_t byte_count, 1938 struct dma_resv *resv, 1939 struct dma_fence **fence, bool direct_submit, 1940 bool vm_needs_flush, bool tmz) 1941 { 1942 enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT : 1943 AMDGPU_IB_POOL_DELAYED; 1944 struct amdgpu_device *adev = ring->adev; 1945 struct amdgpu_job *job; 1946 1947 uint32_t max_bytes; 1948 unsigned num_loops, num_dw; 1949 unsigned i; 1950 int r; 1951 1952 if (!direct_submit && !ring->sched.ready) { 1953 DRM_ERROR("Trying to move memory with ring turned off.\n"); 1954 return -EINVAL; 1955 } 1956 1957 max_bytes = adev->mman.buffer_funcs->copy_max_bytes; 1958 num_loops = DIV_ROUND_UP(byte_count, max_bytes); 1959 num_dw = roundup2(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8); 1960 1961 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job); 1962 if (r) 1963 return r; 1964 1965 if (vm_needs_flush) { 1966 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ? 1967 adev->gmc.pdb0_bo : adev->gart.bo); 1968 job->vm_needs_flush = true; 1969 } 1970 if (resv) { 1971 r = amdgpu_sync_resv(adev, &job->sync, resv, 1972 AMDGPU_SYNC_ALWAYS, 1973 AMDGPU_FENCE_OWNER_UNDEFINED); 1974 if (r) { 1975 DRM_ERROR("sync failed (%d).\n", r); 1976 goto error_free; 1977 } 1978 } 1979 1980 for (i = 0; i < num_loops; i++) { 1981 uint32_t cur_size_in_bytes = min(byte_count, max_bytes); 1982 1983 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset, 1984 dst_offset, cur_size_in_bytes, tmz); 1985 1986 src_offset += cur_size_in_bytes; 1987 dst_offset += cur_size_in_bytes; 1988 byte_count -= cur_size_in_bytes; 1989 } 1990 1991 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 1992 WARN_ON(job->ibs[0].length_dw > num_dw); 1993 if (direct_submit) 1994 r = amdgpu_job_submit_direct(job, ring, fence); 1995 else 1996 r = amdgpu_job_submit(job, &adev->mman.entity, 1997 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 1998 if (r) 1999 goto error_free; 2000 2001 return r; 2002 2003 error_free: 2004 amdgpu_job_free(job); 2005 DRM_ERROR("Error scheduling IBs (%d)\n", r); 2006 return r; 2007 } 2008 2009 int amdgpu_fill_buffer(struct amdgpu_bo *bo, 2010 uint32_t src_data, 2011 struct dma_resv *resv, 2012 struct dma_fence **fence) 2013 { 2014 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 2015 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 2016 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 2017 2018 struct amdgpu_res_cursor cursor; 2019 unsigned int num_loops, num_dw; 2020 uint64_t num_bytes; 2021 2022 struct amdgpu_job *job; 2023 int r; 2024 2025 if (!adev->mman.buffer_funcs_enabled) { 2026 DRM_ERROR("Trying to clear memory with ring turned off.\n"); 2027 return -EINVAL; 2028 } 2029 2030 if (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT) { 2031 DRM_ERROR("Trying to clear preemptible memory.\n"); 2032 return -EINVAL; 2033 } 2034 2035 if (bo->tbo.resource->mem_type == TTM_PL_TT) { 2036 r = amdgpu_ttm_alloc_gart(&bo->tbo); 2037 if (r) 2038 return r; 2039 } 2040 2041 num_bytes = bo->tbo.resource->num_pages << PAGE_SHIFT; 2042 num_loops = 0; 2043 2044 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); 2045 while (cursor.remaining) { 2046 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes); 2047 amdgpu_res_next(&cursor, cursor.size); 2048 } 2049 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw; 2050 2051 /* for IB padding */ 2052 num_dw += 64; 2053 2054 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED, 2055 &job); 2056 if (r) 2057 return r; 2058 2059 if (resv) { 2060 r = amdgpu_sync_resv(adev, &job->sync, resv, 2061 AMDGPU_SYNC_ALWAYS, 2062 AMDGPU_FENCE_OWNER_UNDEFINED); 2063 if (r) { 2064 DRM_ERROR("sync failed (%d).\n", r); 2065 goto error_free; 2066 } 2067 } 2068 2069 amdgpu_res_first(bo->tbo.resource, 0, num_bytes, &cursor); 2070 while (cursor.remaining) { 2071 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes); 2072 uint64_t dst_addr = cursor.start; 2073 2074 dst_addr += amdgpu_ttm_domain_start(adev, 2075 bo->tbo.resource->mem_type); 2076 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr, 2077 cur_size); 2078 2079 amdgpu_res_next(&cursor, cur_size); 2080 } 2081 2082 amdgpu_ring_pad_ib(ring, &job->ibs[0]); 2083 WARN_ON(job->ibs[0].length_dw > num_dw); 2084 r = amdgpu_job_submit(job, &adev->mman.entity, 2085 AMDGPU_FENCE_OWNER_UNDEFINED, fence); 2086 if (r) 2087 goto error_free; 2088 2089 return 0; 2090 2091 error_free: 2092 amdgpu_job_free(job); 2093 return r; 2094 } 2095 2096 #if defined(CONFIG_DEBUG_FS) 2097 2098 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused) 2099 { 2100 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2101 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2102 TTM_PL_VRAM); 2103 struct drm_printer p = drm_seq_file_printer(m); 2104 2105 man->func->debug(man, &p); 2106 return 0; 2107 } 2108 2109 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) 2110 { 2111 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2112 2113 return ttm_pool_debugfs(&adev->mman.bdev.pool, m); 2114 } 2115 2116 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused) 2117 { 2118 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2119 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2120 TTM_PL_TT); 2121 struct drm_printer p = drm_seq_file_printer(m); 2122 2123 man->func->debug(man, &p); 2124 return 0; 2125 } 2126 2127 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused) 2128 { 2129 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2130 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2131 AMDGPU_PL_GDS); 2132 struct drm_printer p = drm_seq_file_printer(m); 2133 2134 man->func->debug(man, &p); 2135 return 0; 2136 } 2137 2138 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused) 2139 { 2140 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2141 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2142 AMDGPU_PL_GWS); 2143 struct drm_printer p = drm_seq_file_printer(m); 2144 2145 man->func->debug(man, &p); 2146 return 0; 2147 } 2148 2149 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused) 2150 { 2151 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 2152 struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, 2153 AMDGPU_PL_OA); 2154 struct drm_printer p = drm_seq_file_printer(m); 2155 2156 man->func->debug(man, &p); 2157 return 0; 2158 } 2159 2160 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table); 2161 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table); 2162 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table); 2163 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table); 2164 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table); 2165 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); 2166 2167 /* 2168 * amdgpu_ttm_vram_read - Linear read access to VRAM 2169 * 2170 * Accesses VRAM via MMIO for debugging purposes. 2171 */ 2172 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, 2173 size_t size, loff_t *pos) 2174 { 2175 struct amdgpu_device *adev = file_inode(f)->i_private; 2176 ssize_t result = 0; 2177 2178 if (size & 0x3 || *pos & 0x3) 2179 return -EINVAL; 2180 2181 if (*pos >= adev->gmc.mc_vram_size) 2182 return -ENXIO; 2183 2184 size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos)); 2185 while (size) { 2186 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4); 2187 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ]; 2188 2189 amdgpu_device_vram_access(adev, *pos, value, bytes, false); 2190 if (copy_to_user(buf, value, bytes)) 2191 return -EFAULT; 2192 2193 result += bytes; 2194 buf += bytes; 2195 *pos += bytes; 2196 size -= bytes; 2197 } 2198 2199 return result; 2200 } 2201 2202 /* 2203 * amdgpu_ttm_vram_write - Linear write access to VRAM 2204 * 2205 * Accesses VRAM via MMIO for debugging purposes. 2206 */ 2207 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, 2208 size_t size, loff_t *pos) 2209 { 2210 struct amdgpu_device *adev = file_inode(f)->i_private; 2211 ssize_t result = 0; 2212 int r; 2213 2214 if (size & 0x3 || *pos & 0x3) 2215 return -EINVAL; 2216 2217 if (*pos >= adev->gmc.mc_vram_size) 2218 return -ENXIO; 2219 2220 while (size) { 2221 uint32_t value; 2222 2223 if (*pos >= adev->gmc.mc_vram_size) 2224 return result; 2225 2226 r = get_user(value, (uint32_t *)buf); 2227 if (r) 2228 return r; 2229 2230 amdgpu_device_mm_access(adev, *pos, &value, 4, true); 2231 2232 result += 4; 2233 buf += 4; 2234 *pos += 4; 2235 size -= 4; 2236 } 2237 2238 return result; 2239 } 2240 2241 static const struct file_operations amdgpu_ttm_vram_fops = { 2242 .owner = THIS_MODULE, 2243 .read = amdgpu_ttm_vram_read, 2244 .write = amdgpu_ttm_vram_write, 2245 .llseek = default_llseek, 2246 }; 2247 2248 /* 2249 * amdgpu_iomem_read - Virtual read access to GPU mapped memory 2250 * 2251 * This function is used to read memory that has been mapped to the 2252 * GPU and the known addresses are not physical addresses but instead 2253 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2254 */ 2255 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf, 2256 size_t size, loff_t *pos) 2257 { 2258 struct amdgpu_device *adev = file_inode(f)->i_private; 2259 struct iommu_domain *dom; 2260 ssize_t result = 0; 2261 int r; 2262 2263 /* retrieve the IOMMU domain if any for this device */ 2264 dom = iommu_get_domain_for_dev(adev->dev); 2265 2266 while (size) { 2267 phys_addr_t addr = *pos & LINUX_PAGE_MASK; 2268 loff_t off = *pos & ~LINUX_PAGE_MASK; 2269 size_t bytes = PAGE_SIZE - off; 2270 unsigned long pfn; 2271 struct vm_page *p; 2272 void *ptr; 2273 2274 bytes = bytes < size ? bytes : size; 2275 2276 /* Translate the bus address to a physical address. If 2277 * the domain is NULL it means there is no IOMMU active 2278 * and the address translation is the identity 2279 */ 2280 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2281 2282 pfn = addr >> PAGE_SHIFT; 2283 if (!pfn_valid(pfn)) 2284 return -EPERM; 2285 2286 p = pfn_to_page(pfn); 2287 if (p->mapping != adev->mman.bdev.dev_mapping) 2288 return -EPERM; 2289 2290 ptr = kmap(p); 2291 r = copy_to_user(buf, ptr + off, bytes); 2292 kunmap(p); 2293 if (r) 2294 return -EFAULT; 2295 2296 size -= bytes; 2297 *pos += bytes; 2298 result += bytes; 2299 } 2300 2301 return result; 2302 } 2303 2304 /* 2305 * amdgpu_iomem_write - Virtual write access to GPU mapped memory 2306 * 2307 * This function is used to write memory that has been mapped to the 2308 * GPU and the known addresses are not physical addresses but instead 2309 * bus addresses (e.g., what you'd put in an IB or ring buffer). 2310 */ 2311 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf, 2312 size_t size, loff_t *pos) 2313 { 2314 struct amdgpu_device *adev = file_inode(f)->i_private; 2315 struct iommu_domain *dom; 2316 ssize_t result = 0; 2317 int r; 2318 2319 dom = iommu_get_domain_for_dev(adev->dev); 2320 2321 while (size) { 2322 phys_addr_t addr = *pos & LINUX_PAGE_MASK; 2323 loff_t off = *pos & ~LINUX_PAGE_MASK; 2324 size_t bytes = PAGE_SIZE - off; 2325 unsigned long pfn; 2326 struct vm_page *p; 2327 void *ptr; 2328 2329 bytes = bytes < size ? bytes : size; 2330 2331 addr = dom ? iommu_iova_to_phys(dom, addr) : addr; 2332 2333 pfn = addr >> PAGE_SHIFT; 2334 if (!pfn_valid(pfn)) 2335 return -EPERM; 2336 2337 p = pfn_to_page(pfn); 2338 if (p->mapping != adev->mman.bdev.dev_mapping) 2339 return -EPERM; 2340 2341 ptr = kmap(p); 2342 r = copy_from_user(ptr + off, buf, bytes); 2343 kunmap(p); 2344 if (r) 2345 return -EFAULT; 2346 2347 size -= bytes; 2348 *pos += bytes; 2349 result += bytes; 2350 } 2351 2352 return result; 2353 } 2354 2355 static const struct file_operations amdgpu_ttm_iomem_fops = { 2356 .owner = THIS_MODULE, 2357 .read = amdgpu_iomem_read, 2358 .write = amdgpu_iomem_write, 2359 .llseek = default_llseek 2360 }; 2361 2362 #endif 2363 2364 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) 2365 { 2366 #if defined(CONFIG_DEBUG_FS) 2367 struct drm_minor *minor = adev_to_drm(adev)->primary; 2368 struct dentry *root = minor->debugfs_root; 2369 2370 debugfs_create_file_size("amdgpu_vram", 0444, root, adev, 2371 &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size); 2372 debugfs_create_file("amdgpu_iomem", 0444, root, adev, 2373 &amdgpu_ttm_iomem_fops); 2374 debugfs_create_file("amdgpu_vram_mm", 0444, root, adev, 2375 &amdgpu_mm_vram_table_fops); 2376 debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev, 2377 &amdgpu_mm_tt_table_fops); 2378 debugfs_create_file("amdgpu_gds_mm", 0444, root, adev, 2379 &amdgpu_mm_gds_table_fops); 2380 debugfs_create_file("amdgpu_gws_mm", 0444, root, adev, 2381 &amdgpu_mm_gws_table_fops); 2382 debugfs_create_file("amdgpu_oa_mm", 0444, root, adev, 2383 &amdgpu_mm_oa_table_fops); 2384 debugfs_create_file("ttm_page_pool", 0444, root, adev, 2385 &amdgpu_ttm_page_pool_fops); 2386 #endif 2387 } 2388