1 /* 2 * Copyright 2017 Valve Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Andres Rodriguez <andresx7@gmail.com> 23 */ 24 25 #include <linux/fdtable.h> 26 #include <linux/pid.h> 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 30 #include "amdgpu_vm.h" 31 32 enum drm_sched_priority amdgpu_to_sched_priority(int amdgpu_priority) 33 { 34 switch (amdgpu_priority) { 35 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 36 return DRM_SCHED_PRIORITY_HIGH_HW; 37 case AMDGPU_CTX_PRIORITY_HIGH: 38 return DRM_SCHED_PRIORITY_HIGH_SW; 39 case AMDGPU_CTX_PRIORITY_NORMAL: 40 return DRM_SCHED_PRIORITY_NORMAL; 41 case AMDGPU_CTX_PRIORITY_LOW: 42 case AMDGPU_CTX_PRIORITY_VERY_LOW: 43 return DRM_SCHED_PRIORITY_LOW; 44 case AMDGPU_CTX_PRIORITY_UNSET: 45 return DRM_SCHED_PRIORITY_UNSET; 46 default: 47 WARN(1, "Invalid context priority %d\n", amdgpu_priority); 48 return DRM_SCHED_PRIORITY_INVALID; 49 } 50 } 51 52 static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev, 53 int fd, 54 enum drm_sched_priority priority) 55 { 56 STUB(); 57 return -ENOSYS; 58 #if 0 59 struct file *filp = fget(fd); 60 struct drm_file *file; 61 struct amdgpu_fpriv *fpriv; 62 struct amdgpu_ctx *ctx; 63 uint32_t id; 64 65 if (!filp) 66 return -EINVAL; 67 68 file = filp->private_data; 69 fpriv = file->driver_priv; 70 idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id) 71 amdgpu_ctx_priority_override(ctx, priority); 72 73 fput(filp); 74 75 return 0; 76 #endif 77 } 78 79 int amdgpu_sched_ioctl(struct drm_device *dev, void *data, 80 struct drm_file *filp) 81 { 82 union drm_amdgpu_sched *args = data; 83 struct amdgpu_device *adev = dev->dev_private; 84 enum drm_sched_priority priority; 85 int r; 86 87 priority = amdgpu_to_sched_priority(args->in.priority); 88 if (args->in.flags || priority == DRM_SCHED_PRIORITY_INVALID) 89 return -EINVAL; 90 91 switch (args->in.op) { 92 case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE: 93 r = amdgpu_sched_process_priority_override(adev, 94 args->in.fd, 95 priority); 96 break; 97 default: 98 DRM_ERROR("Invalid sched op specified: %d\n", args->in.op); 99 r = -EINVAL; 100 break; 101 } 102 103 return r; 104 } 105