1fb4d8502Sjsg /*
2fb4d8502Sjsg * Copyright 2017 Valve Corporation
3fb4d8502Sjsg *
4fb4d8502Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5fb4d8502Sjsg * copy of this software and associated documentation files (the "Software"),
6fb4d8502Sjsg * to deal in the Software without restriction, including without limitation
7fb4d8502Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8fb4d8502Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9fb4d8502Sjsg * Software is furnished to do so, subject to the following conditions:
10fb4d8502Sjsg *
11fb4d8502Sjsg * The above copyright notice and this permission notice shall be included in
12fb4d8502Sjsg * all copies or substantial portions of the Software.
13fb4d8502Sjsg *
14fb4d8502Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15fb4d8502Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16fb4d8502Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17fb4d8502Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18fb4d8502Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19fb4d8502Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20fb4d8502Sjsg * OTHER DEALINGS IN THE SOFTWARE.
21fb4d8502Sjsg *
22fb4d8502Sjsg * Authors: Andres Rodriguez <andresx7@gmail.com>
23fb4d8502Sjsg */
24fb4d8502Sjsg
25fb4d8502Sjsg #include <linux/fdtable.h>
26c349dbc7Sjsg #include <linux/file.h>
27fb4d8502Sjsg #include <linux/pid.h>
28c349dbc7Sjsg
29fb4d8502Sjsg #include <drm/amdgpu_drm.h>
30c349dbc7Sjsg
31fb4d8502Sjsg #include "amdgpu.h"
325ca02815Sjsg #include "amdgpu_sched.h"
33fb4d8502Sjsg #include "amdgpu_vm.h"
34fb4d8502Sjsg
amdgpu_sched_process_priority_override(struct amdgpu_device * adev,int fd,int32_t priority)35fb4d8502Sjsg static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
36fb4d8502Sjsg int fd,
371bb76ff1Sjsg int32_t priority)
38fb4d8502Sjsg {
39fb4d8502Sjsg STUB();
40fb4d8502Sjsg return -ENOSYS;
41c349dbc7Sjsg #ifdef notyet
42c349dbc7Sjsg struct fd f = fdget(fd);
43fb4d8502Sjsg struct amdgpu_fpriv *fpriv;
44*e80e918fSjsg struct amdgpu_ctx_mgr *mgr;
45fb4d8502Sjsg struct amdgpu_ctx *ctx;
46fb4d8502Sjsg uint32_t id;
47c349dbc7Sjsg int r;
48fb4d8502Sjsg
49c349dbc7Sjsg if (!f.file)
50fb4d8502Sjsg return -EINVAL;
51fb4d8502Sjsg
52c349dbc7Sjsg r = amdgpu_file_to_fpriv(f.file, &fpriv);
53c349dbc7Sjsg if (r) {
54c349dbc7Sjsg fdput(f);
55c349dbc7Sjsg return r;
56c349dbc7Sjsg }
57c349dbc7Sjsg
58*e80e918fSjsg mgr = &fpriv->ctx_mgr;
59*e80e918fSjsg mutex_lock(&mgr->lock);
60*e80e918fSjsg idr_for_each_entry(&mgr->ctx_handles, ctx, id)
61fb4d8502Sjsg amdgpu_ctx_priority_override(ctx, priority);
62*e80e918fSjsg mutex_unlock(&mgr->lock);
63fb4d8502Sjsg
64c349dbc7Sjsg fdput(f);
65c349dbc7Sjsg return 0;
66c349dbc7Sjsg #endif
67c349dbc7Sjsg }
68c349dbc7Sjsg
amdgpu_sched_context_priority_override(struct amdgpu_device * adev,int fd,unsigned ctx_id,int32_t priority)69c349dbc7Sjsg static int amdgpu_sched_context_priority_override(struct amdgpu_device *adev,
70c349dbc7Sjsg int fd,
71c349dbc7Sjsg unsigned ctx_id,
721bb76ff1Sjsg int32_t priority)
73c349dbc7Sjsg {
74c349dbc7Sjsg STUB();
75c349dbc7Sjsg return -ENOSYS;
76c349dbc7Sjsg #ifdef notyet
77c349dbc7Sjsg struct fd f = fdget(fd);
78c349dbc7Sjsg struct amdgpu_fpriv *fpriv;
79c349dbc7Sjsg struct amdgpu_ctx *ctx;
80c349dbc7Sjsg int r;
81c349dbc7Sjsg
82c349dbc7Sjsg if (!f.file)
83c349dbc7Sjsg return -EINVAL;
84c349dbc7Sjsg
85c349dbc7Sjsg r = amdgpu_file_to_fpriv(f.file, &fpriv);
86c349dbc7Sjsg if (r) {
87c349dbc7Sjsg fdput(f);
88c349dbc7Sjsg return r;
89c349dbc7Sjsg }
90c349dbc7Sjsg
91c349dbc7Sjsg ctx = amdgpu_ctx_get(fpriv, ctx_id);
92c349dbc7Sjsg
93c349dbc7Sjsg if (!ctx) {
94c349dbc7Sjsg fdput(f);
95c349dbc7Sjsg return -EINVAL;
96c349dbc7Sjsg }
97c349dbc7Sjsg
98c349dbc7Sjsg amdgpu_ctx_priority_override(ctx, priority);
99c349dbc7Sjsg amdgpu_ctx_put(ctx);
100c349dbc7Sjsg fdput(f);
101fb4d8502Sjsg
102fb4d8502Sjsg return 0;
103fb4d8502Sjsg #endif
104fb4d8502Sjsg }
105fb4d8502Sjsg
amdgpu_sched_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)106fb4d8502Sjsg int amdgpu_sched_ioctl(struct drm_device *dev, void *data,
107fb4d8502Sjsg struct drm_file *filp)
108fb4d8502Sjsg {
109fb4d8502Sjsg union drm_amdgpu_sched *args = data;
110ad8b1aafSjsg struct amdgpu_device *adev = drm_to_adev(dev);
111fb4d8502Sjsg int r;
112fb4d8502Sjsg
113ad8b1aafSjsg /* First check the op, then the op's argument.
114ad8b1aafSjsg */
115ad8b1aafSjsg switch (args->in.op) {
116ad8b1aafSjsg case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE:
117ad8b1aafSjsg case AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE:
118ad8b1aafSjsg break;
119ad8b1aafSjsg default:
120ad8b1aafSjsg DRM_ERROR("Invalid sched op specified: %d\n", args->in.op);
121fb4d8502Sjsg return -EINVAL;
122ad8b1aafSjsg }
123ad8b1aafSjsg
1241bb76ff1Sjsg if (!amdgpu_ctx_priority_is_valid(args->in.priority)) {
1251bb76ff1Sjsg WARN(1, "Invalid context priority %d\n", args->in.priority);
1261bb76ff1Sjsg return -EINVAL;
1271bb76ff1Sjsg }
128fb4d8502Sjsg
129fb4d8502Sjsg switch (args->in.op) {
130fb4d8502Sjsg case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE:
131fb4d8502Sjsg r = amdgpu_sched_process_priority_override(adev,
132fb4d8502Sjsg args->in.fd,
1331bb76ff1Sjsg args->in.priority);
134fb4d8502Sjsg break;
135c349dbc7Sjsg case AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE:
136c349dbc7Sjsg r = amdgpu_sched_context_priority_override(adev,
137c349dbc7Sjsg args->in.fd,
138c349dbc7Sjsg args->in.ctx_id,
1391bb76ff1Sjsg args->in.priority);
140c349dbc7Sjsg break;
141fb4d8502Sjsg default:
142ad8b1aafSjsg /* Impossible.
143ad8b1aafSjsg */
144fb4d8502Sjsg r = -EINVAL;
145fb4d8502Sjsg break;
146fb4d8502Sjsg }
147fb4d8502Sjsg
148fb4d8502Sjsg return r;
149fb4d8502Sjsg }
150