1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "amdgpu_ras_eeprom.h" 25 #include "amdgpu.h" 26 #include "amdgpu_ras.h" 27 #include <linux/bits.h> 28 #include "atom.h" 29 #include "amdgpu_eeprom.h" 30 #include "amdgpu_atomfirmware.h" 31 #include <linux/debugfs.h> 32 #include <linux/uaccess.h> 33 34 #include "amdgpu_reset.h" 35 36 /* These are memory addresses as would be seen by one or more EEPROM 37 * chips strung on the I2C bus, usually by manipulating pins 1-3 of a 38 * set of EEPROM devices. They form a continuous memory space. 39 * 40 * The I2C device address includes the device type identifier, 1010b, 41 * which is a reserved value and indicates that this is an I2C EEPROM 42 * device. It also includes the top 3 bits of the 19 bit EEPROM memory 43 * address, namely bits 18, 17, and 16. This makes up the 7 bit 44 * address sent on the I2C bus with bit 0 being the direction bit, 45 * which is not represented here, and sent by the hardware directly. 46 * 47 * For instance, 48 * 50h = 1010000b => device type identifier 1010b, bits 18:16 = 000b, address 0. 49 * 54h = 1010100b => --"--, bits 18:16 = 100b, address 40000h. 50 * 56h = 1010110b => --"--, bits 18:16 = 110b, address 60000h. 51 * Depending on the size of the I2C EEPROM device(s), bits 18:16 may 52 * address memory in a device or a device on the I2C bus, depending on 53 * the status of pins 1-3. See top of amdgpu_eeprom.c. 54 * 55 * The RAS table lives either at address 0 or address 40000h of EEPROM. 56 */ 57 #define EEPROM_I2C_MADDR_0 0x0 58 #define EEPROM_I2C_MADDR_4 0x40000 59 60 /* 61 * The 2 macros bellow represent the actual size in bytes that 62 * those entities occupy in the EEPROM memory. 63 * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which 64 * uses uint64 to store 6b fields such as retired_page. 65 */ 66 #define RAS_TABLE_HEADER_SIZE 20 67 #define RAS_TABLE_RECORD_SIZE 24 68 69 /* Table hdr is 'AMDR' */ 70 #define RAS_TABLE_HDR_VAL 0x414d4452 71 #define RAS_TABLE_VER 0x00010000 72 73 /* Bad GPU tag ‘BADG’ */ 74 #define RAS_TABLE_HDR_BAD 0x42414447 75 76 /* Assume 2-Mbit size EEPROM and take up the whole space. */ 77 #define RAS_TBL_SIZE_BYTES (256 * 1024) 78 #define RAS_TABLE_START 0 79 #define RAS_HDR_START RAS_TABLE_START 80 #define RAS_RECORD_START (RAS_HDR_START + RAS_TABLE_HEADER_SIZE) 81 #define RAS_MAX_RECORD_COUNT ((RAS_TBL_SIZE_BYTES - RAS_TABLE_HEADER_SIZE) \ 82 / RAS_TABLE_RECORD_SIZE) 83 84 /* Given a zero-based index of an EEPROM RAS record, yields the EEPROM 85 * offset off of RAS_TABLE_START. That is, this is something you can 86 * add to control->i2c_address, and then tell I2C layer to read 87 * from/write to there. _N is the so called absolute index, 88 * because it starts right after the table header. 89 */ 90 #define RAS_INDEX_TO_OFFSET(_C, _N) ((_C)->ras_record_offset + \ 91 (_N) * RAS_TABLE_RECORD_SIZE) 92 93 #define RAS_OFFSET_TO_INDEX(_C, _O) (((_O) - \ 94 (_C)->ras_record_offset) / RAS_TABLE_RECORD_SIZE) 95 96 /* Given a 0-based relative record index, 0, 1, 2, ..., etc., off 97 * of "fri", return the absolute record index off of the end of 98 * the table header. 99 */ 100 #define RAS_RI_TO_AI(_C, _I) (((_I) + (_C)->ras_fri) % \ 101 (_C)->ras_max_record_count) 102 103 #define RAS_NUM_RECS(_tbl_hdr) (((_tbl_hdr)->tbl_size - \ 104 RAS_TABLE_HEADER_SIZE) / RAS_TABLE_RECORD_SIZE) 105 106 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_ras, eeprom_control))->adev 107 108 static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) 109 { 110 switch (adev->ip_versions[MP1_HWIP][0]) { 111 case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */ 112 case IP_VERSION(11, 0, 7): /* Sienna cichlid */ 113 case IP_VERSION(13, 0, 0): 114 case IP_VERSION(13, 0, 2): /* Aldebaran */ 115 case IP_VERSION(13, 0, 6): 116 case IP_VERSION(13, 0, 10): 117 return true; 118 default: 119 return false; 120 } 121 } 122 123 static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, 124 struct amdgpu_ras_eeprom_control *control) 125 { 126 struct atom_context *atom_ctx = adev->mode_info.atom_context; 127 u8 i2c_addr; 128 129 if (!control) 130 return false; 131 132 if (amdgpu_atomfirmware_ras_rom_addr(adev, &i2c_addr)) { 133 /* The address given by VBIOS is an 8-bit, wire-format 134 * address, i.e. the most significant byte. 135 * 136 * Normalize it to a 19-bit EEPROM address. Remove the 137 * device type identifier and make it a 7-bit address; 138 * then make it a 19-bit EEPROM address. See top of 139 * amdgpu_eeprom.c. 140 */ 141 i2c_addr = (i2c_addr & 0x0F) >> 1; 142 control->i2c_address = ((u32) i2c_addr) << 16; 143 144 return true; 145 } 146 147 switch (adev->ip_versions[MP1_HWIP][0]) { 148 case IP_VERSION(11, 0, 2): 149 /* VEGA20 and ARCTURUS */ 150 if (adev->asic_type == CHIP_VEGA20) 151 control->i2c_address = EEPROM_I2C_MADDR_0; 152 else if (strnstr(atom_ctx->vbios_version, 153 "D342", 154 sizeof(atom_ctx->vbios_version))) 155 control->i2c_address = EEPROM_I2C_MADDR_0; 156 else 157 control->i2c_address = EEPROM_I2C_MADDR_4; 158 return true; 159 case IP_VERSION(11, 0, 7): 160 control->i2c_address = EEPROM_I2C_MADDR_0; 161 return true; 162 case IP_VERSION(13, 0, 2): 163 if (strnstr(atom_ctx->vbios_version, "D673", 164 sizeof(atom_ctx->vbios_version))) 165 control->i2c_address = EEPROM_I2C_MADDR_4; 166 else 167 control->i2c_address = EEPROM_I2C_MADDR_0; 168 return true; 169 case IP_VERSION(13, 0, 0): 170 if (strnstr(atom_ctx->vbios_pn, "D707", 171 sizeof(atom_ctx->vbios_pn))) 172 control->i2c_address = EEPROM_I2C_MADDR_0; 173 else 174 control->i2c_address = EEPROM_I2C_MADDR_4; 175 return true; 176 case IP_VERSION(13, 0, 6): 177 case IP_VERSION(13, 0, 10): 178 control->i2c_address = EEPROM_I2C_MADDR_4; 179 return true; 180 default: 181 return false; 182 } 183 } 184 185 static void 186 __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr, 187 unsigned char *buf) 188 { 189 u32 *pp = (uint32_t *)buf; 190 191 pp[0] = cpu_to_le32(hdr->header); 192 pp[1] = cpu_to_le32(hdr->version); 193 pp[2] = cpu_to_le32(hdr->first_rec_offset); 194 pp[3] = cpu_to_le32(hdr->tbl_size); 195 pp[4] = cpu_to_le32(hdr->checksum); 196 } 197 198 static void 199 __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr, 200 unsigned char *buf) 201 { 202 u32 *pp = (uint32_t *)buf; 203 204 hdr->header = le32_to_cpu(pp[0]); 205 hdr->version = le32_to_cpu(pp[1]); 206 hdr->first_rec_offset = le32_to_cpu(pp[2]); 207 hdr->tbl_size = le32_to_cpu(pp[3]); 208 hdr->checksum = le32_to_cpu(pp[4]); 209 } 210 211 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) 212 { 213 u8 buf[RAS_TABLE_HEADER_SIZE]; 214 struct amdgpu_device *adev = to_amdgpu_device(control); 215 int res; 216 217 memset(buf, 0, sizeof(buf)); 218 __encode_table_header_to_buf(&control->tbl_hdr, buf); 219 220 /* i2c may be unstable in gpu reset */ 221 down_read(&adev->reset_domain->sem); 222 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 223 control->i2c_address + 224 control->ras_header_offset, 225 buf, RAS_TABLE_HEADER_SIZE); 226 up_read(&adev->reset_domain->sem); 227 228 if (res < 0) { 229 DRM_ERROR("Failed to write EEPROM table header:%d", res); 230 } else if (res < RAS_TABLE_HEADER_SIZE) { 231 DRM_ERROR("Short write:%d out of %d\n", 232 res, RAS_TABLE_HEADER_SIZE); 233 res = -EIO; 234 } else { 235 res = 0; 236 } 237 238 return res; 239 } 240 241 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) 242 { 243 int ii; 244 u8 *pp, csum; 245 size_t sz; 246 247 /* Header checksum, skip checksum field in the calculation */ 248 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); 249 pp = (u8 *) &control->tbl_hdr; 250 csum = 0; 251 for (ii = 0; ii < sz; ii++, pp++) 252 csum += *pp; 253 254 return csum; 255 } 256 257 static int amdgpu_ras_eeprom_correct_header_tag( 258 struct amdgpu_ras_eeprom_control *control, 259 uint32_t header) 260 { 261 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 262 u8 *hh; 263 int res; 264 u8 csum; 265 266 csum = -hdr->checksum; 267 268 hh = (void *) &hdr->header; 269 csum -= (hh[0] + hh[1] + hh[2] + hh[3]); 270 hh = (void *) &header; 271 csum += hh[0] + hh[1] + hh[2] + hh[3]; 272 csum = -csum; 273 mutex_lock(&control->ras_tbl_mutex); 274 hdr->header = header; 275 hdr->checksum = csum; 276 res = __write_table_header(control); 277 mutex_unlock(&control->ras_tbl_mutex); 278 279 return res; 280 } 281 282 /** 283 * amdgpu_ras_eeprom_reset_table -- Reset the RAS EEPROM table 284 * @control: pointer to control structure 285 * 286 * Reset the contents of the header of the RAS EEPROM table. 287 * Return 0 on success, -errno on error. 288 */ 289 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) 290 { 291 struct amdgpu_device *adev = to_amdgpu_device(control); 292 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 293 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 294 u8 csum; 295 int res; 296 297 mutex_lock(&control->ras_tbl_mutex); 298 299 hdr->header = RAS_TABLE_HDR_VAL; 300 hdr->version = RAS_TABLE_VER; 301 hdr->first_rec_offset = RAS_RECORD_START; 302 hdr->tbl_size = RAS_TABLE_HEADER_SIZE; 303 304 csum = __calc_hdr_byte_sum(control); 305 csum = -csum; 306 hdr->checksum = csum; 307 res = __write_table_header(control); 308 309 control->ras_num_recs = 0; 310 control->ras_fri = 0; 311 312 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_recs); 313 314 control->bad_channel_bitmap = 0; 315 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); 316 con->update_channel_flag = false; 317 318 amdgpu_ras_debugfs_set_ret_size(control); 319 320 mutex_unlock(&control->ras_tbl_mutex); 321 322 return res; 323 } 324 325 static void 326 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, 327 struct eeprom_table_record *record, 328 unsigned char *buf) 329 { 330 __le64 tmp = 0; 331 int i = 0; 332 333 /* Next are all record fields according to EEPROM page spec in LE foramt */ 334 buf[i++] = record->err_type; 335 336 buf[i++] = record->bank; 337 338 tmp = cpu_to_le64(record->ts); 339 memcpy(buf + i, &tmp, 8); 340 i += 8; 341 342 tmp = cpu_to_le64((record->offset & 0xffffffffffff)); 343 memcpy(buf + i, &tmp, 6); 344 i += 6; 345 346 buf[i++] = record->mem_channel; 347 buf[i++] = record->mcumc_id; 348 349 tmp = cpu_to_le64((record->retired_page & 0xffffffffffff)); 350 memcpy(buf + i, &tmp, 6); 351 } 352 353 static void 354 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, 355 struct eeprom_table_record *record, 356 unsigned char *buf) 357 { 358 __le64 tmp = 0; 359 int i = 0; 360 361 /* Next are all record fields according to EEPROM page spec in LE foramt */ 362 record->err_type = buf[i++]; 363 364 record->bank = buf[i++]; 365 366 memcpy(&tmp, buf + i, 8); 367 record->ts = le64_to_cpu(tmp); 368 i += 8; 369 370 memcpy(&tmp, buf + i, 6); 371 record->offset = (le64_to_cpu(tmp) & 0xffffffffffff); 372 i += 6; 373 374 record->mem_channel = buf[i++]; 375 record->mcumc_id = buf[i++]; 376 377 memcpy(&tmp, buf + i, 6); 378 record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff); 379 } 380 381 bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev) 382 { 383 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 384 385 if (!__is_ras_eeprom_supported(adev)) 386 return false; 387 388 /* skip check eeprom table for VEGA20 Gaming */ 389 if (!con) 390 return false; 391 else 392 if (!(con->features & BIT(AMDGPU_RAS_BLOCK__UMC))) 393 return false; 394 395 if (con->eeprom_control.tbl_hdr.header == RAS_TABLE_HDR_BAD) { 396 dev_warn(adev->dev, "This GPU is in BAD status."); 397 dev_warn(adev->dev, "Please retire it or set a larger " 398 "threshold value when reloading driver.\n"); 399 return true; 400 } 401 402 return false; 403 } 404 405 /** 406 * __amdgpu_ras_eeprom_write -- write indexed from buffer to EEPROM 407 * @control: pointer to control structure 408 * @buf: pointer to buffer containing data to write 409 * @fri: start writing at this index 410 * @num: number of records to write 411 * 412 * The caller must hold the table mutex in @control. 413 * Return 0 on success, -errno otherwise. 414 */ 415 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, 416 u8 *buf, const u32 fri, const u32 num) 417 { 418 struct amdgpu_device *adev = to_amdgpu_device(control); 419 u32 buf_size; 420 int res; 421 422 /* i2c may be unstable in gpu reset */ 423 down_read(&adev->reset_domain->sem); 424 buf_size = num * RAS_TABLE_RECORD_SIZE; 425 res = amdgpu_eeprom_write(adev->pm.ras_eeprom_i2c_bus, 426 control->i2c_address + 427 RAS_INDEX_TO_OFFSET(control, fri), 428 buf, buf_size); 429 up_read(&adev->reset_domain->sem); 430 if (res < 0) { 431 DRM_ERROR("Writing %d EEPROM table records error:%d", 432 num, res); 433 } else if (res < buf_size) { 434 /* Short write, return error. 435 */ 436 DRM_ERROR("Wrote %d records out of %d", 437 res / RAS_TABLE_RECORD_SIZE, num); 438 res = -EIO; 439 } else { 440 res = 0; 441 } 442 443 return res; 444 } 445 446 static int 447 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, 448 struct eeprom_table_record *record, 449 const u32 num) 450 { 451 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); 452 u32 a, b, i; 453 u8 *buf, *pp; 454 int res; 455 456 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 457 if (!buf) 458 return -ENOMEM; 459 460 /* Encode all of them in one go. 461 */ 462 pp = buf; 463 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 464 __encode_table_record_to_buf(control, &record[i], pp); 465 466 /* update bad channel bitmap */ 467 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 468 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 469 con->update_channel_flag = true; 470 } 471 } 472 473 /* a, first record index to write into. 474 * b, last record index to write into. 475 * a = first index to read (fri) + number of records in the table, 476 * b = a + @num - 1. 477 * Let N = control->ras_max_num_record_count, then we have, 478 * case 0: 0 <= a <= b < N, 479 * just append @num records starting at a; 480 * case 1: 0 <= a < N <= b, 481 * append (N - a) records starting at a, and 482 * append the remainder, b % N + 1, starting at 0. 483 * case 2: 0 <= fri < N <= a <= b, then modulo N we get two subcases, 484 * case 2a: 0 <= a <= b < N 485 * append num records starting at a; and fix fri if b overwrote it, 486 * and since a <= b, if b overwrote it then a must've also, 487 * and if b didn't overwrite it, then a didn't also. 488 * case 2b: 0 <= b < a < N 489 * write num records starting at a, which wraps around 0=N 490 * and overwrite fri unconditionally. Now from case 2a, 491 * this means that b eclipsed fri to overwrite it and wrap 492 * around 0 again, i.e. b = 2N+r pre modulo N, so we unconditionally 493 * set fri = b + 1 (mod N). 494 * Now, since fri is updated in every case, except the trivial case 0, 495 * the number of records present in the table after writing, is, 496 * num_recs - 1 = b - fri (mod N), and we take the positive value, 497 * by adding an arbitrary multiple of N before taking the modulo N 498 * as shown below. 499 */ 500 a = control->ras_fri + control->ras_num_recs; 501 b = a + num - 1; 502 if (b < control->ras_max_record_count) { 503 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 504 } else if (a < control->ras_max_record_count) { 505 u32 g0, g1; 506 507 g0 = control->ras_max_record_count - a; 508 g1 = b % control->ras_max_record_count + 1; 509 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 510 if (res) 511 goto Out; 512 res = __amdgpu_ras_eeprom_write(control, 513 buf + g0 * RAS_TABLE_RECORD_SIZE, 514 0, g1); 515 if (res) 516 goto Out; 517 if (g1 > control->ras_fri) 518 control->ras_fri = g1 % control->ras_max_record_count; 519 } else { 520 a %= control->ras_max_record_count; 521 b %= control->ras_max_record_count; 522 523 if (a <= b) { 524 /* Note that, b - a + 1 = num. */ 525 res = __amdgpu_ras_eeprom_write(control, buf, a, num); 526 if (res) 527 goto Out; 528 if (b >= control->ras_fri) 529 control->ras_fri = (b + 1) % control->ras_max_record_count; 530 } else { 531 u32 g0, g1; 532 533 /* b < a, which means, we write from 534 * a to the end of the table, and from 535 * the start of the table to b. 536 */ 537 g0 = control->ras_max_record_count - a; 538 g1 = b + 1; 539 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); 540 if (res) 541 goto Out; 542 res = __amdgpu_ras_eeprom_write(control, 543 buf + g0 * RAS_TABLE_RECORD_SIZE, 544 0, g1); 545 if (res) 546 goto Out; 547 control->ras_fri = g1 % control->ras_max_record_count; 548 } 549 } 550 control->ras_num_recs = 1 + (control->ras_max_record_count + b 551 - control->ras_fri) 552 % control->ras_max_record_count; 553 Out: 554 kfree(buf); 555 return res; 556 } 557 558 static int 559 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) 560 { 561 struct amdgpu_device *adev = to_amdgpu_device(control); 562 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 563 u8 *buf, *pp, csum; 564 u32 buf_size; 565 int res; 566 567 /* Modify the header if it exceeds. 568 */ 569 if (amdgpu_bad_page_threshold != 0 && 570 control->ras_num_recs >= ras->bad_page_cnt_threshold) { 571 dev_warn(adev->dev, 572 "Saved bad pages %d reaches threshold value %d\n", 573 control->ras_num_recs, ras->bad_page_cnt_threshold); 574 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; 575 } 576 577 control->tbl_hdr.version = RAS_TABLE_VER; 578 control->tbl_hdr.first_rec_offset = RAS_INDEX_TO_OFFSET(control, control->ras_fri); 579 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 580 control->tbl_hdr.checksum = 0; 581 582 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 583 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 584 if (!buf) { 585 DRM_ERROR("allocating memory for table of size %d bytes failed\n", 586 control->tbl_hdr.tbl_size); 587 res = -ENOMEM; 588 goto Out; 589 } 590 591 down_read(&adev->reset_domain->sem); 592 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 593 control->i2c_address + 594 control->ras_record_offset, 595 buf, buf_size); 596 up_read(&adev->reset_domain->sem); 597 if (res < 0) { 598 DRM_ERROR("EEPROM failed reading records:%d\n", 599 res); 600 goto Out; 601 } else if (res < buf_size) { 602 DRM_ERROR("EEPROM read %d out of %d bytes\n", 603 res, buf_size); 604 res = -EIO; 605 goto Out; 606 } 607 608 /* Recalc the checksum. 609 */ 610 csum = 0; 611 for (pp = buf; pp < buf + buf_size; pp++) 612 csum += *pp; 613 614 csum += __calc_hdr_byte_sum(control); 615 /* avoid sign extension when assigning to "checksum" */ 616 csum = -csum; 617 control->tbl_hdr.checksum = csum; 618 res = __write_table_header(control); 619 Out: 620 kfree(buf); 621 return res; 622 } 623 624 /** 625 * amdgpu_ras_eeprom_append -- append records to the EEPROM RAS table 626 * @control: pointer to control structure 627 * @record: array of records to append 628 * @num: number of records in @record array 629 * 630 * Append @num records to the table, calculate the checksum and write 631 * the table back to EEPROM. The maximum number of records that 632 * can be appended is between 1 and control->ras_max_record_count, 633 * regardless of how many records are already stored in the table. 634 * 635 * Return 0 on success or if EEPROM is not supported, -errno on error. 636 */ 637 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, 638 struct eeprom_table_record *record, 639 const u32 num) 640 { 641 struct amdgpu_device *adev = to_amdgpu_device(control); 642 int res; 643 644 if (!__is_ras_eeprom_supported(adev)) 645 return 0; 646 647 if (num == 0) { 648 DRM_ERROR("will not append 0 records\n"); 649 return -EINVAL; 650 } else if (num > control->ras_max_record_count) { 651 DRM_ERROR("cannot append %d records than the size of table %d\n", 652 num, control->ras_max_record_count); 653 return -EINVAL; 654 } 655 656 mutex_lock(&control->ras_tbl_mutex); 657 658 res = amdgpu_ras_eeprom_append_table(control, record, num); 659 if (!res) 660 res = amdgpu_ras_eeprom_update_header(control); 661 if (!res) 662 amdgpu_ras_debugfs_set_ret_size(control); 663 664 mutex_unlock(&control->ras_tbl_mutex); 665 return res; 666 } 667 668 /** 669 * __amdgpu_ras_eeprom_read -- read indexed from EEPROM into buffer 670 * @control: pointer to control structure 671 * @buf: pointer to buffer to read into 672 * @fri: first record index, start reading at this index, absolute index 673 * @num: number of records to read 674 * 675 * The caller must hold the table mutex in @control. 676 * Return 0 on success, -errno otherwise. 677 */ 678 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 679 u8 *buf, const u32 fri, const u32 num) 680 { 681 struct amdgpu_device *adev = to_amdgpu_device(control); 682 u32 buf_size; 683 int res; 684 685 /* i2c may be unstable in gpu reset */ 686 down_read(&adev->reset_domain->sem); 687 buf_size = num * RAS_TABLE_RECORD_SIZE; 688 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 689 control->i2c_address + 690 RAS_INDEX_TO_OFFSET(control, fri), 691 buf, buf_size); 692 up_read(&adev->reset_domain->sem); 693 if (res < 0) { 694 DRM_ERROR("Reading %d EEPROM table records error:%d", 695 num, res); 696 } else if (res < buf_size) { 697 /* Short read, return error. 698 */ 699 DRM_ERROR("Read %d records out of %d", 700 res / RAS_TABLE_RECORD_SIZE, num); 701 res = -EIO; 702 } else { 703 res = 0; 704 } 705 706 return res; 707 } 708 709 /** 710 * amdgpu_ras_eeprom_read -- read EEPROM 711 * @control: pointer to control structure 712 * @record: array of records to read into 713 * @num: number of records in @record 714 * 715 * Reads num records from the RAS table in EEPROM and 716 * writes the data into @record array. 717 * 718 * Returns 0 on success, -errno on error. 719 */ 720 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, 721 struct eeprom_table_record *record, 722 const u32 num) 723 { 724 struct amdgpu_device *adev = to_amdgpu_device(control); 725 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 726 int i, res; 727 u8 *buf, *pp; 728 u32 g0, g1; 729 730 if (!__is_ras_eeprom_supported(adev)) 731 return 0; 732 733 if (num == 0) { 734 DRM_ERROR("will not read 0 records\n"); 735 return -EINVAL; 736 } else if (num > control->ras_num_recs) { 737 DRM_ERROR("too many records to read:%d available:%d\n", 738 num, control->ras_num_recs); 739 return -EINVAL; 740 } 741 742 buf = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); 743 if (!buf) 744 return -ENOMEM; 745 746 /* Determine how many records to read, from the first record 747 * index, fri, to the end of the table, and from the beginning 748 * of the table, such that the total number of records is 749 * @num, and we handle wrap around when fri > 0 and 750 * fri + num > RAS_MAX_RECORD_COUNT. 751 * 752 * First we compute the index of the last element 753 * which would be fetched from each region, 754 * g0 is in [fri, fri + num - 1], and 755 * g1 is in [0, RAS_MAX_RECORD_COUNT - 1]. 756 * Then, if g0 < RAS_MAX_RECORD_COUNT, the index of 757 * the last element to fetch, we set g0 to _the number_ 758 * of elements to fetch, @num, since we know that the last 759 * indexed to be fetched does not exceed the table. 760 * 761 * If, however, g0 >= RAS_MAX_RECORD_COUNT, then 762 * we set g0 to the number of elements to read 763 * until the end of the table, and g1 to the number of 764 * elements to read from the beginning of the table. 765 */ 766 g0 = control->ras_fri + num - 1; 767 g1 = g0 % control->ras_max_record_count; 768 if (g0 < control->ras_max_record_count) { 769 g0 = num; 770 g1 = 0; 771 } else { 772 g0 = control->ras_max_record_count - control->ras_fri; 773 g1 += 1; 774 } 775 776 mutex_lock(&control->ras_tbl_mutex); 777 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); 778 if (res) 779 goto Out; 780 if (g1) { 781 res = __amdgpu_ras_eeprom_read(control, 782 buf + g0 * RAS_TABLE_RECORD_SIZE, 783 0, g1); 784 if (res) 785 goto Out; 786 } 787 788 res = 0; 789 790 /* Read up everything? Then transform. 791 */ 792 pp = buf; 793 for (i = 0; i < num; i++, pp += RAS_TABLE_RECORD_SIZE) { 794 __decode_table_record_from_buf(control, &record[i], pp); 795 796 /* update bad channel bitmap */ 797 if (!(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { 798 control->bad_channel_bitmap |= 1 << record[i].mem_channel; 799 con->update_channel_flag = true; 800 } 801 } 802 Out: 803 kfree(buf); 804 mutex_unlock(&control->ras_tbl_mutex); 805 806 return res; 807 } 808 809 uint32_t amdgpu_ras_eeprom_max_record_count(void) 810 { 811 return RAS_MAX_RECORD_COUNT; 812 } 813 814 #ifdef __linux__ 815 static ssize_t 816 amdgpu_ras_debugfs_eeprom_size_read(struct file *f, char __user *buf, 817 size_t size, loff_t *pos) 818 { 819 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 820 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 821 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 822 u8 data[50]; 823 int res; 824 825 if (!size) 826 return size; 827 828 if (!ras || !control) { 829 res = snprintf(data, sizeof(data), "Not supported\n"); 830 } else { 831 res = snprintf(data, sizeof(data), "%d bytes or %d records\n", 832 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); 833 } 834 835 if (*pos >= res) 836 return 0; 837 838 res -= *pos; 839 res = min_t(size_t, res, size); 840 841 if (copy_to_user(buf, &data[*pos], res)) 842 return -EFAULT; 843 844 *pos += res; 845 846 return res; 847 } 848 849 const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = { 850 .owner = THIS_MODULE, 851 .read = amdgpu_ras_debugfs_eeprom_size_read, 852 .write = NULL, 853 .llseek = default_llseek, 854 }; 855 856 static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n"; 857 static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n"; 858 #define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1) 859 static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n"; 860 static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n"; 861 #define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1) 862 863 static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = { 864 "ignore", 865 "re", 866 "ue", 867 }; 868 869 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) 870 { 871 return strlen(tbl_hdr_str) + tbl_hdr_fmt_size + 872 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; 873 } 874 875 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 876 { 877 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, 878 eeprom_control); 879 struct dentry *de = ras->de_ras_eeprom_table; 880 881 if (de) 882 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); 883 } 884 885 static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf, 886 size_t size, loff_t *pos) 887 { 888 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 889 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 890 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; 891 const size_t orig_size = size; 892 int res = -EFAULT; 893 size_t data_len; 894 895 mutex_lock(&control->ras_tbl_mutex); 896 897 /* We want *pos - data_len > 0, which means there's 898 * bytes to be printed from data. 899 */ 900 data_len = strlen(tbl_hdr_str); 901 if (*pos < data_len) { 902 data_len -= *pos; 903 data_len = min_t(size_t, data_len, size); 904 if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len)) 905 goto Out; 906 buf += data_len; 907 size -= data_len; 908 *pos += data_len; 909 } 910 911 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size; 912 if (*pos < data_len && size > 0) { 913 u8 data[tbl_hdr_fmt_size + 1]; 914 loff_t lpos; 915 916 snprintf(data, sizeof(data), tbl_hdr_fmt, 917 control->tbl_hdr.header, 918 control->tbl_hdr.version, 919 control->tbl_hdr.first_rec_offset, 920 control->tbl_hdr.tbl_size, 921 control->tbl_hdr.checksum); 922 923 data_len -= *pos; 924 data_len = min_t(size_t, data_len, size); 925 lpos = *pos - strlen(tbl_hdr_str); 926 if (copy_to_user(buf, &data[lpos], data_len)) 927 goto Out; 928 buf += data_len; 929 size -= data_len; 930 *pos += data_len; 931 } 932 933 data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str); 934 if (*pos < data_len && size > 0) { 935 loff_t lpos; 936 937 data_len -= *pos; 938 data_len = min_t(size_t, data_len, size); 939 lpos = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size; 940 if (copy_to_user(buf, &rec_hdr_str[lpos], data_len)) 941 goto Out; 942 buf += data_len; 943 size -= data_len; 944 *pos += data_len; 945 } 946 947 data_len = amdgpu_ras_debugfs_table_size(control); 948 if (*pos < data_len && size > 0) { 949 u8 dare[RAS_TABLE_RECORD_SIZE]; 950 u8 data[rec_hdr_fmt_size + 1]; 951 struct eeprom_table_record record; 952 int s, r; 953 954 /* Find the starting record index 955 */ 956 s = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 957 strlen(rec_hdr_str); 958 s = s / rec_hdr_fmt_size; 959 r = *pos - strlen(tbl_hdr_str) - tbl_hdr_fmt_size - 960 strlen(rec_hdr_str); 961 r = r % rec_hdr_fmt_size; 962 963 for ( ; size > 0 && s < control->ras_num_recs; s++) { 964 u32 ai = RAS_RI_TO_AI(control, s); 965 /* Read a single record 966 */ 967 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); 968 if (res) 969 goto Out; 970 __decode_table_record_from_buf(control, &record, dare); 971 snprintf(data, sizeof(data), rec_hdr_fmt, 972 s, 973 RAS_INDEX_TO_OFFSET(control, ai), 974 record_err_type_str[record.err_type], 975 record.bank, 976 record.ts, 977 record.offset, 978 record.mem_channel, 979 record.mcumc_id, 980 record.retired_page); 981 982 data_len = min_t(size_t, rec_hdr_fmt_size - r, size); 983 if (copy_to_user(buf, &data[r], data_len)) { 984 res = -EFAULT; 985 goto Out; 986 } 987 buf += data_len; 988 size -= data_len; 989 *pos += data_len; 990 r = 0; 991 } 992 } 993 res = 0; 994 Out: 995 mutex_unlock(&control->ras_tbl_mutex); 996 return res < 0 ? res : orig_size - size; 997 } 998 999 static ssize_t 1000 amdgpu_ras_debugfs_eeprom_table_read(struct file *f, char __user *buf, 1001 size_t size, loff_t *pos) 1002 { 1003 struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; 1004 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1005 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; 1006 u8 data[81]; 1007 int res; 1008 1009 if (!size) 1010 return size; 1011 1012 if (!ras || !control) { 1013 res = snprintf(data, sizeof(data), "Not supported\n"); 1014 if (*pos >= res) 1015 return 0; 1016 1017 res -= *pos; 1018 res = min_t(size_t, res, size); 1019 1020 if (copy_to_user(buf, &data[*pos], res)) 1021 return -EFAULT; 1022 1023 *pos += res; 1024 1025 return res; 1026 } else { 1027 return amdgpu_ras_debugfs_table_read(f, buf, size, pos); 1028 } 1029 } 1030 1031 const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops = { 1032 .owner = THIS_MODULE, 1033 .read = amdgpu_ras_debugfs_eeprom_table_read, 1034 .write = NULL, 1035 .llseek = default_llseek, 1036 }; 1037 #else /* !__linux__ */ 1038 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) 1039 { 1040 } 1041 #endif 1042 1043 /** 1044 * __verify_ras_table_checksum -- verify the RAS EEPROM table checksum 1045 * @control: pointer to control structure 1046 * 1047 * Check the checksum of the stored in EEPROM RAS table. 1048 * 1049 * Return 0 if the checksum is correct, 1050 * positive if it is not correct, and 1051 * -errno on I/O error. 1052 */ 1053 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) 1054 { 1055 struct amdgpu_device *adev = to_amdgpu_device(control); 1056 int buf_size, res; 1057 u8 csum, *buf, *pp; 1058 1059 buf_size = RAS_TABLE_HEADER_SIZE + 1060 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; 1061 buf = kzalloc(buf_size, GFP_KERNEL); 1062 if (!buf) { 1063 DRM_ERROR("Out of memory checking RAS table checksum.\n"); 1064 return -ENOMEM; 1065 } 1066 1067 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1068 control->i2c_address + 1069 control->ras_header_offset, 1070 buf, buf_size); 1071 if (res < buf_size) { 1072 DRM_ERROR("Partial read for checksum, res:%d\n", res); 1073 /* On partial reads, return -EIO. 1074 */ 1075 if (res >= 0) 1076 res = -EIO; 1077 goto Out; 1078 } 1079 1080 csum = 0; 1081 for (pp = buf; pp < buf + buf_size; pp++) 1082 csum += *pp; 1083 Out: 1084 kfree(buf); 1085 return res < 0 ? res : csum; 1086 } 1087 1088 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control, 1089 bool *exceed_err_limit) 1090 { 1091 struct amdgpu_device *adev = to_amdgpu_device(control); 1092 unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 }; 1093 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; 1094 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1095 int res; 1096 1097 *exceed_err_limit = false; 1098 1099 if (!__is_ras_eeprom_supported(adev)) 1100 return 0; 1101 1102 /* Verify i2c adapter is initialized */ 1103 if (!adev->pm.ras_eeprom_i2c_bus || !adev->pm.ras_eeprom_i2c_bus->algo) 1104 return -ENOENT; 1105 1106 if (!__get_eeprom_i2c_addr(adev, control)) 1107 return -EINVAL; 1108 1109 control->ras_header_offset = RAS_HDR_START; 1110 control->ras_record_offset = RAS_RECORD_START; 1111 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; 1112 rw_init(&control->ras_tbl_mutex, "rastbl"); 1113 1114 /* Read the table header from EEPROM address */ 1115 res = amdgpu_eeprom_read(adev->pm.ras_eeprom_i2c_bus, 1116 control->i2c_address + control->ras_header_offset, 1117 buf, RAS_TABLE_HEADER_SIZE); 1118 if (res < RAS_TABLE_HEADER_SIZE) { 1119 DRM_ERROR("Failed to read EEPROM table header, res:%d", res); 1120 return res >= 0 ? -EIO : res; 1121 } 1122 1123 __decode_table_header_from_buf(hdr, buf); 1124 1125 control->ras_num_recs = RAS_NUM_RECS(hdr); 1126 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); 1127 1128 if (hdr->header == RAS_TABLE_HDR_VAL) { 1129 DRM_DEBUG_DRIVER("Found existing EEPROM table with %d records", 1130 control->ras_num_recs); 1131 res = __verify_ras_table_checksum(control); 1132 if (res) 1133 DRM_ERROR("RAS table incorrect checksum or error:%d\n", 1134 res); 1135 1136 /* Warn if we are at 90% of the threshold or above 1137 */ 1138 if (10 * control->ras_num_recs >= 9 * ras->bad_page_cnt_threshold) 1139 dev_warn(adev->dev, "RAS records:%u exceeds 90%% of threshold:%d", 1140 control->ras_num_recs, 1141 ras->bad_page_cnt_threshold); 1142 } else if (hdr->header == RAS_TABLE_HDR_BAD && 1143 amdgpu_bad_page_threshold != 0) { 1144 res = __verify_ras_table_checksum(control); 1145 if (res) 1146 DRM_ERROR("RAS Table incorrect checksum or error:%d\n", 1147 res); 1148 if (ras->bad_page_cnt_threshold > control->ras_num_recs) { 1149 /* This means that, the threshold was increased since 1150 * the last time the system was booted, and now, 1151 * ras->bad_page_cnt_threshold - control->num_recs > 0, 1152 * so that at least one more record can be saved, 1153 * before the page count threshold is reached. 1154 */ 1155 dev_info(adev->dev, 1156 "records:%d threshold:%d, resetting " 1157 "RAS table header signature", 1158 control->ras_num_recs, 1159 ras->bad_page_cnt_threshold); 1160 res = amdgpu_ras_eeprom_correct_header_tag(control, 1161 RAS_TABLE_HDR_VAL); 1162 } else { 1163 dev_err(adev->dev, "RAS records:%d exceed threshold:%d", 1164 control->ras_num_recs, ras->bad_page_cnt_threshold); 1165 if (amdgpu_bad_page_threshold == -2) { 1166 dev_warn(adev->dev, "GPU will be initialized due to bad_page_threshold = -2."); 1167 res = 0; 1168 } else { 1169 *exceed_err_limit = true; 1170 dev_err(adev->dev, 1171 "RAS records:%d exceed threshold:%d, " 1172 "GPU will not be initialized. Replace this GPU or increase the threshold", 1173 control->ras_num_recs, ras->bad_page_cnt_threshold); 1174 } 1175 } 1176 } else { 1177 DRM_INFO("Creating a new EEPROM table"); 1178 1179 res = amdgpu_ras_eeprom_reset_table(control); 1180 } 1181 1182 return res < 0 ? res : 0; 1183 } 1184