1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 /* 56 * Due to DF Cstate management centralized to PMFW, the firmware 57 * loading sequence will be updated as below: 58 * - Load KDB 59 * - Load SYS_DRV 60 * - Load tOS 61 * - Load PMFW 62 * - Setup TMR 63 * - Load other non-psp fw 64 * - Load ASD 65 * - Load XGMI/RAS/HDCP/DTM TA if any 66 * 67 * This new sequence is required for 68 * - Arcturus and onwards 69 */ 70 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 71 { 72 struct amdgpu_device *adev = psp->adev; 73 74 if (amdgpu_sriov_vf(adev)) { 75 psp->pmfw_centralized_cstate_management = false; 76 return; 77 } 78 79 switch (adev->ip_versions[MP0_HWIP][0]) { 80 case IP_VERSION(11, 0, 0): 81 case IP_VERSION(11, 0, 4): 82 case IP_VERSION(11, 0, 5): 83 case IP_VERSION(11, 0, 7): 84 case IP_VERSION(11, 0, 9): 85 case IP_VERSION(11, 0, 11): 86 case IP_VERSION(11, 0, 12): 87 case IP_VERSION(11, 0, 13): 88 case IP_VERSION(13, 0, 0): 89 case IP_VERSION(13, 0, 2): 90 case IP_VERSION(13, 0, 7): 91 psp->pmfw_centralized_cstate_management = true; 92 break; 93 default: 94 psp->pmfw_centralized_cstate_management = false; 95 break; 96 } 97 } 98 99 static int psp_early_init(void *handle) 100 { 101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 102 struct psp_context *psp = &adev->psp; 103 104 switch (adev->ip_versions[MP0_HWIP][0]) { 105 case IP_VERSION(9, 0, 0): 106 psp_v3_1_set_psp_funcs(psp); 107 psp->autoload_supported = false; 108 break; 109 case IP_VERSION(10, 0, 0): 110 case IP_VERSION(10, 0, 1): 111 psp_v10_0_set_psp_funcs(psp); 112 psp->autoload_supported = false; 113 break; 114 case IP_VERSION(11, 0, 2): 115 case IP_VERSION(11, 0, 4): 116 psp_v11_0_set_psp_funcs(psp); 117 psp->autoload_supported = false; 118 break; 119 case IP_VERSION(11, 0, 0): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 9): 122 case IP_VERSION(11, 0, 7): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 5, 0): 125 case IP_VERSION(11, 0, 12): 126 case IP_VERSION(11, 0, 13): 127 psp_v11_0_set_psp_funcs(psp); 128 psp->autoload_supported = true; 129 break; 130 case IP_VERSION(11, 0, 3): 131 case IP_VERSION(12, 0, 1): 132 psp_v12_0_set_psp_funcs(psp); 133 break; 134 case IP_VERSION(13, 0, 2): 135 psp_v13_0_set_psp_funcs(psp); 136 break; 137 case IP_VERSION(13, 0, 1): 138 case IP_VERSION(13, 0, 3): 139 case IP_VERSION(13, 0, 5): 140 case IP_VERSION(13, 0, 8): 141 case IP_VERSION(13, 0, 10): 142 case IP_VERSION(13, 0, 11): 143 psp_v13_0_set_psp_funcs(psp); 144 psp->autoload_supported = true; 145 break; 146 case IP_VERSION(11, 0, 8): 147 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 148 psp_v11_0_8_set_psp_funcs(psp); 149 psp->autoload_supported = false; 150 } 151 break; 152 case IP_VERSION(13, 0, 0): 153 case IP_VERSION(13, 0, 7): 154 psp_v13_0_set_psp_funcs(psp); 155 psp->autoload_supported = true; 156 break; 157 case IP_VERSION(13, 0, 4): 158 psp_v13_0_4_set_psp_funcs(psp); 159 psp->autoload_supported = true; 160 break; 161 default: 162 return -EINVAL; 163 } 164 165 psp->adev = adev; 166 167 psp_check_pmfw_centralized_cstate_management(psp); 168 169 return 0; 170 } 171 172 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 173 { 174 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 175 &mem_ctx->shared_buf); 176 mem_ctx->shared_bo = NULL; 177 } 178 179 static void psp_free_shared_bufs(struct psp_context *psp) 180 { 181 void *tmr_buf; 182 void **pptr; 183 184 /* free TMR memory buffer */ 185 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 186 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 187 psp->tmr_bo = NULL; 188 189 /* free xgmi shared memory */ 190 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 191 192 /* free ras shared memory */ 193 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 194 195 /* free hdcp shared memory */ 196 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 197 198 /* free dtm shared memory */ 199 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 200 201 /* free rap shared memory */ 202 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 203 204 /* free securedisplay shared memory */ 205 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 206 207 208 } 209 210 static void psp_memory_training_fini(struct psp_context *psp) 211 { 212 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 213 214 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 215 kfree(ctx->sys_cache); 216 ctx->sys_cache = NULL; 217 } 218 219 static int psp_memory_training_init(struct psp_context *psp) 220 { 221 int ret; 222 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 223 224 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 225 DRM_DEBUG("memory training is not supported!\n"); 226 return 0; 227 } 228 229 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 230 if (ctx->sys_cache == NULL) { 231 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 232 ret = -ENOMEM; 233 goto Err_out; 234 } 235 236 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 237 ctx->train_data_size, 238 ctx->p2c_train_data_offset, 239 ctx->c2p_train_data_offset); 240 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 241 return 0; 242 243 Err_out: 244 psp_memory_training_fini(psp); 245 return ret; 246 } 247 248 /* 249 * Helper funciton to query psp runtime database entry 250 * 251 * @adev: amdgpu_device pointer 252 * @entry_type: the type of psp runtime database entry 253 * @db_entry: runtime database entry pointer 254 * 255 * Return false if runtime database doesn't exit or entry is invalid 256 * or true if the specific database entry is found, and copy to @db_entry 257 */ 258 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 259 enum psp_runtime_entry_type entry_type, 260 void *db_entry) 261 { 262 uint64_t db_header_pos, db_dir_pos; 263 struct psp_runtime_data_header db_header = {0}; 264 struct psp_runtime_data_directory db_dir = {0}; 265 bool ret = false; 266 int i; 267 268 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 269 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 270 271 /* read runtime db header from vram */ 272 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 273 sizeof(struct psp_runtime_data_header), false); 274 275 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 276 /* runtime db doesn't exist, exit */ 277 dev_info(adev->dev, "PSP runtime database doesn't exist\n"); 278 return false; 279 } 280 281 /* read runtime database entry from vram */ 282 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 283 sizeof(struct psp_runtime_data_directory), false); 284 285 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 286 /* invalid db entry count, exit */ 287 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 288 return false; 289 } 290 291 /* look up for requested entry type */ 292 for (i = 0; i < db_dir.entry_count && !ret; i++) { 293 if (db_dir.entry_list[i].entry_type == entry_type) { 294 switch (entry_type) { 295 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 296 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 297 /* invalid db entry size */ 298 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 299 return false; 300 } 301 /* read runtime database entry */ 302 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 303 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 304 ret = true; 305 break; 306 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 307 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 308 /* invalid db entry size */ 309 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 310 return false; 311 } 312 /* read runtime database entry */ 313 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 314 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 315 ret = true; 316 break; 317 default: 318 ret = false; 319 break; 320 } 321 } 322 } 323 324 return ret; 325 } 326 327 static int psp_init_sriov_microcode(struct psp_context *psp) 328 { 329 struct amdgpu_device *adev = psp->adev; 330 int ret = 0; 331 332 switch (adev->ip_versions[MP0_HWIP][0]) { 333 case IP_VERSION(9, 0, 0): 334 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 335 ret = psp_init_cap_microcode(psp, "vega10"); 336 break; 337 case IP_VERSION(11, 0, 9): 338 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 339 ret = psp_init_cap_microcode(psp, "navi12"); 340 break; 341 case IP_VERSION(11, 0, 7): 342 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 343 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 344 break; 345 case IP_VERSION(13, 0, 2): 346 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 347 ret = psp_init_cap_microcode(psp, "aldebaran"); 348 ret &= psp_init_ta_microcode(psp, "aldebaran"); 349 break; 350 case IP_VERSION(13, 0, 0): 351 adev->virt.autoload_ucode_id = 0; 352 break; 353 case IP_VERSION(13, 0, 10): 354 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 355 break; 356 default: 357 ret = -EINVAL; 358 break; 359 } 360 return ret; 361 } 362 363 static int psp_sw_init(void *handle) 364 { 365 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 366 struct psp_context *psp = &adev->psp; 367 int ret; 368 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 369 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 370 struct psp_runtime_scpm_entry scpm_entry; 371 372 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 373 if (!psp->cmd) { 374 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 375 ret = -ENOMEM; 376 } 377 378 if (amdgpu_sriov_vf(adev)) 379 ret = psp_init_sriov_microcode(psp); 380 else 381 ret = psp_init_microcode(psp); 382 if (ret) { 383 DRM_ERROR("Failed to load psp firmware!\n"); 384 return ret; 385 } 386 387 adev->psp.xgmi_context.supports_extended_data = 388 !adev->gmc.xgmi.connected_to_cpu && 389 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 390 391 memset(&scpm_entry, 0, sizeof(scpm_entry)); 392 if ((psp_get_runtime_db_entry(adev, 393 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 394 &scpm_entry)) && 395 (SCPM_DISABLE != scpm_entry.scpm_status)) { 396 adev->scpm_enabled = true; 397 adev->scpm_status = scpm_entry.scpm_status; 398 } else { 399 adev->scpm_enabled = false; 400 adev->scpm_status = SCPM_DISABLE; 401 } 402 403 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 404 405 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 406 if (psp_get_runtime_db_entry(adev, 407 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 408 &boot_cfg_entry)) { 409 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 410 if ((psp->boot_cfg_bitmask) & 411 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 412 /* If psp runtime database exists, then 413 * only enable two stage memory training 414 * when TWO_STAGE_DRAM_TRAINING bit is set 415 * in runtime database */ 416 mem_training_ctx->enable_mem_training = true; 417 } 418 419 } else { 420 /* If psp runtime database doesn't exist or 421 * is invalid, force enable two stage memory 422 * training */ 423 mem_training_ctx->enable_mem_training = true; 424 } 425 426 if (mem_training_ctx->enable_mem_training) { 427 ret = psp_memory_training_init(psp); 428 if (ret) { 429 DRM_ERROR("Failed to initialize memory training!\n"); 430 return ret; 431 } 432 433 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 434 if (ret) { 435 DRM_ERROR("Failed to process memory training!\n"); 436 return ret; 437 } 438 } 439 440 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 441 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 442 ret= psp_sysfs_init(adev); 443 if (ret) { 444 return ret; 445 } 446 } 447 448 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 449 amdgpu_sriov_vf(adev) ? 450 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 451 &psp->fw_pri_bo, 452 &psp->fw_pri_mc_addr, 453 &psp->fw_pri_buf); 454 if (ret) 455 return ret; 456 457 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 458 AMDGPU_GEM_DOMAIN_VRAM, 459 &psp->fence_buf_bo, 460 &psp->fence_buf_mc_addr, 461 &psp->fence_buf); 462 if (ret) 463 goto failed1; 464 465 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 466 AMDGPU_GEM_DOMAIN_VRAM, 467 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 468 (void **)&psp->cmd_buf_mem); 469 if (ret) 470 goto failed2; 471 472 return 0; 473 474 failed2: 475 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 476 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 477 failed1: 478 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 479 &psp->fence_buf_mc_addr, &psp->fence_buf); 480 return ret; 481 } 482 483 static int psp_sw_fini(void *handle) 484 { 485 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 486 struct psp_context *psp = &adev->psp; 487 struct psp_gfx_cmd_resp *cmd = psp->cmd; 488 489 psp_memory_training_fini(psp); 490 if (psp->sos_fw) { 491 release_firmware(psp->sos_fw); 492 psp->sos_fw = NULL; 493 } 494 if (psp->asd_fw) { 495 release_firmware(psp->asd_fw); 496 psp->asd_fw = NULL; 497 } 498 if (psp->ta_fw) { 499 release_firmware(psp->ta_fw); 500 psp->ta_fw = NULL; 501 } 502 if (psp->cap_fw) { 503 release_firmware(psp->cap_fw); 504 psp->cap_fw = NULL; 505 } 506 if (psp->toc_fw) { 507 release_firmware(psp->toc_fw); 508 psp->toc_fw = NULL; 509 } 510 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 511 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 512 psp_sysfs_fini(adev); 513 514 kfree(cmd); 515 cmd = NULL; 516 517 if (psp->km_ring.ring_mem) 518 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 519 &psp->km_ring.ring_mem_mc_addr, 520 (void **)&psp->km_ring.ring_mem); 521 522 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 523 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 524 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 525 &psp->fence_buf_mc_addr, &psp->fence_buf); 526 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 527 (void **)&psp->cmd_buf_mem); 528 529 return 0; 530 } 531 532 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 533 uint32_t reg_val, uint32_t mask, bool check_changed) 534 { 535 uint32_t val; 536 int i; 537 struct amdgpu_device *adev = psp->adev; 538 539 if (psp->adev->no_hw_access) 540 return 0; 541 542 for (i = 0; i < adev->usec_timeout; i++) { 543 val = RREG32(reg_index); 544 if (check_changed) { 545 if (val != reg_val) 546 return 0; 547 } else { 548 if ((val & mask) == reg_val) 549 return 0; 550 } 551 udelay(1); 552 } 553 554 return -ETIME; 555 } 556 557 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 558 { 559 switch (cmd_id) { 560 case GFX_CMD_ID_LOAD_TA: 561 return "LOAD_TA"; 562 case GFX_CMD_ID_UNLOAD_TA: 563 return "UNLOAD_TA"; 564 case GFX_CMD_ID_INVOKE_CMD: 565 return "INVOKE_CMD"; 566 case GFX_CMD_ID_LOAD_ASD: 567 return "LOAD_ASD"; 568 case GFX_CMD_ID_SETUP_TMR: 569 return "SETUP_TMR"; 570 case GFX_CMD_ID_LOAD_IP_FW: 571 return "LOAD_IP_FW"; 572 case GFX_CMD_ID_DESTROY_TMR: 573 return "DESTROY_TMR"; 574 case GFX_CMD_ID_SAVE_RESTORE: 575 return "SAVE_RESTORE_IP_FW"; 576 case GFX_CMD_ID_SETUP_VMR: 577 return "SETUP_VMR"; 578 case GFX_CMD_ID_DESTROY_VMR: 579 return "DESTROY_VMR"; 580 case GFX_CMD_ID_PROG_REG: 581 return "PROG_REG"; 582 case GFX_CMD_ID_GET_FW_ATTESTATION: 583 return "GET_FW_ATTESTATION"; 584 case GFX_CMD_ID_LOAD_TOC: 585 return "ID_LOAD_TOC"; 586 case GFX_CMD_ID_AUTOLOAD_RLC: 587 return "AUTOLOAD_RLC"; 588 case GFX_CMD_ID_BOOT_CFG: 589 return "BOOT_CFG"; 590 default: 591 return "UNKNOWN CMD"; 592 } 593 } 594 595 static int 596 psp_cmd_submit_buf(struct psp_context *psp, 597 struct amdgpu_firmware_info *ucode, 598 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 599 { 600 int ret; 601 int index, idx; 602 int timeout = 20000; 603 bool ras_intr = false; 604 bool skip_unsupport = false; 605 606 if (psp->adev->no_hw_access) 607 return 0; 608 609 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 610 return 0; 611 612 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 613 614 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 615 616 index = atomic_inc_return(&psp->fence_value); 617 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 618 if (ret) { 619 atomic_dec(&psp->fence_value); 620 goto exit; 621 } 622 623 amdgpu_device_invalidate_hdp(psp->adev, NULL); 624 while (*((unsigned int *)psp->fence_buf) != index) { 625 if (--timeout == 0) 626 break; 627 /* 628 * Shouldn't wait for timeout when err_event_athub occurs, 629 * because gpu reset thread triggered and lock resource should 630 * be released for psp resume sequence. 631 */ 632 ras_intr = amdgpu_ras_intr_triggered(); 633 if (ras_intr) 634 break; 635 usleep_range(10, 100); 636 amdgpu_device_invalidate_hdp(psp->adev, NULL); 637 } 638 639 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 640 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 641 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 642 643 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 644 645 /* In some cases, psp response status is not 0 even there is no 646 * problem while the command is submitted. Some version of PSP FW 647 * doesn't write 0 to that field. 648 * So here we would like to only print a warning instead of an error 649 * during psp initialization to avoid breaking hw_init and it doesn't 650 * return -EINVAL. 651 */ 652 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 653 if (ucode) 654 DRM_WARN("failed to load ucode %s(0x%X) ", 655 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 656 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 657 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 658 psp->cmd_buf_mem->resp.status); 659 /* If any firmware (including CAP) load fails under SRIOV, it should 660 * return failure to stop the VF from initializing. 661 * Also return failure in case of timeout 662 */ 663 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 664 ret = -EINVAL; 665 goto exit; 666 } 667 } 668 669 if (ucode) { 670 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 671 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 672 } 673 674 exit: 675 drm_dev_exit(idx); 676 return ret; 677 } 678 679 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 680 { 681 struct psp_gfx_cmd_resp *cmd = psp->cmd; 682 683 mutex_lock(&psp->mutex); 684 685 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 686 687 return cmd; 688 } 689 690 static void release_psp_cmd_buf(struct psp_context *psp) 691 { 692 mutex_unlock(&psp->mutex); 693 } 694 695 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 696 struct psp_gfx_cmd_resp *cmd, 697 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 698 { 699 struct amdgpu_device *adev = psp->adev; 700 uint32_t size = amdgpu_bo_size(tmr_bo); 701 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 702 703 if (amdgpu_sriov_vf(psp->adev)) 704 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 705 else 706 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 707 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 708 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 709 cmd->cmd.cmd_setup_tmr.buf_size = size; 710 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 711 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 712 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 713 } 714 715 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 716 uint64_t pri_buf_mc, uint32_t size) 717 { 718 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 719 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 720 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 721 cmd->cmd.cmd_load_toc.toc_size = size; 722 } 723 724 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 725 static int psp_load_toc(struct psp_context *psp, 726 uint32_t *tmr_size) 727 { 728 int ret; 729 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 730 731 /* Copy toc to psp firmware private buffer */ 732 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 733 734 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 735 736 ret = psp_cmd_submit_buf(psp, NULL, cmd, 737 psp->fence_buf_mc_addr); 738 if (!ret) 739 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 740 741 release_psp_cmd_buf(psp); 742 743 return ret; 744 } 745 746 /* Set up Trusted Memory Region */ 747 static int psp_tmr_init(struct psp_context *psp) 748 { 749 int ret = 0; 750 int tmr_size; 751 void *tmr_buf; 752 void **pptr; 753 754 /* 755 * According to HW engineer, they prefer the TMR address be "naturally 756 * aligned" , e.g. the start address be an integer divide of TMR size. 757 * 758 * Note: this memory need be reserved till the driver 759 * uninitializes. 760 */ 761 tmr_size = PSP_TMR_SIZE(psp->adev); 762 763 /* For ASICs support RLC autoload, psp will parse the toc 764 * and calculate the total size of TMR needed */ 765 if (!amdgpu_sriov_vf(psp->adev) && 766 psp->toc.start_addr && 767 psp->toc.size_bytes && 768 psp->fw_pri_buf) { 769 ret = psp_load_toc(psp, &tmr_size); 770 if (ret) { 771 DRM_ERROR("Failed to load toc\n"); 772 return ret; 773 } 774 } 775 776 if (!psp->tmr_bo) { 777 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 778 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT, 779 AMDGPU_GEM_DOMAIN_VRAM, 780 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 781 } 782 783 return ret; 784 } 785 786 static bool psp_skip_tmr(struct psp_context *psp) 787 { 788 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 789 case IP_VERSION(11, 0, 9): 790 case IP_VERSION(11, 0, 7): 791 case IP_VERSION(13, 0, 2): 792 case IP_VERSION(13, 0, 10): 793 return true; 794 default: 795 return false; 796 } 797 } 798 799 static int psp_tmr_load(struct psp_context *psp) 800 { 801 int ret; 802 struct psp_gfx_cmd_resp *cmd; 803 804 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 805 * Already set up by host driver. 806 */ 807 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 808 return 0; 809 810 cmd = acquire_psp_cmd_buf(psp); 811 812 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 813 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 814 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 815 816 ret = psp_cmd_submit_buf(psp, NULL, cmd, 817 psp->fence_buf_mc_addr); 818 819 release_psp_cmd_buf(psp); 820 821 return ret; 822 } 823 824 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 825 struct psp_gfx_cmd_resp *cmd) 826 { 827 if (amdgpu_sriov_vf(psp->adev)) 828 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 829 else 830 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 831 } 832 833 static int psp_tmr_unload(struct psp_context *psp) 834 { 835 int ret; 836 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 837 838 psp_prep_tmr_unload_cmd_buf(psp, cmd); 839 dev_info(psp->adev->dev, "free PSP TMR buffer\n"); 840 841 ret = psp_cmd_submit_buf(psp, NULL, cmd, 842 psp->fence_buf_mc_addr); 843 844 release_psp_cmd_buf(psp); 845 846 return ret; 847 } 848 849 static int psp_tmr_terminate(struct psp_context *psp) 850 { 851 return psp_tmr_unload(psp); 852 } 853 854 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 855 uint64_t *output_ptr) 856 { 857 int ret; 858 struct psp_gfx_cmd_resp *cmd; 859 860 if (!output_ptr) 861 return -EINVAL; 862 863 if (amdgpu_sriov_vf(psp->adev)) 864 return 0; 865 866 cmd = acquire_psp_cmd_buf(psp); 867 868 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 869 870 ret = psp_cmd_submit_buf(psp, NULL, cmd, 871 psp->fence_buf_mc_addr); 872 873 if (!ret) { 874 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 875 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 876 } 877 878 release_psp_cmd_buf(psp); 879 880 return ret; 881 } 882 883 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 884 { 885 struct psp_context *psp = &adev->psp; 886 struct psp_gfx_cmd_resp *cmd; 887 int ret; 888 889 if (amdgpu_sriov_vf(adev)) 890 return 0; 891 892 cmd = acquire_psp_cmd_buf(psp); 893 894 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 895 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 896 897 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 898 if (!ret) { 899 *boot_cfg = 900 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 901 } 902 903 release_psp_cmd_buf(psp); 904 905 return ret; 906 } 907 908 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 909 { 910 int ret; 911 struct psp_context *psp = &adev->psp; 912 struct psp_gfx_cmd_resp *cmd; 913 914 if (amdgpu_sriov_vf(adev)) 915 return 0; 916 917 cmd = acquire_psp_cmd_buf(psp); 918 919 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 920 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 921 cmd->cmd.boot_cfg.boot_config = boot_cfg; 922 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 923 924 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 925 926 release_psp_cmd_buf(psp); 927 928 return ret; 929 } 930 931 static int psp_rl_load(struct amdgpu_device *adev) 932 { 933 int ret; 934 struct psp_context *psp = &adev->psp; 935 struct psp_gfx_cmd_resp *cmd; 936 937 if (!is_psp_fw_valid(psp->rl)) 938 return 0; 939 940 cmd = acquire_psp_cmd_buf(psp); 941 942 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 943 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 944 945 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 946 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 947 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 948 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 949 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 950 951 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 952 953 release_psp_cmd_buf(psp); 954 955 return ret; 956 } 957 958 static int psp_asd_initialize(struct psp_context *psp) 959 { 960 int ret; 961 962 /* If PSP version doesn't match ASD version, asd loading will be failed. 963 * add workaround to bypass it for sriov now. 964 * TODO: add version check to make it common 965 */ 966 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 967 return 0; 968 969 psp->asd_context.mem_context.shared_mc_addr = 0; 970 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 971 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 972 973 ret = psp_ta_load(psp, &psp->asd_context); 974 if (!ret) 975 psp->asd_context.initialized = true; 976 977 return ret; 978 } 979 980 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 981 uint32_t session_id) 982 { 983 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 984 cmd->cmd.cmd_unload_ta.session_id = session_id; 985 } 986 987 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 988 { 989 int ret; 990 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 991 992 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 993 994 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 995 996 release_psp_cmd_buf(psp); 997 998 return ret; 999 } 1000 1001 static int psp_asd_terminate(struct psp_context *psp) 1002 { 1003 int ret; 1004 1005 if (amdgpu_sriov_vf(psp->adev)) 1006 return 0; 1007 1008 if (!psp->asd_context.initialized) 1009 return 0; 1010 1011 ret = psp_ta_unload(psp, &psp->asd_context); 1012 if (!ret) 1013 psp->asd_context.initialized = false; 1014 1015 return ret; 1016 } 1017 1018 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1019 uint32_t id, uint32_t value) 1020 { 1021 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1022 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1023 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1024 } 1025 1026 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1027 uint32_t value) 1028 { 1029 struct psp_gfx_cmd_resp *cmd; 1030 int ret = 0; 1031 1032 if (reg >= PSP_REG_LAST) 1033 return -EINVAL; 1034 1035 cmd = acquire_psp_cmd_buf(psp); 1036 1037 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1038 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1039 if (ret) 1040 DRM_ERROR("PSP failed to program reg id %d", reg); 1041 1042 release_psp_cmd_buf(psp); 1043 1044 return ret; 1045 } 1046 1047 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1048 uint64_t ta_bin_mc, 1049 struct ta_context *context) 1050 { 1051 cmd->cmd_id = context->ta_load_type; 1052 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1053 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1054 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1055 1056 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1057 lower_32_bits(context->mem_context.shared_mc_addr); 1058 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1059 upper_32_bits(context->mem_context.shared_mc_addr); 1060 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1061 } 1062 1063 int psp_ta_init_shared_buf(struct psp_context *psp, 1064 struct ta_mem_context *mem_ctx) 1065 { 1066 /* 1067 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1068 * physical) for ta to host memory 1069 */ 1070 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1071 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1072 &mem_ctx->shared_bo, 1073 &mem_ctx->shared_mc_addr, 1074 &mem_ctx->shared_buf); 1075 } 1076 1077 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1078 uint32_t ta_cmd_id, 1079 struct ta_context *context) 1080 { 1081 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1082 cmd->cmd.cmd_invoke_cmd.session_id = context->session_id; 1083 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1084 1085 cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1; 1086 cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size; 1087 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size; 1088 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo = 1089 lower_32_bits(context->mem_context.shared_mc_addr); 1090 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi = 1091 upper_32_bits(context->mem_context.shared_mc_addr); 1092 } 1093 1094 int psp_ta_invoke_indirect(struct psp_context *psp, 1095 uint32_t ta_cmd_id, 1096 struct ta_context *context) 1097 { 1098 int ret; 1099 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1100 1101 psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context); 1102 1103 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1104 psp->fence_buf_mc_addr); 1105 1106 context->resp_status = cmd->resp.status; 1107 1108 release_psp_cmd_buf(psp); 1109 1110 return ret; 1111 } 1112 1113 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1114 uint32_t ta_cmd_id, 1115 uint32_t session_id) 1116 { 1117 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1118 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1119 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1120 } 1121 1122 int psp_ta_invoke(struct psp_context *psp, 1123 uint32_t ta_cmd_id, 1124 struct ta_context *context) 1125 { 1126 int ret; 1127 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1128 1129 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1130 1131 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1132 psp->fence_buf_mc_addr); 1133 1134 context->resp_status = cmd->resp.status; 1135 1136 release_psp_cmd_buf(psp); 1137 1138 return ret; 1139 } 1140 1141 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1142 { 1143 int ret; 1144 struct psp_gfx_cmd_resp *cmd; 1145 1146 cmd = acquire_psp_cmd_buf(psp); 1147 1148 psp_copy_fw(psp, context->bin_desc.start_addr, 1149 context->bin_desc.size_bytes); 1150 1151 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1152 1153 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1154 psp->fence_buf_mc_addr); 1155 1156 context->resp_status = cmd->resp.status; 1157 1158 if (!ret) { 1159 context->session_id = cmd->resp.session_id; 1160 } 1161 1162 release_psp_cmd_buf(psp); 1163 1164 return ret; 1165 } 1166 1167 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1168 { 1169 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1170 } 1171 1172 int psp_xgmi_terminate(struct psp_context *psp) 1173 { 1174 int ret; 1175 struct amdgpu_device *adev = psp->adev; 1176 1177 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1178 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1179 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1180 adev->gmc.xgmi.connected_to_cpu)) 1181 return 0; 1182 1183 if (!psp->xgmi_context.context.initialized) 1184 return 0; 1185 1186 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1187 1188 psp->xgmi_context.context.initialized = false; 1189 1190 return ret; 1191 } 1192 1193 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1194 { 1195 struct ta_xgmi_shared_memory *xgmi_cmd; 1196 int ret; 1197 1198 if (!psp->ta_fw || 1199 !psp->xgmi_context.context.bin_desc.size_bytes || 1200 !psp->xgmi_context.context.bin_desc.start_addr) 1201 return -ENOENT; 1202 1203 if (!load_ta) 1204 goto invoke; 1205 1206 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1207 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1208 1209 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1210 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1211 if (ret) 1212 return ret; 1213 } 1214 1215 /* Load XGMI TA */ 1216 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1217 if (!ret) 1218 psp->xgmi_context.context.initialized = true; 1219 else 1220 return ret; 1221 1222 invoke: 1223 /* Initialize XGMI session */ 1224 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1225 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1226 xgmi_cmd->flag_extend_link_record = set_extended_data; 1227 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1228 1229 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1230 1231 return ret; 1232 } 1233 1234 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1235 { 1236 struct ta_xgmi_shared_memory *xgmi_cmd; 1237 int ret; 1238 1239 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1240 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1241 1242 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1243 1244 /* Invoke xgmi ta to get hive id */ 1245 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1246 if (ret) 1247 return ret; 1248 1249 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1250 1251 return 0; 1252 } 1253 1254 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1255 { 1256 struct ta_xgmi_shared_memory *xgmi_cmd; 1257 int ret; 1258 1259 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1260 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1261 1262 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1263 1264 /* Invoke xgmi ta to get the node id */ 1265 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1266 if (ret) 1267 return ret; 1268 1269 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1270 1271 return 0; 1272 } 1273 1274 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1275 { 1276 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1277 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1278 } 1279 1280 /* 1281 * Chips that support extended topology information require the driver to 1282 * reflect topology information in the opposite direction. This is 1283 * because the TA has already exceeded its link record limit and if the 1284 * TA holds bi-directional information, the driver would have to do 1285 * multiple fetches instead of just two. 1286 */ 1287 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1288 struct psp_xgmi_node_info node_info) 1289 { 1290 struct amdgpu_device *mirror_adev; 1291 struct amdgpu_hive_info *hive; 1292 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1293 uint64_t dst_node_id = node_info.node_id; 1294 uint8_t dst_num_hops = node_info.num_hops; 1295 uint8_t dst_num_links = node_info.num_links; 1296 1297 hive = amdgpu_get_xgmi_hive(psp->adev); 1298 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1299 struct psp_xgmi_topology_info *mirror_top_info; 1300 int j; 1301 1302 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1303 continue; 1304 1305 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1306 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1307 if (mirror_top_info->nodes[j].node_id != src_node_id) 1308 continue; 1309 1310 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1311 /* 1312 * prevent 0 num_links value re-reflection since reflection 1313 * criteria is based on num_hops (direct or indirect). 1314 * 1315 */ 1316 if (dst_num_links) 1317 mirror_top_info->nodes[j].num_links = dst_num_links; 1318 1319 break; 1320 } 1321 1322 break; 1323 } 1324 1325 amdgpu_put_xgmi_hive(hive); 1326 } 1327 1328 int psp_xgmi_get_topology_info(struct psp_context *psp, 1329 int number_devices, 1330 struct psp_xgmi_topology_info *topology, 1331 bool get_extended_data) 1332 { 1333 struct ta_xgmi_shared_memory *xgmi_cmd; 1334 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1335 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1336 int i; 1337 int ret; 1338 1339 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1340 return -EINVAL; 1341 1342 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1343 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1344 xgmi_cmd->flag_extend_link_record = get_extended_data; 1345 1346 /* Fill in the shared memory with topology information as input */ 1347 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1348 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1349 topology_info_input->num_nodes = number_devices; 1350 1351 for (i = 0; i < topology_info_input->num_nodes; i++) { 1352 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1353 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1354 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1355 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1356 } 1357 1358 /* Invoke xgmi ta to get the topology information */ 1359 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1360 if (ret) 1361 return ret; 1362 1363 /* Read the output topology information from the shared memory */ 1364 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1365 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1366 for (i = 0; i < topology->num_nodes; i++) { 1367 /* extended data will either be 0 or equal to non-extended data */ 1368 if (topology_info_output->nodes[i].num_hops) 1369 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1370 1371 /* non-extended data gets everything here so no need to update */ 1372 if (!get_extended_data) { 1373 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1374 topology->nodes[i].is_sharing_enabled = 1375 topology_info_output->nodes[i].is_sharing_enabled; 1376 topology->nodes[i].sdma_engine = 1377 topology_info_output->nodes[i].sdma_engine; 1378 } 1379 1380 } 1381 1382 /* Invoke xgmi ta again to get the link information */ 1383 if (psp_xgmi_peer_link_info_supported(psp)) { 1384 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1385 1386 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1387 1388 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1389 1390 if (ret) 1391 return ret; 1392 1393 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1394 for (i = 0; i < topology->num_nodes; i++) { 1395 /* accumulate num_links on extended data */ 1396 topology->nodes[i].num_links = get_extended_data ? 1397 topology->nodes[i].num_links + 1398 link_info_output->nodes[i].num_links : 1399 link_info_output->nodes[i].num_links; 1400 1401 /* reflect the topology information for bi-directionality */ 1402 if (psp->xgmi_context.supports_extended_data && 1403 get_extended_data && topology->nodes[i].num_hops) 1404 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1405 } 1406 } 1407 1408 return 0; 1409 } 1410 1411 int psp_xgmi_set_topology_info(struct psp_context *psp, 1412 int number_devices, 1413 struct psp_xgmi_topology_info *topology) 1414 { 1415 struct ta_xgmi_shared_memory *xgmi_cmd; 1416 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1417 int i; 1418 1419 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1420 return -EINVAL; 1421 1422 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1423 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1424 1425 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1426 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1427 topology_info_input->num_nodes = number_devices; 1428 1429 for (i = 0; i < topology_info_input->num_nodes; i++) { 1430 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1431 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1432 topology_info_input->nodes[i].is_sharing_enabled = 1; 1433 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1434 } 1435 1436 /* Invoke xgmi ta to set topology information */ 1437 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1438 } 1439 1440 // ras begin 1441 static void psp_ras_ta_check_status(struct psp_context *psp) 1442 { 1443 struct ta_ras_shared_memory *ras_cmd = 1444 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1445 1446 switch (ras_cmd->ras_status) { 1447 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1448 dev_warn(psp->adev->dev, 1449 "RAS WARNING: cmd failed due to unsupported ip\n"); 1450 break; 1451 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1452 dev_warn(psp->adev->dev, 1453 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1454 break; 1455 case TA_RAS_STATUS__SUCCESS: 1456 break; 1457 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1458 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1459 dev_warn(psp->adev->dev, 1460 "RAS WARNING: Inject error to critical region is not allowed\n"); 1461 break; 1462 default: 1463 dev_warn(psp->adev->dev, 1464 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1465 break; 1466 } 1467 } 1468 1469 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1470 { 1471 struct ta_ras_shared_memory *ras_cmd; 1472 int ret; 1473 1474 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1475 1476 /* 1477 * TODO: bypass the loading in sriov for now 1478 */ 1479 if (amdgpu_sriov_vf(psp->adev)) 1480 return 0; 1481 1482 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1483 1484 if (amdgpu_ras_intr_triggered()) 1485 return ret; 1486 1487 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1488 { 1489 DRM_WARN("RAS: Unsupported Interface"); 1490 return -EINVAL; 1491 } 1492 1493 if (!ret) { 1494 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1495 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1496 1497 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1498 } 1499 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1500 dev_warn(psp->adev->dev, 1501 "RAS internal register access blocked\n"); 1502 1503 psp_ras_ta_check_status(psp); 1504 } 1505 1506 return ret; 1507 } 1508 1509 int psp_ras_enable_features(struct psp_context *psp, 1510 union ta_ras_cmd_input *info, bool enable) 1511 { 1512 struct ta_ras_shared_memory *ras_cmd; 1513 int ret; 1514 1515 if (!psp->ras_context.context.initialized) 1516 return -EINVAL; 1517 1518 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1519 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1520 1521 if (enable) 1522 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1523 else 1524 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1525 1526 ras_cmd->ras_in_message = *info; 1527 1528 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1529 if (ret) 1530 return -EINVAL; 1531 1532 return 0; 1533 } 1534 1535 int psp_ras_terminate(struct psp_context *psp) 1536 { 1537 int ret; 1538 1539 /* 1540 * TODO: bypass the terminate in sriov for now 1541 */ 1542 if (amdgpu_sriov_vf(psp->adev)) 1543 return 0; 1544 1545 if (!psp->ras_context.context.initialized) 1546 return 0; 1547 1548 ret = psp_ta_unload(psp, &psp->ras_context.context); 1549 1550 psp->ras_context.context.initialized = false; 1551 1552 return ret; 1553 } 1554 1555 static int psp_ras_initialize(struct psp_context *psp) 1556 { 1557 int ret; 1558 uint32_t boot_cfg = 0xFF; 1559 struct amdgpu_device *adev = psp->adev; 1560 struct ta_ras_shared_memory *ras_cmd; 1561 1562 /* 1563 * TODO: bypass the initialize in sriov for now 1564 */ 1565 if (amdgpu_sriov_vf(adev)) 1566 return 0; 1567 1568 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1569 !adev->psp.ras_context.context.bin_desc.start_addr) { 1570 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1571 return 0; 1572 } 1573 1574 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1575 /* query GECC enablement status from boot config 1576 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1577 */ 1578 ret = psp_boot_config_get(adev, &boot_cfg); 1579 if (ret) 1580 dev_warn(adev->dev, "PSP get boot config failed\n"); 1581 1582 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1583 if (!boot_cfg) { 1584 dev_info(adev->dev, "GECC is disabled\n"); 1585 } else { 1586 /* disable GECC in next boot cycle if ras is 1587 * disabled by module parameter amdgpu_ras_enable 1588 * and/or amdgpu_ras_mask, or boot_config_get call 1589 * is failed 1590 */ 1591 ret = psp_boot_config_set(adev, 0); 1592 if (ret) 1593 dev_warn(adev->dev, "PSP set boot config failed\n"); 1594 else 1595 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1596 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1597 } 1598 } else { 1599 if (1 == boot_cfg) { 1600 dev_info(adev->dev, "GECC is enabled\n"); 1601 } else { 1602 /* enable GECC in next boot cycle if it is disabled 1603 * in boot config, or force enable GECC if failed to 1604 * get boot configuration 1605 */ 1606 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1607 if (ret) 1608 dev_warn(adev->dev, "PSP set boot config failed\n"); 1609 else 1610 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1611 } 1612 } 1613 } 1614 1615 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1616 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1617 1618 if (!psp->ras_context.context.initialized) { 1619 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1620 if (ret) 1621 return ret; 1622 } 1623 1624 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1625 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1626 1627 if (amdgpu_ras_is_poison_mode_supported(adev)) 1628 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1629 if (!adev->gmc.xgmi.connected_to_cpu) 1630 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1631 1632 ret = psp_ta_load(psp, &psp->ras_context.context); 1633 1634 if (!ret && !ras_cmd->ras_status) 1635 psp->ras_context.context.initialized = true; 1636 else { 1637 if (ras_cmd->ras_status) 1638 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1639 amdgpu_ras_fini(psp->adev); 1640 } 1641 1642 return ret; 1643 } 1644 1645 int psp_ras_trigger_error(struct psp_context *psp, 1646 struct ta_ras_trigger_error_input *info) 1647 { 1648 struct ta_ras_shared_memory *ras_cmd; 1649 int ret; 1650 1651 if (!psp->ras_context.context.initialized) 1652 return -EINVAL; 1653 1654 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1655 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1656 1657 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1658 ras_cmd->ras_in_message.trigger_error = *info; 1659 1660 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1661 if (ret) 1662 return -EINVAL; 1663 1664 /* If err_event_athub occurs error inject was successful, however 1665 return status from TA is no long reliable */ 1666 if (amdgpu_ras_intr_triggered()) 1667 return 0; 1668 1669 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1670 return -EACCES; 1671 else if (ras_cmd->ras_status) 1672 return -EINVAL; 1673 1674 return 0; 1675 } 1676 // ras end 1677 1678 // HDCP start 1679 static int psp_hdcp_initialize(struct psp_context *psp) 1680 { 1681 int ret; 1682 1683 /* 1684 * TODO: bypass the initialize in sriov for now 1685 */ 1686 if (amdgpu_sriov_vf(psp->adev)) 1687 return 0; 1688 1689 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1690 !psp->hdcp_context.context.bin_desc.start_addr) { 1691 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1692 return 0; 1693 } 1694 1695 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1696 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1697 1698 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1699 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1700 if (ret) 1701 return ret; 1702 } 1703 1704 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1705 if (!ret) { 1706 psp->hdcp_context.context.initialized = true; 1707 rw_init(&psp->hdcp_context.mutex, "pspcp"); 1708 } 1709 1710 return ret; 1711 } 1712 1713 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1714 { 1715 /* 1716 * TODO: bypass the loading in sriov for now 1717 */ 1718 if (amdgpu_sriov_vf(psp->adev)) 1719 return 0; 1720 1721 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1722 } 1723 1724 static int psp_hdcp_terminate(struct psp_context *psp) 1725 { 1726 int ret; 1727 1728 /* 1729 * TODO: bypass the terminate in sriov for now 1730 */ 1731 if (amdgpu_sriov_vf(psp->adev)) 1732 return 0; 1733 1734 if (!psp->hdcp_context.context.initialized) 1735 return 0; 1736 1737 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1738 1739 psp->hdcp_context.context.initialized = false; 1740 1741 return ret; 1742 } 1743 // HDCP end 1744 1745 // DTM start 1746 static int psp_dtm_initialize(struct psp_context *psp) 1747 { 1748 int ret; 1749 1750 /* 1751 * TODO: bypass the initialize in sriov for now 1752 */ 1753 if (amdgpu_sriov_vf(psp->adev)) 1754 return 0; 1755 1756 if (!psp->dtm_context.context.bin_desc.size_bytes || 1757 !psp->dtm_context.context.bin_desc.start_addr) { 1758 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1759 return 0; 1760 } 1761 1762 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1763 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1764 1765 if (!psp->dtm_context.context.mem_context.shared_buf) { 1766 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1767 if (ret) 1768 return ret; 1769 } 1770 1771 ret = psp_ta_load(psp, &psp->dtm_context.context); 1772 if (!ret) { 1773 psp->dtm_context.context.initialized = true; 1774 rw_init(&psp->dtm_context.mutex, "pspdtm"); 1775 } 1776 1777 return ret; 1778 } 1779 1780 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1781 { 1782 /* 1783 * TODO: bypass the loading in sriov for now 1784 */ 1785 if (amdgpu_sriov_vf(psp->adev)) 1786 return 0; 1787 1788 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1789 } 1790 1791 static int psp_dtm_terminate(struct psp_context *psp) 1792 { 1793 int ret; 1794 1795 /* 1796 * TODO: bypass the terminate in sriov for now 1797 */ 1798 if (amdgpu_sriov_vf(psp->adev)) 1799 return 0; 1800 1801 if (!psp->dtm_context.context.initialized) 1802 return 0; 1803 1804 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1805 1806 psp->dtm_context.context.initialized = false; 1807 1808 return ret; 1809 } 1810 // DTM end 1811 1812 // RAP start 1813 static int psp_rap_initialize(struct psp_context *psp) 1814 { 1815 int ret; 1816 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1817 1818 /* 1819 * TODO: bypass the initialize in sriov for now 1820 */ 1821 if (amdgpu_sriov_vf(psp->adev)) 1822 return 0; 1823 1824 if (!psp->rap_context.context.bin_desc.size_bytes || 1825 !psp->rap_context.context.bin_desc.start_addr) { 1826 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1827 return 0; 1828 } 1829 1830 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1831 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1832 1833 if (!psp->rap_context.context.mem_context.shared_buf) { 1834 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1835 if (ret) 1836 return ret; 1837 } 1838 1839 ret = psp_ta_load(psp, &psp->rap_context.context); 1840 if (!ret) { 1841 psp->rap_context.context.initialized = true; 1842 rw_init(&psp->rap_context.mutex, "psprap"); 1843 } else 1844 return ret; 1845 1846 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1847 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1848 psp_rap_terminate(psp); 1849 /* free rap shared memory */ 1850 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1851 1852 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1853 ret, status); 1854 1855 return ret; 1856 } 1857 1858 return 0; 1859 } 1860 1861 static int psp_rap_terminate(struct psp_context *psp) 1862 { 1863 int ret; 1864 1865 if (!psp->rap_context.context.initialized) 1866 return 0; 1867 1868 ret = psp_ta_unload(psp, &psp->rap_context.context); 1869 1870 psp->rap_context.context.initialized = false; 1871 1872 return ret; 1873 } 1874 1875 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1876 { 1877 struct ta_rap_shared_memory *rap_cmd; 1878 int ret = 0; 1879 1880 if (!psp->rap_context.context.initialized) 1881 return 0; 1882 1883 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1884 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1885 return -EINVAL; 1886 1887 mutex_lock(&psp->rap_context.mutex); 1888 1889 rap_cmd = (struct ta_rap_shared_memory *) 1890 psp->rap_context.context.mem_context.shared_buf; 1891 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1892 1893 rap_cmd->cmd_id = ta_cmd_id; 1894 rap_cmd->validation_method_id = METHOD_A; 1895 1896 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1897 if (ret) 1898 goto out_unlock; 1899 1900 if (status) 1901 *status = rap_cmd->rap_status; 1902 1903 out_unlock: 1904 mutex_unlock(&psp->rap_context.mutex); 1905 1906 return ret; 1907 } 1908 // RAP end 1909 1910 /* securedisplay start */ 1911 static int psp_securedisplay_initialize(struct psp_context *psp) 1912 { 1913 int ret; 1914 struct securedisplay_cmd *securedisplay_cmd; 1915 1916 /* 1917 * TODO: bypass the initialize in sriov for now 1918 */ 1919 if (amdgpu_sriov_vf(psp->adev)) 1920 return 0; 1921 1922 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1923 !psp->securedisplay_context.context.bin_desc.start_addr) { 1924 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1925 return 0; 1926 } 1927 1928 #ifdef __OpenBSD__ 1929 /* 1930 * with 20230117 or later firmware or later on renoir: 1931 * 1932 * [drm] psp gfx command LOAD_TA(0x1) failed and response status is (0x7) 1933 * [drm] psp gfx command INVOKE_CMD(0x3) failed and response status is (0x4) 1934 * psp_securedisplay_parse_resp_status *ERROR* Secure display: Generic Failure 1935 * psp_securedisplay_initialize *ERROR* SECUREDISPLAY: query 1936 * securedisplay TA failed. ret 0x0 1937 */ 1938 return 0; 1939 #endif 1940 1941 psp->securedisplay_context.context.mem_context.shared_mem_size = 1942 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1943 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1944 1945 if (!psp->securedisplay_context.context.initialized) { 1946 ret = psp_ta_init_shared_buf(psp, 1947 &psp->securedisplay_context.context.mem_context); 1948 if (ret) 1949 return ret; 1950 } 1951 1952 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1953 if (!ret) { 1954 psp->securedisplay_context.context.initialized = true; 1955 rw_init(&psp->securedisplay_context.mutex, "pscm"); 1956 } else 1957 return ret; 1958 1959 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1960 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1961 1962 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1963 if (ret) { 1964 psp_securedisplay_terminate(psp); 1965 /* free securedisplay shared memory */ 1966 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1967 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1968 return -EINVAL; 1969 } 1970 1971 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1972 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1973 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1974 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1975 } 1976 1977 return 0; 1978 } 1979 1980 static int psp_securedisplay_terminate(struct psp_context *psp) 1981 { 1982 int ret; 1983 1984 /* 1985 * TODO:bypass the terminate in sriov for now 1986 */ 1987 if (amdgpu_sriov_vf(psp->adev)) 1988 return 0; 1989 1990 if (!psp->securedisplay_context.context.initialized) 1991 return 0; 1992 1993 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1994 1995 psp->securedisplay_context.context.initialized = false; 1996 1997 return ret; 1998 } 1999 2000 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2001 { 2002 int ret; 2003 2004 if (!psp->securedisplay_context.context.initialized) 2005 return -EINVAL; 2006 2007 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2008 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2009 return -EINVAL; 2010 2011 mutex_lock(&psp->securedisplay_context.mutex); 2012 2013 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2014 2015 mutex_unlock(&psp->securedisplay_context.mutex); 2016 2017 return ret; 2018 } 2019 /* SECUREDISPLAY end */ 2020 2021 static int psp_hw_start(struct psp_context *psp) 2022 { 2023 struct amdgpu_device *adev = psp->adev; 2024 int ret; 2025 2026 if (!amdgpu_sriov_vf(adev)) { 2027 if ((is_psp_fw_valid(psp->kdb)) && 2028 (psp->funcs->bootloader_load_kdb != NULL)) { 2029 ret = psp_bootloader_load_kdb(psp); 2030 if (ret) { 2031 DRM_ERROR("PSP load kdb failed!\n"); 2032 return ret; 2033 } 2034 } 2035 2036 if ((is_psp_fw_valid(psp->spl)) && 2037 (psp->funcs->bootloader_load_spl != NULL)) { 2038 ret = psp_bootloader_load_spl(psp); 2039 if (ret) { 2040 DRM_ERROR("PSP load spl failed!\n"); 2041 return ret; 2042 } 2043 } 2044 2045 if ((is_psp_fw_valid(psp->sys)) && 2046 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2047 ret = psp_bootloader_load_sysdrv(psp); 2048 if (ret) { 2049 DRM_ERROR("PSP load sys drv failed!\n"); 2050 return ret; 2051 } 2052 } 2053 2054 if ((is_psp_fw_valid(psp->soc_drv)) && 2055 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2056 ret = psp_bootloader_load_soc_drv(psp); 2057 if (ret) { 2058 DRM_ERROR("PSP load soc drv failed!\n"); 2059 return ret; 2060 } 2061 } 2062 2063 if ((is_psp_fw_valid(psp->intf_drv)) && 2064 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2065 ret = psp_bootloader_load_intf_drv(psp); 2066 if (ret) { 2067 DRM_ERROR("PSP load intf drv failed!\n"); 2068 return ret; 2069 } 2070 } 2071 2072 if ((is_psp_fw_valid(psp->dbg_drv)) && 2073 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2074 ret = psp_bootloader_load_dbg_drv(psp); 2075 if (ret) { 2076 DRM_ERROR("PSP load dbg drv failed!\n"); 2077 return ret; 2078 } 2079 } 2080 2081 if ((is_psp_fw_valid(psp->ras_drv)) && 2082 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2083 ret = psp_bootloader_load_ras_drv(psp); 2084 if (ret) { 2085 DRM_ERROR("PSP load ras_drv failed!\n"); 2086 return ret; 2087 } 2088 } 2089 2090 if ((is_psp_fw_valid(psp->sos)) && 2091 (psp->funcs->bootloader_load_sos != NULL)) { 2092 ret = psp_bootloader_load_sos(psp); 2093 if (ret) { 2094 DRM_ERROR("PSP load sos failed!\n"); 2095 return ret; 2096 } 2097 } 2098 } 2099 2100 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2101 if (ret) { 2102 DRM_ERROR("PSP create ring failed!\n"); 2103 return ret; 2104 } 2105 2106 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2107 goto skip_pin_bo; 2108 2109 ret = psp_tmr_init(psp); 2110 if (ret) { 2111 DRM_ERROR("PSP tmr init failed!\n"); 2112 return ret; 2113 } 2114 2115 skip_pin_bo: 2116 /* 2117 * For ASICs with DF Cstate management centralized 2118 * to PMFW, TMR setup should be performed after PMFW 2119 * loaded and before other non-psp firmware loaded. 2120 */ 2121 if (psp->pmfw_centralized_cstate_management) { 2122 ret = psp_load_smu_fw(psp); 2123 if (ret) 2124 return ret; 2125 } 2126 2127 ret = psp_tmr_load(psp); 2128 if (ret) { 2129 DRM_ERROR("PSP load tmr failed!\n"); 2130 return ret; 2131 } 2132 2133 return 0; 2134 } 2135 2136 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2137 enum psp_gfx_fw_type *type) 2138 { 2139 switch (ucode->ucode_id) { 2140 case AMDGPU_UCODE_ID_CAP: 2141 *type = GFX_FW_TYPE_CAP; 2142 break; 2143 case AMDGPU_UCODE_ID_SDMA0: 2144 *type = GFX_FW_TYPE_SDMA0; 2145 break; 2146 case AMDGPU_UCODE_ID_SDMA1: 2147 *type = GFX_FW_TYPE_SDMA1; 2148 break; 2149 case AMDGPU_UCODE_ID_SDMA2: 2150 *type = GFX_FW_TYPE_SDMA2; 2151 break; 2152 case AMDGPU_UCODE_ID_SDMA3: 2153 *type = GFX_FW_TYPE_SDMA3; 2154 break; 2155 case AMDGPU_UCODE_ID_SDMA4: 2156 *type = GFX_FW_TYPE_SDMA4; 2157 break; 2158 case AMDGPU_UCODE_ID_SDMA5: 2159 *type = GFX_FW_TYPE_SDMA5; 2160 break; 2161 case AMDGPU_UCODE_ID_SDMA6: 2162 *type = GFX_FW_TYPE_SDMA6; 2163 break; 2164 case AMDGPU_UCODE_ID_SDMA7: 2165 *type = GFX_FW_TYPE_SDMA7; 2166 break; 2167 case AMDGPU_UCODE_ID_CP_MES: 2168 *type = GFX_FW_TYPE_CP_MES; 2169 break; 2170 case AMDGPU_UCODE_ID_CP_MES_DATA: 2171 *type = GFX_FW_TYPE_MES_STACK; 2172 break; 2173 case AMDGPU_UCODE_ID_CP_MES1: 2174 *type = GFX_FW_TYPE_CP_MES_KIQ; 2175 break; 2176 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2177 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2178 break; 2179 case AMDGPU_UCODE_ID_CP_CE: 2180 *type = GFX_FW_TYPE_CP_CE; 2181 break; 2182 case AMDGPU_UCODE_ID_CP_PFP: 2183 *type = GFX_FW_TYPE_CP_PFP; 2184 break; 2185 case AMDGPU_UCODE_ID_CP_ME: 2186 *type = GFX_FW_TYPE_CP_ME; 2187 break; 2188 case AMDGPU_UCODE_ID_CP_MEC1: 2189 *type = GFX_FW_TYPE_CP_MEC; 2190 break; 2191 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2192 *type = GFX_FW_TYPE_CP_MEC_ME1; 2193 break; 2194 case AMDGPU_UCODE_ID_CP_MEC2: 2195 *type = GFX_FW_TYPE_CP_MEC; 2196 break; 2197 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2198 *type = GFX_FW_TYPE_CP_MEC_ME2; 2199 break; 2200 case AMDGPU_UCODE_ID_RLC_P: 2201 *type = GFX_FW_TYPE_RLC_P; 2202 break; 2203 case AMDGPU_UCODE_ID_RLC_V: 2204 *type = GFX_FW_TYPE_RLC_V; 2205 break; 2206 case AMDGPU_UCODE_ID_RLC_G: 2207 *type = GFX_FW_TYPE_RLC_G; 2208 break; 2209 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2210 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2211 break; 2212 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2213 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2214 break; 2215 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2216 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2217 break; 2218 case AMDGPU_UCODE_ID_RLC_IRAM: 2219 *type = GFX_FW_TYPE_RLC_IRAM; 2220 break; 2221 case AMDGPU_UCODE_ID_RLC_DRAM: 2222 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2223 break; 2224 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2225 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2226 break; 2227 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2228 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2229 break; 2230 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2231 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2232 break; 2233 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2234 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2235 break; 2236 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2237 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2238 break; 2239 case AMDGPU_UCODE_ID_SMC: 2240 *type = GFX_FW_TYPE_SMU; 2241 break; 2242 case AMDGPU_UCODE_ID_PPTABLE: 2243 *type = GFX_FW_TYPE_PPTABLE; 2244 break; 2245 case AMDGPU_UCODE_ID_UVD: 2246 *type = GFX_FW_TYPE_UVD; 2247 break; 2248 case AMDGPU_UCODE_ID_UVD1: 2249 *type = GFX_FW_TYPE_UVD1; 2250 break; 2251 case AMDGPU_UCODE_ID_VCE: 2252 *type = GFX_FW_TYPE_VCE; 2253 break; 2254 case AMDGPU_UCODE_ID_VCN: 2255 *type = GFX_FW_TYPE_VCN; 2256 break; 2257 case AMDGPU_UCODE_ID_VCN1: 2258 *type = GFX_FW_TYPE_VCN1; 2259 break; 2260 case AMDGPU_UCODE_ID_DMCU_ERAM: 2261 *type = GFX_FW_TYPE_DMCU_ERAM; 2262 break; 2263 case AMDGPU_UCODE_ID_DMCU_INTV: 2264 *type = GFX_FW_TYPE_DMCU_ISR; 2265 break; 2266 case AMDGPU_UCODE_ID_VCN0_RAM: 2267 *type = GFX_FW_TYPE_VCN0_RAM; 2268 break; 2269 case AMDGPU_UCODE_ID_VCN1_RAM: 2270 *type = GFX_FW_TYPE_VCN1_RAM; 2271 break; 2272 case AMDGPU_UCODE_ID_DMCUB: 2273 *type = GFX_FW_TYPE_DMUB; 2274 break; 2275 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2276 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2277 break; 2278 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2279 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2280 break; 2281 case AMDGPU_UCODE_ID_IMU_I: 2282 *type = GFX_FW_TYPE_IMU_I; 2283 break; 2284 case AMDGPU_UCODE_ID_IMU_D: 2285 *type = GFX_FW_TYPE_IMU_D; 2286 break; 2287 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2288 *type = GFX_FW_TYPE_RS64_PFP; 2289 break; 2290 case AMDGPU_UCODE_ID_CP_RS64_ME: 2291 *type = GFX_FW_TYPE_RS64_ME; 2292 break; 2293 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2294 *type = GFX_FW_TYPE_RS64_MEC; 2295 break; 2296 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2297 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2298 break; 2299 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2300 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2301 break; 2302 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2303 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2304 break; 2305 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2306 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2307 break; 2308 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2309 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2310 break; 2311 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2312 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2313 break; 2314 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2315 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2316 break; 2317 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2318 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2319 break; 2320 case AMDGPU_UCODE_ID_MAXIMUM: 2321 default: 2322 return -EINVAL; 2323 } 2324 2325 return 0; 2326 } 2327 2328 static void psp_print_fw_hdr(struct psp_context *psp, 2329 struct amdgpu_firmware_info *ucode) 2330 { 2331 struct amdgpu_device *adev = psp->adev; 2332 struct common_firmware_header *hdr; 2333 2334 switch (ucode->ucode_id) { 2335 case AMDGPU_UCODE_ID_SDMA0: 2336 case AMDGPU_UCODE_ID_SDMA1: 2337 case AMDGPU_UCODE_ID_SDMA2: 2338 case AMDGPU_UCODE_ID_SDMA3: 2339 case AMDGPU_UCODE_ID_SDMA4: 2340 case AMDGPU_UCODE_ID_SDMA5: 2341 case AMDGPU_UCODE_ID_SDMA6: 2342 case AMDGPU_UCODE_ID_SDMA7: 2343 hdr = (struct common_firmware_header *) 2344 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2345 amdgpu_ucode_print_sdma_hdr(hdr); 2346 break; 2347 case AMDGPU_UCODE_ID_CP_CE: 2348 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2349 amdgpu_ucode_print_gfx_hdr(hdr); 2350 break; 2351 case AMDGPU_UCODE_ID_CP_PFP: 2352 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2353 amdgpu_ucode_print_gfx_hdr(hdr); 2354 break; 2355 case AMDGPU_UCODE_ID_CP_ME: 2356 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2357 amdgpu_ucode_print_gfx_hdr(hdr); 2358 break; 2359 case AMDGPU_UCODE_ID_CP_MEC1: 2360 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2361 amdgpu_ucode_print_gfx_hdr(hdr); 2362 break; 2363 case AMDGPU_UCODE_ID_RLC_G: 2364 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2365 amdgpu_ucode_print_rlc_hdr(hdr); 2366 break; 2367 case AMDGPU_UCODE_ID_SMC: 2368 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2369 amdgpu_ucode_print_smc_hdr(hdr); 2370 break; 2371 default: 2372 break; 2373 } 2374 } 2375 2376 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2377 struct psp_gfx_cmd_resp *cmd) 2378 { 2379 int ret; 2380 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2381 2382 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2383 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2384 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2385 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2386 2387 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2388 if (ret) 2389 DRM_ERROR("Unknown firmware type\n"); 2390 2391 return ret; 2392 } 2393 2394 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2395 struct amdgpu_firmware_info *ucode) 2396 { 2397 int ret = 0; 2398 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2399 2400 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2401 if (!ret) { 2402 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2403 psp->fence_buf_mc_addr); 2404 } 2405 2406 release_psp_cmd_buf(psp); 2407 2408 return ret; 2409 } 2410 2411 static int psp_load_smu_fw(struct psp_context *psp) 2412 { 2413 int ret; 2414 struct amdgpu_device *adev = psp->adev; 2415 struct amdgpu_firmware_info *ucode = 2416 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2417 struct amdgpu_ras *ras = psp->ras_context.ras; 2418 2419 /* 2420 * Skip SMU FW reloading in case of using BACO for runpm only, 2421 * as SMU is always alive. 2422 */ 2423 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2424 return 0; 2425 2426 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2427 return 0; 2428 2429 if ((amdgpu_in_reset(adev) && 2430 ras && adev->ras_enabled && 2431 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2432 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2433 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2434 if (ret) { 2435 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2436 } 2437 } 2438 2439 ret = psp_execute_non_psp_fw_load(psp, ucode); 2440 2441 if (ret) 2442 DRM_ERROR("PSP load smu failed!\n"); 2443 2444 return ret; 2445 } 2446 2447 static bool fw_load_skip_check(struct psp_context *psp, 2448 struct amdgpu_firmware_info *ucode) 2449 { 2450 if (!ucode->fw || !ucode->ucode_size) 2451 return true; 2452 2453 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2454 (psp_smu_reload_quirk(psp) || 2455 psp->autoload_supported || 2456 psp->pmfw_centralized_cstate_management)) 2457 return true; 2458 2459 if (amdgpu_sriov_vf(psp->adev) && 2460 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2461 return true; 2462 2463 if (psp->autoload_supported && 2464 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2465 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2466 /* skip mec JT when autoload is enabled */ 2467 return true; 2468 2469 return false; 2470 } 2471 2472 int psp_load_fw_list(struct psp_context *psp, 2473 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2474 { 2475 int ret = 0, i; 2476 struct amdgpu_firmware_info *ucode; 2477 2478 for (i = 0; i < ucode_count; ++i) { 2479 ucode = ucode_list[i]; 2480 psp_print_fw_hdr(psp, ucode); 2481 ret = psp_execute_non_psp_fw_load(psp, ucode); 2482 if (ret) 2483 return ret; 2484 } 2485 return ret; 2486 } 2487 2488 static int psp_load_non_psp_fw(struct psp_context *psp) 2489 { 2490 int i, ret; 2491 struct amdgpu_firmware_info *ucode; 2492 struct amdgpu_device *adev = psp->adev; 2493 2494 if (psp->autoload_supported && 2495 !psp->pmfw_centralized_cstate_management) { 2496 ret = psp_load_smu_fw(psp); 2497 if (ret) 2498 return ret; 2499 } 2500 2501 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2502 ucode = &adev->firmware.ucode[i]; 2503 2504 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2505 !fw_load_skip_check(psp, ucode)) { 2506 ret = psp_load_smu_fw(psp); 2507 if (ret) 2508 return ret; 2509 continue; 2510 } 2511 2512 if (fw_load_skip_check(psp, ucode)) 2513 continue; 2514 2515 if (psp->autoload_supported && 2516 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2517 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2518 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2519 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2520 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2521 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2522 /* PSP only receive one SDMA fw for sienna_cichlid, 2523 * as all four sdma fw are same */ 2524 continue; 2525 2526 psp_print_fw_hdr(psp, ucode); 2527 2528 ret = psp_execute_non_psp_fw_load(psp, ucode); 2529 if (ret) 2530 return ret; 2531 2532 /* Start rlc autoload after psp recieved all the gfx firmware */ 2533 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2534 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2535 ret = psp_rlc_autoload_start(psp); 2536 if (ret) { 2537 DRM_ERROR("Failed to start rlc autoload\n"); 2538 return ret; 2539 } 2540 } 2541 } 2542 2543 return 0; 2544 } 2545 2546 static int psp_load_fw(struct amdgpu_device *adev) 2547 { 2548 int ret; 2549 struct psp_context *psp = &adev->psp; 2550 2551 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2552 /* should not destroy ring, only stop */ 2553 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2554 } else { 2555 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2556 2557 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2558 if (ret) { 2559 DRM_ERROR("PSP ring init failed!\n"); 2560 goto failed; 2561 } 2562 } 2563 2564 ret = psp_hw_start(psp); 2565 if (ret) 2566 goto failed; 2567 2568 ret = psp_load_non_psp_fw(psp); 2569 if (ret) 2570 goto failed1; 2571 2572 ret = psp_asd_initialize(psp); 2573 if (ret) { 2574 DRM_ERROR("PSP load asd failed!\n"); 2575 goto failed1; 2576 } 2577 2578 ret = psp_rl_load(adev); 2579 if (ret) { 2580 DRM_ERROR("PSP load RL failed!\n"); 2581 goto failed1; 2582 } 2583 2584 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2585 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2586 ret = psp_xgmi_initialize(psp, false, true); 2587 /* Warning the XGMI seesion initialize failure 2588 * Instead of stop driver initialization 2589 */ 2590 if (ret) 2591 dev_err(psp->adev->dev, 2592 "XGMI: Failed to initialize XGMI session\n"); 2593 } 2594 } 2595 2596 if (psp->ta_fw) { 2597 ret = psp_ras_initialize(psp); 2598 if (ret) 2599 dev_err(psp->adev->dev, 2600 "RAS: Failed to initialize RAS\n"); 2601 2602 ret = psp_hdcp_initialize(psp); 2603 if (ret) 2604 dev_err(psp->adev->dev, 2605 "HDCP: Failed to initialize HDCP\n"); 2606 2607 ret = psp_dtm_initialize(psp); 2608 if (ret) 2609 dev_err(psp->adev->dev, 2610 "DTM: Failed to initialize DTM\n"); 2611 2612 ret = psp_rap_initialize(psp); 2613 if (ret) 2614 dev_err(psp->adev->dev, 2615 "RAP: Failed to initialize RAP\n"); 2616 2617 ret = psp_securedisplay_initialize(psp); 2618 if (ret) 2619 dev_err(psp->adev->dev, 2620 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2621 } 2622 2623 return 0; 2624 2625 failed1: 2626 psp_free_shared_bufs(psp); 2627 failed: 2628 /* 2629 * all cleanup jobs (xgmi terminate, ras terminate, 2630 * ring destroy, cmd/fence/fw buffers destory, 2631 * psp->cmd destory) are delayed to psp_hw_fini 2632 */ 2633 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2634 return ret; 2635 } 2636 2637 static int psp_hw_init(void *handle) 2638 { 2639 int ret; 2640 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2641 2642 mutex_lock(&adev->firmware.mutex); 2643 /* 2644 * This sequence is just used on hw_init only once, no need on 2645 * resume. 2646 */ 2647 ret = amdgpu_ucode_init_bo(adev); 2648 if (ret) 2649 goto failed; 2650 2651 ret = psp_load_fw(adev); 2652 if (ret) { 2653 DRM_ERROR("PSP firmware loading failed\n"); 2654 goto failed; 2655 } 2656 2657 mutex_unlock(&adev->firmware.mutex); 2658 return 0; 2659 2660 failed: 2661 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2662 mutex_unlock(&adev->firmware.mutex); 2663 return -EINVAL; 2664 } 2665 2666 static int psp_hw_fini(void *handle) 2667 { 2668 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2669 struct psp_context *psp = &adev->psp; 2670 2671 if (psp->ta_fw) { 2672 psp_ras_terminate(psp); 2673 psp_securedisplay_terminate(psp); 2674 psp_rap_terminate(psp); 2675 psp_dtm_terminate(psp); 2676 psp_hdcp_terminate(psp); 2677 2678 if (adev->gmc.xgmi.num_physical_nodes > 1) 2679 psp_xgmi_terminate(psp); 2680 } 2681 2682 psp_asd_terminate(psp); 2683 psp_tmr_terminate(psp); 2684 2685 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2686 2687 psp_free_shared_bufs(psp); 2688 2689 return 0; 2690 } 2691 2692 static int psp_suspend(void *handle) 2693 { 2694 int ret = 0; 2695 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2696 struct psp_context *psp = &adev->psp; 2697 2698 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2699 psp->xgmi_context.context.initialized) { 2700 ret = psp_xgmi_terminate(psp); 2701 if (ret) { 2702 DRM_ERROR("Failed to terminate xgmi ta\n"); 2703 goto out; 2704 } 2705 } 2706 2707 if (psp->ta_fw) { 2708 ret = psp_ras_terminate(psp); 2709 if (ret) { 2710 DRM_ERROR("Failed to terminate ras ta\n"); 2711 goto out; 2712 } 2713 ret = psp_hdcp_terminate(psp); 2714 if (ret) { 2715 DRM_ERROR("Failed to terminate hdcp ta\n"); 2716 goto out; 2717 } 2718 ret = psp_dtm_terminate(psp); 2719 if (ret) { 2720 DRM_ERROR("Failed to terminate dtm ta\n"); 2721 goto out; 2722 } 2723 ret = psp_rap_terminate(psp); 2724 if (ret) { 2725 DRM_ERROR("Failed to terminate rap ta\n"); 2726 goto out; 2727 } 2728 ret = psp_securedisplay_terminate(psp); 2729 if (ret) { 2730 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2731 goto out; 2732 } 2733 } 2734 2735 ret = psp_asd_terminate(psp); 2736 if (ret) { 2737 DRM_ERROR("Failed to terminate asd\n"); 2738 goto out; 2739 } 2740 2741 ret = psp_tmr_terminate(psp); 2742 if (ret) { 2743 DRM_ERROR("Failed to terminate tmr\n"); 2744 goto out; 2745 } 2746 2747 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2748 if (ret) { 2749 DRM_ERROR("PSP ring stop failed\n"); 2750 } 2751 2752 out: 2753 return ret; 2754 } 2755 2756 static int psp_resume(void *handle) 2757 { 2758 int ret; 2759 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2760 struct psp_context *psp = &adev->psp; 2761 2762 DRM_INFO("PSP is resuming...\n"); 2763 2764 if (psp->mem_train_ctx.enable_mem_training) { 2765 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2766 if (ret) { 2767 DRM_ERROR("Failed to process memory training!\n"); 2768 return ret; 2769 } 2770 } 2771 2772 mutex_lock(&adev->firmware.mutex); 2773 2774 ret = psp_hw_start(psp); 2775 if (ret) 2776 goto failed; 2777 2778 ret = psp_load_non_psp_fw(psp); 2779 if (ret) 2780 goto failed; 2781 2782 ret = psp_asd_initialize(psp); 2783 if (ret) { 2784 DRM_ERROR("PSP load asd failed!\n"); 2785 goto failed; 2786 } 2787 2788 ret = psp_rl_load(adev); 2789 if (ret) { 2790 dev_err(adev->dev, "PSP load RL failed!\n"); 2791 goto failed; 2792 } 2793 2794 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2795 ret = psp_xgmi_initialize(psp, false, true); 2796 /* Warning the XGMI seesion initialize failure 2797 * Instead of stop driver initialization 2798 */ 2799 if (ret) 2800 dev_err(psp->adev->dev, 2801 "XGMI: Failed to initialize XGMI session\n"); 2802 } 2803 2804 if (psp->ta_fw) { 2805 ret = psp_ras_initialize(psp); 2806 if (ret) 2807 dev_err(psp->adev->dev, 2808 "RAS: Failed to initialize RAS\n"); 2809 2810 ret = psp_hdcp_initialize(psp); 2811 if (ret) 2812 dev_err(psp->adev->dev, 2813 "HDCP: Failed to initialize HDCP\n"); 2814 2815 ret = psp_dtm_initialize(psp); 2816 if (ret) 2817 dev_err(psp->adev->dev, 2818 "DTM: Failed to initialize DTM\n"); 2819 2820 ret = psp_rap_initialize(psp); 2821 if (ret) 2822 dev_err(psp->adev->dev, 2823 "RAP: Failed to initialize RAP\n"); 2824 2825 ret = psp_securedisplay_initialize(psp); 2826 if (ret) 2827 dev_err(psp->adev->dev, 2828 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2829 } 2830 2831 mutex_unlock(&adev->firmware.mutex); 2832 2833 return 0; 2834 2835 failed: 2836 DRM_ERROR("PSP resume failed\n"); 2837 mutex_unlock(&adev->firmware.mutex); 2838 return ret; 2839 } 2840 2841 int psp_gpu_reset(struct amdgpu_device *adev) 2842 { 2843 int ret; 2844 2845 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2846 return 0; 2847 2848 mutex_lock(&adev->psp.mutex); 2849 ret = psp_mode1_reset(&adev->psp); 2850 mutex_unlock(&adev->psp.mutex); 2851 2852 return ret; 2853 } 2854 2855 int psp_rlc_autoload_start(struct psp_context *psp) 2856 { 2857 int ret; 2858 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2859 2860 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2861 2862 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2863 psp->fence_buf_mc_addr); 2864 2865 release_psp_cmd_buf(psp); 2866 2867 return ret; 2868 } 2869 2870 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2871 uint64_t cmd_gpu_addr, int cmd_size) 2872 { 2873 struct amdgpu_firmware_info ucode = {0}; 2874 2875 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2876 AMDGPU_UCODE_ID_VCN0_RAM; 2877 ucode.mc_addr = cmd_gpu_addr; 2878 ucode.ucode_size = cmd_size; 2879 2880 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2881 } 2882 2883 int psp_ring_cmd_submit(struct psp_context *psp, 2884 uint64_t cmd_buf_mc_addr, 2885 uint64_t fence_mc_addr, 2886 int index) 2887 { 2888 unsigned int psp_write_ptr_reg = 0; 2889 struct psp_gfx_rb_frame *write_frame; 2890 struct psp_ring *ring = &psp->km_ring; 2891 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2892 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2893 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2894 struct amdgpu_device *adev = psp->adev; 2895 uint32_t ring_size_dw = ring->ring_size / 4; 2896 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2897 2898 /* KM (GPCOM) prepare write pointer */ 2899 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2900 2901 /* Update KM RB frame pointer to new frame */ 2902 /* write_frame ptr increments by size of rb_frame in bytes */ 2903 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2904 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2905 write_frame = ring_buffer_start; 2906 else 2907 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2908 /* Check invalid write_frame ptr address */ 2909 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2910 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2911 ring_buffer_start, ring_buffer_end, write_frame); 2912 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2913 return -EINVAL; 2914 } 2915 2916 /* Initialize KM RB frame */ 2917 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2918 2919 /* Update KM RB frame */ 2920 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2921 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2922 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2923 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2924 write_frame->fence_value = index; 2925 amdgpu_device_flush_hdp(adev, NULL); 2926 2927 /* Update the write Pointer in DWORDs */ 2928 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2929 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2930 return 0; 2931 } 2932 2933 int psp_init_asd_microcode(struct psp_context *psp, 2934 const char *chip_name) 2935 { 2936 struct amdgpu_device *adev = psp->adev; 2937 char fw_name[PSP_FW_NAME_LEN]; 2938 const struct psp_firmware_header_v1_0 *asd_hdr; 2939 int err = 0; 2940 2941 if (!chip_name) { 2942 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2943 return -EINVAL; 2944 } 2945 2946 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2947 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2948 if (err) 2949 goto out; 2950 2951 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2952 if (err) 2953 goto out; 2954 2955 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2956 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2957 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2958 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2959 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2960 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2961 return 0; 2962 out: 2963 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2964 release_firmware(adev->psp.asd_fw); 2965 adev->psp.asd_fw = NULL; 2966 return err; 2967 } 2968 2969 int psp_init_toc_microcode(struct psp_context *psp, 2970 const char *chip_name) 2971 { 2972 struct amdgpu_device *adev = psp->adev; 2973 char fw_name[PSP_FW_NAME_LEN]; 2974 const struct psp_firmware_header_v1_0 *toc_hdr; 2975 int err = 0; 2976 2977 if (!chip_name) { 2978 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2979 return -EINVAL; 2980 } 2981 2982 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2983 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2984 if (err) 2985 goto out; 2986 2987 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2988 if (err) 2989 goto out; 2990 2991 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2992 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2993 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2994 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2995 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2996 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2997 return 0; 2998 out: 2999 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 3000 release_firmware(adev->psp.toc_fw); 3001 adev->psp.toc_fw = NULL; 3002 return err; 3003 } 3004 3005 static int parse_sos_bin_descriptor(struct psp_context *psp, 3006 const struct psp_fw_bin_desc *desc, 3007 const struct psp_firmware_header_v2_0 *sos_hdr) 3008 { 3009 uint8_t *ucode_start_addr = NULL; 3010 3011 if (!psp || !desc || !sos_hdr) 3012 return -EINVAL; 3013 3014 ucode_start_addr = (uint8_t *)sos_hdr + 3015 le32_to_cpu(desc->offset_bytes) + 3016 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3017 3018 switch (desc->fw_type) { 3019 case PSP_FW_TYPE_PSP_SOS: 3020 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3021 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3022 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3023 psp->sos.start_addr = ucode_start_addr; 3024 break; 3025 case PSP_FW_TYPE_PSP_SYS_DRV: 3026 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3027 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3028 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3029 psp->sys.start_addr = ucode_start_addr; 3030 break; 3031 case PSP_FW_TYPE_PSP_KDB: 3032 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3033 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3034 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3035 psp->kdb.start_addr = ucode_start_addr; 3036 break; 3037 case PSP_FW_TYPE_PSP_TOC: 3038 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3039 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3040 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3041 psp->toc.start_addr = ucode_start_addr; 3042 break; 3043 case PSP_FW_TYPE_PSP_SPL: 3044 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3045 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3046 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3047 psp->spl.start_addr = ucode_start_addr; 3048 break; 3049 case PSP_FW_TYPE_PSP_RL: 3050 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3051 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3052 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3053 psp->rl.start_addr = ucode_start_addr; 3054 break; 3055 case PSP_FW_TYPE_PSP_SOC_DRV: 3056 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3057 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3058 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3059 psp->soc_drv.start_addr = ucode_start_addr; 3060 break; 3061 case PSP_FW_TYPE_PSP_INTF_DRV: 3062 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3063 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3064 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3065 psp->intf_drv.start_addr = ucode_start_addr; 3066 break; 3067 case PSP_FW_TYPE_PSP_DBG_DRV: 3068 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3069 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3070 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3071 psp->dbg_drv.start_addr = ucode_start_addr; 3072 break; 3073 case PSP_FW_TYPE_PSP_RAS_DRV: 3074 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3075 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3076 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3077 psp->ras_drv.start_addr = ucode_start_addr; 3078 break; 3079 default: 3080 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3081 break; 3082 } 3083 3084 return 0; 3085 } 3086 3087 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3088 { 3089 const struct psp_firmware_header_v1_0 *sos_hdr; 3090 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3091 uint8_t *ucode_array_start_addr; 3092 3093 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3094 ucode_array_start_addr = (uint8_t *)sos_hdr + 3095 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3096 3097 if (adev->gmc.xgmi.connected_to_cpu || 3098 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3099 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3100 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3101 3102 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3103 adev->psp.sys.start_addr = ucode_array_start_addr; 3104 3105 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3106 adev->psp.sos.start_addr = ucode_array_start_addr + 3107 le32_to_cpu(sos_hdr->sos.offset_bytes); 3108 } else { 3109 /* Load alternate PSP SOS FW */ 3110 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3111 3112 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3113 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3114 3115 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3116 adev->psp.sys.start_addr = ucode_array_start_addr + 3117 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3118 3119 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3120 adev->psp.sos.start_addr = ucode_array_start_addr + 3121 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3122 } 3123 3124 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3125 dev_warn(adev->dev, "PSP SOS FW not available"); 3126 return -EINVAL; 3127 } 3128 3129 return 0; 3130 } 3131 3132 int psp_init_sos_microcode(struct psp_context *psp, 3133 const char *chip_name) 3134 { 3135 struct amdgpu_device *adev = psp->adev; 3136 char fw_name[PSP_FW_NAME_LEN]; 3137 const struct psp_firmware_header_v1_0 *sos_hdr; 3138 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3139 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3140 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3141 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3142 int err = 0; 3143 uint8_t *ucode_array_start_addr; 3144 int fw_index = 0; 3145 3146 if (!chip_name) { 3147 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3148 return -EINVAL; 3149 } 3150 3151 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3152 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3153 if (err) 3154 goto out; 3155 3156 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3157 if (err) 3158 goto out; 3159 3160 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3161 ucode_array_start_addr = (uint8_t *)sos_hdr + 3162 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3163 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3164 3165 switch (sos_hdr->header.header_version_major) { 3166 case 1: 3167 err = psp_init_sos_base_fw(adev); 3168 if (err) 3169 goto out; 3170 3171 if (sos_hdr->header.header_version_minor == 1) { 3172 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3173 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3174 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3175 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3176 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3177 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3178 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3179 } 3180 if (sos_hdr->header.header_version_minor == 2) { 3181 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3182 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3183 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3184 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3185 } 3186 if (sos_hdr->header.header_version_minor == 3) { 3187 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3188 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3189 adev->psp.toc.start_addr = ucode_array_start_addr + 3190 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3191 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3192 adev->psp.kdb.start_addr = ucode_array_start_addr + 3193 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3194 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3195 adev->psp.spl.start_addr = ucode_array_start_addr + 3196 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3197 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3198 adev->psp.rl.start_addr = ucode_array_start_addr + 3199 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3200 } 3201 break; 3202 case 2: 3203 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3204 3205 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3206 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3207 err = -EINVAL; 3208 goto out; 3209 } 3210 3211 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3212 err = parse_sos_bin_descriptor(psp, 3213 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3214 sos_hdr_v2_0); 3215 if (err) 3216 goto out; 3217 } 3218 break; 3219 default: 3220 dev_err(adev->dev, 3221 "unsupported psp sos firmware\n"); 3222 err = -EINVAL; 3223 goto out; 3224 } 3225 3226 return 0; 3227 out: 3228 dev_err(adev->dev, 3229 "failed to init sos firmware\n"); 3230 release_firmware(adev->psp.sos_fw); 3231 adev->psp.sos_fw = NULL; 3232 3233 return err; 3234 } 3235 3236 static int parse_ta_bin_descriptor(struct psp_context *psp, 3237 const struct psp_fw_bin_desc *desc, 3238 const struct ta_firmware_header_v2_0 *ta_hdr) 3239 { 3240 uint8_t *ucode_start_addr = NULL; 3241 3242 if (!psp || !desc || !ta_hdr) 3243 return -EINVAL; 3244 3245 ucode_start_addr = (uint8_t *)ta_hdr + 3246 le32_to_cpu(desc->offset_bytes) + 3247 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3248 3249 switch (desc->fw_type) { 3250 case TA_FW_TYPE_PSP_ASD: 3251 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3252 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3253 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3254 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3255 break; 3256 case TA_FW_TYPE_PSP_XGMI: 3257 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3258 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3259 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3260 break; 3261 case TA_FW_TYPE_PSP_RAS: 3262 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3263 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3264 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3265 break; 3266 case TA_FW_TYPE_PSP_HDCP: 3267 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3268 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3269 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3270 break; 3271 case TA_FW_TYPE_PSP_DTM: 3272 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3273 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3274 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3275 break; 3276 case TA_FW_TYPE_PSP_RAP: 3277 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3278 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3279 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3280 break; 3281 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3282 psp->securedisplay_context.context.bin_desc.fw_version = 3283 le32_to_cpu(desc->fw_version); 3284 psp->securedisplay_context.context.bin_desc.size_bytes = 3285 le32_to_cpu(desc->size_bytes); 3286 psp->securedisplay_context.context.bin_desc.start_addr = 3287 ucode_start_addr; 3288 break; 3289 default: 3290 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3291 break; 3292 } 3293 3294 return 0; 3295 } 3296 3297 int psp_init_ta_microcode(struct psp_context *psp, 3298 const char *chip_name) 3299 { 3300 struct amdgpu_device *adev = psp->adev; 3301 char fw_name[PSP_FW_NAME_LEN]; 3302 const struct ta_firmware_header_v2_0 *ta_hdr; 3303 int err = 0; 3304 int ta_index = 0; 3305 3306 if (!chip_name) { 3307 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3308 return -EINVAL; 3309 } 3310 3311 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3312 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3313 if (err) 3314 goto out; 3315 3316 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3317 if (err) 3318 goto out; 3319 3320 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3321 3322 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3323 dev_err(adev->dev, "unsupported TA header version\n"); 3324 err = -EINVAL; 3325 goto out; 3326 } 3327 3328 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3329 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3330 err = -EINVAL; 3331 goto out; 3332 } 3333 3334 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3335 err = parse_ta_bin_descriptor(psp, 3336 &ta_hdr->ta_fw_bin[ta_index], 3337 ta_hdr); 3338 if (err) 3339 goto out; 3340 } 3341 3342 return 0; 3343 out: 3344 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3345 release_firmware(adev->psp.ta_fw); 3346 adev->psp.ta_fw = NULL; 3347 return err; 3348 } 3349 3350 int psp_init_cap_microcode(struct psp_context *psp, 3351 const char *chip_name) 3352 { 3353 struct amdgpu_device *adev = psp->adev; 3354 char fw_name[PSP_FW_NAME_LEN]; 3355 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3356 struct amdgpu_firmware_info *info = NULL; 3357 int err = 0; 3358 3359 if (!chip_name) { 3360 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3361 return -EINVAL; 3362 } 3363 3364 if (!amdgpu_sriov_vf(adev)) { 3365 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3366 return -EINVAL; 3367 } 3368 3369 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3370 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3371 if (err) { 3372 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3373 err = 0; 3374 goto out; 3375 } 3376 3377 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3378 if (err) { 3379 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3380 goto out; 3381 } 3382 3383 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3384 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3385 info->fw = adev->psp.cap_fw; 3386 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3387 adev->psp.cap_fw->data; 3388 adev->firmware.fw_size += roundup2( 3389 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3390 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3391 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3392 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3393 3394 return 0; 3395 3396 out: 3397 release_firmware(adev->psp.cap_fw); 3398 adev->psp.cap_fw = NULL; 3399 return err; 3400 } 3401 3402 static int psp_set_clockgating_state(void *handle, 3403 enum amd_clockgating_state state) 3404 { 3405 return 0; 3406 } 3407 3408 static int psp_set_powergating_state(void *handle, 3409 enum amd_powergating_state state) 3410 { 3411 return 0; 3412 } 3413 3414 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3415 struct device_attribute *attr, 3416 char *buf) 3417 { 3418 struct drm_device *ddev = dev_get_drvdata(dev); 3419 struct amdgpu_device *adev = drm_to_adev(ddev); 3420 uint32_t fw_ver; 3421 int ret; 3422 3423 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3424 DRM_INFO("PSP block is not ready yet."); 3425 return -EBUSY; 3426 } 3427 3428 mutex_lock(&adev->psp.mutex); 3429 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3430 mutex_unlock(&adev->psp.mutex); 3431 3432 if (ret) { 3433 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3434 return ret; 3435 } 3436 3437 return sysfs_emit(buf, "%x\n", fw_ver); 3438 } 3439 3440 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3441 struct device_attribute *attr, 3442 const char *buf, 3443 size_t count) 3444 { 3445 struct drm_device *ddev = dev_get_drvdata(dev); 3446 struct amdgpu_device *adev = drm_to_adev(ddev); 3447 int ret, idx; 3448 char fw_name[100]; 3449 const struct firmware *usbc_pd_fw; 3450 struct amdgpu_bo *fw_buf_bo = NULL; 3451 uint64_t fw_pri_mc_addr; 3452 void *fw_pri_cpu_addr; 3453 3454 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3455 DRM_INFO("PSP block is not ready yet."); 3456 return -EBUSY; 3457 } 3458 3459 if (!drm_dev_enter(ddev, &idx)) 3460 return -ENODEV; 3461 3462 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3463 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3464 if (ret) 3465 goto fail; 3466 3467 /* LFB address which is aligned to 1MB boundary per PSP request */ 3468 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3469 AMDGPU_GEM_DOMAIN_VRAM, 3470 &fw_buf_bo, 3471 &fw_pri_mc_addr, 3472 &fw_pri_cpu_addr); 3473 if (ret) 3474 goto rel_buf; 3475 3476 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3477 3478 mutex_lock(&adev->psp.mutex); 3479 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3480 mutex_unlock(&adev->psp.mutex); 3481 3482 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3483 3484 rel_buf: 3485 release_firmware(usbc_pd_fw); 3486 fail: 3487 if (ret) { 3488 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3489 count = ret; 3490 } 3491 3492 drm_dev_exit(idx); 3493 return count; 3494 } 3495 3496 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3497 { 3498 int idx; 3499 3500 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3501 return; 3502 3503 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3504 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3505 3506 drm_dev_exit(idx); 3507 } 3508 3509 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3510 psp_usbc_pd_fw_sysfs_read, 3511 psp_usbc_pd_fw_sysfs_write); 3512 3513 int is_psp_fw_valid(struct psp_bin_desc bin) 3514 { 3515 return bin.size_bytes; 3516 } 3517 3518 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3519 struct bin_attribute *bin_attr, 3520 char *buffer, loff_t pos, size_t count) 3521 { 3522 STUB(); 3523 return -ENOSYS; 3524 #ifdef notyet 3525 struct device *dev = kobj_to_dev(kobj); 3526 struct drm_device *ddev = dev_get_drvdata(dev); 3527 struct amdgpu_device *adev = drm_to_adev(ddev); 3528 3529 adev->psp.vbflash_done = false; 3530 3531 /* Safeguard against memory drain */ 3532 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3533 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3534 kvfree(adev->psp.vbflash_tmp_buf); 3535 adev->psp.vbflash_tmp_buf = NULL; 3536 adev->psp.vbflash_image_size = 0; 3537 return -ENOMEM; 3538 } 3539 3540 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3541 if (!adev->psp.vbflash_tmp_buf) { 3542 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3543 if (!adev->psp.vbflash_tmp_buf) 3544 return -ENOMEM; 3545 } 3546 3547 mutex_lock(&adev->psp.mutex); 3548 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3549 adev->psp.vbflash_image_size += count; 3550 mutex_unlock(&adev->psp.mutex); 3551 3552 dev_info(adev->dev, "VBIOS flash write PSP done"); 3553 3554 return count; 3555 #endif 3556 } 3557 3558 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3559 struct bin_attribute *bin_attr, char *buffer, 3560 loff_t pos, size_t count) 3561 { 3562 STUB(); 3563 return -ENOSYS; 3564 #ifdef notyet 3565 struct device *dev = kobj_to_dev(kobj); 3566 struct drm_device *ddev = dev_get_drvdata(dev); 3567 struct amdgpu_device *adev = drm_to_adev(ddev); 3568 struct amdgpu_bo *fw_buf_bo = NULL; 3569 uint64_t fw_pri_mc_addr; 3570 void *fw_pri_cpu_addr; 3571 int ret; 3572 3573 dev_info(adev->dev, "VBIOS flash to PSP started"); 3574 3575 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3576 AMDGPU_GPU_PAGE_SIZE, 3577 AMDGPU_GEM_DOMAIN_VRAM, 3578 &fw_buf_bo, 3579 &fw_pri_mc_addr, 3580 &fw_pri_cpu_addr); 3581 if (ret) 3582 goto rel_buf; 3583 3584 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3585 3586 mutex_lock(&adev->psp.mutex); 3587 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3588 mutex_unlock(&adev->psp.mutex); 3589 3590 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3591 3592 rel_buf: 3593 kvfree(adev->psp.vbflash_tmp_buf); 3594 adev->psp.vbflash_tmp_buf = NULL; 3595 adev->psp.vbflash_image_size = 0; 3596 3597 if (ret) { 3598 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3599 return ret; 3600 } 3601 3602 dev_info(adev->dev, "VBIOS flash to PSP done"); 3603 return 0; 3604 #endif 3605 } 3606 3607 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3608 struct device_attribute *attr, 3609 char *buf) 3610 { 3611 struct drm_device *ddev = dev_get_drvdata(dev); 3612 struct amdgpu_device *adev = drm_to_adev(ddev); 3613 uint32_t vbflash_status; 3614 3615 vbflash_status = psp_vbflash_status(&adev->psp); 3616 if (!adev->psp.vbflash_done) 3617 vbflash_status = 0; 3618 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3619 vbflash_status = 1; 3620 3621 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3622 } 3623 3624 #ifdef notyet 3625 static const struct bin_attribute psp_vbflash_bin_attr = { 3626 .attr = {.name = "psp_vbflash", .mode = 0664}, 3627 .size = 0, 3628 .write = amdgpu_psp_vbflash_write, 3629 .read = amdgpu_psp_vbflash_read, 3630 }; 3631 #endif 3632 3633 static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL); 3634 3635 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3636 { 3637 int ret = 0; 3638 struct psp_context *psp = &adev->psp; 3639 3640 if (amdgpu_sriov_vf(adev)) 3641 return -EINVAL; 3642 3643 switch (adev->ip_versions[MP0_HWIP][0]) { 3644 case IP_VERSION(13, 0, 0): 3645 case IP_VERSION(13, 0, 7): 3646 if (!psp->adev) { 3647 psp->adev = adev; 3648 psp_v13_0_set_psp_funcs(psp); 3649 } 3650 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3651 if (ret) 3652 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3653 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3654 if (ret) 3655 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3656 return ret; 3657 default: 3658 return 0; 3659 } 3660 } 3661 3662 const struct amd_ip_funcs psp_ip_funcs = { 3663 .name = "psp", 3664 .early_init = psp_early_init, 3665 .late_init = NULL, 3666 .sw_init = psp_sw_init, 3667 .sw_fini = psp_sw_fini, 3668 .hw_init = psp_hw_init, 3669 .hw_fini = psp_hw_fini, 3670 .suspend = psp_suspend, 3671 .resume = psp_resume, 3672 .is_idle = NULL, 3673 .check_soft_reset = NULL, 3674 .wait_for_idle = NULL, 3675 .soft_reset = NULL, 3676 .set_clockgating_state = psp_set_clockgating_state, 3677 .set_powergating_state = psp_set_powergating_state, 3678 }; 3679 3680 static int psp_sysfs_init(struct amdgpu_device *adev) 3681 { 3682 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3683 3684 if (ret) 3685 DRM_ERROR("Failed to create USBC PD FW control file!"); 3686 3687 return ret; 3688 } 3689 3690 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3691 { 3692 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3693 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3694 } 3695 3696 static void psp_sysfs_fini(struct amdgpu_device *adev) 3697 { 3698 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3699 } 3700 3701 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3702 { 3703 .type = AMD_IP_BLOCK_TYPE_PSP, 3704 .major = 3, 3705 .minor = 1, 3706 .rev = 0, 3707 .funcs = &psp_ip_funcs, 3708 }; 3709 3710 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3711 { 3712 .type = AMD_IP_BLOCK_TYPE_PSP, 3713 .major = 10, 3714 .minor = 0, 3715 .rev = 0, 3716 .funcs = &psp_ip_funcs, 3717 }; 3718 3719 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3720 { 3721 .type = AMD_IP_BLOCK_TYPE_PSP, 3722 .major = 11, 3723 .minor = 0, 3724 .rev = 0, 3725 .funcs = &psp_ip_funcs, 3726 }; 3727 3728 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3729 .type = AMD_IP_BLOCK_TYPE_PSP, 3730 .major = 11, 3731 .minor = 0, 3732 .rev = 8, 3733 .funcs = &psp_ip_funcs, 3734 }; 3735 3736 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3737 { 3738 .type = AMD_IP_BLOCK_TYPE_PSP, 3739 .major = 12, 3740 .minor = 0, 3741 .rev = 0, 3742 .funcs = &psp_ip_funcs, 3743 }; 3744 3745 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3746 .type = AMD_IP_BLOCK_TYPE_PSP, 3747 .major = 13, 3748 .minor = 0, 3749 .rev = 0, 3750 .funcs = &psp_ip_funcs, 3751 }; 3752 3753 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3754 .type = AMD_IP_BLOCK_TYPE_PSP, 3755 .major = 13, 3756 .minor = 0, 3757 .rev = 4, 3758 .funcs = &psp_ip_funcs, 3759 }; 3760