1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 41 #include "amdgpu_ras.h" 42 #include "amdgpu_securedisplay.h" 43 #include "amdgpu_atomfirmware.h" 44 45 static int psp_sysfs_init(struct amdgpu_device *adev); 46 static void psp_sysfs_fini(struct amdgpu_device *adev); 47 48 static int psp_load_smu_fw(struct psp_context *psp); 49 50 /* 51 * Due to DF Cstate management centralized to PMFW, the firmware 52 * loading sequence will be updated as below: 53 * - Load KDB 54 * - Load SYS_DRV 55 * - Load tOS 56 * - Load PMFW 57 * - Setup TMR 58 * - Load other non-psp fw 59 * - Load ASD 60 * - Load XGMI/RAS/HDCP/DTM TA if any 61 * 62 * This new sequence is required for 63 * - Arcturus and onwards 64 * - Navi12 and onwards 65 */ 66 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 67 { 68 struct amdgpu_device *adev = psp->adev; 69 70 psp->pmfw_centralized_cstate_management = false; 71 72 if (amdgpu_sriov_vf(adev)) 73 return; 74 75 if (adev->flags & AMD_IS_APU) 76 return; 77 78 if ((adev->asic_type >= CHIP_ARCTURUS) || 79 (adev->asic_type >= CHIP_NAVI12)) 80 psp->pmfw_centralized_cstate_management = true; 81 } 82 83 static int psp_early_init(void *handle) 84 { 85 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 86 struct psp_context *psp = &adev->psp; 87 88 switch (adev->asic_type) { 89 case CHIP_VEGA10: 90 case CHIP_VEGA12: 91 psp_v3_1_set_psp_funcs(psp); 92 psp->autoload_supported = false; 93 break; 94 case CHIP_RAVEN: 95 psp_v10_0_set_psp_funcs(psp); 96 psp->autoload_supported = false; 97 break; 98 case CHIP_VEGA20: 99 case CHIP_ARCTURUS: 100 psp_v11_0_set_psp_funcs(psp); 101 psp->autoload_supported = false; 102 break; 103 case CHIP_NAVI10: 104 case CHIP_NAVI14: 105 case CHIP_NAVI12: 106 case CHIP_SIENNA_CICHLID: 107 case CHIP_NAVY_FLOUNDER: 108 case CHIP_VANGOGH: 109 case CHIP_DIMGREY_CAVEFISH: 110 case CHIP_BEIGE_GOBY: 111 psp_v11_0_set_psp_funcs(psp); 112 psp->autoload_supported = true; 113 break; 114 case CHIP_RENOIR: 115 psp_v12_0_set_psp_funcs(psp); 116 break; 117 case CHIP_ALDEBARAN: 118 psp_v13_0_set_psp_funcs(psp); 119 break; 120 case CHIP_YELLOW_CARP: 121 psp_v13_0_set_psp_funcs(psp); 122 psp->autoload_supported = true; 123 break; 124 case CHIP_CYAN_SKILLFISH: 125 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 126 psp_v11_0_8_set_psp_funcs(psp); 127 psp->autoload_supported = false; 128 } 129 break; 130 default: 131 return -EINVAL; 132 } 133 134 psp->adev = adev; 135 136 psp_check_pmfw_centralized_cstate_management(psp); 137 138 return 0; 139 } 140 141 static void psp_memory_training_fini(struct psp_context *psp) 142 { 143 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 144 145 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 146 kfree(ctx->sys_cache); 147 ctx->sys_cache = NULL; 148 } 149 150 static int psp_memory_training_init(struct psp_context *psp) 151 { 152 int ret; 153 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 154 155 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 156 DRM_DEBUG("memory training is not supported!\n"); 157 return 0; 158 } 159 160 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 161 if (ctx->sys_cache == NULL) { 162 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 163 ret = -ENOMEM; 164 goto Err_out; 165 } 166 167 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 168 ctx->train_data_size, 169 ctx->p2c_train_data_offset, 170 ctx->c2p_train_data_offset); 171 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 172 return 0; 173 174 Err_out: 175 psp_memory_training_fini(psp); 176 return ret; 177 } 178 179 /* 180 * Helper funciton to query psp runtime database entry 181 * 182 * @adev: amdgpu_device pointer 183 * @entry_type: the type of psp runtime database entry 184 * @db_entry: runtime database entry pointer 185 * 186 * Return false if runtime database doesn't exit or entry is invalid 187 * or true if the specific database entry is found, and copy to @db_entry 188 */ 189 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 190 enum psp_runtime_entry_type entry_type, 191 void *db_entry) 192 { 193 uint64_t db_header_pos, db_dir_pos; 194 struct psp_runtime_data_header db_header = {0}; 195 struct psp_runtime_data_directory db_dir = {0}; 196 bool ret = false; 197 int i; 198 199 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 200 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 201 202 /* read runtime db header from vram */ 203 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 204 sizeof(struct psp_runtime_data_header), false); 205 206 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 207 /* runtime db doesn't exist, exit */ 208 dev_info(adev->dev, "PSP runtime database doesn't exist\n"); 209 return false; 210 } 211 212 /* read runtime database entry from vram */ 213 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 214 sizeof(struct psp_runtime_data_directory), false); 215 216 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 217 /* invalid db entry count, exit */ 218 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 219 return false; 220 } 221 222 /* look up for requested entry type */ 223 for (i = 0; i < db_dir.entry_count && !ret; i++) { 224 if (db_dir.entry_list[i].entry_type == entry_type) { 225 switch (entry_type) { 226 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 227 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 228 /* invalid db entry size */ 229 dev_warn(adev->dev, "Invalid PSP runtime database entry size\n"); 230 return false; 231 } 232 /* read runtime database entry */ 233 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 234 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 235 ret = true; 236 break; 237 default: 238 ret = false; 239 break; 240 } 241 } 242 } 243 244 return ret; 245 } 246 247 static int psp_sw_init(void *handle) 248 { 249 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 250 struct psp_context *psp = &adev->psp; 251 int ret; 252 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 253 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 254 255 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 256 if (!psp->cmd) { 257 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 258 ret = -ENOMEM; 259 } 260 261 if (!amdgpu_sriov_vf(adev)) { 262 ret = psp_init_microcode(psp); 263 if (ret) { 264 DRM_ERROR("Failed to load psp firmware!\n"); 265 return ret; 266 } 267 } else if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_ALDEBARAN) { 268 ret = psp_init_ta_microcode(psp, "aldebaran"); 269 if (ret) { 270 DRM_ERROR("Failed to initialize ta microcode!\n"); 271 return ret; 272 } 273 } 274 275 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 276 if (psp_get_runtime_db_entry(adev, 277 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 278 &boot_cfg_entry)) { 279 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 280 if ((psp->boot_cfg_bitmask) & 281 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 282 /* If psp runtime database exists, then 283 * only enable two stage memory training 284 * when TWO_STAGE_DRAM_TRAINING bit is set 285 * in runtime database */ 286 mem_training_ctx->enable_mem_training = true; 287 } 288 289 } else { 290 /* If psp runtime database doesn't exist or 291 * is invalid, force enable two stage memory 292 * training */ 293 mem_training_ctx->enable_mem_training = true; 294 } 295 296 if (mem_training_ctx->enable_mem_training) { 297 ret = psp_memory_training_init(psp); 298 if (ret) { 299 DRM_ERROR("Failed to initialize memory training!\n"); 300 return ret; 301 } 302 303 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 304 if (ret) { 305 DRM_ERROR("Failed to process memory training!\n"); 306 return ret; 307 } 308 } 309 310 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) { 311 ret= psp_sysfs_init(adev); 312 if (ret) { 313 return ret; 314 } 315 } 316 317 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 318 amdgpu_sriov_vf(adev) ? 319 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 320 &psp->fw_pri_bo, 321 &psp->fw_pri_mc_addr, 322 &psp->fw_pri_buf); 323 if (ret) 324 return ret; 325 326 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 327 AMDGPU_GEM_DOMAIN_VRAM, 328 &psp->fence_buf_bo, 329 &psp->fence_buf_mc_addr, 330 &psp->fence_buf); 331 if (ret) 332 goto failed1; 333 334 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 335 AMDGPU_GEM_DOMAIN_VRAM, 336 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 337 (void **)&psp->cmd_buf_mem); 338 if (ret) 339 goto failed2; 340 341 return 0; 342 343 failed2: 344 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 345 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 346 failed1: 347 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 348 &psp->fence_buf_mc_addr, &psp->fence_buf); 349 return ret; 350 } 351 352 static int psp_sw_fini(void *handle) 353 { 354 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 355 struct psp_context *psp = &adev->psp; 356 struct psp_gfx_cmd_resp *cmd = psp->cmd; 357 358 psp_memory_training_fini(psp); 359 if (psp->sos_fw) { 360 release_firmware(psp->sos_fw); 361 psp->sos_fw = NULL; 362 } 363 if (psp->asd_fw) { 364 release_firmware(psp->asd_fw); 365 psp->asd_fw = NULL; 366 } 367 if (psp->ta_fw) { 368 release_firmware(psp->ta_fw); 369 psp->ta_fw = NULL; 370 } 371 372 if (adev->asic_type == CHIP_NAVI10 || 373 adev->asic_type == CHIP_SIENNA_CICHLID) 374 psp_sysfs_fini(adev); 375 376 kfree(cmd); 377 cmd = NULL; 378 379 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 380 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 381 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 382 &psp->fence_buf_mc_addr, &psp->fence_buf); 383 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 384 (void **)&psp->cmd_buf_mem); 385 386 return 0; 387 } 388 389 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 390 uint32_t reg_val, uint32_t mask, bool check_changed) 391 { 392 uint32_t val; 393 int i; 394 struct amdgpu_device *adev = psp->adev; 395 396 if (psp->adev->no_hw_access) 397 return 0; 398 399 for (i = 0; i < adev->usec_timeout; i++) { 400 val = RREG32(reg_index); 401 if (check_changed) { 402 if (val != reg_val) 403 return 0; 404 } else { 405 if ((val & mask) == reg_val) 406 return 0; 407 } 408 udelay(1); 409 } 410 411 return -ETIME; 412 } 413 414 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 415 { 416 switch (cmd_id) { 417 case GFX_CMD_ID_LOAD_TA: 418 return "LOAD_TA"; 419 case GFX_CMD_ID_UNLOAD_TA: 420 return "UNLOAD_TA"; 421 case GFX_CMD_ID_INVOKE_CMD: 422 return "INVOKE_CMD"; 423 case GFX_CMD_ID_LOAD_ASD: 424 return "LOAD_ASD"; 425 case GFX_CMD_ID_SETUP_TMR: 426 return "SETUP_TMR"; 427 case GFX_CMD_ID_LOAD_IP_FW: 428 return "LOAD_IP_FW"; 429 case GFX_CMD_ID_DESTROY_TMR: 430 return "DESTROY_TMR"; 431 case GFX_CMD_ID_SAVE_RESTORE: 432 return "SAVE_RESTORE_IP_FW"; 433 case GFX_CMD_ID_SETUP_VMR: 434 return "SETUP_VMR"; 435 case GFX_CMD_ID_DESTROY_VMR: 436 return "DESTROY_VMR"; 437 case GFX_CMD_ID_PROG_REG: 438 return "PROG_REG"; 439 case GFX_CMD_ID_GET_FW_ATTESTATION: 440 return "GET_FW_ATTESTATION"; 441 case GFX_CMD_ID_LOAD_TOC: 442 return "ID_LOAD_TOC"; 443 case GFX_CMD_ID_AUTOLOAD_RLC: 444 return "AUTOLOAD_RLC"; 445 case GFX_CMD_ID_BOOT_CFG: 446 return "BOOT_CFG"; 447 default: 448 return "UNKNOWN CMD"; 449 } 450 } 451 452 static int 453 psp_cmd_submit_buf(struct psp_context *psp, 454 struct amdgpu_firmware_info *ucode, 455 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 456 { 457 int ret; 458 int index, idx; 459 int timeout = 20000; 460 bool ras_intr = false; 461 bool skip_unsupport = false; 462 463 if (psp->adev->no_hw_access) 464 return 0; 465 466 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 467 return 0; 468 469 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 470 471 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 472 473 index = atomic_inc_return(&psp->fence_value); 474 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 475 if (ret) { 476 atomic_dec(&psp->fence_value); 477 goto exit; 478 } 479 480 amdgpu_device_invalidate_hdp(psp->adev, NULL); 481 while (*((unsigned int *)psp->fence_buf) != index) { 482 if (--timeout == 0) 483 break; 484 /* 485 * Shouldn't wait for timeout when err_event_athub occurs, 486 * because gpu reset thread triggered and lock resource should 487 * be released for psp resume sequence. 488 */ 489 ras_intr = amdgpu_ras_intr_triggered(); 490 if (ras_intr) 491 break; 492 usleep_range(10, 100); 493 amdgpu_device_invalidate_hdp(psp->adev, NULL); 494 } 495 496 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 497 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 498 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 499 500 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 501 502 /* In some cases, psp response status is not 0 even there is no 503 * problem while the command is submitted. Some version of PSP FW 504 * doesn't write 0 to that field. 505 * So here we would like to only print a warning instead of an error 506 * during psp initialization to avoid breaking hw_init and it doesn't 507 * return -EINVAL. 508 */ 509 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 510 if (ucode) 511 DRM_WARN("failed to load ucode %s(0x%X) ", 512 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 513 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 514 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 515 psp->cmd_buf_mem->resp.status); 516 if (!timeout) { 517 ret = -EINVAL; 518 goto exit; 519 } 520 } 521 522 if (ucode) { 523 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 524 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 525 } 526 527 exit: 528 drm_dev_exit(idx); 529 return ret; 530 } 531 532 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 533 { 534 struct psp_gfx_cmd_resp *cmd = psp->cmd; 535 536 mutex_lock(&psp->mutex); 537 538 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 539 540 return cmd; 541 } 542 543 void release_psp_cmd_buf(struct psp_context *psp) 544 { 545 mutex_unlock(&psp->mutex); 546 } 547 548 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 549 struct psp_gfx_cmd_resp *cmd, 550 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 551 { 552 struct amdgpu_device *adev = psp->adev; 553 uint32_t size = amdgpu_bo_size(tmr_bo); 554 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 555 556 if (amdgpu_sriov_vf(psp->adev)) 557 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 558 else 559 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 560 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 561 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 562 cmd->cmd.cmd_setup_tmr.buf_size = size; 563 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 564 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 565 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 566 } 567 568 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 569 uint64_t pri_buf_mc, uint32_t size) 570 { 571 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 572 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 573 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 574 cmd->cmd.cmd_load_toc.toc_size = size; 575 } 576 577 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 578 static int psp_load_toc(struct psp_context *psp, 579 uint32_t *tmr_size) 580 { 581 int ret; 582 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 583 584 /* Copy toc to psp firmware private buffer */ 585 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 586 587 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 588 589 ret = psp_cmd_submit_buf(psp, NULL, cmd, 590 psp->fence_buf_mc_addr); 591 if (!ret) 592 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 593 594 release_psp_cmd_buf(psp); 595 596 return ret; 597 } 598 599 /* Set up Trusted Memory Region */ 600 static int psp_tmr_init(struct psp_context *psp) 601 { 602 int ret; 603 int tmr_size; 604 void *tmr_buf; 605 void **pptr; 606 607 /* 608 * According to HW engineer, they prefer the TMR address be "naturally 609 * aligned" , e.g. the start address be an integer divide of TMR size. 610 * 611 * Note: this memory need be reserved till the driver 612 * uninitializes. 613 */ 614 tmr_size = PSP_TMR_SIZE(psp->adev); 615 616 /* For ASICs support RLC autoload, psp will parse the toc 617 * and calculate the total size of TMR needed */ 618 if (!amdgpu_sriov_vf(psp->adev) && 619 psp->toc.start_addr && 620 psp->toc.size_bytes && 621 psp->fw_pri_buf) { 622 ret = psp_load_toc(psp, &tmr_size); 623 if (ret) { 624 DRM_ERROR("Failed to load toc\n"); 625 return ret; 626 } 627 } 628 629 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 630 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), 631 AMDGPU_GEM_DOMAIN_VRAM, 632 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 633 634 return ret; 635 } 636 637 static bool psp_skip_tmr(struct psp_context *psp) 638 { 639 switch (psp->adev->asic_type) { 640 case CHIP_NAVI12: 641 case CHIP_SIENNA_CICHLID: 642 case CHIP_ALDEBARAN: 643 return true; 644 default: 645 return false; 646 } 647 } 648 649 static int psp_tmr_load(struct psp_context *psp) 650 { 651 int ret; 652 struct psp_gfx_cmd_resp *cmd; 653 654 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 655 * Already set up by host driver. 656 */ 657 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 658 return 0; 659 660 cmd = acquire_psp_cmd_buf(psp); 661 662 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 663 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 664 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 665 666 ret = psp_cmd_submit_buf(psp, NULL, cmd, 667 psp->fence_buf_mc_addr); 668 669 release_psp_cmd_buf(psp); 670 671 return ret; 672 } 673 674 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 675 struct psp_gfx_cmd_resp *cmd) 676 { 677 if (amdgpu_sriov_vf(psp->adev)) 678 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 679 else 680 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 681 } 682 683 static int psp_tmr_unload(struct psp_context *psp) 684 { 685 int ret; 686 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 687 688 psp_prep_tmr_unload_cmd_buf(psp, cmd); 689 DRM_INFO("free PSP TMR buffer\n"); 690 691 ret = psp_cmd_submit_buf(psp, NULL, cmd, 692 psp->fence_buf_mc_addr); 693 694 release_psp_cmd_buf(psp); 695 696 return ret; 697 } 698 699 static int psp_tmr_terminate(struct psp_context *psp) 700 { 701 int ret; 702 void *tmr_buf; 703 void **pptr; 704 705 ret = psp_tmr_unload(psp); 706 if (ret) 707 return ret; 708 709 /* free TMR memory buffer */ 710 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 711 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 712 713 return 0; 714 } 715 716 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 717 uint64_t *output_ptr) 718 { 719 int ret; 720 struct psp_gfx_cmd_resp *cmd; 721 722 if (!output_ptr) 723 return -EINVAL; 724 725 if (amdgpu_sriov_vf(psp->adev)) 726 return 0; 727 728 cmd = acquire_psp_cmd_buf(psp); 729 730 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 731 732 ret = psp_cmd_submit_buf(psp, NULL, cmd, 733 psp->fence_buf_mc_addr); 734 735 if (!ret) { 736 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 737 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 738 } 739 740 release_psp_cmd_buf(psp); 741 742 return ret; 743 } 744 745 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 746 { 747 struct psp_context *psp = &adev->psp; 748 struct psp_gfx_cmd_resp *cmd; 749 int ret; 750 751 if (amdgpu_sriov_vf(adev)) 752 return 0; 753 754 cmd = acquire_psp_cmd_buf(psp); 755 756 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 757 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 758 759 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 760 if (!ret) { 761 *boot_cfg = 762 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 763 } 764 765 release_psp_cmd_buf(psp); 766 767 return ret; 768 } 769 770 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 771 { 772 int ret; 773 struct psp_context *psp = &adev->psp; 774 struct psp_gfx_cmd_resp *cmd; 775 776 if (amdgpu_sriov_vf(adev)) 777 return 0; 778 779 cmd = acquire_psp_cmd_buf(psp); 780 781 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 782 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 783 cmd->cmd.boot_cfg.boot_config = boot_cfg; 784 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 785 786 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 787 788 release_psp_cmd_buf(psp); 789 790 return ret; 791 } 792 793 static int psp_rl_load(struct amdgpu_device *adev) 794 { 795 int ret; 796 struct psp_context *psp = &adev->psp; 797 struct psp_gfx_cmd_resp *cmd; 798 799 if (!is_psp_fw_valid(psp->rl)) 800 return 0; 801 802 cmd = acquire_psp_cmd_buf(psp); 803 804 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 805 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 806 807 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 808 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 809 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 810 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 811 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 812 813 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 814 815 release_psp_cmd_buf(psp); 816 817 return ret; 818 } 819 820 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 821 uint64_t asd_mc, uint32_t size) 822 { 823 cmd->cmd_id = GFX_CMD_ID_LOAD_ASD; 824 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc); 825 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc); 826 cmd->cmd.cmd_load_ta.app_len = size; 827 828 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0; 829 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0; 830 cmd->cmd.cmd_load_ta.cmd_buf_len = 0; 831 } 832 833 static int psp_asd_load(struct psp_context *psp) 834 { 835 int ret; 836 struct psp_gfx_cmd_resp *cmd; 837 838 /* If PSP version doesn't match ASD version, asd loading will be failed. 839 * add workaround to bypass it for sriov now. 840 * TODO: add version check to make it common 841 */ 842 if (amdgpu_sriov_vf(psp->adev) || !psp->asd.size_bytes) 843 return 0; 844 845 cmd = acquire_psp_cmd_buf(psp); 846 847 psp_copy_fw(psp, psp->asd.start_addr, psp->asd.size_bytes); 848 849 psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr, 850 psp->asd.size_bytes); 851 852 ret = psp_cmd_submit_buf(psp, NULL, cmd, 853 psp->fence_buf_mc_addr); 854 if (!ret) { 855 psp->asd_context.asd_initialized = true; 856 psp->asd_context.session_id = cmd->resp.session_id; 857 } 858 859 release_psp_cmd_buf(psp); 860 861 return ret; 862 } 863 864 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 865 uint32_t session_id) 866 { 867 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 868 cmd->cmd.cmd_unload_ta.session_id = session_id; 869 } 870 871 static int psp_asd_unload(struct psp_context *psp) 872 { 873 int ret; 874 struct psp_gfx_cmd_resp *cmd; 875 876 if (amdgpu_sriov_vf(psp->adev)) 877 return 0; 878 879 if (!psp->asd_context.asd_initialized) 880 return 0; 881 882 cmd = acquire_psp_cmd_buf(psp); 883 884 psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id); 885 886 ret = psp_cmd_submit_buf(psp, NULL, cmd, 887 psp->fence_buf_mc_addr); 888 if (!ret) 889 psp->asd_context.asd_initialized = false; 890 891 release_psp_cmd_buf(psp); 892 893 return ret; 894 } 895 896 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 897 uint32_t id, uint32_t value) 898 { 899 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 900 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 901 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 902 } 903 904 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 905 uint32_t value) 906 { 907 struct psp_gfx_cmd_resp *cmd; 908 int ret = 0; 909 910 if (reg >= PSP_REG_LAST) 911 return -EINVAL; 912 913 cmd = acquire_psp_cmd_buf(psp); 914 915 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 916 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 917 if (ret) 918 DRM_ERROR("PSP failed to program reg id %d", reg); 919 920 release_psp_cmd_buf(psp); 921 922 return ret; 923 } 924 925 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 926 uint64_t ta_bin_mc, 927 uint32_t ta_bin_size, 928 uint64_t ta_shared_mc, 929 uint32_t ta_shared_size) 930 { 931 cmd->cmd_id = GFX_CMD_ID_LOAD_TA; 932 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 933 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 934 cmd->cmd.cmd_load_ta.app_len = ta_bin_size; 935 936 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc); 937 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc); 938 cmd->cmd.cmd_load_ta.cmd_buf_len = ta_shared_size; 939 } 940 941 static int psp_ta_init_shared_buf(struct psp_context *psp, 942 struct ta_mem_context *mem_ctx, 943 uint32_t shared_mem_size) 944 { 945 int ret; 946 947 /* 948 * Allocate 16k memory aligned to 4k from Frame Buffer (local 949 * physical) for ta to host memory 950 */ 951 ret = amdgpu_bo_create_kernel(psp->adev, shared_mem_size, PAGE_SIZE, 952 AMDGPU_GEM_DOMAIN_VRAM, 953 &mem_ctx->shared_bo, 954 &mem_ctx->shared_mc_addr, 955 &mem_ctx->shared_buf); 956 957 return ret; 958 } 959 960 static void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 961 { 962 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 963 &mem_ctx->shared_buf); 964 } 965 966 static int psp_xgmi_init_shared_buf(struct psp_context *psp) 967 { 968 return psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context, 969 PSP_XGMI_SHARED_MEM_SIZE); 970 } 971 972 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 973 uint32_t ta_cmd_id, 974 uint32_t session_id) 975 { 976 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 977 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 978 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 979 } 980 981 static int psp_ta_invoke(struct psp_context *psp, 982 uint32_t ta_cmd_id, 983 uint32_t session_id) 984 { 985 int ret; 986 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 987 988 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id); 989 990 ret = psp_cmd_submit_buf(psp, NULL, cmd, 991 psp->fence_buf_mc_addr); 992 993 release_psp_cmd_buf(psp); 994 995 return ret; 996 } 997 998 static int psp_xgmi_load(struct psp_context *psp) 999 { 1000 int ret; 1001 struct psp_gfx_cmd_resp *cmd; 1002 1003 /* 1004 * TODO: bypass the loading in sriov for now 1005 */ 1006 1007 cmd = acquire_psp_cmd_buf(psp); 1008 1009 psp_copy_fw(psp, psp->xgmi.start_addr, psp->xgmi.size_bytes); 1010 1011 psp_prep_ta_load_cmd_buf(cmd, 1012 psp->fw_pri_mc_addr, 1013 psp->xgmi.size_bytes, 1014 psp->xgmi_context.context.mem_context.shared_mc_addr, 1015 PSP_XGMI_SHARED_MEM_SIZE); 1016 1017 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1018 psp->fence_buf_mc_addr); 1019 1020 if (!ret) { 1021 psp->xgmi_context.context.initialized = true; 1022 psp->xgmi_context.context.session_id = cmd->resp.session_id; 1023 } 1024 1025 release_psp_cmd_buf(psp); 1026 1027 return ret; 1028 } 1029 1030 static int psp_xgmi_unload(struct psp_context *psp) 1031 { 1032 int ret; 1033 struct psp_gfx_cmd_resp *cmd; 1034 struct amdgpu_device *adev = psp->adev; 1035 1036 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1037 if (adev->asic_type == CHIP_ARCTURUS || 1038 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu)) 1039 return 0; 1040 1041 /* 1042 * TODO: bypass the unloading in sriov for now 1043 */ 1044 1045 cmd = acquire_psp_cmd_buf(psp); 1046 1047 psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.context.session_id); 1048 1049 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1050 psp->fence_buf_mc_addr); 1051 1052 release_psp_cmd_buf(psp); 1053 1054 return ret; 1055 } 1056 1057 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1058 { 1059 return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.context.session_id); 1060 } 1061 1062 int psp_xgmi_terminate(struct psp_context *psp) 1063 { 1064 int ret; 1065 1066 if (!psp->xgmi_context.context.initialized) 1067 return 0; 1068 1069 ret = psp_xgmi_unload(psp); 1070 if (ret) 1071 return ret; 1072 1073 psp->xgmi_context.context.initialized = false; 1074 1075 /* free xgmi shared memory */ 1076 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 1077 1078 return 0; 1079 } 1080 1081 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1082 { 1083 struct ta_xgmi_shared_memory *xgmi_cmd; 1084 int ret; 1085 1086 if (!psp->ta_fw || 1087 !psp->xgmi.size_bytes || 1088 !psp->xgmi.start_addr) 1089 return -ENOENT; 1090 1091 if (!load_ta) 1092 goto invoke; 1093 1094 if (!psp->xgmi_context.context.initialized) { 1095 ret = psp_xgmi_init_shared_buf(psp); 1096 if (ret) 1097 return ret; 1098 } 1099 1100 /* Load XGMI TA */ 1101 ret = psp_xgmi_load(psp); 1102 if (ret) 1103 return ret; 1104 1105 invoke: 1106 /* Initialize XGMI session */ 1107 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1108 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1109 xgmi_cmd->flag_extend_link_record = set_extended_data; 1110 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1111 1112 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1113 1114 return ret; 1115 } 1116 1117 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1118 { 1119 struct ta_xgmi_shared_memory *xgmi_cmd; 1120 int ret; 1121 1122 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1123 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1124 1125 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1126 1127 /* Invoke xgmi ta to get hive id */ 1128 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1129 if (ret) 1130 return ret; 1131 1132 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1133 1134 return 0; 1135 } 1136 1137 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1138 { 1139 struct ta_xgmi_shared_memory *xgmi_cmd; 1140 int ret; 1141 1142 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1143 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1144 1145 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1146 1147 /* Invoke xgmi ta to get the node id */ 1148 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1149 if (ret) 1150 return ret; 1151 1152 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1153 1154 return 0; 1155 } 1156 1157 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1158 { 1159 return psp->adev->asic_type == CHIP_ALDEBARAN && 1160 psp->xgmi.feature_version >= 0x2000000b; 1161 } 1162 1163 /* 1164 * Chips that support extended topology information require the driver to 1165 * reflect topology information in the opposite direction. This is 1166 * because the TA has already exceeded its link record limit and if the 1167 * TA holds bi-directional information, the driver would have to do 1168 * multiple fetches instead of just two. 1169 */ 1170 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1171 struct psp_xgmi_node_info node_info) 1172 { 1173 struct amdgpu_device *mirror_adev; 1174 struct amdgpu_hive_info *hive; 1175 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1176 uint64_t dst_node_id = node_info.node_id; 1177 uint8_t dst_num_hops = node_info.num_hops; 1178 uint8_t dst_num_links = node_info.num_links; 1179 1180 hive = amdgpu_get_xgmi_hive(psp->adev); 1181 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1182 struct psp_xgmi_topology_info *mirror_top_info; 1183 int j; 1184 1185 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1186 continue; 1187 1188 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1189 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1190 if (mirror_top_info->nodes[j].node_id != src_node_id) 1191 continue; 1192 1193 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1194 /* 1195 * prevent 0 num_links value re-reflection since reflection 1196 * criteria is based on num_hops (direct or indirect). 1197 * 1198 */ 1199 if (dst_num_links) 1200 mirror_top_info->nodes[j].num_links = dst_num_links; 1201 1202 break; 1203 } 1204 1205 break; 1206 } 1207 } 1208 1209 int psp_xgmi_get_topology_info(struct psp_context *psp, 1210 int number_devices, 1211 struct psp_xgmi_topology_info *topology, 1212 bool get_extended_data) 1213 { 1214 struct ta_xgmi_shared_memory *xgmi_cmd; 1215 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1216 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1217 int i; 1218 int ret; 1219 1220 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1221 return -EINVAL; 1222 1223 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1224 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1225 xgmi_cmd->flag_extend_link_record = get_extended_data; 1226 1227 /* Fill in the shared memory with topology information as input */ 1228 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1229 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1230 topology_info_input->num_nodes = number_devices; 1231 1232 for (i = 0; i < topology_info_input->num_nodes; i++) { 1233 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1234 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1235 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1236 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1237 } 1238 1239 /* Invoke xgmi ta to get the topology information */ 1240 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1241 if (ret) 1242 return ret; 1243 1244 /* Read the output topology information from the shared memory */ 1245 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1246 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1247 for (i = 0; i < topology->num_nodes; i++) { 1248 /* extended data will either be 0 or equal to non-extended data */ 1249 if (topology_info_output->nodes[i].num_hops) 1250 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1251 1252 /* non-extended data gets everything here so no need to update */ 1253 if (!get_extended_data) { 1254 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1255 topology->nodes[i].is_sharing_enabled = 1256 topology_info_output->nodes[i].is_sharing_enabled; 1257 topology->nodes[i].sdma_engine = 1258 topology_info_output->nodes[i].sdma_engine; 1259 } 1260 1261 } 1262 1263 /* Invoke xgmi ta again to get the link information */ 1264 if (psp_xgmi_peer_link_info_supported(psp)) { 1265 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1266 1267 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1268 1269 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1270 1271 if (ret) 1272 return ret; 1273 1274 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1275 for (i = 0; i < topology->num_nodes; i++) { 1276 /* accumulate num_links on extended data */ 1277 topology->nodes[i].num_links = get_extended_data ? 1278 topology->nodes[i].num_links + 1279 link_info_output->nodes[i].num_links : 1280 link_info_output->nodes[i].num_links; 1281 1282 /* reflect the topology information for bi-directionality */ 1283 if (psp->xgmi_context.supports_extended_data && 1284 get_extended_data && topology->nodes[i].num_hops) 1285 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1286 } 1287 } 1288 1289 return 0; 1290 } 1291 1292 int psp_xgmi_set_topology_info(struct psp_context *psp, 1293 int number_devices, 1294 struct psp_xgmi_topology_info *topology) 1295 { 1296 struct ta_xgmi_shared_memory *xgmi_cmd; 1297 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1298 int i; 1299 1300 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1301 return -EINVAL; 1302 1303 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1304 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1305 1306 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1307 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1308 topology_info_input->num_nodes = number_devices; 1309 1310 for (i = 0; i < topology_info_input->num_nodes; i++) { 1311 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1312 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1313 topology_info_input->nodes[i].is_sharing_enabled = 1; 1314 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1315 } 1316 1317 /* Invoke xgmi ta to set topology information */ 1318 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1319 } 1320 1321 // ras begin 1322 static int psp_ras_init_shared_buf(struct psp_context *psp) 1323 { 1324 return psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context, 1325 PSP_RAS_SHARED_MEM_SIZE); 1326 } 1327 1328 static int psp_ras_load(struct psp_context *psp) 1329 { 1330 int ret; 1331 struct psp_gfx_cmd_resp *cmd; 1332 struct ta_ras_shared_memory *ras_cmd; 1333 1334 /* 1335 * TODO: bypass the loading in sriov for now 1336 */ 1337 if (amdgpu_sriov_vf(psp->adev)) 1338 return 0; 1339 1340 psp_copy_fw(psp, psp->ras.start_addr, psp->ras.size_bytes); 1341 1342 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1343 1344 if (psp->adev->gmc.xgmi.connected_to_cpu) 1345 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1346 else 1347 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1348 1349 cmd = acquire_psp_cmd_buf(psp); 1350 1351 psp_prep_ta_load_cmd_buf(cmd, 1352 psp->fw_pri_mc_addr, 1353 psp->ras.size_bytes, 1354 psp->ras_context.context.mem_context.shared_mc_addr, 1355 PSP_RAS_SHARED_MEM_SIZE); 1356 1357 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1358 psp->fence_buf_mc_addr); 1359 1360 if (!ret) { 1361 psp->ras_context.context.session_id = cmd->resp.session_id; 1362 1363 if (!ras_cmd->ras_status) 1364 psp->ras_context.context.initialized = true; 1365 else 1366 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1367 } 1368 1369 release_psp_cmd_buf(psp); 1370 1371 if (ret || ras_cmd->ras_status) 1372 amdgpu_ras_fini(psp->adev); 1373 1374 return ret; 1375 } 1376 1377 static int psp_ras_unload(struct psp_context *psp) 1378 { 1379 int ret; 1380 struct psp_gfx_cmd_resp *cmd; 1381 1382 /* 1383 * TODO: bypass the unloading in sriov for now 1384 */ 1385 if (amdgpu_sriov_vf(psp->adev)) 1386 return 0; 1387 1388 cmd = acquire_psp_cmd_buf(psp); 1389 1390 psp_prep_ta_unload_cmd_buf(cmd, psp->ras_context.context.session_id); 1391 1392 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1393 psp->fence_buf_mc_addr); 1394 1395 release_psp_cmd_buf(psp); 1396 1397 return ret; 1398 } 1399 1400 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1401 { 1402 struct ta_ras_shared_memory *ras_cmd; 1403 int ret; 1404 1405 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1406 1407 /* 1408 * TODO: bypass the loading in sriov for now 1409 */ 1410 if (amdgpu_sriov_vf(psp->adev)) 1411 return 0; 1412 1413 ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras_context.context.session_id); 1414 1415 if (amdgpu_ras_intr_triggered()) 1416 return ret; 1417 1418 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1419 { 1420 DRM_WARN("RAS: Unsupported Interface"); 1421 return -EINVAL; 1422 } 1423 1424 if (!ret) { 1425 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1426 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1427 1428 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1429 } 1430 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1431 dev_warn(psp->adev->dev, 1432 "RAS internal register access blocked\n"); 1433 } 1434 1435 return ret; 1436 } 1437 1438 static int psp_ras_status_to_errno(struct amdgpu_device *adev, 1439 enum ta_ras_status ras_status) 1440 { 1441 int ret = -EINVAL; 1442 1443 switch (ras_status) { 1444 case TA_RAS_STATUS__SUCCESS: 1445 ret = 0; 1446 break; 1447 case TA_RAS_STATUS__RESET_NEEDED: 1448 ret = -EAGAIN; 1449 break; 1450 case TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE: 1451 dev_warn(adev->dev, "RAS WARN: ras function unavailable\n"); 1452 break; 1453 case TA_RAS_STATUS__ERROR_ASD_READ_WRITE: 1454 dev_warn(adev->dev, "RAS WARN: asd read or write failed\n"); 1455 break; 1456 default: 1457 dev_err(adev->dev, "RAS ERROR: ras function failed ret 0x%X\n", ret); 1458 } 1459 1460 return ret; 1461 } 1462 1463 int psp_ras_enable_features(struct psp_context *psp, 1464 union ta_ras_cmd_input *info, bool enable) 1465 { 1466 struct ta_ras_shared_memory *ras_cmd; 1467 int ret; 1468 1469 if (!psp->ras_context.context.initialized) 1470 return -EINVAL; 1471 1472 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1473 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1474 1475 if (enable) 1476 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1477 else 1478 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1479 1480 ras_cmd->ras_in_message = *info; 1481 1482 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1483 if (ret) 1484 return -EINVAL; 1485 1486 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1487 } 1488 1489 static int psp_ras_terminate(struct psp_context *psp) 1490 { 1491 int ret; 1492 1493 /* 1494 * TODO: bypass the terminate in sriov for now 1495 */ 1496 if (amdgpu_sriov_vf(psp->adev)) 1497 return 0; 1498 1499 if (!psp->ras_context.context.initialized) 1500 return 0; 1501 1502 ret = psp_ras_unload(psp); 1503 if (ret) 1504 return ret; 1505 1506 psp->ras_context.context.initialized = false; 1507 1508 /* free ras shared memory */ 1509 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 1510 1511 return 0; 1512 } 1513 1514 static int psp_ras_initialize(struct psp_context *psp) 1515 { 1516 int ret; 1517 uint32_t boot_cfg = 0xFF; 1518 struct amdgpu_device *adev = psp->adev; 1519 1520 /* 1521 * TODO: bypass the initialize in sriov for now 1522 */ 1523 if (amdgpu_sriov_vf(adev)) 1524 return 0; 1525 1526 if (!adev->psp.ras.size_bytes || 1527 !adev->psp.ras.start_addr) { 1528 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1529 return 0; 1530 } 1531 1532 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1533 /* query GECC enablement status from boot config 1534 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1535 */ 1536 ret = psp_boot_config_get(adev, &boot_cfg); 1537 if (ret) 1538 dev_warn(adev->dev, "PSP get boot config failed\n"); 1539 1540 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1541 if (!boot_cfg) { 1542 dev_info(adev->dev, "GECC is disabled\n"); 1543 } else { 1544 /* disable GECC in next boot cycle if ras is 1545 * disabled by module parameter amdgpu_ras_enable 1546 * and/or amdgpu_ras_mask, or boot_config_get call 1547 * is failed 1548 */ 1549 ret = psp_boot_config_set(adev, 0); 1550 if (ret) 1551 dev_warn(adev->dev, "PSP set boot config failed\n"); 1552 else 1553 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1554 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1555 } 1556 } else { 1557 if (1 == boot_cfg) { 1558 dev_info(adev->dev, "GECC is enabled\n"); 1559 } else { 1560 /* enable GECC in next boot cycle if it is disabled 1561 * in boot config, or force enable GECC if failed to 1562 * get boot configuration 1563 */ 1564 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1565 if (ret) 1566 dev_warn(adev->dev, "PSP set boot config failed\n"); 1567 else 1568 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1569 } 1570 } 1571 } 1572 1573 if (!psp->ras_context.context.initialized) { 1574 ret = psp_ras_init_shared_buf(psp); 1575 if (ret) 1576 return ret; 1577 } 1578 1579 ret = psp_ras_load(psp); 1580 if (ret) 1581 return ret; 1582 1583 return 0; 1584 } 1585 1586 int psp_ras_trigger_error(struct psp_context *psp, 1587 struct ta_ras_trigger_error_input *info) 1588 { 1589 struct ta_ras_shared_memory *ras_cmd; 1590 int ret; 1591 1592 if (!psp->ras_context.context.initialized) 1593 return -EINVAL; 1594 1595 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1596 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1597 1598 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1599 ras_cmd->ras_in_message.trigger_error = *info; 1600 1601 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1602 if (ret) 1603 return -EINVAL; 1604 1605 /* If err_event_athub occurs error inject was successful, however 1606 return status from TA is no long reliable */ 1607 if (amdgpu_ras_intr_triggered()) 1608 return 0; 1609 1610 return psp_ras_status_to_errno(psp->adev, ras_cmd->ras_status); 1611 } 1612 // ras end 1613 1614 // HDCP start 1615 static int psp_hdcp_init_shared_buf(struct psp_context *psp) 1616 { 1617 return psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context, 1618 PSP_HDCP_SHARED_MEM_SIZE); 1619 } 1620 1621 static int psp_hdcp_load(struct psp_context *psp) 1622 { 1623 int ret; 1624 struct psp_gfx_cmd_resp *cmd; 1625 1626 /* 1627 * TODO: bypass the loading in sriov for now 1628 */ 1629 if (amdgpu_sriov_vf(psp->adev)) 1630 return 0; 1631 1632 psp_copy_fw(psp, psp->hdcp.start_addr, 1633 psp->hdcp.size_bytes); 1634 1635 cmd = acquire_psp_cmd_buf(psp); 1636 1637 psp_prep_ta_load_cmd_buf(cmd, 1638 psp->fw_pri_mc_addr, 1639 psp->hdcp.size_bytes, 1640 psp->hdcp_context.context.mem_context.shared_mc_addr, 1641 PSP_HDCP_SHARED_MEM_SIZE); 1642 1643 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1644 1645 if (!ret) { 1646 psp->hdcp_context.context.initialized = true; 1647 psp->hdcp_context.context.session_id = cmd->resp.session_id; 1648 rw_init(&psp->hdcp_context.mutex, "pspcp"); 1649 } 1650 1651 release_psp_cmd_buf(psp); 1652 1653 return ret; 1654 } 1655 static int psp_hdcp_initialize(struct psp_context *psp) 1656 { 1657 int ret; 1658 1659 /* 1660 * TODO: bypass the initialize in sriov for now 1661 */ 1662 if (amdgpu_sriov_vf(psp->adev)) 1663 return 0; 1664 1665 if (!psp->hdcp.size_bytes || 1666 !psp->hdcp.start_addr) { 1667 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1668 return 0; 1669 } 1670 1671 if (!psp->hdcp_context.context.initialized) { 1672 ret = psp_hdcp_init_shared_buf(psp); 1673 if (ret) 1674 return ret; 1675 } 1676 1677 ret = psp_hdcp_load(psp); 1678 if (ret) 1679 return ret; 1680 1681 return 0; 1682 } 1683 1684 static int psp_hdcp_unload(struct psp_context *psp) 1685 { 1686 int ret; 1687 struct psp_gfx_cmd_resp *cmd; 1688 1689 /* 1690 * TODO: bypass the unloading in sriov for now 1691 */ 1692 if (amdgpu_sriov_vf(psp->adev)) 1693 return 0; 1694 1695 cmd = acquire_psp_cmd_buf(psp); 1696 1697 psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.context.session_id); 1698 1699 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1700 1701 release_psp_cmd_buf(psp); 1702 1703 return ret; 1704 } 1705 1706 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1707 { 1708 /* 1709 * TODO: bypass the loading in sriov for now 1710 */ 1711 if (amdgpu_sriov_vf(psp->adev)) 1712 return 0; 1713 1714 return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.context.session_id); 1715 } 1716 1717 static int psp_hdcp_terminate(struct psp_context *psp) 1718 { 1719 int ret; 1720 1721 /* 1722 * TODO: bypass the terminate in sriov for now 1723 */ 1724 if (amdgpu_sriov_vf(psp->adev)) 1725 return 0; 1726 1727 if (!psp->hdcp_context.context.initialized) { 1728 if (psp->hdcp_context.context.mem_context.shared_buf) 1729 goto out; 1730 else 1731 return 0; 1732 } 1733 1734 ret = psp_hdcp_unload(psp); 1735 if (ret) 1736 return ret; 1737 1738 psp->hdcp_context.context.initialized = false; 1739 1740 out: 1741 /* free hdcp shared memory */ 1742 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 1743 1744 return 0; 1745 } 1746 // HDCP end 1747 1748 // DTM start 1749 static int psp_dtm_init_shared_buf(struct psp_context *psp) 1750 { 1751 return psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context, 1752 PSP_DTM_SHARED_MEM_SIZE); 1753 } 1754 1755 static int psp_dtm_load(struct psp_context *psp) 1756 { 1757 int ret; 1758 struct psp_gfx_cmd_resp *cmd; 1759 1760 /* 1761 * TODO: bypass the loading in sriov for now 1762 */ 1763 if (amdgpu_sriov_vf(psp->adev)) 1764 return 0; 1765 1766 psp_copy_fw(psp, psp->dtm.start_addr, psp->dtm.size_bytes); 1767 1768 cmd = acquire_psp_cmd_buf(psp); 1769 1770 psp_prep_ta_load_cmd_buf(cmd, 1771 psp->fw_pri_mc_addr, 1772 psp->dtm.size_bytes, 1773 psp->dtm_context.context.mem_context.shared_mc_addr, 1774 PSP_DTM_SHARED_MEM_SIZE); 1775 1776 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1777 1778 if (!ret) { 1779 psp->dtm_context.context.initialized = true; 1780 psp->dtm_context.context.session_id = cmd->resp.session_id; 1781 rw_init(&psp->dtm_context.mutex, "pspdtm"); 1782 } 1783 1784 release_psp_cmd_buf(psp); 1785 1786 return ret; 1787 } 1788 1789 static int psp_dtm_initialize(struct psp_context *psp) 1790 { 1791 int ret; 1792 1793 /* 1794 * TODO: bypass the initialize in sriov for now 1795 */ 1796 if (amdgpu_sriov_vf(psp->adev)) 1797 return 0; 1798 1799 if (!psp->dtm.size_bytes || 1800 !psp->dtm.start_addr) { 1801 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1802 return 0; 1803 } 1804 1805 if (!psp->dtm_context.context.initialized) { 1806 ret = psp_dtm_init_shared_buf(psp); 1807 if (ret) 1808 return ret; 1809 } 1810 1811 ret = psp_dtm_load(psp); 1812 if (ret) 1813 return ret; 1814 1815 return 0; 1816 } 1817 1818 static int psp_dtm_unload(struct psp_context *psp) 1819 { 1820 int ret; 1821 struct psp_gfx_cmd_resp *cmd; 1822 1823 /* 1824 * TODO: bypass the unloading in sriov for now 1825 */ 1826 if (amdgpu_sriov_vf(psp->adev)) 1827 return 0; 1828 1829 cmd = acquire_psp_cmd_buf(psp); 1830 1831 psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.context.session_id); 1832 1833 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1834 1835 release_psp_cmd_buf(psp); 1836 1837 return ret; 1838 } 1839 1840 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1841 { 1842 /* 1843 * TODO: bypass the loading in sriov for now 1844 */ 1845 if (amdgpu_sriov_vf(psp->adev)) 1846 return 0; 1847 1848 return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.context.session_id); 1849 } 1850 1851 static int psp_dtm_terminate(struct psp_context *psp) 1852 { 1853 int ret; 1854 1855 /* 1856 * TODO: bypass the terminate in sriov for now 1857 */ 1858 if (amdgpu_sriov_vf(psp->adev)) 1859 return 0; 1860 1861 if (!psp->dtm_context.context.initialized) { 1862 if (psp->dtm_context.context.mem_context.shared_buf) 1863 goto out; 1864 else 1865 return 0; 1866 } 1867 1868 ret = psp_dtm_unload(psp); 1869 if (ret) 1870 return ret; 1871 1872 psp->dtm_context.context.initialized = false; 1873 1874 out: 1875 /* free dtm shared memory */ 1876 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 1877 1878 return 0; 1879 } 1880 // DTM end 1881 1882 // RAP start 1883 static int psp_rap_init_shared_buf(struct psp_context *psp) 1884 { 1885 return psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context, 1886 PSP_RAP_SHARED_MEM_SIZE); 1887 } 1888 1889 static int psp_rap_load(struct psp_context *psp) 1890 { 1891 int ret; 1892 struct psp_gfx_cmd_resp *cmd; 1893 1894 psp_copy_fw(psp, psp->rap.start_addr, psp->rap.size_bytes); 1895 1896 cmd = acquire_psp_cmd_buf(psp); 1897 1898 psp_prep_ta_load_cmd_buf(cmd, 1899 psp->fw_pri_mc_addr, 1900 psp->rap.size_bytes, 1901 psp->rap_context.context.mem_context.shared_mc_addr, 1902 PSP_RAP_SHARED_MEM_SIZE); 1903 1904 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1905 1906 if (!ret) { 1907 psp->rap_context.context.initialized = true; 1908 psp->rap_context.context.session_id = cmd->resp.session_id; 1909 rw_init(&psp->rap_context.mutex, "psprap"); 1910 } 1911 1912 release_psp_cmd_buf(psp); 1913 1914 return ret; 1915 } 1916 1917 static int psp_rap_unload(struct psp_context *psp) 1918 { 1919 int ret; 1920 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1921 1922 psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.context.session_id); 1923 1924 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1925 1926 release_psp_cmd_buf(psp); 1927 1928 return ret; 1929 } 1930 1931 static int psp_rap_initialize(struct psp_context *psp) 1932 { 1933 int ret; 1934 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1935 1936 /* 1937 * TODO: bypass the initialize in sriov for now 1938 */ 1939 if (amdgpu_sriov_vf(psp->adev)) 1940 return 0; 1941 1942 if (!psp->rap.size_bytes || 1943 !psp->rap.start_addr) { 1944 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1945 return 0; 1946 } 1947 1948 if (!psp->rap_context.context.initialized) { 1949 ret = psp_rap_init_shared_buf(psp); 1950 if (ret) 1951 return ret; 1952 } 1953 1954 ret = psp_rap_load(psp); 1955 if (ret) 1956 return ret; 1957 1958 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1959 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1960 psp_rap_unload(psp); 1961 1962 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1963 1964 psp->rap_context.context.initialized = false; 1965 1966 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1967 ret, status); 1968 1969 return ret; 1970 } 1971 1972 return 0; 1973 } 1974 1975 static int psp_rap_terminate(struct psp_context *psp) 1976 { 1977 int ret; 1978 1979 if (!psp->rap_context.context.initialized) 1980 return 0; 1981 1982 ret = psp_rap_unload(psp); 1983 1984 psp->rap_context.context.initialized = false; 1985 1986 /* free rap shared memory */ 1987 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1988 1989 return ret; 1990 } 1991 1992 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1993 { 1994 struct ta_rap_shared_memory *rap_cmd; 1995 int ret = 0; 1996 1997 if (!psp->rap_context.context.initialized) 1998 return 0; 1999 2000 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 2001 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 2002 return -EINVAL; 2003 2004 mutex_lock(&psp->rap_context.mutex); 2005 2006 rap_cmd = (struct ta_rap_shared_memory *) 2007 psp->rap_context.context.mem_context.shared_buf; 2008 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 2009 2010 rap_cmd->cmd_id = ta_cmd_id; 2011 rap_cmd->validation_method_id = METHOD_A; 2012 2013 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.context.session_id); 2014 if (ret) 2015 goto out_unlock; 2016 2017 if (status) 2018 *status = rap_cmd->rap_status; 2019 2020 out_unlock: 2021 mutex_unlock(&psp->rap_context.mutex); 2022 2023 return ret; 2024 } 2025 // RAP end 2026 2027 /* securedisplay start */ 2028 static int psp_securedisplay_init_shared_buf(struct psp_context *psp) 2029 { 2030 return psp_ta_init_shared_buf( 2031 psp, &psp->securedisplay_context.context.mem_context, 2032 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 2033 } 2034 2035 static int psp_securedisplay_load(struct psp_context *psp) 2036 { 2037 int ret; 2038 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2039 2040 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 2041 memcpy(psp->fw_pri_buf, psp->securedisplay.start_addr, psp->securedisplay.size_bytes); 2042 2043 psp_prep_ta_load_cmd_buf(cmd, 2044 psp->fw_pri_mc_addr, 2045 psp->securedisplay.size_bytes, 2046 psp->securedisplay_context.context.mem_context.shared_mc_addr, 2047 PSP_SECUREDISPLAY_SHARED_MEM_SIZE); 2048 2049 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 2050 2051 if (!ret) { 2052 psp->securedisplay_context.context.initialized = true; 2053 psp->securedisplay_context.context.session_id = cmd->resp.session_id; 2054 rw_init(&psp->securedisplay_context.mutex, "pscm"); 2055 } 2056 2057 release_psp_cmd_buf(psp); 2058 2059 return ret; 2060 } 2061 2062 static int psp_securedisplay_unload(struct psp_context *psp) 2063 { 2064 int ret; 2065 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2066 2067 psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.context.session_id); 2068 2069 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 2070 2071 release_psp_cmd_buf(psp); 2072 2073 return ret; 2074 } 2075 2076 static int psp_securedisplay_initialize(struct psp_context *psp) 2077 { 2078 int ret; 2079 struct securedisplay_cmd *securedisplay_cmd; 2080 2081 /* 2082 * TODO: bypass the initialize in sriov for now 2083 */ 2084 if (amdgpu_sriov_vf(psp->adev)) 2085 return 0; 2086 2087 if (!psp->securedisplay.size_bytes || 2088 !psp->securedisplay.start_addr) { 2089 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 2090 return 0; 2091 } 2092 2093 if (!psp->securedisplay_context.context.initialized) { 2094 ret = psp_securedisplay_init_shared_buf(psp); 2095 if (ret) 2096 return ret; 2097 } 2098 2099 ret = psp_securedisplay_load(psp); 2100 if (ret) 2101 return ret; 2102 2103 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 2104 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2105 2106 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 2107 if (ret) { 2108 psp_securedisplay_unload(psp); 2109 2110 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2111 2112 psp->securedisplay_context.context.initialized = false; 2113 2114 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 2115 return -EINVAL; 2116 } 2117 2118 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 2119 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 2120 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 2121 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 2122 } 2123 2124 return 0; 2125 } 2126 2127 static int psp_securedisplay_terminate(struct psp_context *psp) 2128 { 2129 int ret; 2130 2131 /* 2132 * TODO:bypass the terminate in sriov for now 2133 */ 2134 if (amdgpu_sriov_vf(psp->adev)) 2135 return 0; 2136 2137 if (!psp->securedisplay_context.context.initialized) 2138 return 0; 2139 2140 ret = psp_securedisplay_unload(psp); 2141 if (ret) 2142 return ret; 2143 2144 psp->securedisplay_context.context.initialized = false; 2145 2146 /* free securedisplay shared memory */ 2147 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 2148 2149 return ret; 2150 } 2151 2152 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2153 { 2154 int ret; 2155 2156 if (!psp->securedisplay_context.context.initialized) 2157 return -EINVAL; 2158 2159 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2160 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2161 return -EINVAL; 2162 2163 mutex_lock(&psp->securedisplay_context.mutex); 2164 2165 ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.context.session_id); 2166 2167 mutex_unlock(&psp->securedisplay_context.mutex); 2168 2169 return ret; 2170 } 2171 /* SECUREDISPLAY end */ 2172 2173 static int psp_hw_start(struct psp_context *psp) 2174 { 2175 struct amdgpu_device *adev = psp->adev; 2176 int ret; 2177 2178 if (!amdgpu_sriov_vf(adev)) { 2179 if ((is_psp_fw_valid(psp->kdb)) && 2180 (psp->funcs->bootloader_load_kdb != NULL)) { 2181 ret = psp_bootloader_load_kdb(psp); 2182 if (ret) { 2183 DRM_ERROR("PSP load kdb failed!\n"); 2184 return ret; 2185 } 2186 } 2187 2188 if ((is_psp_fw_valid(psp->spl)) && 2189 (psp->funcs->bootloader_load_spl != NULL)) { 2190 ret = psp_bootloader_load_spl(psp); 2191 if (ret) { 2192 DRM_ERROR("PSP load spl failed!\n"); 2193 return ret; 2194 } 2195 } 2196 2197 if ((is_psp_fw_valid(psp->sys)) && 2198 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2199 ret = psp_bootloader_load_sysdrv(psp); 2200 if (ret) { 2201 DRM_ERROR("PSP load sys drv failed!\n"); 2202 return ret; 2203 } 2204 } 2205 2206 if ((is_psp_fw_valid(psp->soc_drv)) && 2207 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2208 ret = psp_bootloader_load_soc_drv(psp); 2209 if (ret) { 2210 DRM_ERROR("PSP load soc drv failed!\n"); 2211 return ret; 2212 } 2213 } 2214 2215 if ((is_psp_fw_valid(psp->intf_drv)) && 2216 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2217 ret = psp_bootloader_load_intf_drv(psp); 2218 if (ret) { 2219 DRM_ERROR("PSP load intf drv failed!\n"); 2220 return ret; 2221 } 2222 } 2223 2224 if ((is_psp_fw_valid(psp->dbg_drv)) && 2225 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2226 ret = psp_bootloader_load_dbg_drv(psp); 2227 if (ret) { 2228 DRM_ERROR("PSP load dbg drv failed!\n"); 2229 return ret; 2230 } 2231 } 2232 2233 if ((is_psp_fw_valid(psp->sos)) && 2234 (psp->funcs->bootloader_load_sos != NULL)) { 2235 ret = psp_bootloader_load_sos(psp); 2236 if (ret) { 2237 DRM_ERROR("PSP load sos failed!\n"); 2238 return ret; 2239 } 2240 } 2241 } 2242 2243 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2244 if (ret) { 2245 DRM_ERROR("PSP create ring failed!\n"); 2246 return ret; 2247 } 2248 2249 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2250 goto skip_pin_bo; 2251 2252 ret = psp_tmr_init(psp); 2253 if (ret) { 2254 DRM_ERROR("PSP tmr init failed!\n"); 2255 return ret; 2256 } 2257 2258 skip_pin_bo: 2259 /* 2260 * For ASICs with DF Cstate management centralized 2261 * to PMFW, TMR setup should be performed after PMFW 2262 * loaded and before other non-psp firmware loaded. 2263 */ 2264 if (psp->pmfw_centralized_cstate_management) { 2265 ret = psp_load_smu_fw(psp); 2266 if (ret) 2267 return ret; 2268 } 2269 2270 ret = psp_tmr_load(psp); 2271 if (ret) { 2272 DRM_ERROR("PSP load tmr failed!\n"); 2273 return ret; 2274 } 2275 2276 return 0; 2277 } 2278 2279 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2280 enum psp_gfx_fw_type *type) 2281 { 2282 switch (ucode->ucode_id) { 2283 case AMDGPU_UCODE_ID_SDMA0: 2284 *type = GFX_FW_TYPE_SDMA0; 2285 break; 2286 case AMDGPU_UCODE_ID_SDMA1: 2287 *type = GFX_FW_TYPE_SDMA1; 2288 break; 2289 case AMDGPU_UCODE_ID_SDMA2: 2290 *type = GFX_FW_TYPE_SDMA2; 2291 break; 2292 case AMDGPU_UCODE_ID_SDMA3: 2293 *type = GFX_FW_TYPE_SDMA3; 2294 break; 2295 case AMDGPU_UCODE_ID_SDMA4: 2296 *type = GFX_FW_TYPE_SDMA4; 2297 break; 2298 case AMDGPU_UCODE_ID_SDMA5: 2299 *type = GFX_FW_TYPE_SDMA5; 2300 break; 2301 case AMDGPU_UCODE_ID_SDMA6: 2302 *type = GFX_FW_TYPE_SDMA6; 2303 break; 2304 case AMDGPU_UCODE_ID_SDMA7: 2305 *type = GFX_FW_TYPE_SDMA7; 2306 break; 2307 case AMDGPU_UCODE_ID_CP_MES: 2308 *type = GFX_FW_TYPE_CP_MES; 2309 break; 2310 case AMDGPU_UCODE_ID_CP_MES_DATA: 2311 *type = GFX_FW_TYPE_MES_STACK; 2312 break; 2313 case AMDGPU_UCODE_ID_CP_CE: 2314 *type = GFX_FW_TYPE_CP_CE; 2315 break; 2316 case AMDGPU_UCODE_ID_CP_PFP: 2317 *type = GFX_FW_TYPE_CP_PFP; 2318 break; 2319 case AMDGPU_UCODE_ID_CP_ME: 2320 *type = GFX_FW_TYPE_CP_ME; 2321 break; 2322 case AMDGPU_UCODE_ID_CP_MEC1: 2323 *type = GFX_FW_TYPE_CP_MEC; 2324 break; 2325 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2326 *type = GFX_FW_TYPE_CP_MEC_ME1; 2327 break; 2328 case AMDGPU_UCODE_ID_CP_MEC2: 2329 *type = GFX_FW_TYPE_CP_MEC; 2330 break; 2331 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2332 *type = GFX_FW_TYPE_CP_MEC_ME2; 2333 break; 2334 case AMDGPU_UCODE_ID_RLC_G: 2335 *type = GFX_FW_TYPE_RLC_G; 2336 break; 2337 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2338 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2339 break; 2340 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2341 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2342 break; 2343 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2344 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2345 break; 2346 case AMDGPU_UCODE_ID_RLC_IRAM: 2347 *type = GFX_FW_TYPE_RLC_IRAM; 2348 break; 2349 case AMDGPU_UCODE_ID_RLC_DRAM: 2350 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2351 break; 2352 case AMDGPU_UCODE_ID_SMC: 2353 *type = GFX_FW_TYPE_SMU; 2354 break; 2355 case AMDGPU_UCODE_ID_UVD: 2356 *type = GFX_FW_TYPE_UVD; 2357 break; 2358 case AMDGPU_UCODE_ID_UVD1: 2359 *type = GFX_FW_TYPE_UVD1; 2360 break; 2361 case AMDGPU_UCODE_ID_VCE: 2362 *type = GFX_FW_TYPE_VCE; 2363 break; 2364 case AMDGPU_UCODE_ID_VCN: 2365 *type = GFX_FW_TYPE_VCN; 2366 break; 2367 case AMDGPU_UCODE_ID_VCN1: 2368 *type = GFX_FW_TYPE_VCN1; 2369 break; 2370 case AMDGPU_UCODE_ID_DMCU_ERAM: 2371 *type = GFX_FW_TYPE_DMCU_ERAM; 2372 break; 2373 case AMDGPU_UCODE_ID_DMCU_INTV: 2374 *type = GFX_FW_TYPE_DMCU_ISR; 2375 break; 2376 case AMDGPU_UCODE_ID_VCN0_RAM: 2377 *type = GFX_FW_TYPE_VCN0_RAM; 2378 break; 2379 case AMDGPU_UCODE_ID_VCN1_RAM: 2380 *type = GFX_FW_TYPE_VCN1_RAM; 2381 break; 2382 case AMDGPU_UCODE_ID_DMCUB: 2383 *type = GFX_FW_TYPE_DMUB; 2384 break; 2385 case AMDGPU_UCODE_ID_MAXIMUM: 2386 default: 2387 return -EINVAL; 2388 } 2389 2390 return 0; 2391 } 2392 2393 static void psp_print_fw_hdr(struct psp_context *psp, 2394 struct amdgpu_firmware_info *ucode) 2395 { 2396 struct amdgpu_device *adev = psp->adev; 2397 struct common_firmware_header *hdr; 2398 2399 switch (ucode->ucode_id) { 2400 case AMDGPU_UCODE_ID_SDMA0: 2401 case AMDGPU_UCODE_ID_SDMA1: 2402 case AMDGPU_UCODE_ID_SDMA2: 2403 case AMDGPU_UCODE_ID_SDMA3: 2404 case AMDGPU_UCODE_ID_SDMA4: 2405 case AMDGPU_UCODE_ID_SDMA5: 2406 case AMDGPU_UCODE_ID_SDMA6: 2407 case AMDGPU_UCODE_ID_SDMA7: 2408 hdr = (struct common_firmware_header *) 2409 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2410 amdgpu_ucode_print_sdma_hdr(hdr); 2411 break; 2412 case AMDGPU_UCODE_ID_CP_CE: 2413 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2414 amdgpu_ucode_print_gfx_hdr(hdr); 2415 break; 2416 case AMDGPU_UCODE_ID_CP_PFP: 2417 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2418 amdgpu_ucode_print_gfx_hdr(hdr); 2419 break; 2420 case AMDGPU_UCODE_ID_CP_ME: 2421 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2422 amdgpu_ucode_print_gfx_hdr(hdr); 2423 break; 2424 case AMDGPU_UCODE_ID_CP_MEC1: 2425 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2426 amdgpu_ucode_print_gfx_hdr(hdr); 2427 break; 2428 case AMDGPU_UCODE_ID_RLC_G: 2429 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2430 amdgpu_ucode_print_rlc_hdr(hdr); 2431 break; 2432 case AMDGPU_UCODE_ID_SMC: 2433 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2434 amdgpu_ucode_print_smc_hdr(hdr); 2435 break; 2436 default: 2437 break; 2438 } 2439 } 2440 2441 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2442 struct psp_gfx_cmd_resp *cmd) 2443 { 2444 int ret; 2445 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2446 2447 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2448 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2449 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2450 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2451 2452 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2453 if (ret) 2454 DRM_ERROR("Unknown firmware type\n"); 2455 2456 return ret; 2457 } 2458 2459 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2460 struct amdgpu_firmware_info *ucode) 2461 { 2462 int ret = 0; 2463 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2464 2465 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2466 if (!ret) { 2467 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2468 psp->fence_buf_mc_addr); 2469 } 2470 2471 release_psp_cmd_buf(psp); 2472 2473 return ret; 2474 } 2475 2476 static int psp_load_smu_fw(struct psp_context *psp) 2477 { 2478 int ret; 2479 struct amdgpu_device *adev = psp->adev; 2480 struct amdgpu_firmware_info *ucode = 2481 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2482 struct amdgpu_ras *ras = psp->ras_context.ras; 2483 2484 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2485 return 0; 2486 2487 if ((amdgpu_in_reset(adev) && 2488 ras && adev->ras_enabled && 2489 (adev->asic_type == CHIP_ARCTURUS || 2490 adev->asic_type == CHIP_VEGA20))) { 2491 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2492 if (ret) { 2493 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2494 } 2495 } 2496 2497 ret = psp_execute_non_psp_fw_load(psp, ucode); 2498 2499 if (ret) 2500 DRM_ERROR("PSP load smu failed!\n"); 2501 2502 return ret; 2503 } 2504 2505 static bool fw_load_skip_check(struct psp_context *psp, 2506 struct amdgpu_firmware_info *ucode) 2507 { 2508 if (!ucode->fw || !ucode->ucode_size) 2509 return true; 2510 2511 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2512 (psp_smu_reload_quirk(psp) || 2513 psp->autoload_supported || 2514 psp->pmfw_centralized_cstate_management)) 2515 return true; 2516 2517 if (amdgpu_sriov_vf(psp->adev) && 2518 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0 2519 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 2520 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 2521 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3 2522 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4 2523 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5 2524 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6 2525 || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7 2526 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G 2527 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL 2528 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM 2529 || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM 2530 || ucode->ucode_id == AMDGPU_UCODE_ID_SMC)) 2531 /*skip ucode loading in SRIOV VF */ 2532 return true; 2533 2534 if (psp->autoload_supported && 2535 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2536 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2537 /* skip mec JT when autoload is enabled */ 2538 return true; 2539 2540 return false; 2541 } 2542 2543 int psp_load_fw_list(struct psp_context *psp, 2544 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2545 { 2546 int ret = 0, i; 2547 struct amdgpu_firmware_info *ucode; 2548 2549 for (i = 0; i < ucode_count; ++i) { 2550 ucode = ucode_list[i]; 2551 psp_print_fw_hdr(psp, ucode); 2552 ret = psp_execute_non_psp_fw_load(psp, ucode); 2553 if (ret) 2554 return ret; 2555 } 2556 return ret; 2557 } 2558 2559 static int psp_load_non_psp_fw(struct psp_context *psp) 2560 { 2561 int i, ret; 2562 struct amdgpu_firmware_info *ucode; 2563 struct amdgpu_device *adev = psp->adev; 2564 2565 if (psp->autoload_supported && 2566 !psp->pmfw_centralized_cstate_management) { 2567 ret = psp_load_smu_fw(psp); 2568 if (ret) 2569 return ret; 2570 } 2571 2572 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2573 ucode = &adev->firmware.ucode[i]; 2574 2575 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2576 !fw_load_skip_check(psp, ucode)) { 2577 ret = psp_load_smu_fw(psp); 2578 if (ret) 2579 return ret; 2580 continue; 2581 } 2582 2583 if (fw_load_skip_check(psp, ucode)) 2584 continue; 2585 2586 if (psp->autoload_supported && 2587 (adev->asic_type >= CHIP_SIENNA_CICHLID && 2588 adev->asic_type <= CHIP_DIMGREY_CAVEFISH) && 2589 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2590 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2591 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2592 /* PSP only receive one SDMA fw for sienna_cichlid, 2593 * as all four sdma fw are same */ 2594 continue; 2595 2596 psp_print_fw_hdr(psp, ucode); 2597 2598 ret = psp_execute_non_psp_fw_load(psp, ucode); 2599 if (ret) 2600 return ret; 2601 2602 /* Start rlc autoload after psp recieved all the gfx firmware */ 2603 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2604 AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) { 2605 ret = psp_rlc_autoload_start(psp); 2606 if (ret) { 2607 DRM_ERROR("Failed to start rlc autoload\n"); 2608 return ret; 2609 } 2610 } 2611 } 2612 2613 return 0; 2614 } 2615 2616 static int psp_load_fw(struct amdgpu_device *adev) 2617 { 2618 int ret; 2619 struct psp_context *psp = &adev->psp; 2620 2621 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2622 /* should not destroy ring, only stop */ 2623 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2624 } else { 2625 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2626 2627 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2628 if (ret) { 2629 DRM_ERROR("PSP ring init failed!\n"); 2630 goto failed; 2631 } 2632 } 2633 2634 ret = psp_hw_start(psp); 2635 if (ret) 2636 goto failed; 2637 2638 ret = psp_load_non_psp_fw(psp); 2639 if (ret) 2640 goto failed; 2641 2642 ret = psp_asd_load(psp); 2643 if (ret) { 2644 DRM_ERROR("PSP load asd failed!\n"); 2645 return ret; 2646 } 2647 2648 ret = psp_rl_load(adev); 2649 if (ret) { 2650 DRM_ERROR("PSP load RL failed!\n"); 2651 return ret; 2652 } 2653 2654 if (psp->ta_fw) { 2655 ret = psp_ras_initialize(psp); 2656 if (ret) 2657 dev_err(psp->adev->dev, 2658 "RAS: Failed to initialize RAS\n"); 2659 2660 ret = psp_hdcp_initialize(psp); 2661 if (ret) 2662 dev_err(psp->adev->dev, 2663 "HDCP: Failed to initialize HDCP\n"); 2664 2665 ret = psp_dtm_initialize(psp); 2666 if (ret) 2667 dev_err(psp->adev->dev, 2668 "DTM: Failed to initialize DTM\n"); 2669 2670 ret = psp_rap_initialize(psp); 2671 if (ret) 2672 dev_err(psp->adev->dev, 2673 "RAP: Failed to initialize RAP\n"); 2674 2675 ret = psp_securedisplay_initialize(psp); 2676 if (ret) 2677 dev_err(psp->adev->dev, 2678 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2679 } 2680 2681 return 0; 2682 2683 failed: 2684 /* 2685 * all cleanup jobs (xgmi terminate, ras terminate, 2686 * ring destroy, cmd/fence/fw buffers destory, 2687 * psp->cmd destory) are delayed to psp_hw_fini 2688 */ 2689 return ret; 2690 } 2691 2692 static int psp_hw_init(void *handle) 2693 { 2694 int ret; 2695 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2696 2697 mutex_lock(&adev->firmware.mutex); 2698 /* 2699 * This sequence is just used on hw_init only once, no need on 2700 * resume. 2701 */ 2702 ret = amdgpu_ucode_init_bo(adev); 2703 if (ret) 2704 goto failed; 2705 2706 ret = psp_load_fw(adev); 2707 if (ret) { 2708 DRM_ERROR("PSP firmware loading failed\n"); 2709 goto failed; 2710 } 2711 2712 mutex_unlock(&adev->firmware.mutex); 2713 return 0; 2714 2715 failed: 2716 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2717 mutex_unlock(&adev->firmware.mutex); 2718 return -EINVAL; 2719 } 2720 2721 static int psp_hw_fini(void *handle) 2722 { 2723 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2724 struct psp_context *psp = &adev->psp; 2725 2726 if (psp->ta_fw) { 2727 psp_ras_terminate(psp); 2728 psp_securedisplay_terminate(psp); 2729 psp_rap_terminate(psp); 2730 psp_dtm_terminate(psp); 2731 psp_hdcp_terminate(psp); 2732 2733 if (adev->gmc.xgmi.num_physical_nodes > 1) 2734 psp_xgmi_terminate(psp); 2735 } 2736 2737 psp_asd_unload(psp); 2738 2739 psp_tmr_terminate(psp); 2740 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2741 2742 return 0; 2743 } 2744 2745 static int psp_suspend(void *handle) 2746 { 2747 int ret; 2748 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2749 struct psp_context *psp = &adev->psp; 2750 2751 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2752 psp->xgmi_context.context.initialized) { 2753 ret = psp_xgmi_terminate(psp); 2754 if (ret) { 2755 DRM_ERROR("Failed to terminate xgmi ta\n"); 2756 return ret; 2757 } 2758 } 2759 2760 if (psp->ta_fw) { 2761 ret = psp_ras_terminate(psp); 2762 if (ret) { 2763 DRM_ERROR("Failed to terminate ras ta\n"); 2764 return ret; 2765 } 2766 ret = psp_hdcp_terminate(psp); 2767 if (ret) { 2768 DRM_ERROR("Failed to terminate hdcp ta\n"); 2769 return ret; 2770 } 2771 ret = psp_dtm_terminate(psp); 2772 if (ret) { 2773 DRM_ERROR("Failed to terminate dtm ta\n"); 2774 return ret; 2775 } 2776 ret = psp_rap_terminate(psp); 2777 if (ret) { 2778 DRM_ERROR("Failed to terminate rap ta\n"); 2779 return ret; 2780 } 2781 ret = psp_securedisplay_terminate(psp); 2782 if (ret) { 2783 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2784 return ret; 2785 } 2786 } 2787 2788 ret = psp_asd_unload(psp); 2789 if (ret) { 2790 DRM_ERROR("Failed to unload asd\n"); 2791 return ret; 2792 } 2793 2794 ret = psp_tmr_terminate(psp); 2795 if (ret) { 2796 DRM_ERROR("Failed to terminate tmr\n"); 2797 return ret; 2798 } 2799 2800 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2801 if (ret) { 2802 DRM_ERROR("PSP ring stop failed\n"); 2803 return ret; 2804 } 2805 2806 return 0; 2807 } 2808 2809 static int psp_resume(void *handle) 2810 { 2811 int ret; 2812 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2813 struct psp_context *psp = &adev->psp; 2814 2815 DRM_INFO("PSP is resuming...\n"); 2816 2817 if (psp->mem_train_ctx.enable_mem_training) { 2818 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2819 if (ret) { 2820 DRM_ERROR("Failed to process memory training!\n"); 2821 return ret; 2822 } 2823 } 2824 2825 mutex_lock(&adev->firmware.mutex); 2826 2827 ret = psp_hw_start(psp); 2828 if (ret) 2829 goto failed; 2830 2831 ret = psp_load_non_psp_fw(psp); 2832 if (ret) 2833 goto failed; 2834 2835 ret = psp_asd_load(psp); 2836 if (ret) { 2837 DRM_ERROR("PSP load asd failed!\n"); 2838 goto failed; 2839 } 2840 2841 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2842 ret = psp_xgmi_initialize(psp, false, true); 2843 /* Warning the XGMI seesion initialize failure 2844 * Instead of stop driver initialization 2845 */ 2846 if (ret) 2847 dev_err(psp->adev->dev, 2848 "XGMI: Failed to initialize XGMI session\n"); 2849 } 2850 2851 if (psp->ta_fw) { 2852 ret = psp_ras_initialize(psp); 2853 if (ret) 2854 dev_err(psp->adev->dev, 2855 "RAS: Failed to initialize RAS\n"); 2856 2857 ret = psp_hdcp_initialize(psp); 2858 if (ret) 2859 dev_err(psp->adev->dev, 2860 "HDCP: Failed to initialize HDCP\n"); 2861 2862 ret = psp_dtm_initialize(psp); 2863 if (ret) 2864 dev_err(psp->adev->dev, 2865 "DTM: Failed to initialize DTM\n"); 2866 2867 ret = psp_rap_initialize(psp); 2868 if (ret) 2869 dev_err(psp->adev->dev, 2870 "RAP: Failed to initialize RAP\n"); 2871 2872 ret = psp_securedisplay_initialize(psp); 2873 if (ret) 2874 dev_err(psp->adev->dev, 2875 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2876 } 2877 2878 mutex_unlock(&adev->firmware.mutex); 2879 2880 return 0; 2881 2882 failed: 2883 DRM_ERROR("PSP resume failed\n"); 2884 mutex_unlock(&adev->firmware.mutex); 2885 return ret; 2886 } 2887 2888 int psp_gpu_reset(struct amdgpu_device *adev) 2889 { 2890 int ret; 2891 2892 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2893 return 0; 2894 2895 mutex_lock(&adev->psp.mutex); 2896 ret = psp_mode1_reset(&adev->psp); 2897 mutex_unlock(&adev->psp.mutex); 2898 2899 return ret; 2900 } 2901 2902 int psp_rlc_autoload_start(struct psp_context *psp) 2903 { 2904 int ret; 2905 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2906 2907 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2908 2909 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2910 psp->fence_buf_mc_addr); 2911 2912 release_psp_cmd_buf(psp); 2913 2914 return ret; 2915 } 2916 2917 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2918 uint64_t cmd_gpu_addr, int cmd_size) 2919 { 2920 struct amdgpu_firmware_info ucode = {0}; 2921 2922 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2923 AMDGPU_UCODE_ID_VCN0_RAM; 2924 ucode.mc_addr = cmd_gpu_addr; 2925 ucode.ucode_size = cmd_size; 2926 2927 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2928 } 2929 2930 int psp_ring_cmd_submit(struct psp_context *psp, 2931 uint64_t cmd_buf_mc_addr, 2932 uint64_t fence_mc_addr, 2933 int index) 2934 { 2935 unsigned int psp_write_ptr_reg = 0; 2936 struct psp_gfx_rb_frame *write_frame; 2937 struct psp_ring *ring = &psp->km_ring; 2938 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2939 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2940 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2941 struct amdgpu_device *adev = psp->adev; 2942 uint32_t ring_size_dw = ring->ring_size / 4; 2943 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2944 2945 /* KM (GPCOM) prepare write pointer */ 2946 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2947 2948 /* Update KM RB frame pointer to new frame */ 2949 /* write_frame ptr increments by size of rb_frame in bytes */ 2950 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2951 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2952 write_frame = ring_buffer_start; 2953 else 2954 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2955 /* Check invalid write_frame ptr address */ 2956 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2957 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2958 ring_buffer_start, ring_buffer_end, write_frame); 2959 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2960 return -EINVAL; 2961 } 2962 2963 /* Initialize KM RB frame */ 2964 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2965 2966 /* Update KM RB frame */ 2967 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2968 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2969 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2970 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2971 write_frame->fence_value = index; 2972 amdgpu_device_flush_hdp(adev, NULL); 2973 2974 /* Update the write Pointer in DWORDs */ 2975 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2976 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2977 return 0; 2978 } 2979 2980 int psp_init_asd_microcode(struct psp_context *psp, 2981 const char *chip_name) 2982 { 2983 struct amdgpu_device *adev = psp->adev; 2984 char fw_name[PSP_FW_NAME_LEN]; 2985 const struct psp_firmware_header_v1_0 *asd_hdr; 2986 int err = 0; 2987 2988 if (!chip_name) { 2989 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2990 return -EINVAL; 2991 } 2992 2993 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2994 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2995 if (err) 2996 goto out; 2997 2998 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2999 if (err) 3000 goto out; 3001 3002 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 3003 adev->psp.asd.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 3004 adev->psp.asd.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 3005 adev->psp.asd.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 3006 adev->psp.asd.start_addr = (uint8_t *)asd_hdr + 3007 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 3008 return 0; 3009 out: 3010 dev_err(adev->dev, "fail to initialize asd microcode\n"); 3011 release_firmware(adev->psp.asd_fw); 3012 adev->psp.asd_fw = NULL; 3013 return err; 3014 } 3015 3016 int psp_init_toc_microcode(struct psp_context *psp, 3017 const char *chip_name) 3018 { 3019 struct amdgpu_device *adev = psp->adev; 3020 char fw_name[PSP_FW_NAME_LEN]; 3021 const struct psp_firmware_header_v1_0 *toc_hdr; 3022 int err = 0; 3023 3024 if (!chip_name) { 3025 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 3026 return -EINVAL; 3027 } 3028 3029 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 3030 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 3031 if (err) 3032 goto out; 3033 3034 err = amdgpu_ucode_validate(adev->psp.toc_fw); 3035 if (err) 3036 goto out; 3037 3038 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 3039 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 3040 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 3041 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 3042 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 3043 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 3044 return 0; 3045 out: 3046 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 3047 release_firmware(adev->psp.toc_fw); 3048 adev->psp.toc_fw = NULL; 3049 return err; 3050 } 3051 3052 static int parse_sos_bin_descriptor(struct psp_context *psp, 3053 const struct psp_fw_bin_desc *desc, 3054 const struct psp_firmware_header_v2_0 *sos_hdr) 3055 { 3056 uint8_t *ucode_start_addr = NULL; 3057 3058 if (!psp || !desc || !sos_hdr) 3059 return -EINVAL; 3060 3061 ucode_start_addr = (uint8_t *)sos_hdr + 3062 le32_to_cpu(desc->offset_bytes) + 3063 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3064 3065 switch (desc->fw_type) { 3066 case PSP_FW_TYPE_PSP_SOS: 3067 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3068 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3069 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3070 psp->sos.start_addr = ucode_start_addr; 3071 break; 3072 case PSP_FW_TYPE_PSP_SYS_DRV: 3073 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3074 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3075 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3076 psp->sys.start_addr = ucode_start_addr; 3077 break; 3078 case PSP_FW_TYPE_PSP_KDB: 3079 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3080 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3081 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3082 psp->kdb.start_addr = ucode_start_addr; 3083 break; 3084 case PSP_FW_TYPE_PSP_TOC: 3085 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3086 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3087 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3088 psp->toc.start_addr = ucode_start_addr; 3089 break; 3090 case PSP_FW_TYPE_PSP_SPL: 3091 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3092 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3093 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3094 psp->spl.start_addr = ucode_start_addr; 3095 break; 3096 case PSP_FW_TYPE_PSP_RL: 3097 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3098 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3099 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3100 psp->rl.start_addr = ucode_start_addr; 3101 break; 3102 case PSP_FW_TYPE_PSP_SOC_DRV: 3103 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3104 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3105 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3106 psp->soc_drv.start_addr = ucode_start_addr; 3107 break; 3108 case PSP_FW_TYPE_PSP_INTF_DRV: 3109 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3110 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3111 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3112 psp->intf_drv.start_addr = ucode_start_addr; 3113 break; 3114 case PSP_FW_TYPE_PSP_DBG_DRV: 3115 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3116 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3117 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3118 psp->dbg_drv.start_addr = ucode_start_addr; 3119 break; 3120 default: 3121 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3122 break; 3123 } 3124 3125 return 0; 3126 } 3127 3128 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3129 { 3130 const struct psp_firmware_header_v1_0 *sos_hdr; 3131 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3132 uint8_t *ucode_array_start_addr; 3133 3134 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3135 ucode_array_start_addr = (uint8_t *)sos_hdr + 3136 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3137 3138 if (adev->gmc.xgmi.connected_to_cpu || (adev->asic_type != CHIP_ALDEBARAN)) { 3139 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3140 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3141 3142 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3143 adev->psp.sys.start_addr = ucode_array_start_addr; 3144 3145 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3146 adev->psp.sos.start_addr = ucode_array_start_addr + 3147 le32_to_cpu(sos_hdr->sos.offset_bytes); 3148 adev->psp.xgmi_context.supports_extended_data = false; 3149 } else { 3150 /* Load alternate PSP SOS FW */ 3151 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3152 3153 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3154 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3155 3156 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3157 adev->psp.sys.start_addr = ucode_array_start_addr + 3158 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3159 3160 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3161 adev->psp.sos.start_addr = ucode_array_start_addr + 3162 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3163 adev->psp.xgmi_context.supports_extended_data = true; 3164 } 3165 3166 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3167 dev_warn(adev->dev, "PSP SOS FW not available"); 3168 return -EINVAL; 3169 } 3170 3171 return 0; 3172 } 3173 3174 int psp_init_sos_microcode(struct psp_context *psp, 3175 const char *chip_name) 3176 { 3177 struct amdgpu_device *adev = psp->adev; 3178 char fw_name[PSP_FW_NAME_LEN]; 3179 const struct psp_firmware_header_v1_0 *sos_hdr; 3180 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3181 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3182 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3183 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3184 int err = 0; 3185 uint8_t *ucode_array_start_addr; 3186 int fw_index = 0; 3187 3188 if (!chip_name) { 3189 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3190 return -EINVAL; 3191 } 3192 3193 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3194 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3195 if (err) 3196 goto out; 3197 3198 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3199 if (err) 3200 goto out; 3201 3202 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3203 ucode_array_start_addr = (uint8_t *)sos_hdr + 3204 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3205 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3206 3207 switch (sos_hdr->header.header_version_major) { 3208 case 1: 3209 err = psp_init_sos_base_fw(adev); 3210 if (err) 3211 goto out; 3212 3213 if (sos_hdr->header.header_version_minor == 1) { 3214 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3215 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3216 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3217 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3218 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3219 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3220 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3221 } 3222 if (sos_hdr->header.header_version_minor == 2) { 3223 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3224 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3225 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3226 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3227 } 3228 if (sos_hdr->header.header_version_minor == 3) { 3229 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3230 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3231 adev->psp.toc.start_addr = ucode_array_start_addr + 3232 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3233 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3234 adev->psp.kdb.start_addr = ucode_array_start_addr + 3235 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3236 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3237 adev->psp.spl.start_addr = ucode_array_start_addr + 3238 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3239 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3240 adev->psp.rl.start_addr = ucode_array_start_addr + 3241 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3242 } 3243 break; 3244 case 2: 3245 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3246 3247 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3248 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3249 err = -EINVAL; 3250 goto out; 3251 } 3252 3253 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3254 err = parse_sos_bin_descriptor(psp, 3255 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3256 sos_hdr_v2_0); 3257 if (err) 3258 goto out; 3259 } 3260 break; 3261 default: 3262 dev_err(adev->dev, 3263 "unsupported psp sos firmware\n"); 3264 err = -EINVAL; 3265 goto out; 3266 } 3267 3268 return 0; 3269 out: 3270 dev_err(adev->dev, 3271 "failed to init sos firmware\n"); 3272 release_firmware(adev->psp.sos_fw); 3273 adev->psp.sos_fw = NULL; 3274 3275 return err; 3276 } 3277 3278 static int parse_ta_bin_descriptor(struct psp_context *psp, 3279 const struct psp_fw_bin_desc *desc, 3280 const struct ta_firmware_header_v2_0 *ta_hdr) 3281 { 3282 uint8_t *ucode_start_addr = NULL; 3283 3284 if (!psp || !desc || !ta_hdr) 3285 return -EINVAL; 3286 3287 ucode_start_addr = (uint8_t *)ta_hdr + 3288 le32_to_cpu(desc->offset_bytes) + 3289 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3290 3291 switch (desc->fw_type) { 3292 case TA_FW_TYPE_PSP_ASD: 3293 psp->asd.fw_version = le32_to_cpu(desc->fw_version); 3294 psp->asd.feature_version = le32_to_cpu(desc->fw_version); 3295 psp->asd.size_bytes = le32_to_cpu(desc->size_bytes); 3296 psp->asd.start_addr = ucode_start_addr; 3297 break; 3298 case TA_FW_TYPE_PSP_XGMI: 3299 psp->xgmi.feature_version = le32_to_cpu(desc->fw_version); 3300 psp->xgmi.size_bytes = le32_to_cpu(desc->size_bytes); 3301 psp->xgmi.start_addr = ucode_start_addr; 3302 break; 3303 case TA_FW_TYPE_PSP_RAS: 3304 psp->ras.feature_version = le32_to_cpu(desc->fw_version); 3305 psp->ras.size_bytes = le32_to_cpu(desc->size_bytes); 3306 psp->ras.start_addr = ucode_start_addr; 3307 break; 3308 case TA_FW_TYPE_PSP_HDCP: 3309 psp->hdcp.feature_version = le32_to_cpu(desc->fw_version); 3310 psp->hdcp.size_bytes = le32_to_cpu(desc->size_bytes); 3311 psp->hdcp.start_addr = ucode_start_addr; 3312 break; 3313 case TA_FW_TYPE_PSP_DTM: 3314 psp->dtm.feature_version = le32_to_cpu(desc->fw_version); 3315 psp->dtm.size_bytes = le32_to_cpu(desc->size_bytes); 3316 psp->dtm.start_addr = ucode_start_addr; 3317 break; 3318 case TA_FW_TYPE_PSP_RAP: 3319 psp->rap.feature_version = le32_to_cpu(desc->fw_version); 3320 psp->rap.size_bytes = le32_to_cpu(desc->size_bytes); 3321 psp->rap.start_addr = ucode_start_addr; 3322 break; 3323 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3324 psp->securedisplay.feature_version = le32_to_cpu(desc->fw_version); 3325 psp->securedisplay.size_bytes = le32_to_cpu(desc->size_bytes); 3326 psp->securedisplay.start_addr = ucode_start_addr; 3327 break; 3328 default: 3329 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3330 break; 3331 } 3332 3333 return 0; 3334 } 3335 3336 int psp_init_ta_microcode(struct psp_context *psp, 3337 const char *chip_name) 3338 { 3339 struct amdgpu_device *adev = psp->adev; 3340 char fw_name[PSP_FW_NAME_LEN]; 3341 const struct ta_firmware_header_v2_0 *ta_hdr; 3342 int err = 0; 3343 int ta_index = 0; 3344 3345 if (!chip_name) { 3346 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3347 return -EINVAL; 3348 } 3349 3350 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3351 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3352 if (err) 3353 goto out; 3354 3355 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3356 if (err) 3357 goto out; 3358 3359 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3360 3361 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3362 dev_err(adev->dev, "unsupported TA header version\n"); 3363 err = -EINVAL; 3364 goto out; 3365 } 3366 3367 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3368 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3369 err = -EINVAL; 3370 goto out; 3371 } 3372 3373 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3374 err = parse_ta_bin_descriptor(psp, 3375 &ta_hdr->ta_fw_bin[ta_index], 3376 ta_hdr); 3377 if (err) 3378 goto out; 3379 } 3380 3381 return 0; 3382 out: 3383 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3384 release_firmware(adev->psp.ta_fw); 3385 adev->psp.ta_fw = NULL; 3386 return err; 3387 } 3388 3389 static int psp_set_clockgating_state(void *handle, 3390 enum amd_clockgating_state state) 3391 { 3392 return 0; 3393 } 3394 3395 static int psp_set_powergating_state(void *handle, 3396 enum amd_powergating_state state) 3397 { 3398 return 0; 3399 } 3400 3401 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3402 struct device_attribute *attr, 3403 char *buf) 3404 { 3405 STUB(); 3406 return -ENOSYS; 3407 #ifdef notyet 3408 struct drm_device *ddev = dev_get_drvdata(dev); 3409 struct amdgpu_device *adev = drm_to_adev(ddev); 3410 uint32_t fw_ver; 3411 int ret; 3412 3413 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3414 DRM_INFO("PSP block is not ready yet."); 3415 return -EBUSY; 3416 } 3417 3418 mutex_lock(&adev->psp.mutex); 3419 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3420 mutex_unlock(&adev->psp.mutex); 3421 3422 if (ret) { 3423 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3424 return ret; 3425 } 3426 3427 return sysfs_emit(buf, "%x\n", fw_ver); 3428 } 3429 3430 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3431 struct device_attribute *attr, 3432 const char *buf, 3433 size_t count) 3434 { 3435 struct drm_device *ddev = dev_get_drvdata(dev); 3436 struct amdgpu_device *adev = drm_to_adev(ddev); 3437 int ret, idx; 3438 char fw_name[100]; 3439 const struct firmware *usbc_pd_fw; 3440 struct amdgpu_bo *fw_buf_bo = NULL; 3441 uint64_t fw_pri_mc_addr; 3442 void *fw_pri_cpu_addr; 3443 3444 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3445 DRM_INFO("PSP block is not ready yet."); 3446 return -EBUSY; 3447 } 3448 3449 if (!drm_dev_enter(ddev, &idx)) 3450 return -ENODEV; 3451 3452 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3453 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3454 if (ret) 3455 goto fail; 3456 3457 /* LFB address which is aligned to 1MB boundary per PSP request */ 3458 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3459 AMDGPU_GEM_DOMAIN_VRAM, 3460 &fw_buf_bo, 3461 &fw_pri_mc_addr, 3462 &fw_pri_cpu_addr); 3463 if (ret) 3464 goto rel_buf; 3465 3466 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3467 3468 mutex_lock(&adev->psp.mutex); 3469 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3470 mutex_unlock(&adev->psp.mutex); 3471 3472 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3473 3474 rel_buf: 3475 release_firmware(usbc_pd_fw); 3476 fail: 3477 if (ret) { 3478 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3479 count = ret; 3480 } 3481 3482 drm_dev_exit(idx); 3483 return count; 3484 #endif 3485 } 3486 3487 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3488 { 3489 int idx; 3490 3491 if (!drm_dev_enter(&psp->adev->ddev, &idx)) 3492 return; 3493 3494 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3495 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3496 3497 drm_dev_exit(idx); 3498 } 3499 3500 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3501 psp_usbc_pd_fw_sysfs_read, 3502 psp_usbc_pd_fw_sysfs_write); 3503 3504 int is_psp_fw_valid(struct psp_bin_desc bin) 3505 { 3506 return bin.size_bytes; 3507 } 3508 3509 const struct amd_ip_funcs psp_ip_funcs = { 3510 .name = "psp", 3511 .early_init = psp_early_init, 3512 .late_init = NULL, 3513 .sw_init = psp_sw_init, 3514 .sw_fini = psp_sw_fini, 3515 .hw_init = psp_hw_init, 3516 .hw_fini = psp_hw_fini, 3517 .suspend = psp_suspend, 3518 .resume = psp_resume, 3519 .is_idle = NULL, 3520 .check_soft_reset = NULL, 3521 .wait_for_idle = NULL, 3522 .soft_reset = NULL, 3523 .set_clockgating_state = psp_set_clockgating_state, 3524 .set_powergating_state = psp_set_powergating_state, 3525 }; 3526 3527 static int psp_sysfs_init(struct amdgpu_device *adev) 3528 { 3529 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3530 3531 if (ret) 3532 DRM_ERROR("Failed to create USBC PD FW control file!"); 3533 3534 return ret; 3535 } 3536 3537 static void psp_sysfs_fini(struct amdgpu_device *adev) 3538 { 3539 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3540 } 3541 3542 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3543 { 3544 .type = AMD_IP_BLOCK_TYPE_PSP, 3545 .major = 3, 3546 .minor = 1, 3547 .rev = 0, 3548 .funcs = &psp_ip_funcs, 3549 }; 3550 3551 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3552 { 3553 .type = AMD_IP_BLOCK_TYPE_PSP, 3554 .major = 10, 3555 .minor = 0, 3556 .rev = 0, 3557 .funcs = &psp_ip_funcs, 3558 }; 3559 3560 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3561 { 3562 .type = AMD_IP_BLOCK_TYPE_PSP, 3563 .major = 11, 3564 .minor = 0, 3565 .rev = 0, 3566 .funcs = &psp_ip_funcs, 3567 }; 3568 3569 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3570 .type = AMD_IP_BLOCK_TYPE_PSP, 3571 .major = 11, 3572 .minor = 0, 3573 .rev = 8, 3574 .funcs = &psp_ip_funcs, 3575 }; 3576 3577 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3578 { 3579 .type = AMD_IP_BLOCK_TYPE_PSP, 3580 .major = 12, 3581 .minor = 0, 3582 .rev = 0, 3583 .funcs = &psp_ip_funcs, 3584 }; 3585 3586 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3587 .type = AMD_IP_BLOCK_TYPE_PSP, 3588 .major = 13, 3589 .minor = 0, 3590 .rev = 0, 3591 .funcs = &psp_ip_funcs, 3592 }; 3593