1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include <drm/drm_drv.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_ucode.h" 32 #include "amdgpu_xgmi.h" 33 #include "soc15_common.h" 34 #include "psp_v3_1.h" 35 #include "psp_v10_0.h" 36 #include "psp_v11_0.h" 37 #include "psp_v11_0_8.h" 38 #include "psp_v12_0.h" 39 #include "psp_v13_0.h" 40 #include "psp_v13_0_4.h" 41 42 #include "amdgpu_ras.h" 43 #include "amdgpu_securedisplay.h" 44 #include "amdgpu_atomfirmware.h" 45 46 #define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3) 47 48 static int psp_sysfs_init(struct amdgpu_device *adev); 49 static void psp_sysfs_fini(struct amdgpu_device *adev); 50 51 static int psp_load_smu_fw(struct psp_context *psp); 52 static int psp_rap_terminate(struct psp_context *psp); 53 static int psp_securedisplay_terminate(struct psp_context *psp); 54 55 /* 56 * Due to DF Cstate management centralized to PMFW, the firmware 57 * loading sequence will be updated as below: 58 * - Load KDB 59 * - Load SYS_DRV 60 * - Load tOS 61 * - Load PMFW 62 * - Setup TMR 63 * - Load other non-psp fw 64 * - Load ASD 65 * - Load XGMI/RAS/HDCP/DTM TA if any 66 * 67 * This new sequence is required for 68 * - Arcturus and onwards 69 */ 70 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp) 71 { 72 struct amdgpu_device *adev = psp->adev; 73 74 if (amdgpu_sriov_vf(adev)) { 75 psp->pmfw_centralized_cstate_management = false; 76 return; 77 } 78 79 switch (adev->ip_versions[MP0_HWIP][0]) { 80 case IP_VERSION(11, 0, 0): 81 case IP_VERSION(11, 0, 4): 82 case IP_VERSION(11, 0, 5): 83 case IP_VERSION(11, 0, 7): 84 case IP_VERSION(11, 0, 9): 85 case IP_VERSION(11, 0, 11): 86 case IP_VERSION(11, 0, 12): 87 case IP_VERSION(11, 0, 13): 88 case IP_VERSION(13, 0, 0): 89 case IP_VERSION(13, 0, 2): 90 case IP_VERSION(13, 0, 7): 91 psp->pmfw_centralized_cstate_management = true; 92 break; 93 default: 94 psp->pmfw_centralized_cstate_management = false; 95 break; 96 } 97 } 98 99 static int psp_early_init(void *handle) 100 { 101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 102 struct psp_context *psp = &adev->psp; 103 104 switch (adev->ip_versions[MP0_HWIP][0]) { 105 case IP_VERSION(9, 0, 0): 106 psp_v3_1_set_psp_funcs(psp); 107 psp->autoload_supported = false; 108 break; 109 case IP_VERSION(10, 0, 0): 110 case IP_VERSION(10, 0, 1): 111 psp_v10_0_set_psp_funcs(psp); 112 psp->autoload_supported = false; 113 break; 114 case IP_VERSION(11, 0, 2): 115 case IP_VERSION(11, 0, 4): 116 psp_v11_0_set_psp_funcs(psp); 117 psp->autoload_supported = false; 118 break; 119 case IP_VERSION(11, 0, 0): 120 case IP_VERSION(11, 0, 5): 121 case IP_VERSION(11, 0, 9): 122 case IP_VERSION(11, 0, 7): 123 case IP_VERSION(11, 0, 11): 124 case IP_VERSION(11, 5, 0): 125 case IP_VERSION(11, 0, 12): 126 case IP_VERSION(11, 0, 13): 127 psp_v11_0_set_psp_funcs(psp); 128 psp->autoload_supported = true; 129 break; 130 case IP_VERSION(11, 0, 3): 131 case IP_VERSION(12, 0, 1): 132 psp_v12_0_set_psp_funcs(psp); 133 break; 134 case IP_VERSION(13, 0, 2): 135 psp_v13_0_set_psp_funcs(psp); 136 break; 137 case IP_VERSION(13, 0, 1): 138 case IP_VERSION(13, 0, 3): 139 case IP_VERSION(13, 0, 5): 140 case IP_VERSION(13, 0, 8): 141 case IP_VERSION(13, 0, 10): 142 case IP_VERSION(13, 0, 11): 143 psp_v13_0_set_psp_funcs(psp); 144 psp->autoload_supported = true; 145 break; 146 case IP_VERSION(11, 0, 8): 147 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 148 psp_v11_0_8_set_psp_funcs(psp); 149 psp->autoload_supported = false; 150 } 151 break; 152 case IP_VERSION(13, 0, 0): 153 case IP_VERSION(13, 0, 7): 154 psp_v13_0_set_psp_funcs(psp); 155 psp->autoload_supported = true; 156 break; 157 case IP_VERSION(13, 0, 4): 158 psp_v13_0_4_set_psp_funcs(psp); 159 psp->autoload_supported = true; 160 break; 161 default: 162 return -EINVAL; 163 } 164 165 psp->adev = adev; 166 167 psp_check_pmfw_centralized_cstate_management(psp); 168 169 return 0; 170 } 171 172 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx) 173 { 174 amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr, 175 &mem_ctx->shared_buf); 176 mem_ctx->shared_bo = NULL; 177 } 178 179 static void psp_free_shared_bufs(struct psp_context *psp) 180 { 181 void *tmr_buf; 182 void **pptr; 183 184 /* free TMR memory buffer */ 185 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 186 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr); 187 psp->tmr_bo = NULL; 188 189 /* free xgmi shared memory */ 190 psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context); 191 192 /* free ras shared memory */ 193 psp_ta_free_shared_buf(&psp->ras_context.context.mem_context); 194 195 /* free hdcp shared memory */ 196 psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context); 197 198 /* free dtm shared memory */ 199 psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context); 200 201 /* free rap shared memory */ 202 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 203 204 /* free securedisplay shared memory */ 205 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 206 207 208 } 209 210 static void psp_memory_training_fini(struct psp_context *psp) 211 { 212 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 213 214 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT; 215 kfree(ctx->sys_cache); 216 ctx->sys_cache = NULL; 217 } 218 219 static int psp_memory_training_init(struct psp_context *psp) 220 { 221 int ret; 222 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 223 224 if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) { 225 DRM_DEBUG("memory training is not supported!\n"); 226 return 0; 227 } 228 229 ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL); 230 if (ctx->sys_cache == NULL) { 231 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n"); 232 ret = -ENOMEM; 233 goto Err_out; 234 } 235 236 DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n", 237 ctx->train_data_size, 238 ctx->p2c_train_data_offset, 239 ctx->c2p_train_data_offset); 240 ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS; 241 return 0; 242 243 Err_out: 244 psp_memory_training_fini(psp); 245 return ret; 246 } 247 248 /* 249 * Helper funciton to query psp runtime database entry 250 * 251 * @adev: amdgpu_device pointer 252 * @entry_type: the type of psp runtime database entry 253 * @db_entry: runtime database entry pointer 254 * 255 * Return false if runtime database doesn't exit or entry is invalid 256 * or true if the specific database entry is found, and copy to @db_entry 257 */ 258 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, 259 enum psp_runtime_entry_type entry_type, 260 void *db_entry) 261 { 262 uint64_t db_header_pos, db_dir_pos; 263 struct psp_runtime_data_header db_header = {0}; 264 struct psp_runtime_data_directory db_dir = {0}; 265 bool ret = false; 266 int i; 267 268 db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET; 269 db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header); 270 271 /* read runtime db header from vram */ 272 amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header, 273 sizeof(struct psp_runtime_data_header), false); 274 275 if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) { 276 /* runtime db doesn't exist, exit */ 277 dev_info(adev->dev, "PSP runtime database doesn't exist\n"); 278 return false; 279 } 280 281 /* read runtime database entry from vram */ 282 amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir, 283 sizeof(struct psp_runtime_data_directory), false); 284 285 if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) { 286 /* invalid db entry count, exit */ 287 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n"); 288 return false; 289 } 290 291 /* look up for requested entry type */ 292 for (i = 0; i < db_dir.entry_count && !ret; i++) { 293 if (db_dir.entry_list[i].entry_type == entry_type) { 294 switch (entry_type) { 295 case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG: 296 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) { 297 /* invalid db entry size */ 298 dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n"); 299 return false; 300 } 301 /* read runtime database entry */ 302 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 303 (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false); 304 ret = true; 305 break; 306 case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS: 307 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) { 308 /* invalid db entry size */ 309 dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n"); 310 return false; 311 } 312 /* read runtime database entry */ 313 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset, 314 (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false); 315 ret = true; 316 break; 317 default: 318 ret = false; 319 break; 320 } 321 } 322 } 323 324 return ret; 325 } 326 327 static int psp_init_sriov_microcode(struct psp_context *psp) 328 { 329 struct amdgpu_device *adev = psp->adev; 330 int ret = 0; 331 332 switch (adev->ip_versions[MP0_HWIP][0]) { 333 case IP_VERSION(9, 0, 0): 334 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 335 ret = psp_init_cap_microcode(psp, "vega10"); 336 break; 337 case IP_VERSION(11, 0, 9): 338 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 339 ret = psp_init_cap_microcode(psp, "navi12"); 340 break; 341 case IP_VERSION(11, 0, 7): 342 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 343 ret = psp_init_cap_microcode(psp, "sienna_cichlid"); 344 break; 345 case IP_VERSION(13, 0, 2): 346 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 347 ret = psp_init_cap_microcode(psp, "aldebaran"); 348 ret &= psp_init_ta_microcode(psp, "aldebaran"); 349 break; 350 case IP_VERSION(13, 0, 0): 351 adev->virt.autoload_ucode_id = 0; 352 break; 353 case IP_VERSION(13, 0, 10): 354 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA; 355 break; 356 default: 357 ret = -EINVAL; 358 break; 359 } 360 return ret; 361 } 362 363 static int psp_sw_init(void *handle) 364 { 365 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 366 struct psp_context *psp = &adev->psp; 367 int ret; 368 struct psp_runtime_boot_cfg_entry boot_cfg_entry; 369 struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx; 370 struct psp_runtime_scpm_entry scpm_entry; 371 372 psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL); 373 if (!psp->cmd) { 374 DRM_ERROR("Failed to allocate memory to command buffer!\n"); 375 ret = -ENOMEM; 376 } 377 378 if (amdgpu_sriov_vf(adev)) 379 ret = psp_init_sriov_microcode(psp); 380 else 381 ret = psp_init_microcode(psp); 382 if (ret) { 383 DRM_ERROR("Failed to load psp firmware!\n"); 384 return ret; 385 } 386 387 adev->psp.xgmi_context.supports_extended_data = 388 !adev->gmc.xgmi.connected_to_cpu && 389 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); 390 391 memset(&scpm_entry, 0, sizeof(scpm_entry)); 392 if ((psp_get_runtime_db_entry(adev, 393 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS, 394 &scpm_entry)) && 395 (SCPM_DISABLE != scpm_entry.scpm_status)) { 396 adev->scpm_enabled = true; 397 adev->scpm_status = scpm_entry.scpm_status; 398 } else { 399 adev->scpm_enabled = false; 400 adev->scpm_status = SCPM_DISABLE; 401 } 402 403 /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */ 404 405 memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry)); 406 if (psp_get_runtime_db_entry(adev, 407 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG, 408 &boot_cfg_entry)) { 409 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask; 410 if ((psp->boot_cfg_bitmask) & 411 BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) { 412 /* If psp runtime database exists, then 413 * only enable two stage memory training 414 * when TWO_STAGE_DRAM_TRAINING bit is set 415 * in runtime database */ 416 mem_training_ctx->enable_mem_training = true; 417 } 418 419 } else { 420 /* If psp runtime database doesn't exist or 421 * is invalid, force enable two stage memory 422 * training */ 423 mem_training_ctx->enable_mem_training = true; 424 } 425 426 if (mem_training_ctx->enable_mem_training) { 427 ret = psp_memory_training_init(psp); 428 if (ret) { 429 DRM_ERROR("Failed to initialize memory training!\n"); 430 return ret; 431 } 432 433 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT); 434 if (ret) { 435 DRM_ERROR("Failed to process memory training!\n"); 436 return ret; 437 } 438 } 439 440 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 441 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) { 442 ret= psp_sysfs_init(adev); 443 if (ret) { 444 return ret; 445 } 446 } 447 448 ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG, 449 amdgpu_sriov_vf(adev) ? 450 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 451 &psp->fw_pri_bo, 452 &psp->fw_pri_mc_addr, 453 &psp->fw_pri_buf); 454 if (ret) 455 return ret; 456 457 ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE, 458 AMDGPU_GEM_DOMAIN_VRAM, 459 &psp->fence_buf_bo, 460 &psp->fence_buf_mc_addr, 461 &psp->fence_buf); 462 if (ret) 463 goto failed1; 464 465 ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE, 466 AMDGPU_GEM_DOMAIN_VRAM, 467 &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 468 (void **)&psp->cmd_buf_mem); 469 if (ret) 470 goto failed2; 471 472 return 0; 473 474 failed2: 475 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 476 &psp->fence_buf_mc_addr, &psp->fence_buf); 477 failed1: 478 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 479 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 480 return ret; 481 } 482 483 static int psp_sw_fini(void *handle) 484 { 485 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 486 struct psp_context *psp = &adev->psp; 487 struct psp_gfx_cmd_resp *cmd = psp->cmd; 488 489 psp_memory_training_fini(psp); 490 if (psp->sos_fw) { 491 release_firmware(psp->sos_fw); 492 psp->sos_fw = NULL; 493 } 494 if (psp->asd_fw) { 495 release_firmware(psp->asd_fw); 496 psp->asd_fw = NULL; 497 } 498 if (psp->ta_fw) { 499 release_firmware(psp->ta_fw); 500 psp->ta_fw = NULL; 501 } 502 if (psp->cap_fw) { 503 release_firmware(psp->cap_fw); 504 psp->cap_fw = NULL; 505 } 506 if (psp->toc_fw) { 507 release_firmware(psp->toc_fw); 508 psp->toc_fw = NULL; 509 } 510 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) || 511 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) 512 psp_sysfs_fini(adev); 513 514 kfree(cmd); 515 cmd = NULL; 516 517 psp_free_shared_bufs(psp); 518 519 if (psp->km_ring.ring_mem) 520 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 521 &psp->km_ring.ring_mem_mc_addr, 522 (void **)&psp->km_ring.ring_mem); 523 524 amdgpu_bo_free_kernel(&psp->fw_pri_bo, 525 &psp->fw_pri_mc_addr, &psp->fw_pri_buf); 526 amdgpu_bo_free_kernel(&psp->fence_buf_bo, 527 &psp->fence_buf_mc_addr, &psp->fence_buf); 528 amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr, 529 (void **)&psp->cmd_buf_mem); 530 531 return 0; 532 } 533 534 int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 535 uint32_t reg_val, uint32_t mask, bool check_changed) 536 { 537 uint32_t val; 538 int i; 539 struct amdgpu_device *adev = psp->adev; 540 541 if (psp->adev->no_hw_access) 542 return 0; 543 544 for (i = 0; i < adev->usec_timeout; i++) { 545 val = RREG32(reg_index); 546 if (check_changed) { 547 if (val != reg_val) 548 return 0; 549 } else { 550 if ((val & mask) == reg_val) 551 return 0; 552 } 553 udelay(1); 554 } 555 556 return -ETIME; 557 } 558 559 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) 560 { 561 switch (cmd_id) { 562 case GFX_CMD_ID_LOAD_TA: 563 return "LOAD_TA"; 564 case GFX_CMD_ID_UNLOAD_TA: 565 return "UNLOAD_TA"; 566 case GFX_CMD_ID_INVOKE_CMD: 567 return "INVOKE_CMD"; 568 case GFX_CMD_ID_LOAD_ASD: 569 return "LOAD_ASD"; 570 case GFX_CMD_ID_SETUP_TMR: 571 return "SETUP_TMR"; 572 case GFX_CMD_ID_LOAD_IP_FW: 573 return "LOAD_IP_FW"; 574 case GFX_CMD_ID_DESTROY_TMR: 575 return "DESTROY_TMR"; 576 case GFX_CMD_ID_SAVE_RESTORE: 577 return "SAVE_RESTORE_IP_FW"; 578 case GFX_CMD_ID_SETUP_VMR: 579 return "SETUP_VMR"; 580 case GFX_CMD_ID_DESTROY_VMR: 581 return "DESTROY_VMR"; 582 case GFX_CMD_ID_PROG_REG: 583 return "PROG_REG"; 584 case GFX_CMD_ID_GET_FW_ATTESTATION: 585 return "GET_FW_ATTESTATION"; 586 case GFX_CMD_ID_LOAD_TOC: 587 return "ID_LOAD_TOC"; 588 case GFX_CMD_ID_AUTOLOAD_RLC: 589 return "AUTOLOAD_RLC"; 590 case GFX_CMD_ID_BOOT_CFG: 591 return "BOOT_CFG"; 592 default: 593 return "UNKNOWN CMD"; 594 } 595 } 596 597 static int 598 psp_cmd_submit_buf(struct psp_context *psp, 599 struct amdgpu_firmware_info *ucode, 600 struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr) 601 { 602 int ret; 603 int index, idx; 604 int timeout = 20000; 605 bool ras_intr = false; 606 bool skip_unsupport = false; 607 608 if (psp->adev->no_hw_access) 609 return 0; 610 611 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 612 return 0; 613 614 memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE); 615 616 memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp)); 617 618 index = atomic_inc_return(&psp->fence_value); 619 ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index); 620 if (ret) { 621 atomic_dec(&psp->fence_value); 622 goto exit; 623 } 624 625 amdgpu_device_invalidate_hdp(psp->adev, NULL); 626 while (*((unsigned int *)psp->fence_buf) != index) { 627 if (--timeout == 0) 628 break; 629 /* 630 * Shouldn't wait for timeout when err_event_athub occurs, 631 * because gpu reset thread triggered and lock resource should 632 * be released for psp resume sequence. 633 */ 634 ras_intr = amdgpu_ras_intr_triggered(); 635 if (ras_intr) 636 break; 637 usleep_range(10, 100); 638 amdgpu_device_invalidate_hdp(psp->adev, NULL); 639 } 640 641 /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */ 642 skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED || 643 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); 644 645 memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp)); 646 647 /* In some cases, psp response status is not 0 even there is no 648 * problem while the command is submitted. Some version of PSP FW 649 * doesn't write 0 to that field. 650 * So here we would like to only print a warning instead of an error 651 * during psp initialization to avoid breaking hw_init and it doesn't 652 * return -EINVAL. 653 */ 654 if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) { 655 if (ucode) 656 DRM_WARN("failed to load ucode %s(0x%X) ", 657 amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id); 658 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n", 659 psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id, 660 psp->cmd_buf_mem->resp.status); 661 /* If any firmware (including CAP) load fails under SRIOV, it should 662 * return failure to stop the VF from initializing. 663 * Also return failure in case of timeout 664 */ 665 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { 666 ret = -EINVAL; 667 goto exit; 668 } 669 } 670 671 if (ucode) { 672 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo; 673 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi; 674 } 675 676 exit: 677 drm_dev_exit(idx); 678 return ret; 679 } 680 681 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp) 682 { 683 struct psp_gfx_cmd_resp *cmd = psp->cmd; 684 685 mutex_lock(&psp->mutex); 686 687 memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp)); 688 689 return cmd; 690 } 691 692 static void release_psp_cmd_buf(struct psp_context *psp) 693 { 694 mutex_unlock(&psp->mutex); 695 } 696 697 static void psp_prep_tmr_cmd_buf(struct psp_context *psp, 698 struct psp_gfx_cmd_resp *cmd, 699 uint64_t tmr_mc, struct amdgpu_bo *tmr_bo) 700 { 701 struct amdgpu_device *adev = psp->adev; 702 uint32_t size = amdgpu_bo_size(tmr_bo); 703 uint64_t tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo); 704 705 if (amdgpu_sriov_vf(psp->adev)) 706 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR; 707 else 708 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR; 709 cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc); 710 cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc); 711 cmd->cmd.cmd_setup_tmr.buf_size = size; 712 cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1; 713 cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa); 714 cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa); 715 } 716 717 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd, 718 uint64_t pri_buf_mc, uint32_t size) 719 { 720 cmd->cmd_id = GFX_CMD_ID_LOAD_TOC; 721 cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc); 722 cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc); 723 cmd->cmd.cmd_load_toc.toc_size = size; 724 } 725 726 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */ 727 static int psp_load_toc(struct psp_context *psp, 728 uint32_t *tmr_size) 729 { 730 int ret; 731 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 732 733 /* Copy toc to psp firmware private buffer */ 734 psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes); 735 736 psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes); 737 738 ret = psp_cmd_submit_buf(psp, NULL, cmd, 739 psp->fence_buf_mc_addr); 740 if (!ret) 741 *tmr_size = psp->cmd_buf_mem->resp.tmr_size; 742 743 release_psp_cmd_buf(psp); 744 745 return ret; 746 } 747 748 /* Set up Trusted Memory Region */ 749 static int psp_tmr_init(struct psp_context *psp) 750 { 751 int ret = 0; 752 int tmr_size; 753 void *tmr_buf; 754 void **pptr; 755 756 /* 757 * According to HW engineer, they prefer the TMR address be "naturally 758 * aligned" , e.g. the start address be an integer divide of TMR size. 759 * 760 * Note: this memory need be reserved till the driver 761 * uninitializes. 762 */ 763 tmr_size = PSP_TMR_SIZE(psp->adev); 764 765 /* For ASICs support RLC autoload, psp will parse the toc 766 * and calculate the total size of TMR needed */ 767 if (!amdgpu_sriov_vf(psp->adev) && 768 psp->toc.start_addr && 769 psp->toc.size_bytes && 770 psp->fw_pri_buf) { 771 ret = psp_load_toc(psp, &tmr_size); 772 if (ret) { 773 DRM_ERROR("Failed to load toc\n"); 774 return ret; 775 } 776 } 777 778 if (!psp->tmr_bo) { 779 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; 780 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT, 781 AMDGPU_GEM_DOMAIN_VRAM, 782 &psp->tmr_bo, &psp->tmr_mc_addr, pptr); 783 } 784 785 return ret; 786 } 787 788 static bool psp_skip_tmr(struct psp_context *psp) 789 { 790 switch (psp->adev->ip_versions[MP0_HWIP][0]) { 791 case IP_VERSION(11, 0, 9): 792 case IP_VERSION(11, 0, 7): 793 case IP_VERSION(13, 0, 2): 794 case IP_VERSION(13, 0, 10): 795 return true; 796 default: 797 return false; 798 } 799 } 800 801 static int psp_tmr_load(struct psp_context *psp) 802 { 803 int ret; 804 struct psp_gfx_cmd_resp *cmd; 805 806 /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR. 807 * Already set up by host driver. 808 */ 809 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) 810 return 0; 811 812 cmd = acquire_psp_cmd_buf(psp); 813 814 psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo); 815 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n", 816 amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr); 817 818 ret = psp_cmd_submit_buf(psp, NULL, cmd, 819 psp->fence_buf_mc_addr); 820 821 release_psp_cmd_buf(psp); 822 823 return ret; 824 } 825 826 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp, 827 struct psp_gfx_cmd_resp *cmd) 828 { 829 if (amdgpu_sriov_vf(psp->adev)) 830 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR; 831 else 832 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR; 833 } 834 835 static int psp_tmr_unload(struct psp_context *psp) 836 { 837 int ret; 838 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 839 840 psp_prep_tmr_unload_cmd_buf(psp, cmd); 841 dev_info(psp->adev->dev, "free PSP TMR buffer\n"); 842 843 ret = psp_cmd_submit_buf(psp, NULL, cmd, 844 psp->fence_buf_mc_addr); 845 846 release_psp_cmd_buf(psp); 847 848 return ret; 849 } 850 851 static int psp_tmr_terminate(struct psp_context *psp) 852 { 853 return psp_tmr_unload(psp); 854 } 855 856 int psp_get_fw_attestation_records_addr(struct psp_context *psp, 857 uint64_t *output_ptr) 858 { 859 int ret; 860 struct psp_gfx_cmd_resp *cmd; 861 862 if (!output_ptr) 863 return -EINVAL; 864 865 if (amdgpu_sriov_vf(psp->adev)) 866 return 0; 867 868 cmd = acquire_psp_cmd_buf(psp); 869 870 cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION; 871 872 ret = psp_cmd_submit_buf(psp, NULL, cmd, 873 psp->fence_buf_mc_addr); 874 875 if (!ret) { 876 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) + 877 ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32); 878 } 879 880 release_psp_cmd_buf(psp); 881 882 return ret; 883 } 884 885 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg) 886 { 887 struct psp_context *psp = &adev->psp; 888 struct psp_gfx_cmd_resp *cmd; 889 int ret; 890 891 if (amdgpu_sriov_vf(adev)) 892 return 0; 893 894 cmd = acquire_psp_cmd_buf(psp); 895 896 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 897 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET; 898 899 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 900 if (!ret) { 901 *boot_cfg = 902 (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0; 903 } 904 905 release_psp_cmd_buf(psp); 906 907 return ret; 908 } 909 910 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg) 911 { 912 int ret; 913 struct psp_context *psp = &adev->psp; 914 struct psp_gfx_cmd_resp *cmd; 915 916 if (amdgpu_sriov_vf(adev)) 917 return 0; 918 919 cmd = acquire_psp_cmd_buf(psp); 920 921 cmd->cmd_id = GFX_CMD_ID_BOOT_CFG; 922 cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET; 923 cmd->cmd.boot_cfg.boot_config = boot_cfg; 924 cmd->cmd.boot_cfg.boot_config_valid = boot_cfg; 925 926 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 927 928 release_psp_cmd_buf(psp); 929 930 return ret; 931 } 932 933 static int psp_rl_load(struct amdgpu_device *adev) 934 { 935 int ret; 936 struct psp_context *psp = &adev->psp; 937 struct psp_gfx_cmd_resp *cmd; 938 939 if (!is_psp_fw_valid(psp->rl)) 940 return 0; 941 942 cmd = acquire_psp_cmd_buf(psp); 943 944 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 945 memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes); 946 947 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 948 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr); 949 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr); 950 cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes; 951 cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST; 952 953 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 954 955 release_psp_cmd_buf(psp); 956 957 return ret; 958 } 959 960 static int psp_asd_initialize(struct psp_context *psp) 961 { 962 int ret; 963 964 /* If PSP version doesn't match ASD version, asd loading will be failed. 965 * add workaround to bypass it for sriov now. 966 * TODO: add version check to make it common 967 */ 968 if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes) 969 return 0; 970 971 psp->asd_context.mem_context.shared_mc_addr = 0; 972 psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE; 973 psp->asd_context.ta_load_type = GFX_CMD_ID_LOAD_ASD; 974 975 ret = psp_ta_load(psp, &psp->asd_context); 976 if (!ret) 977 psp->asd_context.initialized = true; 978 979 return ret; 980 } 981 982 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd, 983 uint32_t session_id) 984 { 985 cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA; 986 cmd->cmd.cmd_unload_ta.session_id = session_id; 987 } 988 989 int psp_ta_unload(struct psp_context *psp, struct ta_context *context) 990 { 991 int ret; 992 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 993 994 psp_prep_ta_unload_cmd_buf(cmd, context->session_id); 995 996 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 997 998 release_psp_cmd_buf(psp); 999 1000 return ret; 1001 } 1002 1003 static int psp_asd_terminate(struct psp_context *psp) 1004 { 1005 int ret; 1006 1007 if (amdgpu_sriov_vf(psp->adev)) 1008 return 0; 1009 1010 if (!psp->asd_context.initialized) 1011 return 0; 1012 1013 ret = psp_ta_unload(psp, &psp->asd_context); 1014 if (!ret) 1015 psp->asd_context.initialized = false; 1016 1017 return ret; 1018 } 1019 1020 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1021 uint32_t id, uint32_t value) 1022 { 1023 cmd->cmd_id = GFX_CMD_ID_PROG_REG; 1024 cmd->cmd.cmd_setup_reg_prog.reg_value = value; 1025 cmd->cmd.cmd_setup_reg_prog.reg_id = id; 1026 } 1027 1028 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg, 1029 uint32_t value) 1030 { 1031 struct psp_gfx_cmd_resp *cmd; 1032 int ret = 0; 1033 1034 if (reg >= PSP_REG_LAST) 1035 return -EINVAL; 1036 1037 cmd = acquire_psp_cmd_buf(psp); 1038 1039 psp_prep_reg_prog_cmd_buf(cmd, reg, value); 1040 ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); 1041 if (ret) 1042 DRM_ERROR("PSP failed to program reg id %d", reg); 1043 1044 release_psp_cmd_buf(psp); 1045 1046 return ret; 1047 } 1048 1049 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1050 uint64_t ta_bin_mc, 1051 struct ta_context *context) 1052 { 1053 cmd->cmd_id = context->ta_load_type; 1054 cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(ta_bin_mc); 1055 cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(ta_bin_mc); 1056 cmd->cmd.cmd_load_ta.app_len = context->bin_desc.size_bytes; 1057 1058 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 1059 lower_32_bits(context->mem_context.shared_mc_addr); 1060 cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 1061 upper_32_bits(context->mem_context.shared_mc_addr); 1062 cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size; 1063 } 1064 1065 int psp_ta_init_shared_buf(struct psp_context *psp, 1066 struct ta_mem_context *mem_ctx) 1067 { 1068 /* 1069 * Allocate 16k memory aligned to 4k from Frame Buffer (local 1070 * physical) for ta to host memory 1071 */ 1072 return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size, 1073 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, 1074 &mem_ctx->shared_bo, 1075 &mem_ctx->shared_mc_addr, 1076 &mem_ctx->shared_buf); 1077 } 1078 1079 static void psp_prep_ta_invoke_indirect_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1080 uint32_t ta_cmd_id, 1081 struct ta_context *context) 1082 { 1083 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1084 cmd->cmd.cmd_invoke_cmd.session_id = context->session_id; 1085 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1086 1087 cmd->cmd.cmd_invoke_cmd.buf.num_desc = 1; 1088 cmd->cmd.cmd_invoke_cmd.buf.total_size = context->mem_context.shared_mem_size; 1089 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_size = context->mem_context.shared_mem_size; 1090 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_lo = 1091 lower_32_bits(context->mem_context.shared_mc_addr); 1092 cmd->cmd.cmd_invoke_cmd.buf.buf_desc[0].buf_phy_addr_hi = 1093 upper_32_bits(context->mem_context.shared_mc_addr); 1094 } 1095 1096 int psp_ta_invoke_indirect(struct psp_context *psp, 1097 uint32_t ta_cmd_id, 1098 struct ta_context *context) 1099 { 1100 int ret; 1101 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1102 1103 psp_prep_ta_invoke_indirect_cmd_buf(cmd, ta_cmd_id, context); 1104 1105 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1106 psp->fence_buf_mc_addr); 1107 1108 context->resp_status = cmd->resp.status; 1109 1110 release_psp_cmd_buf(psp); 1111 1112 return ret; 1113 } 1114 1115 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd, 1116 uint32_t ta_cmd_id, 1117 uint32_t session_id) 1118 { 1119 cmd->cmd_id = GFX_CMD_ID_INVOKE_CMD; 1120 cmd->cmd.cmd_invoke_cmd.session_id = session_id; 1121 cmd->cmd.cmd_invoke_cmd.ta_cmd_id = ta_cmd_id; 1122 } 1123 1124 int psp_ta_invoke(struct psp_context *psp, 1125 uint32_t ta_cmd_id, 1126 struct ta_context *context) 1127 { 1128 int ret; 1129 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 1130 1131 psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id); 1132 1133 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1134 psp->fence_buf_mc_addr); 1135 1136 context->resp_status = cmd->resp.status; 1137 1138 release_psp_cmd_buf(psp); 1139 1140 return ret; 1141 } 1142 1143 int psp_ta_load(struct psp_context *psp, struct ta_context *context) 1144 { 1145 int ret; 1146 struct psp_gfx_cmd_resp *cmd; 1147 1148 cmd = acquire_psp_cmd_buf(psp); 1149 1150 psp_copy_fw(psp, context->bin_desc.start_addr, 1151 context->bin_desc.size_bytes); 1152 1153 psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context); 1154 1155 ret = psp_cmd_submit_buf(psp, NULL, cmd, 1156 psp->fence_buf_mc_addr); 1157 1158 context->resp_status = cmd->resp.status; 1159 1160 if (!ret) { 1161 context->session_id = cmd->resp.session_id; 1162 } 1163 1164 release_psp_cmd_buf(psp); 1165 1166 return ret; 1167 } 1168 1169 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1170 { 1171 return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context); 1172 } 1173 1174 int psp_xgmi_terminate(struct psp_context *psp) 1175 { 1176 int ret; 1177 struct amdgpu_device *adev = psp->adev; 1178 1179 /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */ 1180 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 1181 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1182 adev->gmc.xgmi.connected_to_cpu)) 1183 return 0; 1184 1185 if (!psp->xgmi_context.context.initialized) 1186 return 0; 1187 1188 ret = psp_ta_unload(psp, &psp->xgmi_context.context); 1189 1190 psp->xgmi_context.context.initialized = false; 1191 1192 return ret; 1193 } 1194 1195 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta) 1196 { 1197 struct ta_xgmi_shared_memory *xgmi_cmd; 1198 int ret; 1199 1200 if (!psp->ta_fw || 1201 !psp->xgmi_context.context.bin_desc.size_bytes || 1202 !psp->xgmi_context.context.bin_desc.start_addr) 1203 return -ENOENT; 1204 1205 if (!load_ta) 1206 goto invoke; 1207 1208 psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE; 1209 psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1210 1211 if (!psp->xgmi_context.context.mem_context.shared_buf) { 1212 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context); 1213 if (ret) 1214 return ret; 1215 } 1216 1217 /* Load XGMI TA */ 1218 ret = psp_ta_load(psp, &psp->xgmi_context.context); 1219 if (!ret) 1220 psp->xgmi_context.context.initialized = true; 1221 else 1222 return ret; 1223 1224 invoke: 1225 /* Initialize XGMI session */ 1226 xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf); 1227 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1228 xgmi_cmd->flag_extend_link_record = set_extended_data; 1229 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE; 1230 1231 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1232 1233 return ret; 1234 } 1235 1236 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id) 1237 { 1238 struct ta_xgmi_shared_memory *xgmi_cmd; 1239 int ret; 1240 1241 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1242 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1243 1244 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID; 1245 1246 /* Invoke xgmi ta to get hive id */ 1247 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1248 if (ret) 1249 return ret; 1250 1251 *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id; 1252 1253 return 0; 1254 } 1255 1256 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id) 1257 { 1258 struct ta_xgmi_shared_memory *xgmi_cmd; 1259 int ret; 1260 1261 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1262 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1263 1264 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID; 1265 1266 /* Invoke xgmi ta to get the node id */ 1267 ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id); 1268 if (ret) 1269 return ret; 1270 1271 *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id; 1272 1273 return 0; 1274 } 1275 1276 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp) 1277 { 1278 return psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && 1279 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b; 1280 } 1281 1282 /* 1283 * Chips that support extended topology information require the driver to 1284 * reflect topology information in the opposite direction. This is 1285 * because the TA has already exceeded its link record limit and if the 1286 * TA holds bi-directional information, the driver would have to do 1287 * multiple fetches instead of just two. 1288 */ 1289 static void psp_xgmi_reflect_topology_info(struct psp_context *psp, 1290 struct psp_xgmi_node_info node_info) 1291 { 1292 struct amdgpu_device *mirror_adev; 1293 struct amdgpu_hive_info *hive; 1294 uint64_t src_node_id = psp->adev->gmc.xgmi.node_id; 1295 uint64_t dst_node_id = node_info.node_id; 1296 uint8_t dst_num_hops = node_info.num_hops; 1297 uint8_t dst_num_links = node_info.num_links; 1298 1299 hive = amdgpu_get_xgmi_hive(psp->adev); 1300 list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) { 1301 struct psp_xgmi_topology_info *mirror_top_info; 1302 int j; 1303 1304 if (mirror_adev->gmc.xgmi.node_id != dst_node_id) 1305 continue; 1306 1307 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info; 1308 for (j = 0; j < mirror_top_info->num_nodes; j++) { 1309 if (mirror_top_info->nodes[j].node_id != src_node_id) 1310 continue; 1311 1312 mirror_top_info->nodes[j].num_hops = dst_num_hops; 1313 /* 1314 * prevent 0 num_links value re-reflection since reflection 1315 * criteria is based on num_hops (direct or indirect). 1316 * 1317 */ 1318 if (dst_num_links) 1319 mirror_top_info->nodes[j].num_links = dst_num_links; 1320 1321 break; 1322 } 1323 1324 break; 1325 } 1326 1327 amdgpu_put_xgmi_hive(hive); 1328 } 1329 1330 int psp_xgmi_get_topology_info(struct psp_context *psp, 1331 int number_devices, 1332 struct psp_xgmi_topology_info *topology, 1333 bool get_extended_data) 1334 { 1335 struct ta_xgmi_shared_memory *xgmi_cmd; 1336 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1337 struct ta_xgmi_cmd_get_topology_info_output *topology_info_output; 1338 int i; 1339 int ret; 1340 1341 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1342 return -EINVAL; 1343 1344 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1345 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1346 xgmi_cmd->flag_extend_link_record = get_extended_data; 1347 1348 /* Fill in the shared memory with topology information as input */ 1349 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1350 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO; 1351 topology_info_input->num_nodes = number_devices; 1352 1353 for (i = 0; i < topology_info_input->num_nodes; i++) { 1354 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1355 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1356 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled; 1357 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1358 } 1359 1360 /* Invoke xgmi ta to get the topology information */ 1361 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO); 1362 if (ret) 1363 return ret; 1364 1365 /* Read the output topology information from the shared memory */ 1366 topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info; 1367 topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes; 1368 for (i = 0; i < topology->num_nodes; i++) { 1369 /* extended data will either be 0 or equal to non-extended data */ 1370 if (topology_info_output->nodes[i].num_hops) 1371 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops; 1372 1373 /* non-extended data gets everything here so no need to update */ 1374 if (!get_extended_data) { 1375 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id; 1376 topology->nodes[i].is_sharing_enabled = 1377 topology_info_output->nodes[i].is_sharing_enabled; 1378 topology->nodes[i].sdma_engine = 1379 topology_info_output->nodes[i].sdma_engine; 1380 } 1381 1382 } 1383 1384 /* Invoke xgmi ta again to get the link information */ 1385 if (psp_xgmi_peer_link_info_supported(psp)) { 1386 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output; 1387 1388 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS; 1389 1390 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS); 1391 1392 if (ret) 1393 return ret; 1394 1395 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info; 1396 for (i = 0; i < topology->num_nodes; i++) { 1397 /* accumulate num_links on extended data */ 1398 topology->nodes[i].num_links = get_extended_data ? 1399 topology->nodes[i].num_links + 1400 link_info_output->nodes[i].num_links : 1401 link_info_output->nodes[i].num_links; 1402 1403 /* reflect the topology information for bi-directionality */ 1404 if (psp->xgmi_context.supports_extended_data && 1405 get_extended_data && topology->nodes[i].num_hops) 1406 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]); 1407 } 1408 } 1409 1410 return 0; 1411 } 1412 1413 int psp_xgmi_set_topology_info(struct psp_context *psp, 1414 int number_devices, 1415 struct psp_xgmi_topology_info *topology) 1416 { 1417 struct ta_xgmi_shared_memory *xgmi_cmd; 1418 struct ta_xgmi_cmd_get_topology_info_input *topology_info_input; 1419 int i; 1420 1421 if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES) 1422 return -EINVAL; 1423 1424 xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf; 1425 memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory)); 1426 1427 topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info; 1428 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO; 1429 topology_info_input->num_nodes = number_devices; 1430 1431 for (i = 0; i < topology_info_input->num_nodes; i++) { 1432 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id; 1433 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops; 1434 topology_info_input->nodes[i].is_sharing_enabled = 1; 1435 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine; 1436 } 1437 1438 /* Invoke xgmi ta to set topology information */ 1439 return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO); 1440 } 1441 1442 // ras begin 1443 static void psp_ras_ta_check_status(struct psp_context *psp) 1444 { 1445 struct ta_ras_shared_memory *ras_cmd = 1446 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1447 1448 switch (ras_cmd->ras_status) { 1449 case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP: 1450 dev_warn(psp->adev->dev, 1451 "RAS WARNING: cmd failed due to unsupported ip\n"); 1452 break; 1453 case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ: 1454 dev_warn(psp->adev->dev, 1455 "RAS WARNING: cmd failed due to unsupported error injection\n"); 1456 break; 1457 case TA_RAS_STATUS__SUCCESS: 1458 break; 1459 case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED: 1460 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR) 1461 dev_warn(psp->adev->dev, 1462 "RAS WARNING: Inject error to critical region is not allowed\n"); 1463 break; 1464 default: 1465 dev_warn(psp->adev->dev, 1466 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status); 1467 break; 1468 } 1469 } 1470 1471 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1472 { 1473 struct ta_ras_shared_memory *ras_cmd; 1474 int ret; 1475 1476 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1477 1478 /* 1479 * TODO: bypass the loading in sriov for now 1480 */ 1481 if (amdgpu_sriov_vf(psp->adev)) 1482 return 0; 1483 1484 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context); 1485 1486 if (amdgpu_ras_intr_triggered()) 1487 return ret; 1488 1489 if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) 1490 { 1491 DRM_WARN("RAS: Unsupported Interface"); 1492 return -EINVAL; 1493 } 1494 1495 if (!ret) { 1496 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) { 1497 dev_warn(psp->adev->dev, "ECC switch disabled\n"); 1498 1499 ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE; 1500 } 1501 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag) 1502 dev_warn(psp->adev->dev, 1503 "RAS internal register access blocked\n"); 1504 1505 psp_ras_ta_check_status(psp); 1506 } 1507 1508 return ret; 1509 } 1510 1511 int psp_ras_enable_features(struct psp_context *psp, 1512 union ta_ras_cmd_input *info, bool enable) 1513 { 1514 struct ta_ras_shared_memory *ras_cmd; 1515 int ret; 1516 1517 if (!psp->ras_context.context.initialized) 1518 return -EINVAL; 1519 1520 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1521 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1522 1523 if (enable) 1524 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES; 1525 else 1526 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES; 1527 1528 ras_cmd->ras_in_message = *info; 1529 1530 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1531 if (ret) 1532 return -EINVAL; 1533 1534 return 0; 1535 } 1536 1537 int psp_ras_terminate(struct psp_context *psp) 1538 { 1539 int ret; 1540 1541 /* 1542 * TODO: bypass the terminate in sriov for now 1543 */ 1544 if (amdgpu_sriov_vf(psp->adev)) 1545 return 0; 1546 1547 if (!psp->ras_context.context.initialized) 1548 return 0; 1549 1550 ret = psp_ta_unload(psp, &psp->ras_context.context); 1551 1552 psp->ras_context.context.initialized = false; 1553 1554 return ret; 1555 } 1556 1557 static int psp_ras_initialize(struct psp_context *psp) 1558 { 1559 int ret; 1560 uint32_t boot_cfg = 0xFF; 1561 struct amdgpu_device *adev = psp->adev; 1562 struct ta_ras_shared_memory *ras_cmd; 1563 1564 /* 1565 * TODO: bypass the initialize in sriov for now 1566 */ 1567 if (amdgpu_sriov_vf(adev)) 1568 return 0; 1569 1570 if (!adev->psp.ras_context.context.bin_desc.size_bytes || 1571 !adev->psp.ras_context.context.bin_desc.start_addr) { 1572 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n"); 1573 return 0; 1574 } 1575 1576 if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) { 1577 /* query GECC enablement status from boot config 1578 * boot_cfg: 1: GECC is enabled or 0: GECC is disabled 1579 */ 1580 ret = psp_boot_config_get(adev, &boot_cfg); 1581 if (ret) 1582 dev_warn(adev->dev, "PSP get boot config failed\n"); 1583 1584 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) { 1585 if (!boot_cfg) { 1586 dev_info(adev->dev, "GECC is disabled\n"); 1587 } else { 1588 /* disable GECC in next boot cycle if ras is 1589 * disabled by module parameter amdgpu_ras_enable 1590 * and/or amdgpu_ras_mask, or boot_config_get call 1591 * is failed 1592 */ 1593 ret = psp_boot_config_set(adev, 0); 1594 if (ret) 1595 dev_warn(adev->dev, "PSP set boot config failed\n"); 1596 else 1597 dev_warn(adev->dev, "GECC will be disabled in next boot cycle " 1598 "if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n"); 1599 } 1600 } else { 1601 if (1 == boot_cfg) { 1602 dev_info(adev->dev, "GECC is enabled\n"); 1603 } else { 1604 /* enable GECC in next boot cycle if it is disabled 1605 * in boot config, or force enable GECC if failed to 1606 * get boot configuration 1607 */ 1608 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC); 1609 if (ret) 1610 dev_warn(adev->dev, "PSP set boot config failed\n"); 1611 else 1612 dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n"); 1613 } 1614 } 1615 } 1616 1617 psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE; 1618 psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1619 1620 if (!psp->ras_context.context.initialized) { 1621 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context); 1622 if (ret) 1623 return ret; 1624 } 1625 1626 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1627 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1628 1629 if (amdgpu_ras_is_poison_mode_supported(adev)) 1630 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1; 1631 if (!adev->gmc.xgmi.connected_to_cpu) 1632 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1; 1633 1634 ret = psp_ta_load(psp, &psp->ras_context.context); 1635 1636 if (!ret && !ras_cmd->ras_status) 1637 psp->ras_context.context.initialized = true; 1638 else { 1639 if (ras_cmd->ras_status) 1640 dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status); 1641 amdgpu_ras_fini(psp->adev); 1642 } 1643 1644 return ret; 1645 } 1646 1647 int psp_ras_trigger_error(struct psp_context *psp, 1648 struct ta_ras_trigger_error_input *info) 1649 { 1650 struct ta_ras_shared_memory *ras_cmd; 1651 int ret; 1652 1653 if (!psp->ras_context.context.initialized) 1654 return -EINVAL; 1655 1656 ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf; 1657 memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory)); 1658 1659 ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR; 1660 ras_cmd->ras_in_message.trigger_error = *info; 1661 1662 ret = psp_ras_invoke(psp, ras_cmd->cmd_id); 1663 if (ret) 1664 return -EINVAL; 1665 1666 /* If err_event_athub occurs error inject was successful, however 1667 return status from TA is no long reliable */ 1668 if (amdgpu_ras_intr_triggered()) 1669 return 0; 1670 1671 if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED) 1672 return -EACCES; 1673 else if (ras_cmd->ras_status) 1674 return -EINVAL; 1675 1676 return 0; 1677 } 1678 // ras end 1679 1680 // HDCP start 1681 static int psp_hdcp_initialize(struct psp_context *psp) 1682 { 1683 int ret; 1684 1685 /* 1686 * TODO: bypass the initialize in sriov for now 1687 */ 1688 if (amdgpu_sriov_vf(psp->adev)) 1689 return 0; 1690 1691 if (!psp->hdcp_context.context.bin_desc.size_bytes || 1692 !psp->hdcp_context.context.bin_desc.start_addr) { 1693 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n"); 1694 return 0; 1695 } 1696 1697 psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE; 1698 psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1699 1700 if (!psp->hdcp_context.context.mem_context.shared_buf) { 1701 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context); 1702 if (ret) 1703 return ret; 1704 } 1705 1706 ret = psp_ta_load(psp, &psp->hdcp_context.context); 1707 if (!ret) { 1708 psp->hdcp_context.context.initialized = true; 1709 rw_init(&psp->hdcp_context.mutex, "pspcp"); 1710 } 1711 1712 return ret; 1713 } 1714 1715 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1716 { 1717 /* 1718 * TODO: bypass the loading in sriov for now 1719 */ 1720 if (amdgpu_sriov_vf(psp->adev)) 1721 return 0; 1722 1723 return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context); 1724 } 1725 1726 static int psp_hdcp_terminate(struct psp_context *psp) 1727 { 1728 int ret; 1729 1730 /* 1731 * TODO: bypass the terminate in sriov for now 1732 */ 1733 if (amdgpu_sriov_vf(psp->adev)) 1734 return 0; 1735 1736 if (!psp->hdcp_context.context.initialized) 1737 return 0; 1738 1739 ret = psp_ta_unload(psp, &psp->hdcp_context.context); 1740 1741 psp->hdcp_context.context.initialized = false; 1742 1743 return ret; 1744 } 1745 // HDCP end 1746 1747 // DTM start 1748 static int psp_dtm_initialize(struct psp_context *psp) 1749 { 1750 int ret; 1751 1752 /* 1753 * TODO: bypass the initialize in sriov for now 1754 */ 1755 if (amdgpu_sriov_vf(psp->adev)) 1756 return 0; 1757 1758 if (!psp->dtm_context.context.bin_desc.size_bytes || 1759 !psp->dtm_context.context.bin_desc.start_addr) { 1760 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n"); 1761 return 0; 1762 } 1763 1764 psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE; 1765 psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1766 1767 if (!psp->dtm_context.context.mem_context.shared_buf) { 1768 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context); 1769 if (ret) 1770 return ret; 1771 } 1772 1773 ret = psp_ta_load(psp, &psp->dtm_context.context); 1774 if (!ret) { 1775 psp->dtm_context.context.initialized = true; 1776 rw_init(&psp->dtm_context.mutex, "pspdtm"); 1777 } 1778 1779 return ret; 1780 } 1781 1782 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 1783 { 1784 /* 1785 * TODO: bypass the loading in sriov for now 1786 */ 1787 if (amdgpu_sriov_vf(psp->adev)) 1788 return 0; 1789 1790 return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context); 1791 } 1792 1793 static int psp_dtm_terminate(struct psp_context *psp) 1794 { 1795 int ret; 1796 1797 /* 1798 * TODO: bypass the terminate in sriov for now 1799 */ 1800 if (amdgpu_sriov_vf(psp->adev)) 1801 return 0; 1802 1803 if (!psp->dtm_context.context.initialized) 1804 return 0; 1805 1806 ret = psp_ta_unload(psp, &psp->dtm_context.context); 1807 1808 psp->dtm_context.context.initialized = false; 1809 1810 return ret; 1811 } 1812 // DTM end 1813 1814 // RAP start 1815 static int psp_rap_initialize(struct psp_context *psp) 1816 { 1817 int ret; 1818 enum ta_rap_status status = TA_RAP_STATUS__SUCCESS; 1819 1820 /* 1821 * TODO: bypass the initialize in sriov for now 1822 */ 1823 if (amdgpu_sriov_vf(psp->adev)) 1824 return 0; 1825 1826 if (!psp->rap_context.context.bin_desc.size_bytes || 1827 !psp->rap_context.context.bin_desc.start_addr) { 1828 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n"); 1829 return 0; 1830 } 1831 1832 psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE; 1833 psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1834 1835 if (!psp->rap_context.context.mem_context.shared_buf) { 1836 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context); 1837 if (ret) 1838 return ret; 1839 } 1840 1841 ret = psp_ta_load(psp, &psp->rap_context.context); 1842 if (!ret) { 1843 psp->rap_context.context.initialized = true; 1844 rw_init(&psp->rap_context.mutex, "psprap"); 1845 } else 1846 return ret; 1847 1848 ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status); 1849 if (ret || status != TA_RAP_STATUS__SUCCESS) { 1850 psp_rap_terminate(psp); 1851 /* free rap shared memory */ 1852 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context); 1853 1854 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n", 1855 ret, status); 1856 1857 return ret; 1858 } 1859 1860 return 0; 1861 } 1862 1863 static int psp_rap_terminate(struct psp_context *psp) 1864 { 1865 int ret; 1866 1867 if (!psp->rap_context.context.initialized) 1868 return 0; 1869 1870 ret = psp_ta_unload(psp, &psp->rap_context.context); 1871 1872 psp->rap_context.context.initialized = false; 1873 1874 return ret; 1875 } 1876 1877 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status) 1878 { 1879 struct ta_rap_shared_memory *rap_cmd; 1880 int ret = 0; 1881 1882 if (!psp->rap_context.context.initialized) 1883 return 0; 1884 1885 if (ta_cmd_id != TA_CMD_RAP__INITIALIZE && 1886 ta_cmd_id != TA_CMD_RAP__VALIDATE_L0) 1887 return -EINVAL; 1888 1889 mutex_lock(&psp->rap_context.mutex); 1890 1891 rap_cmd = (struct ta_rap_shared_memory *) 1892 psp->rap_context.context.mem_context.shared_buf; 1893 memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory)); 1894 1895 rap_cmd->cmd_id = ta_cmd_id; 1896 rap_cmd->validation_method_id = METHOD_A; 1897 1898 ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context); 1899 if (ret) 1900 goto out_unlock; 1901 1902 if (status) 1903 *status = rap_cmd->rap_status; 1904 1905 out_unlock: 1906 mutex_unlock(&psp->rap_context.mutex); 1907 1908 return ret; 1909 } 1910 // RAP end 1911 1912 /* securedisplay start */ 1913 static int psp_securedisplay_initialize(struct psp_context *psp) 1914 { 1915 int ret; 1916 struct securedisplay_cmd *securedisplay_cmd; 1917 1918 /* 1919 * TODO: bypass the initialize in sriov for now 1920 */ 1921 if (amdgpu_sriov_vf(psp->adev)) 1922 return 0; 1923 1924 if (!psp->securedisplay_context.context.bin_desc.size_bytes || 1925 !psp->securedisplay_context.context.bin_desc.start_addr) { 1926 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n"); 1927 return 0; 1928 } 1929 1930 #ifdef __OpenBSD__ 1931 /* 1932 * with 20230117 or later firmware or later on renoir: 1933 * 1934 * [drm] psp gfx command LOAD_TA(0x1) failed and response status is (0x7) 1935 * [drm] psp gfx command INVOKE_CMD(0x3) failed and response status is (0x4) 1936 * psp_securedisplay_parse_resp_status *ERROR* Secure display: Generic Failure 1937 * psp_securedisplay_initialize *ERROR* SECUREDISPLAY: query 1938 * securedisplay TA failed. ret 0x0 1939 */ 1940 return 0; 1941 #endif 1942 1943 psp->securedisplay_context.context.mem_context.shared_mem_size = 1944 PSP_SECUREDISPLAY_SHARED_MEM_SIZE; 1945 psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA; 1946 1947 if (!psp->securedisplay_context.context.initialized) { 1948 ret = psp_ta_init_shared_buf(psp, 1949 &psp->securedisplay_context.context.mem_context); 1950 if (ret) 1951 return ret; 1952 } 1953 1954 ret = psp_ta_load(psp, &psp->securedisplay_context.context); 1955 if (!ret) { 1956 psp->securedisplay_context.context.initialized = true; 1957 rw_init(&psp->securedisplay_context.mutex, "pscm"); 1958 } else 1959 return ret; 1960 1961 psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, 1962 TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1963 1964 ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA); 1965 if (ret) { 1966 psp_securedisplay_terminate(psp); 1967 /* free securedisplay shared memory */ 1968 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context); 1969 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n"); 1970 return -EINVAL; 1971 } 1972 1973 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) { 1974 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); 1975 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n", 1976 securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); 1977 /* don't try again */ 1978 psp->securedisplay_context.context.bin_desc.size_bytes = 0; 1979 } 1980 1981 return 0; 1982 } 1983 1984 static int psp_securedisplay_terminate(struct psp_context *psp) 1985 { 1986 int ret; 1987 1988 /* 1989 * TODO:bypass the terminate in sriov for now 1990 */ 1991 if (amdgpu_sriov_vf(psp->adev)) 1992 return 0; 1993 1994 if (!psp->securedisplay_context.context.initialized) 1995 return 0; 1996 1997 ret = psp_ta_unload(psp, &psp->securedisplay_context.context); 1998 1999 psp->securedisplay_context.context.initialized = false; 2000 2001 return ret; 2002 } 2003 2004 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) 2005 { 2006 int ret; 2007 2008 if (!psp->securedisplay_context.context.initialized) 2009 return -EINVAL; 2010 2011 if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA && 2012 ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC) 2013 return -EINVAL; 2014 2015 mutex_lock(&psp->securedisplay_context.mutex); 2016 2017 ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context); 2018 2019 mutex_unlock(&psp->securedisplay_context.mutex); 2020 2021 return ret; 2022 } 2023 /* SECUREDISPLAY end */ 2024 2025 static int psp_hw_start(struct psp_context *psp) 2026 { 2027 struct amdgpu_device *adev = psp->adev; 2028 int ret; 2029 2030 if (!amdgpu_sriov_vf(adev)) { 2031 if ((is_psp_fw_valid(psp->kdb)) && 2032 (psp->funcs->bootloader_load_kdb != NULL)) { 2033 ret = psp_bootloader_load_kdb(psp); 2034 if (ret) { 2035 DRM_ERROR("PSP load kdb failed!\n"); 2036 return ret; 2037 } 2038 } 2039 2040 if ((is_psp_fw_valid(psp->spl)) && 2041 (psp->funcs->bootloader_load_spl != NULL)) { 2042 ret = psp_bootloader_load_spl(psp); 2043 if (ret) { 2044 DRM_ERROR("PSP load spl failed!\n"); 2045 return ret; 2046 } 2047 } 2048 2049 if ((is_psp_fw_valid(psp->sys)) && 2050 (psp->funcs->bootloader_load_sysdrv != NULL)) { 2051 ret = psp_bootloader_load_sysdrv(psp); 2052 if (ret) { 2053 DRM_ERROR("PSP load sys drv failed!\n"); 2054 return ret; 2055 } 2056 } 2057 2058 if ((is_psp_fw_valid(psp->soc_drv)) && 2059 (psp->funcs->bootloader_load_soc_drv != NULL)) { 2060 ret = psp_bootloader_load_soc_drv(psp); 2061 if (ret) { 2062 DRM_ERROR("PSP load soc drv failed!\n"); 2063 return ret; 2064 } 2065 } 2066 2067 if ((is_psp_fw_valid(psp->intf_drv)) && 2068 (psp->funcs->bootloader_load_intf_drv != NULL)) { 2069 ret = psp_bootloader_load_intf_drv(psp); 2070 if (ret) { 2071 DRM_ERROR("PSP load intf drv failed!\n"); 2072 return ret; 2073 } 2074 } 2075 2076 if ((is_psp_fw_valid(psp->dbg_drv)) && 2077 (psp->funcs->bootloader_load_dbg_drv != NULL)) { 2078 ret = psp_bootloader_load_dbg_drv(psp); 2079 if (ret) { 2080 DRM_ERROR("PSP load dbg drv failed!\n"); 2081 return ret; 2082 } 2083 } 2084 2085 if ((is_psp_fw_valid(psp->ras_drv)) && 2086 (psp->funcs->bootloader_load_ras_drv != NULL)) { 2087 ret = psp_bootloader_load_ras_drv(psp); 2088 if (ret) { 2089 DRM_ERROR("PSP load ras_drv failed!\n"); 2090 return ret; 2091 } 2092 } 2093 2094 if ((is_psp_fw_valid(psp->sos)) && 2095 (psp->funcs->bootloader_load_sos != NULL)) { 2096 ret = psp_bootloader_load_sos(psp); 2097 if (ret) { 2098 DRM_ERROR("PSP load sos failed!\n"); 2099 return ret; 2100 } 2101 } 2102 } 2103 2104 ret = psp_ring_create(psp, PSP_RING_TYPE__KM); 2105 if (ret) { 2106 DRM_ERROR("PSP create ring failed!\n"); 2107 return ret; 2108 } 2109 2110 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) 2111 goto skip_pin_bo; 2112 2113 ret = psp_tmr_init(psp); 2114 if (ret) { 2115 DRM_ERROR("PSP tmr init failed!\n"); 2116 return ret; 2117 } 2118 2119 skip_pin_bo: 2120 /* 2121 * For ASICs with DF Cstate management centralized 2122 * to PMFW, TMR setup should be performed after PMFW 2123 * loaded and before other non-psp firmware loaded. 2124 */ 2125 if (psp->pmfw_centralized_cstate_management) { 2126 ret = psp_load_smu_fw(psp); 2127 if (ret) 2128 return ret; 2129 } 2130 2131 ret = psp_tmr_load(psp); 2132 if (ret) { 2133 DRM_ERROR("PSP load tmr failed!\n"); 2134 return ret; 2135 } 2136 2137 return 0; 2138 } 2139 2140 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, 2141 enum psp_gfx_fw_type *type) 2142 { 2143 switch (ucode->ucode_id) { 2144 case AMDGPU_UCODE_ID_CAP: 2145 *type = GFX_FW_TYPE_CAP; 2146 break; 2147 case AMDGPU_UCODE_ID_SDMA0: 2148 *type = GFX_FW_TYPE_SDMA0; 2149 break; 2150 case AMDGPU_UCODE_ID_SDMA1: 2151 *type = GFX_FW_TYPE_SDMA1; 2152 break; 2153 case AMDGPU_UCODE_ID_SDMA2: 2154 *type = GFX_FW_TYPE_SDMA2; 2155 break; 2156 case AMDGPU_UCODE_ID_SDMA3: 2157 *type = GFX_FW_TYPE_SDMA3; 2158 break; 2159 case AMDGPU_UCODE_ID_SDMA4: 2160 *type = GFX_FW_TYPE_SDMA4; 2161 break; 2162 case AMDGPU_UCODE_ID_SDMA5: 2163 *type = GFX_FW_TYPE_SDMA5; 2164 break; 2165 case AMDGPU_UCODE_ID_SDMA6: 2166 *type = GFX_FW_TYPE_SDMA6; 2167 break; 2168 case AMDGPU_UCODE_ID_SDMA7: 2169 *type = GFX_FW_TYPE_SDMA7; 2170 break; 2171 case AMDGPU_UCODE_ID_CP_MES: 2172 *type = GFX_FW_TYPE_CP_MES; 2173 break; 2174 case AMDGPU_UCODE_ID_CP_MES_DATA: 2175 *type = GFX_FW_TYPE_MES_STACK; 2176 break; 2177 case AMDGPU_UCODE_ID_CP_MES1: 2178 *type = GFX_FW_TYPE_CP_MES_KIQ; 2179 break; 2180 case AMDGPU_UCODE_ID_CP_MES1_DATA: 2181 *type = GFX_FW_TYPE_MES_KIQ_STACK; 2182 break; 2183 case AMDGPU_UCODE_ID_CP_CE: 2184 *type = GFX_FW_TYPE_CP_CE; 2185 break; 2186 case AMDGPU_UCODE_ID_CP_PFP: 2187 *type = GFX_FW_TYPE_CP_PFP; 2188 break; 2189 case AMDGPU_UCODE_ID_CP_ME: 2190 *type = GFX_FW_TYPE_CP_ME; 2191 break; 2192 case AMDGPU_UCODE_ID_CP_MEC1: 2193 *type = GFX_FW_TYPE_CP_MEC; 2194 break; 2195 case AMDGPU_UCODE_ID_CP_MEC1_JT: 2196 *type = GFX_FW_TYPE_CP_MEC_ME1; 2197 break; 2198 case AMDGPU_UCODE_ID_CP_MEC2: 2199 *type = GFX_FW_TYPE_CP_MEC; 2200 break; 2201 case AMDGPU_UCODE_ID_CP_MEC2_JT: 2202 *type = GFX_FW_TYPE_CP_MEC_ME2; 2203 break; 2204 case AMDGPU_UCODE_ID_RLC_P: 2205 *type = GFX_FW_TYPE_RLC_P; 2206 break; 2207 case AMDGPU_UCODE_ID_RLC_V: 2208 *type = GFX_FW_TYPE_RLC_V; 2209 break; 2210 case AMDGPU_UCODE_ID_RLC_G: 2211 *type = GFX_FW_TYPE_RLC_G; 2212 break; 2213 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL: 2214 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL; 2215 break; 2216 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM: 2217 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM; 2218 break; 2219 case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM: 2220 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM; 2221 break; 2222 case AMDGPU_UCODE_ID_RLC_IRAM: 2223 *type = GFX_FW_TYPE_RLC_IRAM; 2224 break; 2225 case AMDGPU_UCODE_ID_RLC_DRAM: 2226 *type = GFX_FW_TYPE_RLC_DRAM_BOOT; 2227 break; 2228 case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS: 2229 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS; 2230 break; 2231 case AMDGPU_UCODE_ID_SE0_TAP_DELAYS: 2232 *type = GFX_FW_TYPE_SE0_TAP_DELAYS; 2233 break; 2234 case AMDGPU_UCODE_ID_SE1_TAP_DELAYS: 2235 *type = GFX_FW_TYPE_SE1_TAP_DELAYS; 2236 break; 2237 case AMDGPU_UCODE_ID_SE2_TAP_DELAYS: 2238 *type = GFX_FW_TYPE_SE2_TAP_DELAYS; 2239 break; 2240 case AMDGPU_UCODE_ID_SE3_TAP_DELAYS: 2241 *type = GFX_FW_TYPE_SE3_TAP_DELAYS; 2242 break; 2243 case AMDGPU_UCODE_ID_SMC: 2244 *type = GFX_FW_TYPE_SMU; 2245 break; 2246 case AMDGPU_UCODE_ID_PPTABLE: 2247 *type = GFX_FW_TYPE_PPTABLE; 2248 break; 2249 case AMDGPU_UCODE_ID_UVD: 2250 *type = GFX_FW_TYPE_UVD; 2251 break; 2252 case AMDGPU_UCODE_ID_UVD1: 2253 *type = GFX_FW_TYPE_UVD1; 2254 break; 2255 case AMDGPU_UCODE_ID_VCE: 2256 *type = GFX_FW_TYPE_VCE; 2257 break; 2258 case AMDGPU_UCODE_ID_VCN: 2259 *type = GFX_FW_TYPE_VCN; 2260 break; 2261 case AMDGPU_UCODE_ID_VCN1: 2262 *type = GFX_FW_TYPE_VCN1; 2263 break; 2264 case AMDGPU_UCODE_ID_DMCU_ERAM: 2265 *type = GFX_FW_TYPE_DMCU_ERAM; 2266 break; 2267 case AMDGPU_UCODE_ID_DMCU_INTV: 2268 *type = GFX_FW_TYPE_DMCU_ISR; 2269 break; 2270 case AMDGPU_UCODE_ID_VCN0_RAM: 2271 *type = GFX_FW_TYPE_VCN0_RAM; 2272 break; 2273 case AMDGPU_UCODE_ID_VCN1_RAM: 2274 *type = GFX_FW_TYPE_VCN1_RAM; 2275 break; 2276 case AMDGPU_UCODE_ID_DMCUB: 2277 *type = GFX_FW_TYPE_DMUB; 2278 break; 2279 case AMDGPU_UCODE_ID_SDMA_UCODE_TH0: 2280 *type = GFX_FW_TYPE_SDMA_UCODE_TH0; 2281 break; 2282 case AMDGPU_UCODE_ID_SDMA_UCODE_TH1: 2283 *type = GFX_FW_TYPE_SDMA_UCODE_TH1; 2284 break; 2285 case AMDGPU_UCODE_ID_IMU_I: 2286 *type = GFX_FW_TYPE_IMU_I; 2287 break; 2288 case AMDGPU_UCODE_ID_IMU_D: 2289 *type = GFX_FW_TYPE_IMU_D; 2290 break; 2291 case AMDGPU_UCODE_ID_CP_RS64_PFP: 2292 *type = GFX_FW_TYPE_RS64_PFP; 2293 break; 2294 case AMDGPU_UCODE_ID_CP_RS64_ME: 2295 *type = GFX_FW_TYPE_RS64_ME; 2296 break; 2297 case AMDGPU_UCODE_ID_CP_RS64_MEC: 2298 *type = GFX_FW_TYPE_RS64_MEC; 2299 break; 2300 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 2301 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK; 2302 break; 2303 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 2304 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK; 2305 break; 2306 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 2307 *type = GFX_FW_TYPE_RS64_ME_P0_STACK; 2308 break; 2309 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 2310 *type = GFX_FW_TYPE_RS64_ME_P1_STACK; 2311 break; 2312 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 2313 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK; 2314 break; 2315 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 2316 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK; 2317 break; 2318 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 2319 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK; 2320 break; 2321 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 2322 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK; 2323 break; 2324 case AMDGPU_UCODE_ID_MAXIMUM: 2325 default: 2326 return -EINVAL; 2327 } 2328 2329 return 0; 2330 } 2331 2332 static void psp_print_fw_hdr(struct psp_context *psp, 2333 struct amdgpu_firmware_info *ucode) 2334 { 2335 struct amdgpu_device *adev = psp->adev; 2336 struct common_firmware_header *hdr; 2337 2338 switch (ucode->ucode_id) { 2339 case AMDGPU_UCODE_ID_SDMA0: 2340 case AMDGPU_UCODE_ID_SDMA1: 2341 case AMDGPU_UCODE_ID_SDMA2: 2342 case AMDGPU_UCODE_ID_SDMA3: 2343 case AMDGPU_UCODE_ID_SDMA4: 2344 case AMDGPU_UCODE_ID_SDMA5: 2345 case AMDGPU_UCODE_ID_SDMA6: 2346 case AMDGPU_UCODE_ID_SDMA7: 2347 hdr = (struct common_firmware_header *) 2348 adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data; 2349 amdgpu_ucode_print_sdma_hdr(hdr); 2350 break; 2351 case AMDGPU_UCODE_ID_CP_CE: 2352 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data; 2353 amdgpu_ucode_print_gfx_hdr(hdr); 2354 break; 2355 case AMDGPU_UCODE_ID_CP_PFP: 2356 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data; 2357 amdgpu_ucode_print_gfx_hdr(hdr); 2358 break; 2359 case AMDGPU_UCODE_ID_CP_ME: 2360 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data; 2361 amdgpu_ucode_print_gfx_hdr(hdr); 2362 break; 2363 case AMDGPU_UCODE_ID_CP_MEC1: 2364 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data; 2365 amdgpu_ucode_print_gfx_hdr(hdr); 2366 break; 2367 case AMDGPU_UCODE_ID_RLC_G: 2368 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data; 2369 amdgpu_ucode_print_rlc_hdr(hdr); 2370 break; 2371 case AMDGPU_UCODE_ID_SMC: 2372 hdr = (struct common_firmware_header *)adev->pm.fw->data; 2373 amdgpu_ucode_print_smc_hdr(hdr); 2374 break; 2375 default: 2376 break; 2377 } 2378 } 2379 2380 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode, 2381 struct psp_gfx_cmd_resp *cmd) 2382 { 2383 int ret; 2384 uint64_t fw_mem_mc_addr = ucode->mc_addr; 2385 2386 cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW; 2387 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr); 2388 cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr); 2389 cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size; 2390 2391 ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type); 2392 if (ret) 2393 DRM_ERROR("Unknown firmware type\n"); 2394 2395 return ret; 2396 } 2397 2398 static int psp_execute_non_psp_fw_load(struct psp_context *psp, 2399 struct amdgpu_firmware_info *ucode) 2400 { 2401 int ret = 0; 2402 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2403 2404 ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd); 2405 if (!ret) { 2406 ret = psp_cmd_submit_buf(psp, ucode, cmd, 2407 psp->fence_buf_mc_addr); 2408 } 2409 2410 release_psp_cmd_buf(psp); 2411 2412 return ret; 2413 } 2414 2415 static int psp_load_smu_fw(struct psp_context *psp) 2416 { 2417 int ret; 2418 struct amdgpu_device *adev = psp->adev; 2419 struct amdgpu_firmware_info *ucode = 2420 &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; 2421 struct amdgpu_ras *ras = psp->ras_context.ras; 2422 2423 /* 2424 * Skip SMU FW reloading in case of using BACO for runpm only, 2425 * as SMU is always alive. 2426 */ 2427 if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO)) 2428 return 0; 2429 2430 if (!ucode->fw || amdgpu_sriov_vf(psp->adev)) 2431 return 0; 2432 2433 if ((amdgpu_in_reset(adev) && 2434 ras && adev->ras_enabled && 2435 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || 2436 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) { 2437 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD); 2438 if (ret) { 2439 DRM_WARN("Failed to set MP1 state prepare for reload\n"); 2440 } 2441 } 2442 2443 ret = psp_execute_non_psp_fw_load(psp, ucode); 2444 2445 if (ret) 2446 DRM_ERROR("PSP load smu failed!\n"); 2447 2448 return ret; 2449 } 2450 2451 static bool fw_load_skip_check(struct psp_context *psp, 2452 struct amdgpu_firmware_info *ucode) 2453 { 2454 if (!ucode->fw || !ucode->ucode_size) 2455 return true; 2456 2457 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2458 (psp_smu_reload_quirk(psp) || 2459 psp->autoload_supported || 2460 psp->pmfw_centralized_cstate_management)) 2461 return true; 2462 2463 if (amdgpu_sriov_vf(psp->adev) && 2464 amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id)) 2465 return true; 2466 2467 if (psp->autoload_supported && 2468 (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 2469 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)) 2470 /* skip mec JT when autoload is enabled */ 2471 return true; 2472 2473 return false; 2474 } 2475 2476 int psp_load_fw_list(struct psp_context *psp, 2477 struct amdgpu_firmware_info **ucode_list, int ucode_count) 2478 { 2479 int ret = 0, i; 2480 struct amdgpu_firmware_info *ucode; 2481 2482 for (i = 0; i < ucode_count; ++i) { 2483 ucode = ucode_list[i]; 2484 psp_print_fw_hdr(psp, ucode); 2485 ret = psp_execute_non_psp_fw_load(psp, ucode); 2486 if (ret) 2487 return ret; 2488 } 2489 return ret; 2490 } 2491 2492 static int psp_load_non_psp_fw(struct psp_context *psp) 2493 { 2494 int i, ret; 2495 struct amdgpu_firmware_info *ucode; 2496 struct amdgpu_device *adev = psp->adev; 2497 2498 if (psp->autoload_supported && 2499 !psp->pmfw_centralized_cstate_management) { 2500 ret = psp_load_smu_fw(psp); 2501 if (ret) 2502 return ret; 2503 } 2504 2505 for (i = 0; i < adev->firmware.max_ucodes; i++) { 2506 ucode = &adev->firmware.ucode[i]; 2507 2508 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC && 2509 !fw_load_skip_check(psp, ucode)) { 2510 ret = psp_load_smu_fw(psp); 2511 if (ret) 2512 return ret; 2513 continue; 2514 } 2515 2516 if (fw_load_skip_check(psp, ucode)) 2517 continue; 2518 2519 if (psp->autoload_supported && 2520 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) || 2521 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) || 2522 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) && 2523 (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 || 2524 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 || 2525 ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3)) 2526 /* PSP only receive one SDMA fw for sienna_cichlid, 2527 * as all four sdma fw are same */ 2528 continue; 2529 2530 psp_print_fw_hdr(psp, ucode); 2531 2532 ret = psp_execute_non_psp_fw_load(psp, ucode); 2533 if (ret) 2534 return ret; 2535 2536 /* Start rlc autoload after psp recieved all the gfx firmware */ 2537 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? 2538 adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { 2539 ret = psp_rlc_autoload_start(psp); 2540 if (ret) { 2541 DRM_ERROR("Failed to start rlc autoload\n"); 2542 return ret; 2543 } 2544 } 2545 } 2546 2547 return 0; 2548 } 2549 2550 static int psp_load_fw(struct amdgpu_device *adev) 2551 { 2552 int ret; 2553 struct psp_context *psp = &adev->psp; 2554 2555 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2556 /* should not destroy ring, only stop */ 2557 psp_ring_stop(psp, PSP_RING_TYPE__KM); 2558 } else { 2559 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE); 2560 2561 ret = psp_ring_init(psp, PSP_RING_TYPE__KM); 2562 if (ret) { 2563 DRM_ERROR("PSP ring init failed!\n"); 2564 goto failed; 2565 } 2566 } 2567 2568 ret = psp_hw_start(psp); 2569 if (ret) 2570 goto failed; 2571 2572 ret = psp_load_non_psp_fw(psp); 2573 if (ret) 2574 goto failed1; 2575 2576 ret = psp_asd_initialize(psp); 2577 if (ret) { 2578 DRM_ERROR("PSP load asd failed!\n"); 2579 goto failed1; 2580 } 2581 2582 ret = psp_rl_load(adev); 2583 if (ret) { 2584 DRM_ERROR("PSP load RL failed!\n"); 2585 goto failed1; 2586 } 2587 2588 if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) { 2589 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2590 ret = psp_xgmi_initialize(psp, false, true); 2591 /* Warning the XGMI seesion initialize failure 2592 * Instead of stop driver initialization 2593 */ 2594 if (ret) 2595 dev_err(psp->adev->dev, 2596 "XGMI: Failed to initialize XGMI session\n"); 2597 } 2598 } 2599 2600 if (psp->ta_fw) { 2601 ret = psp_ras_initialize(psp); 2602 if (ret) 2603 dev_err(psp->adev->dev, 2604 "RAS: Failed to initialize RAS\n"); 2605 2606 ret = psp_hdcp_initialize(psp); 2607 if (ret) 2608 dev_err(psp->adev->dev, 2609 "HDCP: Failed to initialize HDCP\n"); 2610 2611 ret = psp_dtm_initialize(psp); 2612 if (ret) 2613 dev_err(psp->adev->dev, 2614 "DTM: Failed to initialize DTM\n"); 2615 2616 ret = psp_rap_initialize(psp); 2617 if (ret) 2618 dev_err(psp->adev->dev, 2619 "RAP: Failed to initialize RAP\n"); 2620 2621 ret = psp_securedisplay_initialize(psp); 2622 if (ret) 2623 dev_err(psp->adev->dev, 2624 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2625 } 2626 2627 return 0; 2628 2629 failed1: 2630 psp_free_shared_bufs(psp); 2631 failed: 2632 /* 2633 * all cleanup jobs (xgmi terminate, ras terminate, 2634 * ring destroy, cmd/fence/fw buffers destory, 2635 * psp->cmd destory) are delayed to psp_hw_fini 2636 */ 2637 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2638 return ret; 2639 } 2640 2641 static int psp_hw_init(void *handle) 2642 { 2643 int ret; 2644 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2645 2646 mutex_lock(&adev->firmware.mutex); 2647 /* 2648 * This sequence is just used on hw_init only once, no need on 2649 * resume. 2650 */ 2651 ret = amdgpu_ucode_init_bo(adev); 2652 if (ret) 2653 goto failed; 2654 2655 ret = psp_load_fw(adev); 2656 if (ret) { 2657 DRM_ERROR("PSP firmware loading failed\n"); 2658 goto failed; 2659 } 2660 2661 mutex_unlock(&adev->firmware.mutex); 2662 return 0; 2663 2664 failed: 2665 adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT; 2666 mutex_unlock(&adev->firmware.mutex); 2667 return -EINVAL; 2668 } 2669 2670 static int psp_hw_fini(void *handle) 2671 { 2672 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2673 struct psp_context *psp = &adev->psp; 2674 2675 if (psp->ta_fw) { 2676 psp_ras_terminate(psp); 2677 psp_securedisplay_terminate(psp); 2678 psp_rap_terminate(psp); 2679 psp_dtm_terminate(psp); 2680 psp_hdcp_terminate(psp); 2681 2682 if (adev->gmc.xgmi.num_physical_nodes > 1) 2683 psp_xgmi_terminate(psp); 2684 } 2685 2686 psp_asd_terminate(psp); 2687 psp_tmr_terminate(psp); 2688 2689 psp_ring_destroy(psp, PSP_RING_TYPE__KM); 2690 2691 return 0; 2692 } 2693 2694 static int psp_suspend(void *handle) 2695 { 2696 int ret = 0; 2697 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2698 struct psp_context *psp = &adev->psp; 2699 2700 if (adev->gmc.xgmi.num_physical_nodes > 1 && 2701 psp->xgmi_context.context.initialized) { 2702 ret = psp_xgmi_terminate(psp); 2703 if (ret) { 2704 DRM_ERROR("Failed to terminate xgmi ta\n"); 2705 goto out; 2706 } 2707 } 2708 2709 if (psp->ta_fw) { 2710 ret = psp_ras_terminate(psp); 2711 if (ret) { 2712 DRM_ERROR("Failed to terminate ras ta\n"); 2713 goto out; 2714 } 2715 ret = psp_hdcp_terminate(psp); 2716 if (ret) { 2717 DRM_ERROR("Failed to terminate hdcp ta\n"); 2718 goto out; 2719 } 2720 ret = psp_dtm_terminate(psp); 2721 if (ret) { 2722 DRM_ERROR("Failed to terminate dtm ta\n"); 2723 goto out; 2724 } 2725 ret = psp_rap_terminate(psp); 2726 if (ret) { 2727 DRM_ERROR("Failed to terminate rap ta\n"); 2728 goto out; 2729 } 2730 ret = psp_securedisplay_terminate(psp); 2731 if (ret) { 2732 DRM_ERROR("Failed to terminate securedisplay ta\n"); 2733 goto out; 2734 } 2735 } 2736 2737 ret = psp_asd_terminate(psp); 2738 if (ret) { 2739 DRM_ERROR("Failed to terminate asd\n"); 2740 goto out; 2741 } 2742 2743 ret = psp_tmr_terminate(psp); 2744 if (ret) { 2745 DRM_ERROR("Failed to terminate tmr\n"); 2746 goto out; 2747 } 2748 2749 ret = psp_ring_stop(psp, PSP_RING_TYPE__KM); 2750 if (ret) { 2751 DRM_ERROR("PSP ring stop failed\n"); 2752 } 2753 2754 out: 2755 return ret; 2756 } 2757 2758 static int psp_resume(void *handle) 2759 { 2760 int ret; 2761 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2762 struct psp_context *psp = &adev->psp; 2763 2764 DRM_INFO("PSP is resuming...\n"); 2765 2766 if (psp->mem_train_ctx.enable_mem_training) { 2767 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME); 2768 if (ret) { 2769 DRM_ERROR("Failed to process memory training!\n"); 2770 return ret; 2771 } 2772 } 2773 2774 mutex_lock(&adev->firmware.mutex); 2775 2776 ret = psp_hw_start(psp); 2777 if (ret) 2778 goto failed; 2779 2780 ret = psp_load_non_psp_fw(psp); 2781 if (ret) 2782 goto failed; 2783 2784 ret = psp_asd_initialize(psp); 2785 if (ret) { 2786 DRM_ERROR("PSP load asd failed!\n"); 2787 goto failed; 2788 } 2789 2790 ret = psp_rl_load(adev); 2791 if (ret) { 2792 dev_err(adev->dev, "PSP load RL failed!\n"); 2793 goto failed; 2794 } 2795 2796 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2797 ret = psp_xgmi_initialize(psp, false, true); 2798 /* Warning the XGMI seesion initialize failure 2799 * Instead of stop driver initialization 2800 */ 2801 if (ret) 2802 dev_err(psp->adev->dev, 2803 "XGMI: Failed to initialize XGMI session\n"); 2804 } 2805 2806 if (psp->ta_fw) { 2807 ret = psp_ras_initialize(psp); 2808 if (ret) 2809 dev_err(psp->adev->dev, 2810 "RAS: Failed to initialize RAS\n"); 2811 2812 ret = psp_hdcp_initialize(psp); 2813 if (ret) 2814 dev_err(psp->adev->dev, 2815 "HDCP: Failed to initialize HDCP\n"); 2816 2817 ret = psp_dtm_initialize(psp); 2818 if (ret) 2819 dev_err(psp->adev->dev, 2820 "DTM: Failed to initialize DTM\n"); 2821 2822 ret = psp_rap_initialize(psp); 2823 if (ret) 2824 dev_err(psp->adev->dev, 2825 "RAP: Failed to initialize RAP\n"); 2826 2827 ret = psp_securedisplay_initialize(psp); 2828 if (ret) 2829 dev_err(psp->adev->dev, 2830 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n"); 2831 } 2832 2833 mutex_unlock(&adev->firmware.mutex); 2834 2835 return 0; 2836 2837 failed: 2838 DRM_ERROR("PSP resume failed\n"); 2839 mutex_unlock(&adev->firmware.mutex); 2840 return ret; 2841 } 2842 2843 int psp_gpu_reset(struct amdgpu_device *adev) 2844 { 2845 int ret; 2846 2847 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 2848 return 0; 2849 2850 mutex_lock(&adev->psp.mutex); 2851 ret = psp_mode1_reset(&adev->psp); 2852 mutex_unlock(&adev->psp.mutex); 2853 2854 return ret; 2855 } 2856 2857 int psp_rlc_autoload_start(struct psp_context *psp) 2858 { 2859 int ret; 2860 struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); 2861 2862 cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC; 2863 2864 ret = psp_cmd_submit_buf(psp, NULL, cmd, 2865 psp->fence_buf_mc_addr); 2866 2867 release_psp_cmd_buf(psp); 2868 2869 return ret; 2870 } 2871 2872 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx, 2873 uint64_t cmd_gpu_addr, int cmd_size) 2874 { 2875 struct amdgpu_firmware_info ucode = {0}; 2876 2877 ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : 2878 AMDGPU_UCODE_ID_VCN0_RAM; 2879 ucode.mc_addr = cmd_gpu_addr; 2880 ucode.ucode_size = cmd_size; 2881 2882 return psp_execute_non_psp_fw_load(&adev->psp, &ucode); 2883 } 2884 2885 int psp_ring_cmd_submit(struct psp_context *psp, 2886 uint64_t cmd_buf_mc_addr, 2887 uint64_t fence_mc_addr, 2888 int index) 2889 { 2890 unsigned int psp_write_ptr_reg = 0; 2891 struct psp_gfx_rb_frame *write_frame; 2892 struct psp_ring *ring = &psp->km_ring; 2893 struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem; 2894 struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start + 2895 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1; 2896 struct amdgpu_device *adev = psp->adev; 2897 uint32_t ring_size_dw = ring->ring_size / 4; 2898 uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4; 2899 2900 /* KM (GPCOM) prepare write pointer */ 2901 psp_write_ptr_reg = psp_ring_get_wptr(psp); 2902 2903 /* Update KM RB frame pointer to new frame */ 2904 /* write_frame ptr increments by size of rb_frame in bytes */ 2905 /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */ 2906 if ((psp_write_ptr_reg % ring_size_dw) == 0) 2907 write_frame = ring_buffer_start; 2908 else 2909 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw); 2910 /* Check invalid write_frame ptr address */ 2911 if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) { 2912 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n", 2913 ring_buffer_start, ring_buffer_end, write_frame); 2914 DRM_ERROR("write_frame is pointing to address out of bounds\n"); 2915 return -EINVAL; 2916 } 2917 2918 /* Initialize KM RB frame */ 2919 memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame)); 2920 2921 /* Update KM RB frame */ 2922 write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr); 2923 write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr); 2924 write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr); 2925 write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr); 2926 write_frame->fence_value = index; 2927 amdgpu_device_flush_hdp(adev, NULL); 2928 2929 /* Update the write Pointer in DWORDs */ 2930 psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw; 2931 psp_ring_set_wptr(psp, psp_write_ptr_reg); 2932 return 0; 2933 } 2934 2935 int psp_init_asd_microcode(struct psp_context *psp, 2936 const char *chip_name) 2937 { 2938 struct amdgpu_device *adev = psp->adev; 2939 char fw_name[PSP_FW_NAME_LEN]; 2940 const struct psp_firmware_header_v1_0 *asd_hdr; 2941 int err = 0; 2942 2943 if (!chip_name) { 2944 dev_err(adev->dev, "invalid chip name for asd microcode\n"); 2945 return -EINVAL; 2946 } 2947 2948 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name); 2949 err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev); 2950 if (err) 2951 goto out; 2952 2953 err = amdgpu_ucode_validate(adev->psp.asd_fw); 2954 if (err) 2955 goto out; 2956 2957 asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data; 2958 adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version); 2959 adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version); 2960 adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes); 2961 adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr + 2962 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes); 2963 return 0; 2964 out: 2965 dev_err(adev->dev, "fail to initialize asd microcode\n"); 2966 release_firmware(adev->psp.asd_fw); 2967 adev->psp.asd_fw = NULL; 2968 return err; 2969 } 2970 2971 int psp_init_toc_microcode(struct psp_context *psp, 2972 const char *chip_name) 2973 { 2974 struct amdgpu_device *adev = psp->adev; 2975 char fw_name[PSP_FW_NAME_LEN]; 2976 const struct psp_firmware_header_v1_0 *toc_hdr; 2977 int err = 0; 2978 2979 if (!chip_name) { 2980 dev_err(adev->dev, "invalid chip name for toc microcode\n"); 2981 return -EINVAL; 2982 } 2983 2984 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name); 2985 err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev); 2986 if (err) 2987 goto out; 2988 2989 err = amdgpu_ucode_validate(adev->psp.toc_fw); 2990 if (err) 2991 goto out; 2992 2993 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 2994 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 2995 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 2996 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 2997 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 2998 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 2999 return 0; 3000 out: 3001 dev_err(adev->dev, "fail to request/validate toc microcode\n"); 3002 release_firmware(adev->psp.toc_fw); 3003 adev->psp.toc_fw = NULL; 3004 return err; 3005 } 3006 3007 static int parse_sos_bin_descriptor(struct psp_context *psp, 3008 const struct psp_fw_bin_desc *desc, 3009 const struct psp_firmware_header_v2_0 *sos_hdr) 3010 { 3011 uint8_t *ucode_start_addr = NULL; 3012 3013 if (!psp || !desc || !sos_hdr) 3014 return -EINVAL; 3015 3016 ucode_start_addr = (uint8_t *)sos_hdr + 3017 le32_to_cpu(desc->offset_bytes) + 3018 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3019 3020 switch (desc->fw_type) { 3021 case PSP_FW_TYPE_PSP_SOS: 3022 psp->sos.fw_version = le32_to_cpu(desc->fw_version); 3023 psp->sos.feature_version = le32_to_cpu(desc->fw_version); 3024 psp->sos.size_bytes = le32_to_cpu(desc->size_bytes); 3025 psp->sos.start_addr = ucode_start_addr; 3026 break; 3027 case PSP_FW_TYPE_PSP_SYS_DRV: 3028 psp->sys.fw_version = le32_to_cpu(desc->fw_version); 3029 psp->sys.feature_version = le32_to_cpu(desc->fw_version); 3030 psp->sys.size_bytes = le32_to_cpu(desc->size_bytes); 3031 psp->sys.start_addr = ucode_start_addr; 3032 break; 3033 case PSP_FW_TYPE_PSP_KDB: 3034 psp->kdb.fw_version = le32_to_cpu(desc->fw_version); 3035 psp->kdb.feature_version = le32_to_cpu(desc->fw_version); 3036 psp->kdb.size_bytes = le32_to_cpu(desc->size_bytes); 3037 psp->kdb.start_addr = ucode_start_addr; 3038 break; 3039 case PSP_FW_TYPE_PSP_TOC: 3040 psp->toc.fw_version = le32_to_cpu(desc->fw_version); 3041 psp->toc.feature_version = le32_to_cpu(desc->fw_version); 3042 psp->toc.size_bytes = le32_to_cpu(desc->size_bytes); 3043 psp->toc.start_addr = ucode_start_addr; 3044 break; 3045 case PSP_FW_TYPE_PSP_SPL: 3046 psp->spl.fw_version = le32_to_cpu(desc->fw_version); 3047 psp->spl.feature_version = le32_to_cpu(desc->fw_version); 3048 psp->spl.size_bytes = le32_to_cpu(desc->size_bytes); 3049 psp->spl.start_addr = ucode_start_addr; 3050 break; 3051 case PSP_FW_TYPE_PSP_RL: 3052 psp->rl.fw_version = le32_to_cpu(desc->fw_version); 3053 psp->rl.feature_version = le32_to_cpu(desc->fw_version); 3054 psp->rl.size_bytes = le32_to_cpu(desc->size_bytes); 3055 psp->rl.start_addr = ucode_start_addr; 3056 break; 3057 case PSP_FW_TYPE_PSP_SOC_DRV: 3058 psp->soc_drv.fw_version = le32_to_cpu(desc->fw_version); 3059 psp->soc_drv.feature_version = le32_to_cpu(desc->fw_version); 3060 psp->soc_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3061 psp->soc_drv.start_addr = ucode_start_addr; 3062 break; 3063 case PSP_FW_TYPE_PSP_INTF_DRV: 3064 psp->intf_drv.fw_version = le32_to_cpu(desc->fw_version); 3065 psp->intf_drv.feature_version = le32_to_cpu(desc->fw_version); 3066 psp->intf_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3067 psp->intf_drv.start_addr = ucode_start_addr; 3068 break; 3069 case PSP_FW_TYPE_PSP_DBG_DRV: 3070 psp->dbg_drv.fw_version = le32_to_cpu(desc->fw_version); 3071 psp->dbg_drv.feature_version = le32_to_cpu(desc->fw_version); 3072 psp->dbg_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3073 psp->dbg_drv.start_addr = ucode_start_addr; 3074 break; 3075 case PSP_FW_TYPE_PSP_RAS_DRV: 3076 psp->ras_drv.fw_version = le32_to_cpu(desc->fw_version); 3077 psp->ras_drv.feature_version = le32_to_cpu(desc->fw_version); 3078 psp->ras_drv.size_bytes = le32_to_cpu(desc->size_bytes); 3079 psp->ras_drv.start_addr = ucode_start_addr; 3080 break; 3081 default: 3082 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type); 3083 break; 3084 } 3085 3086 return 0; 3087 } 3088 3089 static int psp_init_sos_base_fw(struct amdgpu_device *adev) 3090 { 3091 const struct psp_firmware_header_v1_0 *sos_hdr; 3092 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3093 uint8_t *ucode_array_start_addr; 3094 3095 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3096 ucode_array_start_addr = (uint8_t *)sos_hdr + 3097 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3098 3099 if (adev->gmc.xgmi.connected_to_cpu || 3100 (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) { 3101 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version); 3102 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version); 3103 3104 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes); 3105 adev->psp.sys.start_addr = ucode_array_start_addr; 3106 3107 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes); 3108 adev->psp.sos.start_addr = ucode_array_start_addr + 3109 le32_to_cpu(sos_hdr->sos.offset_bytes); 3110 } else { 3111 /* Load alternate PSP SOS FW */ 3112 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3113 3114 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3115 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version); 3116 3117 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes); 3118 adev->psp.sys.start_addr = ucode_array_start_addr + 3119 le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes); 3120 3121 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes); 3122 adev->psp.sos.start_addr = ucode_array_start_addr + 3123 le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes); 3124 } 3125 3126 if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) { 3127 dev_warn(adev->dev, "PSP SOS FW not available"); 3128 return -EINVAL; 3129 } 3130 3131 return 0; 3132 } 3133 3134 int psp_init_sos_microcode(struct psp_context *psp, 3135 const char *chip_name) 3136 { 3137 struct amdgpu_device *adev = psp->adev; 3138 char fw_name[PSP_FW_NAME_LEN]; 3139 const struct psp_firmware_header_v1_0 *sos_hdr; 3140 const struct psp_firmware_header_v1_1 *sos_hdr_v1_1; 3141 const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; 3142 const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; 3143 const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; 3144 int err = 0; 3145 uint8_t *ucode_array_start_addr; 3146 int fw_index = 0; 3147 3148 if (!chip_name) { 3149 dev_err(adev->dev, "invalid chip name for sos microcode\n"); 3150 return -EINVAL; 3151 } 3152 3153 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name); 3154 err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev); 3155 if (err) 3156 goto out; 3157 3158 err = amdgpu_ucode_validate(adev->psp.sos_fw); 3159 if (err) 3160 goto out; 3161 3162 sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data; 3163 ucode_array_start_addr = (uint8_t *)sos_hdr + 3164 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes); 3165 amdgpu_ucode_print_psp_hdr(&sos_hdr->header); 3166 3167 switch (sos_hdr->header.header_version_major) { 3168 case 1: 3169 err = psp_init_sos_base_fw(adev); 3170 if (err) 3171 goto out; 3172 3173 if (sos_hdr->header.header_version_minor == 1) { 3174 sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data; 3175 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes); 3176 adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3177 le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes); 3178 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes); 3179 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3180 le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes); 3181 } 3182 if (sos_hdr->header.header_version_minor == 2) { 3183 sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data; 3184 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes); 3185 adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr + 3186 le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes); 3187 } 3188 if (sos_hdr->header.header_version_minor == 3) { 3189 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data; 3190 adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes); 3191 adev->psp.toc.start_addr = ucode_array_start_addr + 3192 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes); 3193 adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes); 3194 adev->psp.kdb.start_addr = ucode_array_start_addr + 3195 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes); 3196 adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes); 3197 adev->psp.spl.start_addr = ucode_array_start_addr + 3198 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes); 3199 adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes); 3200 adev->psp.rl.start_addr = ucode_array_start_addr + 3201 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes); 3202 } 3203 break; 3204 case 2: 3205 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; 3206 3207 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3208 dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); 3209 err = -EINVAL; 3210 goto out; 3211 } 3212 3213 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { 3214 err = parse_sos_bin_descriptor(psp, 3215 &sos_hdr_v2_0->psp_fw_bin[fw_index], 3216 sos_hdr_v2_0); 3217 if (err) 3218 goto out; 3219 } 3220 break; 3221 default: 3222 dev_err(adev->dev, 3223 "unsupported psp sos firmware\n"); 3224 err = -EINVAL; 3225 goto out; 3226 } 3227 3228 return 0; 3229 out: 3230 dev_err(adev->dev, 3231 "failed to init sos firmware\n"); 3232 release_firmware(adev->psp.sos_fw); 3233 adev->psp.sos_fw = NULL; 3234 3235 return err; 3236 } 3237 3238 static int parse_ta_bin_descriptor(struct psp_context *psp, 3239 const struct psp_fw_bin_desc *desc, 3240 const struct ta_firmware_header_v2_0 *ta_hdr) 3241 { 3242 uint8_t *ucode_start_addr = NULL; 3243 3244 if (!psp || !desc || !ta_hdr) 3245 return -EINVAL; 3246 3247 ucode_start_addr = (uint8_t *)ta_hdr + 3248 le32_to_cpu(desc->offset_bytes) + 3249 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 3250 3251 switch (desc->fw_type) { 3252 case TA_FW_TYPE_PSP_ASD: 3253 psp->asd_context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3254 psp->asd_context.bin_desc.feature_version = le32_to_cpu(desc->fw_version); 3255 psp->asd_context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3256 psp->asd_context.bin_desc.start_addr = ucode_start_addr; 3257 break; 3258 case TA_FW_TYPE_PSP_XGMI: 3259 psp->xgmi_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3260 psp->xgmi_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3261 psp->xgmi_context.context.bin_desc.start_addr = ucode_start_addr; 3262 break; 3263 case TA_FW_TYPE_PSP_RAS: 3264 psp->ras_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3265 psp->ras_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3266 psp->ras_context.context.bin_desc.start_addr = ucode_start_addr; 3267 break; 3268 case TA_FW_TYPE_PSP_HDCP: 3269 psp->hdcp_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3270 psp->hdcp_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3271 psp->hdcp_context.context.bin_desc.start_addr = ucode_start_addr; 3272 break; 3273 case TA_FW_TYPE_PSP_DTM: 3274 psp->dtm_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3275 psp->dtm_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3276 psp->dtm_context.context.bin_desc.start_addr = ucode_start_addr; 3277 break; 3278 case TA_FW_TYPE_PSP_RAP: 3279 psp->rap_context.context.bin_desc.fw_version = le32_to_cpu(desc->fw_version); 3280 psp->rap_context.context.bin_desc.size_bytes = le32_to_cpu(desc->size_bytes); 3281 psp->rap_context.context.bin_desc.start_addr = ucode_start_addr; 3282 break; 3283 case TA_FW_TYPE_PSP_SECUREDISPLAY: 3284 psp->securedisplay_context.context.bin_desc.fw_version = 3285 le32_to_cpu(desc->fw_version); 3286 psp->securedisplay_context.context.bin_desc.size_bytes = 3287 le32_to_cpu(desc->size_bytes); 3288 psp->securedisplay_context.context.bin_desc.start_addr = 3289 ucode_start_addr; 3290 break; 3291 default: 3292 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type); 3293 break; 3294 } 3295 3296 return 0; 3297 } 3298 3299 int psp_init_ta_microcode(struct psp_context *psp, 3300 const char *chip_name) 3301 { 3302 struct amdgpu_device *adev = psp->adev; 3303 char fw_name[PSP_FW_NAME_LEN]; 3304 const struct ta_firmware_header_v2_0 *ta_hdr; 3305 int err = 0; 3306 int ta_index = 0; 3307 3308 if (!chip_name) { 3309 dev_err(adev->dev, "invalid chip name for ta microcode\n"); 3310 return -EINVAL; 3311 } 3312 3313 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 3314 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 3315 if (err) 3316 goto out; 3317 3318 err = amdgpu_ucode_validate(adev->psp.ta_fw); 3319 if (err) 3320 goto out; 3321 3322 ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data; 3323 3324 if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) { 3325 dev_err(adev->dev, "unsupported TA header version\n"); 3326 err = -EINVAL; 3327 goto out; 3328 } 3329 3330 if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { 3331 dev_err(adev->dev, "packed TA count exceeds maximum limit\n"); 3332 err = -EINVAL; 3333 goto out; 3334 } 3335 3336 for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) { 3337 err = parse_ta_bin_descriptor(psp, 3338 &ta_hdr->ta_fw_bin[ta_index], 3339 ta_hdr); 3340 if (err) 3341 goto out; 3342 } 3343 3344 return 0; 3345 out: 3346 dev_err(adev->dev, "fail to initialize ta microcode\n"); 3347 release_firmware(adev->psp.ta_fw); 3348 adev->psp.ta_fw = NULL; 3349 return err; 3350 } 3351 3352 int psp_init_cap_microcode(struct psp_context *psp, 3353 const char *chip_name) 3354 { 3355 struct amdgpu_device *adev = psp->adev; 3356 char fw_name[PSP_FW_NAME_LEN]; 3357 const struct psp_firmware_header_v1_0 *cap_hdr_v1_0; 3358 struct amdgpu_firmware_info *info = NULL; 3359 int err = 0; 3360 3361 if (!chip_name) { 3362 dev_err(adev->dev, "invalid chip name for cap microcode\n"); 3363 return -EINVAL; 3364 } 3365 3366 if (!amdgpu_sriov_vf(adev)) { 3367 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n"); 3368 return -EINVAL; 3369 } 3370 3371 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name); 3372 err = request_firmware(&adev->psp.cap_fw, fw_name, adev->dev); 3373 if (err) { 3374 dev_warn(adev->dev, "cap microcode does not exist, skip\n"); 3375 err = 0; 3376 goto out; 3377 } 3378 3379 err = amdgpu_ucode_validate(adev->psp.cap_fw); 3380 if (err) { 3381 dev_err(adev->dev, "fail to initialize cap microcode\n"); 3382 goto out; 3383 } 3384 3385 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP]; 3386 info->ucode_id = AMDGPU_UCODE_ID_CAP; 3387 info->fw = adev->psp.cap_fw; 3388 cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *) 3389 adev->psp.cap_fw->data; 3390 adev->firmware.fw_size += roundup2( 3391 le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE); 3392 adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version); 3393 adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version); 3394 adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes); 3395 3396 return 0; 3397 3398 out: 3399 release_firmware(adev->psp.cap_fw); 3400 adev->psp.cap_fw = NULL; 3401 return err; 3402 } 3403 3404 static int psp_set_clockgating_state(void *handle, 3405 enum amd_clockgating_state state) 3406 { 3407 return 0; 3408 } 3409 3410 static int psp_set_powergating_state(void *handle, 3411 enum amd_powergating_state state) 3412 { 3413 return 0; 3414 } 3415 3416 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev, 3417 struct device_attribute *attr, 3418 char *buf) 3419 { 3420 struct drm_device *ddev = dev_get_drvdata(dev); 3421 struct amdgpu_device *adev = drm_to_adev(ddev); 3422 uint32_t fw_ver; 3423 int ret; 3424 3425 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3426 DRM_INFO("PSP block is not ready yet."); 3427 return -EBUSY; 3428 } 3429 3430 mutex_lock(&adev->psp.mutex); 3431 ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver); 3432 mutex_unlock(&adev->psp.mutex); 3433 3434 if (ret) { 3435 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret); 3436 return ret; 3437 } 3438 3439 return sysfs_emit(buf, "%x\n", fw_ver); 3440 } 3441 3442 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev, 3443 struct device_attribute *attr, 3444 const char *buf, 3445 size_t count) 3446 { 3447 struct drm_device *ddev = dev_get_drvdata(dev); 3448 struct amdgpu_device *adev = drm_to_adev(ddev); 3449 int ret, idx; 3450 char fw_name[100]; 3451 const struct firmware *usbc_pd_fw; 3452 struct amdgpu_bo *fw_buf_bo = NULL; 3453 uint64_t fw_pri_mc_addr; 3454 void *fw_pri_cpu_addr; 3455 3456 if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) { 3457 DRM_INFO("PSP block is not ready yet."); 3458 return -EBUSY; 3459 } 3460 3461 if (!drm_dev_enter(ddev, &idx)) 3462 return -ENODEV; 3463 3464 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf); 3465 ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev); 3466 if (ret) 3467 goto fail; 3468 3469 /* LFB address which is aligned to 1MB boundary per PSP request */ 3470 ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000, 3471 AMDGPU_GEM_DOMAIN_VRAM, 3472 &fw_buf_bo, 3473 &fw_pri_mc_addr, 3474 &fw_pri_cpu_addr); 3475 if (ret) 3476 goto rel_buf; 3477 3478 memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size); 3479 3480 mutex_lock(&adev->psp.mutex); 3481 ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr); 3482 mutex_unlock(&adev->psp.mutex); 3483 3484 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3485 3486 rel_buf: 3487 release_firmware(usbc_pd_fw); 3488 fail: 3489 if (ret) { 3490 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret); 3491 count = ret; 3492 } 3493 3494 drm_dev_exit(idx); 3495 return count; 3496 } 3497 3498 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size) 3499 { 3500 int idx; 3501 3502 if (!drm_dev_enter(adev_to_drm(psp->adev), &idx)) 3503 return; 3504 3505 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 3506 memcpy(psp->fw_pri_buf, start_addr, bin_size); 3507 3508 drm_dev_exit(idx); 3509 } 3510 3511 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR, 3512 psp_usbc_pd_fw_sysfs_read, 3513 psp_usbc_pd_fw_sysfs_write); 3514 3515 int is_psp_fw_valid(struct psp_bin_desc bin) 3516 { 3517 return bin.size_bytes; 3518 } 3519 3520 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj, 3521 struct bin_attribute *bin_attr, 3522 char *buffer, loff_t pos, size_t count) 3523 { 3524 STUB(); 3525 return -ENOSYS; 3526 #ifdef notyet 3527 struct device *dev = kobj_to_dev(kobj); 3528 struct drm_device *ddev = dev_get_drvdata(dev); 3529 struct amdgpu_device *adev = drm_to_adev(ddev); 3530 3531 adev->psp.vbflash_done = false; 3532 3533 /* Safeguard against memory drain */ 3534 if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) { 3535 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B); 3536 kvfree(adev->psp.vbflash_tmp_buf); 3537 adev->psp.vbflash_tmp_buf = NULL; 3538 adev->psp.vbflash_image_size = 0; 3539 return -ENOMEM; 3540 } 3541 3542 /* TODO Just allocate max for now and optimize to realloc later if needed */ 3543 if (!adev->psp.vbflash_tmp_buf) { 3544 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL); 3545 if (!adev->psp.vbflash_tmp_buf) 3546 return -ENOMEM; 3547 } 3548 3549 mutex_lock(&adev->psp.mutex); 3550 memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count); 3551 adev->psp.vbflash_image_size += count; 3552 mutex_unlock(&adev->psp.mutex); 3553 3554 dev_info(adev->dev, "VBIOS flash write PSP done"); 3555 3556 return count; 3557 #endif 3558 } 3559 3560 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj, 3561 struct bin_attribute *bin_attr, char *buffer, 3562 loff_t pos, size_t count) 3563 { 3564 STUB(); 3565 return -ENOSYS; 3566 #ifdef notyet 3567 struct device *dev = kobj_to_dev(kobj); 3568 struct drm_device *ddev = dev_get_drvdata(dev); 3569 struct amdgpu_device *adev = drm_to_adev(ddev); 3570 struct amdgpu_bo *fw_buf_bo = NULL; 3571 uint64_t fw_pri_mc_addr; 3572 void *fw_pri_cpu_addr; 3573 int ret; 3574 3575 if (adev->psp.vbflash_image_size == 0) 3576 return -EINVAL; 3577 3578 dev_info(adev->dev, "VBIOS flash to PSP started"); 3579 3580 ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size, 3581 AMDGPU_GPU_PAGE_SIZE, 3582 AMDGPU_GEM_DOMAIN_VRAM, 3583 &fw_buf_bo, 3584 &fw_pri_mc_addr, 3585 &fw_pri_cpu_addr); 3586 if (ret) 3587 goto rel_buf; 3588 3589 memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size); 3590 3591 mutex_lock(&adev->psp.mutex); 3592 ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr); 3593 mutex_unlock(&adev->psp.mutex); 3594 3595 amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr); 3596 3597 rel_buf: 3598 kvfree(adev->psp.vbflash_tmp_buf); 3599 adev->psp.vbflash_tmp_buf = NULL; 3600 adev->psp.vbflash_image_size = 0; 3601 3602 if (ret) { 3603 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret); 3604 return ret; 3605 } 3606 3607 dev_info(adev->dev, "VBIOS flash to PSP done"); 3608 return 0; 3609 #endif 3610 } 3611 3612 static ssize_t amdgpu_psp_vbflash_status(struct device *dev, 3613 struct device_attribute *attr, 3614 char *buf) 3615 { 3616 struct drm_device *ddev = dev_get_drvdata(dev); 3617 struct amdgpu_device *adev = drm_to_adev(ddev); 3618 uint32_t vbflash_status; 3619 3620 vbflash_status = psp_vbflash_status(&adev->psp); 3621 if (!adev->psp.vbflash_done) 3622 vbflash_status = 0; 3623 else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000)) 3624 vbflash_status = 1; 3625 3626 return sysfs_emit(buf, "0x%x\n", vbflash_status); 3627 } 3628 3629 #ifdef notyet 3630 static const struct bin_attribute psp_vbflash_bin_attr = { 3631 .attr = {.name = "psp_vbflash", .mode = 0660}, 3632 .size = 0, 3633 .write = amdgpu_psp_vbflash_write, 3634 .read = amdgpu_psp_vbflash_read, 3635 }; 3636 #endif 3637 3638 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL); 3639 3640 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev) 3641 { 3642 int ret = 0; 3643 struct psp_context *psp = &adev->psp; 3644 3645 if (amdgpu_sriov_vf(adev)) 3646 return -EINVAL; 3647 3648 switch (adev->ip_versions[MP0_HWIP][0]) { 3649 case IP_VERSION(13, 0, 0): 3650 case IP_VERSION(13, 0, 7): 3651 if (!psp->adev) { 3652 psp->adev = adev; 3653 psp_v13_0_set_psp_funcs(psp); 3654 } 3655 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3656 if (ret) 3657 dev_err(adev->dev, "Failed to create device file psp_vbflash"); 3658 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status); 3659 if (ret) 3660 dev_err(adev->dev, "Failed to create device file psp_vbflash_status"); 3661 return ret; 3662 default: 3663 return 0; 3664 } 3665 } 3666 3667 const struct amd_ip_funcs psp_ip_funcs = { 3668 .name = "psp", 3669 .early_init = psp_early_init, 3670 .late_init = NULL, 3671 .sw_init = psp_sw_init, 3672 .sw_fini = psp_sw_fini, 3673 .hw_init = psp_hw_init, 3674 .hw_fini = psp_hw_fini, 3675 .suspend = psp_suspend, 3676 .resume = psp_resume, 3677 .is_idle = NULL, 3678 .check_soft_reset = NULL, 3679 .wait_for_idle = NULL, 3680 .soft_reset = NULL, 3681 .set_clockgating_state = psp_set_clockgating_state, 3682 .set_powergating_state = psp_set_powergating_state, 3683 }; 3684 3685 static int psp_sysfs_init(struct amdgpu_device *adev) 3686 { 3687 int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw); 3688 3689 if (ret) 3690 DRM_ERROR("Failed to create USBC PD FW control file!"); 3691 3692 return ret; 3693 } 3694 3695 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev) 3696 { 3697 sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr); 3698 device_remove_file(adev->dev, &dev_attr_psp_vbflash_status); 3699 } 3700 3701 static void psp_sysfs_fini(struct amdgpu_device *adev) 3702 { 3703 device_remove_file(adev->dev, &dev_attr_usbc_pd_fw); 3704 } 3705 3706 const struct amdgpu_ip_block_version psp_v3_1_ip_block = 3707 { 3708 .type = AMD_IP_BLOCK_TYPE_PSP, 3709 .major = 3, 3710 .minor = 1, 3711 .rev = 0, 3712 .funcs = &psp_ip_funcs, 3713 }; 3714 3715 const struct amdgpu_ip_block_version psp_v10_0_ip_block = 3716 { 3717 .type = AMD_IP_BLOCK_TYPE_PSP, 3718 .major = 10, 3719 .minor = 0, 3720 .rev = 0, 3721 .funcs = &psp_ip_funcs, 3722 }; 3723 3724 const struct amdgpu_ip_block_version psp_v11_0_ip_block = 3725 { 3726 .type = AMD_IP_BLOCK_TYPE_PSP, 3727 .major = 11, 3728 .minor = 0, 3729 .rev = 0, 3730 .funcs = &psp_ip_funcs, 3731 }; 3732 3733 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = { 3734 .type = AMD_IP_BLOCK_TYPE_PSP, 3735 .major = 11, 3736 .minor = 0, 3737 .rev = 8, 3738 .funcs = &psp_ip_funcs, 3739 }; 3740 3741 const struct amdgpu_ip_block_version psp_v12_0_ip_block = 3742 { 3743 .type = AMD_IP_BLOCK_TYPE_PSP, 3744 .major = 12, 3745 .minor = 0, 3746 .rev = 0, 3747 .funcs = &psp_ip_funcs, 3748 }; 3749 3750 const struct amdgpu_ip_block_version psp_v13_0_ip_block = { 3751 .type = AMD_IP_BLOCK_TYPE_PSP, 3752 .major = 13, 3753 .minor = 0, 3754 .rev = 0, 3755 .funcs = &psp_ip_funcs, 3756 }; 3757 3758 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = { 3759 .type = AMD_IP_BLOCK_TYPE_PSP, 3760 .major = 13, 3761 .minor = 0, 3762 .rev = 4, 3763 .funcs = &psp_ip_funcs, 3764 }; 3765