1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_OBJECT_H__ 29 #define __AMDGPU_OBJECT_H__ 30 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 #include "amdgpu_res_cursor.h" 34 35 #ifdef CONFIG_MMU_NOTIFIER 36 #include <linux/mmu_notifier.h> 37 #endif 38 39 #define AMDGPU_BO_INVALID_OFFSET LONG_MAX 40 #define AMDGPU_BO_MAX_PLACEMENTS 3 41 42 /* BO flag to indicate a KFD userptr BO */ 43 #define AMDGPU_AMDKFD_CREATE_USERPTR_BO (1ULL << 63) 44 45 #define to_amdgpu_bo_user(abo) container_of((abo), struct amdgpu_bo_user, bo) 46 #define to_amdgpu_bo_vm(abo) container_of((abo), struct amdgpu_bo_vm, bo) 47 48 struct amdgpu_bo_param { 49 unsigned long size; 50 int byte_align; 51 u32 bo_ptr_size; 52 u32 domain; 53 u32 preferred_domain; 54 u64 flags; 55 enum ttm_bo_type type; 56 bool no_wait_gpu; 57 struct dma_resv *resv; 58 void (*destroy)(struct ttm_buffer_object *bo); 59 /* xcp partition number plus 1, 0 means any partition */ 60 int8_t xcp_id_plus1; 61 }; 62 63 /* bo virtual addresses in a vm */ 64 struct amdgpu_bo_va_mapping { 65 struct amdgpu_bo_va *bo_va; 66 struct list_head list; 67 struct rb_node rb; 68 uint64_t start; 69 uint64_t last; 70 uint64_t __subtree_last; 71 uint64_t offset; 72 uint64_t flags; 73 }; 74 75 /* User space allocated BO in a VM */ 76 struct amdgpu_bo_va { 77 struct amdgpu_vm_bo_base base; 78 79 /* protected by bo being reserved */ 80 unsigned ref_count; 81 82 /* all other members protected by the VM PD being reserved */ 83 struct dma_fence *last_pt_update; 84 85 /* mappings for this bo_va */ 86 struct list_head invalids; 87 struct list_head valids; 88 89 /* If the mappings are cleared or filled */ 90 bool cleared; 91 92 bool is_xgmi; 93 }; 94 95 struct amdgpu_bo { 96 /* Protected by tbo.reserved */ 97 u32 preferred_domains; 98 u32 allowed_domains; 99 struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS]; 100 struct ttm_placement placement; 101 struct ttm_buffer_object tbo; 102 struct ttm_bo_kmap_obj kmap; 103 u64 flags; 104 /* per VM structure for page tables and with virtual addresses */ 105 struct amdgpu_vm_bo_base *vm_bo; 106 /* Constant after initialization */ 107 struct amdgpu_device *adev; 108 struct amdgpu_bo *parent; 109 110 #ifdef CONFIG_MMU_NOTIFIER 111 struct mmu_interval_notifier notifier; 112 #endif 113 struct kgd_mem *kfd_bo; 114 115 /* 116 * For GPUs with spatial partitioning, xcp partition number, -1 means 117 * any partition. For other ASICs without spatial partition, always 0 118 * for memory accounting. 119 */ 120 int8_t xcp_id; 121 }; 122 123 struct amdgpu_bo_user { 124 struct amdgpu_bo bo; 125 u64 tiling_flags; 126 u64 metadata_flags; 127 void *metadata; 128 u32 metadata_size; 129 130 }; 131 132 struct amdgpu_bo_vm { 133 struct amdgpu_bo bo; 134 struct amdgpu_bo *shadow; 135 struct list_head shadow_list; 136 struct amdgpu_vm_bo_base entries[]; 137 }; 138 139 struct amdgpu_mem_stats { 140 /* current VRAM usage, includes visible VRAM */ 141 uint64_t vram; 142 /* current visible VRAM usage */ 143 uint64_t visible_vram; 144 /* current GTT usage */ 145 uint64_t gtt; 146 /* current system memory usage */ 147 uint64_t cpu; 148 /* sum of evicted buffers, includes visible VRAM */ 149 uint64_t evicted_vram; 150 /* sum of evicted buffers due to CPU access */ 151 uint64_t evicted_visible_vram; 152 /* how much userspace asked for, includes vis.VRAM */ 153 uint64_t requested_vram; 154 /* how much userspace asked for */ 155 uint64_t requested_visible_vram; 156 /* how much userspace asked for */ 157 uint64_t requested_gtt; 158 }; 159 160 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo) 161 { 162 return container_of(tbo, struct amdgpu_bo, tbo); 163 } 164 165 /** 166 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type 167 * @mem_type: ttm memory type 168 * 169 * Returns corresponding domain of the ttm mem_type 170 */ 171 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) 172 { 173 switch (mem_type) { 174 case TTM_PL_VRAM: 175 return AMDGPU_GEM_DOMAIN_VRAM; 176 case TTM_PL_TT: 177 return AMDGPU_GEM_DOMAIN_GTT; 178 case TTM_PL_SYSTEM: 179 return AMDGPU_GEM_DOMAIN_CPU; 180 case AMDGPU_PL_GDS: 181 return AMDGPU_GEM_DOMAIN_GDS; 182 case AMDGPU_PL_GWS: 183 return AMDGPU_GEM_DOMAIN_GWS; 184 case AMDGPU_PL_OA: 185 return AMDGPU_GEM_DOMAIN_OA; 186 case AMDGPU_PL_DOORBELL: 187 return AMDGPU_GEM_DOMAIN_DOORBELL; 188 default: 189 break; 190 } 191 return 0; 192 } 193 194 /** 195 * amdgpu_bo_reserve - reserve bo 196 * @bo: bo structure 197 * @no_intr: don't return -ERESTARTSYS on pending signal 198 * 199 * Returns: 200 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 201 * a signal. Release all buffer reservations and return to user-space. 202 */ 203 static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr) 204 { 205 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 206 int r; 207 208 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL); 209 if (unlikely(r != 0)) { 210 if (r != -ERESTARTSYS) 211 dev_err(adev->dev, "%p reserve failed\n", bo); 212 return r; 213 } 214 return 0; 215 } 216 217 static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo) 218 { 219 ttm_bo_unreserve(&bo->tbo); 220 } 221 222 static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo) 223 { 224 return bo->tbo.base.size; 225 } 226 227 static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo) 228 { 229 return bo->tbo.base.size / AMDGPU_GPU_PAGE_SIZE; 230 } 231 232 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo) 233 { 234 return (bo->tbo.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; 235 } 236 237 /** 238 * amdgpu_bo_mmap_offset - return mmap offset of bo 239 * @bo: amdgpu object for which we query the offset 240 * 241 * Returns mmap offset of the object. 242 */ 243 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) 244 { 245 return drm_vma_node_offset_addr(&bo->tbo.base.vma_node); 246 } 247 248 /** 249 * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM 250 */ 251 static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo) 252 { 253 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 254 struct amdgpu_res_cursor cursor; 255 256 if (!bo->tbo.resource || bo->tbo.resource->mem_type != TTM_PL_VRAM) 257 return false; 258 259 amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); 260 while (cursor.remaining) { 261 if (cursor.start < adev->gmc.visible_vram_size) 262 return true; 263 264 amdgpu_res_next(&cursor, cursor.size); 265 } 266 267 return false; 268 } 269 270 /** 271 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced 272 */ 273 static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo) 274 { 275 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC; 276 } 277 278 /** 279 * amdgpu_bo_encrypted - test if the BO is encrypted 280 * @bo: pointer to a buffer object 281 * 282 * Return true if the buffer object is encrypted, false otherwise. 283 */ 284 static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo) 285 { 286 return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED; 287 } 288 289 /** 290 * amdgpu_bo_shadowed - check if the BO is shadowed 291 * 292 * @bo: BO to be tested. 293 * 294 * Returns: 295 * NULL if not shadowed or else return a BO pointer. 296 */ 297 static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo) 298 { 299 if (bo->tbo.type == ttm_bo_type_kernel) 300 return to_amdgpu_bo_vm(bo)->shadow; 301 302 return NULL; 303 } 304 305 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 306 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 307 308 int amdgpu_bo_create(struct amdgpu_device *adev, 309 struct amdgpu_bo_param *bp, 310 struct amdgpu_bo **bo_ptr); 311 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 312 unsigned long size, int align, 313 u32 domain, struct amdgpu_bo **bo_ptr, 314 u64 *gpu_addr, void **cpu_addr); 315 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 316 unsigned long size, int align, 317 u32 domain, struct amdgpu_bo **bo_ptr, 318 u64 *gpu_addr, void **cpu_addr); 319 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 320 uint64_t offset, uint64_t size, 321 struct amdgpu_bo **bo_ptr, void **cpu_addr); 322 int amdgpu_bo_create_user(struct amdgpu_device *adev, 323 struct amdgpu_bo_param *bp, 324 struct amdgpu_bo_user **ubo_ptr); 325 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 326 struct amdgpu_bo_param *bp, 327 struct amdgpu_bo_vm **ubo_ptr); 328 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 329 void **cpu_addr); 330 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); 331 void *amdgpu_bo_kptr(struct amdgpu_bo *bo); 332 void amdgpu_bo_kunmap(struct amdgpu_bo *bo); 333 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); 334 void amdgpu_bo_unref(struct amdgpu_bo **bo); 335 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain); 336 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 337 u64 min_offset, u64 max_offset); 338 void amdgpu_bo_unpin(struct amdgpu_bo *bo); 339 int amdgpu_bo_init(struct amdgpu_device *adev); 340 void amdgpu_bo_fini(struct amdgpu_device *adev); 341 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); 342 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags); 343 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 344 uint32_t metadata_size, uint64_t flags); 345 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 346 size_t buffer_size, uint32_t *metadata_size, 347 uint64_t *flags); 348 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 349 bool evict, 350 struct ttm_resource *new_mem); 351 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo); 352 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 353 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 354 bool shared); 355 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 356 enum amdgpu_sync_mode sync_mode, void *owner, 357 bool intr); 358 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr); 359 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); 360 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo); 361 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, 362 struct amdgpu_mem_stats *stats); 363 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo); 364 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, 365 struct dma_fence **fence); 366 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, 367 uint32_t domain); 368 369 /* 370 * sub allocation 371 */ 372 static inline struct amdgpu_sa_manager * 373 to_amdgpu_sa_manager(struct drm_suballoc_manager *manager) 374 { 375 return container_of(manager, struct amdgpu_sa_manager, base); 376 } 377 378 static inline uint64_t amdgpu_sa_bo_gpu_addr(struct drm_suballoc *sa_bo) 379 { 380 return to_amdgpu_sa_manager(sa_bo->manager)->gpu_addr + 381 drm_suballoc_soffset(sa_bo); 382 } 383 384 static inline void *amdgpu_sa_bo_cpu_addr(struct drm_suballoc *sa_bo) 385 { 386 return to_amdgpu_sa_manager(sa_bo->manager)->cpu_ptr + 387 drm_suballoc_soffset(sa_bo); 388 } 389 390 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, 391 struct amdgpu_sa_manager *sa_manager, 392 unsigned size, u32 align, u32 domain); 393 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev, 394 struct amdgpu_sa_manager *sa_manager); 395 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev, 396 struct amdgpu_sa_manager *sa_manager); 397 int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, 398 struct drm_suballoc **sa_bo, 399 unsigned int size); 400 void amdgpu_sa_bo_free(struct amdgpu_device *adev, 401 struct drm_suballoc **sa_bo, 402 struct dma_fence *fence); 403 #if defined(CONFIG_DEBUG_FS) 404 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, 405 struct seq_file *m); 406 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m); 407 #endif 408 void amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 409 410 bool amdgpu_bo_support_uswc(u64 bo_flags); 411 412 413 #endif 414