1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_OBJECT_H__ 29 #define __AMDGPU_OBJECT_H__ 30 31 #include <drm/amdgpu_drm.h> 32 #include "amdgpu.h" 33 #ifdef CONFIG_MMU_NOTIFIER 34 #include <linux/mmu_notifier.h> 35 #endif 36 37 #define AMDGPU_BO_INVALID_OFFSET LONG_MAX 38 #define AMDGPU_BO_MAX_PLACEMENTS 3 39 40 struct amdgpu_bo_param { 41 unsigned long size; 42 int byte_align; 43 u32 domain; 44 u32 preferred_domain; 45 u64 flags; 46 enum ttm_bo_type type; 47 bool no_wait_gpu; 48 struct dma_resv *resv; 49 }; 50 51 /* bo virtual addresses in a vm */ 52 struct amdgpu_bo_va_mapping { 53 struct amdgpu_bo_va *bo_va; 54 struct list_head list; 55 struct rb_node rb; 56 uint64_t start; 57 uint64_t last; 58 uint64_t __subtree_last; 59 uint64_t offset; 60 uint64_t flags; 61 }; 62 63 /* User space allocated BO in a VM */ 64 struct amdgpu_bo_va { 65 struct amdgpu_vm_bo_base base; 66 67 /* protected by bo being reserved */ 68 unsigned ref_count; 69 70 /* all other members protected by the VM PD being reserved */ 71 struct dma_fence *last_pt_update; 72 73 /* mappings for this bo_va */ 74 struct list_head invalids; 75 struct list_head valids; 76 77 /* If the mappings are cleared or filled */ 78 bool cleared; 79 80 bool is_xgmi; 81 }; 82 83 struct amdgpu_bo { 84 /* Protected by tbo.reserved */ 85 u32 preferred_domains; 86 u32 allowed_domains; 87 struct ttm_place placements[AMDGPU_BO_MAX_PLACEMENTS]; 88 struct ttm_placement placement; 89 struct ttm_buffer_object tbo; 90 struct ttm_bo_kmap_obj kmap; 91 u64 flags; 92 unsigned pin_count; 93 u64 tiling_flags; 94 u64 metadata_flags; 95 void *metadata; 96 u32 metadata_size; 97 unsigned prime_shared_count; 98 /* per VM structure for page tables and with virtual addresses */ 99 struct amdgpu_vm_bo_base *vm_bo; 100 /* Constant after initialization */ 101 struct amdgpu_device *adev; 102 struct amdgpu_bo *parent; 103 struct amdgpu_bo *shadow; 104 105 struct ttm_bo_kmap_obj dma_buf_vmap; 106 struct amdgpu_mn *mn; 107 108 109 #ifdef CONFIG_MMU_NOTIFIER 110 struct mmu_interval_notifier notifier; 111 #endif 112 113 struct list_head shadow_list; 114 115 struct kgd_mem *kfd_bo; 116 }; 117 118 static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo) 119 { 120 return container_of(tbo, struct amdgpu_bo, tbo); 121 } 122 123 /** 124 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type 125 * @mem_type: ttm memory type 126 * 127 * Returns corresponding domain of the ttm mem_type 128 */ 129 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) 130 { 131 switch (mem_type) { 132 case TTM_PL_VRAM: 133 return AMDGPU_GEM_DOMAIN_VRAM; 134 case TTM_PL_TT: 135 return AMDGPU_GEM_DOMAIN_GTT; 136 case TTM_PL_SYSTEM: 137 return AMDGPU_GEM_DOMAIN_CPU; 138 case AMDGPU_PL_GDS: 139 return AMDGPU_GEM_DOMAIN_GDS; 140 case AMDGPU_PL_GWS: 141 return AMDGPU_GEM_DOMAIN_GWS; 142 case AMDGPU_PL_OA: 143 return AMDGPU_GEM_DOMAIN_OA; 144 default: 145 break; 146 } 147 return 0; 148 } 149 150 /** 151 * amdgpu_bo_reserve - reserve bo 152 * @bo: bo structure 153 * @no_intr: don't return -ERESTARTSYS on pending signal 154 * 155 * Returns: 156 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 157 * a signal. Release all buffer reservations and return to user-space. 158 */ 159 static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr) 160 { 161 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 162 int r; 163 164 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL); 165 if (unlikely(r != 0)) { 166 if (r != -ERESTARTSYS) 167 dev_err(adev->dev, "%p reserve failed\n", bo); 168 return r; 169 } 170 return 0; 171 } 172 173 static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo) 174 { 175 ttm_bo_unreserve(&bo->tbo); 176 } 177 178 static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo) 179 { 180 return bo->tbo.num_pages << PAGE_SHIFT; 181 } 182 183 static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo) 184 { 185 return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; 186 } 187 188 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo) 189 { 190 return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; 191 } 192 193 /** 194 * amdgpu_bo_mmap_offset - return mmap offset of bo 195 * @bo: amdgpu object for which we query the offset 196 * 197 * Returns mmap offset of the object. 198 */ 199 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) 200 { 201 return drm_vma_node_offset_addr(&bo->tbo.base.vma_node); 202 } 203 204 /** 205 * amdgpu_bo_in_cpu_visible_vram - check if BO is (partly) in visible VRAM 206 */ 207 static inline bool amdgpu_bo_in_cpu_visible_vram(struct amdgpu_bo *bo) 208 { 209 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 210 unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 211 struct drm_mm_node *node = bo->tbo.mem.mm_node; 212 unsigned long pages_left; 213 214 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) 215 return false; 216 217 for (pages_left = bo->tbo.mem.num_pages; pages_left; 218 pages_left -= node->size, node++) 219 if (node->start < fpfn) 220 return true; 221 222 return false; 223 } 224 225 /** 226 * amdgpu_bo_explicit_sync - return whether the bo is explicitly synced 227 */ 228 static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo) 229 { 230 return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC; 231 } 232 233 /** 234 * amdgpu_bo_encrypted - test if the BO is encrypted 235 * @bo: pointer to a buffer object 236 * 237 * Return true if the buffer object is encrypted, false otherwise. 238 */ 239 static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo) 240 { 241 return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED; 242 } 243 244 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 245 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 246 247 int amdgpu_bo_create(struct amdgpu_device *adev, 248 struct amdgpu_bo_param *bp, 249 struct amdgpu_bo **bo_ptr); 250 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 251 unsigned long size, int align, 252 u32 domain, struct amdgpu_bo **bo_ptr, 253 u64 *gpu_addr, void **cpu_addr); 254 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 255 unsigned long size, int align, 256 u32 domain, struct amdgpu_bo **bo_ptr, 257 u64 *gpu_addr, void **cpu_addr); 258 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 259 uint64_t offset, uint64_t size, uint32_t domain, 260 struct amdgpu_bo **bo_ptr, void **cpu_addr); 261 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 262 void **cpu_addr); 263 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); 264 void *amdgpu_bo_kptr(struct amdgpu_bo *bo); 265 void amdgpu_bo_kunmap(struct amdgpu_bo *bo); 266 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); 267 void amdgpu_bo_unref(struct amdgpu_bo **bo); 268 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain); 269 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 270 u64 min_offset, u64 max_offset); 271 int amdgpu_bo_unpin(struct amdgpu_bo *bo); 272 int amdgpu_bo_evict_vram(struct amdgpu_device *adev); 273 int amdgpu_bo_init(struct amdgpu_device *adev); 274 int amdgpu_bo_late_init(struct amdgpu_device *adev); 275 void amdgpu_bo_fini(struct amdgpu_device *adev); 276 #ifdef notyet 277 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 278 struct vm_area_struct *vma); 279 #endif 280 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); 281 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags); 282 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 283 uint32_t metadata_size, uint64_t flags); 284 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 285 size_t buffer_size, uint32_t *metadata_size, 286 uint64_t *flags); 287 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 288 bool evict, 289 struct ttm_resource *new_mem); 290 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo); 291 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 292 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 293 bool shared); 294 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 295 enum amdgpu_sync_mode sync_mode, void *owner, 296 bool intr); 297 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr); 298 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); 299 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo); 300 int amdgpu_bo_validate(struct amdgpu_bo *bo); 301 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, 302 struct dma_fence **fence); 303 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 304 uint32_t domain); 305 306 /* 307 * sub allocation 308 */ 309 310 static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo) 311 { 312 return sa_bo->manager->gpu_addr + sa_bo->soffset; 313 } 314 315 static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo) 316 { 317 return sa_bo->manager->cpu_ptr + sa_bo->soffset; 318 } 319 320 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, 321 struct amdgpu_sa_manager *sa_manager, 322 unsigned size, u32 align, u32 domain); 323 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev, 324 struct amdgpu_sa_manager *sa_manager); 325 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev, 326 struct amdgpu_sa_manager *sa_manager); 327 int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, 328 struct amdgpu_sa_bo **sa_bo, 329 unsigned size, unsigned align); 330 void amdgpu_sa_bo_free(struct amdgpu_device *adev, 331 struct amdgpu_sa_bo **sa_bo, 332 struct dma_fence *fence); 333 #if defined(CONFIG_DEBUG_FS) 334 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, 335 struct seq_file *m); 336 #endif 337 int amdgpu_debugfs_sa_init(struct amdgpu_device *adev); 338 339 bool amdgpu_bo_support_uswc(u64 bo_flags); 340 341 342 #endif 343