1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/drm_drv.h> 37 #include <drm/amdgpu_drm.h> 38 #include <drm/drm_cache.h> 39 #include "amdgpu.h" 40 #include "amdgpu_trace.h" 41 #include "amdgpu_amdkfd.h" 42 43 /** 44 * DOC: amdgpu_object 45 * 46 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 47 * represents memory used by driver (VRAM, system memory, etc.). The driver 48 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 49 * to create/destroy/set buffer object which are then managed by the kernel TTM 50 * memory manager. 51 * The interfaces are also used internally by kernel clients, including gfx, 52 * uvd, etc. for kernel managed allocations used by the GPU. 53 * 54 */ 55 56 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 57 { 58 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 59 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 60 61 amdgpu_bo_kunmap(bo); 62 63 if (bo->tbo.base.import_attach) 64 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 65 drm_gem_object_release(&bo->tbo.base); 66 amdgpu_bo_unref(&bo->parent); 67 kvfree(bo); 68 } 69 70 static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) 71 { 72 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 73 struct amdgpu_bo_user *ubo; 74 75 ubo = to_amdgpu_bo_user(bo); 76 kfree(ubo->metadata); 77 amdgpu_bo_destroy(tbo); 78 } 79 80 static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) 81 { 82 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 83 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 84 struct amdgpu_bo_vm *vmbo; 85 86 vmbo = to_amdgpu_bo_vm(bo); 87 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 88 if (!list_empty(&vmbo->shadow_list)) { 89 mutex_lock(&adev->shadow_list_lock); 90 list_del_init(&vmbo->shadow_list); 91 mutex_unlock(&adev->shadow_list_lock); 92 } 93 94 amdgpu_bo_destroy(tbo); 95 } 96 97 /** 98 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 99 * @bo: buffer object to be checked 100 * 101 * Uses destroy function associated with the object to determine if this is 102 * an &amdgpu_bo. 103 * 104 * Returns: 105 * true if the object belongs to &amdgpu_bo, false if not. 106 */ 107 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 108 { 109 if (bo->destroy == &amdgpu_bo_destroy || 110 bo->destroy == &amdgpu_bo_user_destroy || 111 bo->destroy == &amdgpu_bo_vm_destroy) 112 return true; 113 114 return false; 115 } 116 117 /** 118 * amdgpu_bo_placement_from_domain - set buffer's placement 119 * @abo: &amdgpu_bo buffer object whose placement is to be set 120 * @domain: requested domain 121 * 122 * Sets buffer's placement according to requested domain and the buffer's 123 * flags. 124 */ 125 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 126 { 127 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 128 struct ttm_placement *placement = &abo->placement; 129 struct ttm_place *places = abo->placements; 130 u64 flags = abo->flags; 131 u32 c = 0; 132 133 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 134 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 135 136 places[c].fpfn = 0; 137 places[c].lpfn = 0; 138 places[c].mem_type = TTM_PL_VRAM; 139 places[c].flags = 0; 140 141 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 142 places[c].lpfn = visible_pfn; 143 else 144 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 145 146 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 147 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 148 c++; 149 } 150 151 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 152 places[c].fpfn = 0; 153 places[c].lpfn = 0; 154 places[c].mem_type = 155 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ? 156 AMDGPU_PL_PREEMPT : TTM_PL_TT; 157 places[c].flags = 0; 158 c++; 159 } 160 161 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 162 places[c].fpfn = 0; 163 places[c].lpfn = 0; 164 places[c].mem_type = TTM_PL_SYSTEM; 165 places[c].flags = 0; 166 c++; 167 } 168 169 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 170 places[c].fpfn = 0; 171 places[c].lpfn = 0; 172 places[c].mem_type = AMDGPU_PL_GDS; 173 places[c].flags = 0; 174 c++; 175 } 176 177 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 178 places[c].fpfn = 0; 179 places[c].lpfn = 0; 180 places[c].mem_type = AMDGPU_PL_GWS; 181 places[c].flags = 0; 182 c++; 183 } 184 185 if (domain & AMDGPU_GEM_DOMAIN_OA) { 186 places[c].fpfn = 0; 187 places[c].lpfn = 0; 188 places[c].mem_type = AMDGPU_PL_OA; 189 places[c].flags = 0; 190 c++; 191 } 192 193 if (!c) { 194 places[c].fpfn = 0; 195 places[c].lpfn = 0; 196 places[c].mem_type = TTM_PL_SYSTEM; 197 places[c].flags = 0; 198 c++; 199 } 200 201 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); 202 203 placement->num_placement = c; 204 placement->placement = places; 205 206 placement->num_busy_placement = c; 207 placement->busy_placement = places; 208 } 209 210 /** 211 * amdgpu_bo_create_reserved - create reserved BO for kernel use 212 * 213 * @adev: amdgpu device object 214 * @size: size for the new BO 215 * @align: alignment for the new BO 216 * @domain: where to place it 217 * @bo_ptr: used to initialize BOs in structures 218 * @gpu_addr: GPU addr of the pinned BO 219 * @cpu_addr: optional CPU address mapping 220 * 221 * Allocates and pins a BO for kernel internal use, and returns it still 222 * reserved. 223 * 224 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 225 * 226 * Returns: 227 * 0 on success, negative error code otherwise. 228 */ 229 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 230 unsigned long size, int align, 231 u32 domain, struct amdgpu_bo **bo_ptr, 232 u64 *gpu_addr, void **cpu_addr) 233 { 234 struct amdgpu_bo_param bp; 235 bool free = false; 236 int r; 237 238 if (!size) { 239 amdgpu_bo_unref(bo_ptr); 240 return 0; 241 } 242 243 memset(&bp, 0, sizeof(bp)); 244 bp.size = size; 245 bp.byte_align = align; 246 bp.domain = domain; 247 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 248 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 249 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 250 bp.type = ttm_bo_type_kernel; 251 bp.resv = NULL; 252 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 253 254 if (!*bo_ptr) { 255 r = amdgpu_bo_create(adev, &bp, bo_ptr); 256 if (r) { 257 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 258 r); 259 return r; 260 } 261 free = true; 262 } 263 264 r = amdgpu_bo_reserve(*bo_ptr, false); 265 if (r) { 266 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 267 goto error_free; 268 } 269 270 r = amdgpu_bo_pin(*bo_ptr, domain); 271 if (r) { 272 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 273 goto error_unreserve; 274 } 275 276 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 277 if (r) { 278 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 279 goto error_unpin; 280 } 281 282 if (gpu_addr) 283 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 284 285 if (cpu_addr) { 286 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 287 if (r) { 288 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 289 goto error_unpin; 290 } 291 } 292 293 return 0; 294 295 error_unpin: 296 amdgpu_bo_unpin(*bo_ptr); 297 error_unreserve: 298 amdgpu_bo_unreserve(*bo_ptr); 299 300 error_free: 301 if (free) 302 amdgpu_bo_unref(bo_ptr); 303 304 return r; 305 } 306 307 /** 308 * amdgpu_bo_create_kernel - create BO for kernel use 309 * 310 * @adev: amdgpu device object 311 * @size: size for the new BO 312 * @align: alignment for the new BO 313 * @domain: where to place it 314 * @bo_ptr: used to initialize BOs in structures 315 * @gpu_addr: GPU addr of the pinned BO 316 * @cpu_addr: optional CPU address mapping 317 * 318 * Allocates and pins a BO for kernel internal use. 319 * 320 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 321 * 322 * Returns: 323 * 0 on success, negative error code otherwise. 324 */ 325 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 326 unsigned long size, int align, 327 u32 domain, struct amdgpu_bo **bo_ptr, 328 u64 *gpu_addr, void **cpu_addr) 329 { 330 int r; 331 332 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 333 gpu_addr, cpu_addr); 334 335 if (r) 336 return r; 337 338 if (*bo_ptr) 339 amdgpu_bo_unreserve(*bo_ptr); 340 341 return 0; 342 } 343 344 /** 345 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 346 * 347 * @adev: amdgpu device object 348 * @offset: offset of the BO 349 * @size: size of the BO 350 * @domain: where to place it 351 * @bo_ptr: used to initialize BOs in structures 352 * @cpu_addr: optional CPU address mapping 353 * 354 * Creates a kernel BO at a specific offset in the address space of the domain. 355 * 356 * Returns: 357 * 0 on success, negative error code otherwise. 358 */ 359 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 360 uint64_t offset, uint64_t size, uint32_t domain, 361 struct amdgpu_bo **bo_ptr, void **cpu_addr) 362 { 363 struct ttm_operation_ctx ctx = { false, false }; 364 unsigned int i; 365 int r; 366 367 offset &= LINUX_PAGE_MASK; 368 size = roundup2(size, PAGE_SIZE); 369 370 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr, 371 NULL, cpu_addr); 372 if (r) 373 return r; 374 375 if ((*bo_ptr) == NULL) 376 return 0; 377 378 /* 379 * Remove the original mem node and create a new one at the request 380 * position. 381 */ 382 if (cpu_addr) 383 amdgpu_bo_kunmap(*bo_ptr); 384 385 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource); 386 387 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 388 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 389 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 390 } 391 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 392 &(*bo_ptr)->tbo.resource, &ctx); 393 if (r) 394 goto error; 395 396 if (cpu_addr) { 397 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 398 if (r) 399 goto error; 400 } 401 402 amdgpu_bo_unreserve(*bo_ptr); 403 return 0; 404 405 error: 406 amdgpu_bo_unreserve(*bo_ptr); 407 amdgpu_bo_unref(bo_ptr); 408 return r; 409 } 410 411 /** 412 * amdgpu_bo_free_kernel - free BO for kernel use 413 * 414 * @bo: amdgpu BO to free 415 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 416 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 417 * 418 * unmaps and unpin a BO for kernel internal use. 419 */ 420 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 421 void **cpu_addr) 422 { 423 if (*bo == NULL) 424 return; 425 426 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 427 if (cpu_addr) 428 amdgpu_bo_kunmap(*bo); 429 430 amdgpu_bo_unpin(*bo); 431 amdgpu_bo_unreserve(*bo); 432 } 433 amdgpu_bo_unref(bo); 434 435 if (gpu_addr) 436 *gpu_addr = 0; 437 438 if (cpu_addr) 439 *cpu_addr = NULL; 440 } 441 442 /* Validate bo size is bit bigger then the request domain */ 443 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 444 unsigned long size, u32 domain) 445 { 446 struct ttm_resource_manager *man = NULL; 447 448 /* 449 * If GTT is part of requested domains the check must succeed to 450 * allow fall back to GTT. 451 */ 452 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 453 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT); 454 455 if (man && size < man->size) 456 return true; 457 else if (!man) 458 WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized"); 459 goto fail; 460 } else if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 461 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 462 463 if (man && size < man->size) 464 return true; 465 goto fail; 466 } 467 468 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 469 return true; 470 471 fail: 472 if (man) 473 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 474 man->size); 475 return false; 476 } 477 478 bool amdgpu_bo_support_uswc(u64 bo_flags) 479 { 480 481 #ifdef CONFIG_X86_32 482 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 483 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 484 */ 485 return false; 486 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 487 /* Don't try to enable write-combining when it can't work, or things 488 * may be slow 489 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 490 */ 491 492 #ifndef CONFIG_COMPILE_TEST 493 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 494 thanks to write-combining 495 #endif 496 497 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 498 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 499 "better performance thanks to write-combining\n"); 500 return false; 501 #else 502 /* For architectures that don't support WC memory, 503 * mask out the WC flag from the BO 504 */ 505 if (!drm_arch_can_wc_memory()) 506 return false; 507 508 return true; 509 #endif 510 } 511 512 /** 513 * amdgpu_bo_create - create an &amdgpu_bo buffer object 514 * @adev: amdgpu device object 515 * @bp: parameters to be used for the buffer object 516 * @bo_ptr: pointer to the buffer object pointer 517 * 518 * Creates an &amdgpu_bo buffer object. 519 * 520 * Returns: 521 * 0 for success or a negative error code on failure. 522 */ 523 int amdgpu_bo_create(struct amdgpu_device *adev, 524 struct amdgpu_bo_param *bp, 525 struct amdgpu_bo **bo_ptr) 526 { 527 struct ttm_operation_ctx ctx = { 528 .interruptible = (bp->type != ttm_bo_type_kernel), 529 .no_wait_gpu = bp->no_wait_gpu, 530 /* We opt to avoid OOM on system pages allocations */ 531 .gfp_retry_mayfail = true, 532 .allow_res_evict = bp->type != ttm_bo_type_kernel, 533 .resv = bp->resv 534 }; 535 struct amdgpu_bo *bo; 536 unsigned long page_align, size = bp->size; 537 int r; 538 539 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 540 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 541 /* GWS and OA don't need any alignment. */ 542 page_align = bp->byte_align; 543 size <<= PAGE_SHIFT; 544 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 545 /* Both size and alignment must be a multiple of 4. */ 546 page_align = roundup2(bp->byte_align, 4); 547 size = roundup2(size, 4) << PAGE_SHIFT; 548 } else { 549 /* Memory should be aligned at least to a page size. */ 550 page_align = roundup2(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 551 size = roundup2(size, PAGE_SIZE); 552 } 553 554 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 555 return -ENOMEM; 556 557 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo)); 558 559 *bo_ptr = NULL; 560 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL); 561 if (bo == NULL) 562 return -ENOMEM; 563 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size); 564 bo->adev = adev; 565 bo->vm_bo = NULL; 566 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 567 bp->domain; 568 bo->allowed_domains = bo->preferred_domains; 569 if (bp->type != ttm_bo_type_kernel && 570 !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) && 571 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 572 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 573 574 bo->flags = bp->flags; 575 576 if (!amdgpu_bo_support_uswc(bo->flags)) 577 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 578 579 if (adev->ras_enabled) 580 bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 581 582 bo->tbo.bdev = &adev->mman.bdev; 583 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 584 AMDGPU_GEM_DOMAIN_GDS)) 585 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 586 else 587 amdgpu_bo_placement_from_domain(bo, bp->domain); 588 if (bp->type == ttm_bo_type_kernel) 589 bo->tbo.priority = 1; 590 591 if (!bp->destroy) 592 bp->destroy = &amdgpu_bo_destroy; 593 594 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type, 595 &bo->placement, page_align, &ctx, NULL, 596 bp->resv, bp->destroy); 597 if (unlikely(r != 0)) 598 return r; 599 600 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 601 bo->tbo.resource->mem_type == TTM_PL_VRAM && 602 bo->tbo.resource->start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 603 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 604 ctx.bytes_moved); 605 else 606 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 607 608 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 609 bo->tbo.resource->mem_type == TTM_PL_VRAM) { 610 struct dma_fence *fence; 611 612 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 613 if (unlikely(r)) 614 goto fail_unreserve; 615 616 dma_resv_add_fence(bo->tbo.base.resv, fence, 617 DMA_RESV_USAGE_KERNEL); 618 dma_fence_put(fence); 619 } 620 if (!bp->resv) 621 amdgpu_bo_unreserve(bo); 622 *bo_ptr = bo; 623 624 trace_amdgpu_bo_create(bo); 625 626 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 627 if (bp->type == ttm_bo_type_device) 628 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 629 630 return 0; 631 632 fail_unreserve: 633 if (!bp->resv) 634 dma_resv_unlock(bo->tbo.base.resv); 635 amdgpu_bo_unref(&bo); 636 return r; 637 } 638 639 /** 640 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object 641 * @adev: amdgpu device object 642 * @bp: parameters to be used for the buffer object 643 * @ubo_ptr: pointer to the buffer object pointer 644 * 645 * Create a BO to be used by user application; 646 * 647 * Returns: 648 * 0 for success or a negative error code on failure. 649 */ 650 651 int amdgpu_bo_create_user(struct amdgpu_device *adev, 652 struct amdgpu_bo_param *bp, 653 struct amdgpu_bo_user **ubo_ptr) 654 { 655 struct amdgpu_bo *bo_ptr; 656 int r; 657 658 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user); 659 bp->destroy = &amdgpu_bo_user_destroy; 660 r = amdgpu_bo_create(adev, bp, &bo_ptr); 661 if (r) 662 return r; 663 664 *ubo_ptr = to_amdgpu_bo_user(bo_ptr); 665 return r; 666 } 667 668 /** 669 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object 670 * @adev: amdgpu device object 671 * @bp: parameters to be used for the buffer object 672 * @vmbo_ptr: pointer to the buffer object pointer 673 * 674 * Create a BO to be for GPUVM. 675 * 676 * Returns: 677 * 0 for success or a negative error code on failure. 678 */ 679 680 int amdgpu_bo_create_vm(struct amdgpu_device *adev, 681 struct amdgpu_bo_param *bp, 682 struct amdgpu_bo_vm **vmbo_ptr) 683 { 684 struct amdgpu_bo *bo_ptr; 685 int r; 686 687 /* bo_ptr_size will be determined by the caller and it depends on 688 * num of amdgpu_vm_pt entries. 689 */ 690 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm)); 691 r = amdgpu_bo_create(adev, bp, &bo_ptr); 692 if (r) 693 return r; 694 695 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr); 696 INIT_LIST_HEAD(&(*vmbo_ptr)->shadow_list); 697 /* Set destroy callback to amdgpu_bo_vm_destroy after vmbo->shadow_list 698 * is initialized. 699 */ 700 bo_ptr->tbo.destroy = &amdgpu_bo_vm_destroy; 701 return r; 702 } 703 704 /** 705 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list 706 * 707 * @vmbo: BO that will be inserted into the shadow list 708 * 709 * Insert a BO to the shadow list. 710 */ 711 void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) 712 { 713 struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); 714 715 mutex_lock(&adev->shadow_list_lock); 716 list_add_tail(&vmbo->shadow_list, &adev->shadow_list); 717 mutex_unlock(&adev->shadow_list_lock); 718 } 719 720 /** 721 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 722 * 723 * @shadow: &amdgpu_bo shadow to be restored 724 * @fence: dma_fence associated with the operation 725 * 726 * Copies a buffer object's shadow content back to the object. 727 * This is used for recovering a buffer from its shadow in case of a gpu 728 * reset where vram context may be lost. 729 * 730 * Returns: 731 * 0 for success or a negative error code on failure. 732 */ 733 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 734 735 { 736 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 737 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 738 uint64_t shadow_addr, parent_addr; 739 740 shadow_addr = amdgpu_bo_gpu_offset(shadow); 741 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 742 743 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 744 amdgpu_bo_size(shadow), NULL, fence, 745 true, false, false); 746 } 747 748 /** 749 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 750 * @bo: &amdgpu_bo buffer object to be mapped 751 * @ptr: kernel virtual address to be returned 752 * 753 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 754 * amdgpu_bo_kptr() to get the kernel virtual address. 755 * 756 * Returns: 757 * 0 for success or a negative error code on failure. 758 */ 759 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 760 { 761 void *kptr; 762 long r; 763 764 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 765 return -EPERM; 766 767 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, 768 false, MAX_SCHEDULE_TIMEOUT); 769 if (r < 0) 770 return r; 771 772 kptr = amdgpu_bo_kptr(bo); 773 if (kptr) { 774 if (ptr) 775 *ptr = kptr; 776 return 0; 777 } 778 779 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.resource->num_pages, &bo->kmap); 780 if (r) 781 return r; 782 783 if (ptr) 784 *ptr = amdgpu_bo_kptr(bo); 785 786 return 0; 787 } 788 789 /** 790 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 791 * @bo: &amdgpu_bo buffer object 792 * 793 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 794 * 795 * Returns: 796 * the virtual address of a buffer object area. 797 */ 798 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 799 { 800 bool is_iomem; 801 802 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 803 } 804 805 /** 806 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 807 * @bo: &amdgpu_bo buffer object to be unmapped 808 * 809 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 810 */ 811 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 812 { 813 if (bo->kmap.bo) 814 ttm_bo_kunmap(&bo->kmap); 815 } 816 817 /** 818 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 819 * @bo: &amdgpu_bo buffer object 820 * 821 * References the contained &ttm_buffer_object. 822 * 823 * Returns: 824 * a refcounted pointer to the &amdgpu_bo buffer object. 825 */ 826 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 827 { 828 if (bo == NULL) 829 return NULL; 830 831 ttm_bo_get(&bo->tbo); 832 return bo; 833 } 834 835 /** 836 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 837 * @bo: &amdgpu_bo buffer object 838 * 839 * Unreferences the contained &ttm_buffer_object and clear the pointer 840 */ 841 void amdgpu_bo_unref(struct amdgpu_bo **bo) 842 { 843 struct ttm_buffer_object *tbo; 844 845 if ((*bo) == NULL) 846 return; 847 848 tbo = &((*bo)->tbo); 849 ttm_bo_put(tbo); 850 *bo = NULL; 851 } 852 853 /** 854 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 855 * @bo: &amdgpu_bo buffer object to be pinned 856 * @domain: domain to be pinned to 857 * @min_offset: the start of requested address range 858 * @max_offset: the end of requested address range 859 * 860 * Pins the buffer object according to requested domain and address range. If 861 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 862 * pin_count and pin_size accordingly. 863 * 864 * Pinning means to lock pages in memory along with keeping them at a fixed 865 * offset. It is required when a buffer can not be moved, for example, when 866 * a display buffer is being scanned out. 867 * 868 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 869 * where to pin a buffer if there are specific restrictions on where a buffer 870 * must be located. 871 * 872 * Returns: 873 * 0 for success or a negative error code on failure. 874 */ 875 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 876 u64 min_offset, u64 max_offset) 877 { 878 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 879 struct ttm_operation_ctx ctx = { false, false }; 880 int r, i; 881 882 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 883 return -EPERM; 884 885 if (WARN_ON_ONCE(min_offset > max_offset)) 886 return -EINVAL; 887 888 /* Check domain to be pinned to against preferred domains */ 889 if (bo->preferred_domains & domain) 890 domain = bo->preferred_domains & domain; 891 892 /* A shared bo cannot be migrated to VRAM */ 893 if (bo->tbo.base.import_attach) { 894 if (domain & AMDGPU_GEM_DOMAIN_GTT) 895 domain = AMDGPU_GEM_DOMAIN_GTT; 896 else 897 return -EINVAL; 898 } 899 900 if (bo->tbo.pin_count) { 901 uint32_t mem_type = bo->tbo.resource->mem_type; 902 uint32_t mem_flags = bo->tbo.resource->placement; 903 904 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 905 return -EINVAL; 906 907 if ((mem_type == TTM_PL_VRAM) && 908 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) && 909 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS)) 910 return -EINVAL; 911 912 ttm_bo_pin(&bo->tbo); 913 914 if (max_offset != 0) { 915 u64 domain_start = amdgpu_ttm_domain_start(adev, 916 mem_type); 917 WARN_ON_ONCE(max_offset < 918 (amdgpu_bo_gpu_offset(bo) - domain_start)); 919 } 920 921 return 0; 922 } 923 924 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 925 * See function amdgpu_display_supported_domains() 926 */ 927 domain = amdgpu_bo_get_preferred_domain(adev, domain); 928 929 #ifdef notyet 930 if (bo->tbo.base.import_attach) 931 dma_buf_pin(bo->tbo.base.import_attach); 932 #endif 933 934 /* force to pin into visible video ram */ 935 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 936 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 937 amdgpu_bo_placement_from_domain(bo, domain); 938 for (i = 0; i < bo->placement.num_placement; i++) { 939 unsigned fpfn, lpfn; 940 941 fpfn = min_offset >> PAGE_SHIFT; 942 lpfn = max_offset >> PAGE_SHIFT; 943 944 if (fpfn > bo->placements[i].fpfn) 945 bo->placements[i].fpfn = fpfn; 946 if (!bo->placements[i].lpfn || 947 (lpfn && lpfn < bo->placements[i].lpfn)) 948 bo->placements[i].lpfn = lpfn; 949 } 950 951 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 952 if (unlikely(r)) { 953 dev_err(adev->dev, "%p pin failed\n", bo); 954 goto error; 955 } 956 957 ttm_bo_pin(&bo->tbo); 958 959 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 960 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 961 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 962 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 963 &adev->visible_pin_size); 964 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 965 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 966 } 967 968 error: 969 return r; 970 } 971 972 /** 973 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 974 * @bo: &amdgpu_bo buffer object to be pinned 975 * @domain: domain to be pinned to 976 * 977 * A simple wrapper to amdgpu_bo_pin_restricted(). 978 * Provides a simpler API for buffers that do not have any strict restrictions 979 * on where a buffer must be located. 980 * 981 * Returns: 982 * 0 for success or a negative error code on failure. 983 */ 984 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 985 { 986 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 987 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 988 } 989 990 /** 991 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 992 * @bo: &amdgpu_bo buffer object to be unpinned 993 * 994 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 995 * Changes placement and pin size accordingly. 996 * 997 * Returns: 998 * 0 for success or a negative error code on failure. 999 */ 1000 void amdgpu_bo_unpin(struct amdgpu_bo *bo) 1001 { 1002 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1003 1004 ttm_bo_unpin(&bo->tbo); 1005 if (bo->tbo.pin_count) 1006 return; 1007 1008 #ifdef notyet 1009 if (bo->tbo.base.import_attach) 1010 dma_buf_unpin(bo->tbo.base.import_attach); 1011 #endif 1012 1013 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { 1014 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 1015 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 1016 &adev->visible_pin_size); 1017 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) { 1018 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 1019 } 1020 } 1021 1022 static const char *amdgpu_vram_names[] = { 1023 "UNKNOWN", 1024 "GDDR1", 1025 "DDR2", 1026 "GDDR3", 1027 "GDDR4", 1028 "GDDR5", 1029 "HBM", 1030 "DDR3", 1031 "DDR4", 1032 "GDDR6", 1033 "DDR5", 1034 "LPDDR4", 1035 "LPDDR5" 1036 }; 1037 1038 /** 1039 * amdgpu_bo_init - initialize memory manager 1040 * @adev: amdgpu device object 1041 * 1042 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1043 * 1044 * Returns: 1045 * 0 for success or a negative error code on failure. 1046 */ 1047 int amdgpu_bo_init(struct amdgpu_device *adev) 1048 { 1049 /* On A+A platform, VRAM can be mapped as WB */ 1050 if (!adev->gmc.xgmi.connected_to_cpu) { 1051 #ifdef __linux__ 1052 /* reserve PAT memory space to WC for VRAM */ 1053 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1054 adev->gmc.aper_size); 1055 1056 if (r) { 1057 DRM_ERROR("Unable to set WC memtype for the aperture base\n"); 1058 return r; 1059 } 1060 1061 /* Add an MTRR for the VRAM */ 1062 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1063 adev->gmc.aper_size); 1064 #else 1065 paddr_t start, end; 1066 1067 drm_mtrr_add(adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC); 1068 1069 start = atop(bus_space_mmap(adev->memt, adev->gmc.aper_base, 0, 0, 0)); 1070 end = start + atop(adev->gmc.aper_size); 1071 uvm_page_physload(start, end, start, end, PHYSLOAD_DEVICE); 1072 #endif 1073 } 1074 1075 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1076 adev->gmc.mc_vram_size >> 20, 1077 (unsigned long long)adev->gmc.aper_size >> 20); 1078 DRM_INFO("RAM width %dbits %s\n", 1079 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1080 return amdgpu_ttm_init(adev); 1081 } 1082 1083 /** 1084 * amdgpu_bo_fini - tear down memory manager 1085 * @adev: amdgpu device object 1086 * 1087 * Reverses amdgpu_bo_init() to tear down memory manager. 1088 */ 1089 void amdgpu_bo_fini(struct amdgpu_device *adev) 1090 { 1091 int idx; 1092 1093 amdgpu_ttm_fini(adev); 1094 1095 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 1096 1097 if (!adev->gmc.xgmi.connected_to_cpu) { 1098 #ifdef __linux__ 1099 arch_phys_wc_del(adev->gmc.vram_mtrr); 1100 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1101 #else 1102 drm_mtrr_del(0, adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC); 1103 1104 #endif 1105 } 1106 drm_dev_exit(idx); 1107 } 1108 } 1109 1110 /** 1111 * amdgpu_bo_set_tiling_flags - set tiling flags 1112 * @bo: &amdgpu_bo buffer object 1113 * @tiling_flags: new flags 1114 * 1115 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1116 * kernel driver to set the tiling flags on a buffer. 1117 * 1118 * Returns: 1119 * 0 for success or a negative error code on failure. 1120 */ 1121 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1122 { 1123 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1124 struct amdgpu_bo_user *ubo; 1125 1126 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1127 if (adev->family <= AMDGPU_FAMILY_CZ && 1128 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1129 return -EINVAL; 1130 1131 ubo = to_amdgpu_bo_user(bo); 1132 ubo->tiling_flags = tiling_flags; 1133 return 0; 1134 } 1135 1136 /** 1137 * amdgpu_bo_get_tiling_flags - get tiling flags 1138 * @bo: &amdgpu_bo buffer object 1139 * @tiling_flags: returned flags 1140 * 1141 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1142 * set the tiling flags on a buffer. 1143 */ 1144 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1145 { 1146 struct amdgpu_bo_user *ubo; 1147 1148 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1149 dma_resv_assert_held(bo->tbo.base.resv); 1150 ubo = to_amdgpu_bo_user(bo); 1151 1152 if (tiling_flags) 1153 *tiling_flags = ubo->tiling_flags; 1154 } 1155 1156 /** 1157 * amdgpu_bo_set_metadata - set metadata 1158 * @bo: &amdgpu_bo buffer object 1159 * @metadata: new metadata 1160 * @metadata_size: size of the new metadata 1161 * @flags: flags of the new metadata 1162 * 1163 * Sets buffer object's metadata, its size and flags. 1164 * Used via GEM ioctl. 1165 * 1166 * Returns: 1167 * 0 for success or a negative error code on failure. 1168 */ 1169 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1170 uint32_t metadata_size, uint64_t flags) 1171 { 1172 struct amdgpu_bo_user *ubo; 1173 void *buffer; 1174 1175 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1176 ubo = to_amdgpu_bo_user(bo); 1177 if (!metadata_size) { 1178 if (ubo->metadata_size) { 1179 kfree(ubo->metadata); 1180 ubo->metadata = NULL; 1181 ubo->metadata_size = 0; 1182 } 1183 return 0; 1184 } 1185 1186 if (metadata == NULL) 1187 return -EINVAL; 1188 1189 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1190 if (buffer == NULL) 1191 return -ENOMEM; 1192 1193 kfree(ubo->metadata); 1194 ubo->metadata_flags = flags; 1195 ubo->metadata = buffer; 1196 ubo->metadata_size = metadata_size; 1197 1198 return 0; 1199 } 1200 1201 /** 1202 * amdgpu_bo_get_metadata - get metadata 1203 * @bo: &amdgpu_bo buffer object 1204 * @buffer: returned metadata 1205 * @buffer_size: size of the buffer 1206 * @metadata_size: size of the returned metadata 1207 * @flags: flags of the returned metadata 1208 * 1209 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1210 * less than metadata_size. 1211 * Used via GEM ioctl. 1212 * 1213 * Returns: 1214 * 0 for success or a negative error code on failure. 1215 */ 1216 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1217 size_t buffer_size, uint32_t *metadata_size, 1218 uint64_t *flags) 1219 { 1220 struct amdgpu_bo_user *ubo; 1221 1222 if (!buffer && !metadata_size) 1223 return -EINVAL; 1224 1225 BUG_ON(bo->tbo.type == ttm_bo_type_kernel); 1226 ubo = to_amdgpu_bo_user(bo); 1227 if (metadata_size) 1228 *metadata_size = ubo->metadata_size; 1229 1230 if (buffer) { 1231 if (buffer_size < ubo->metadata_size) 1232 return -EINVAL; 1233 1234 if (ubo->metadata_size) 1235 memcpy(buffer, ubo->metadata, ubo->metadata_size); 1236 } 1237 1238 if (flags) 1239 *flags = ubo->metadata_flags; 1240 1241 return 0; 1242 } 1243 1244 /** 1245 * amdgpu_bo_move_notify - notification about a memory move 1246 * @bo: pointer to a buffer object 1247 * @evict: if this move is evicting the buffer from the graphics address space 1248 * @new_mem: new information of the bufer object 1249 * 1250 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1251 * bookkeeping. 1252 * TTM driver callback which is called when ttm moves a buffer. 1253 */ 1254 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1255 bool evict, 1256 struct ttm_resource *new_mem) 1257 { 1258 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1259 struct amdgpu_bo *abo; 1260 struct ttm_resource *old_mem = bo->resource; 1261 1262 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1263 return; 1264 1265 abo = ttm_to_amdgpu_bo(bo); 1266 amdgpu_vm_bo_invalidate(adev, abo, evict); 1267 1268 amdgpu_bo_kunmap(abo); 1269 1270 #ifdef notyet 1271 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1272 bo->resource->mem_type != TTM_PL_SYSTEM) 1273 dma_buf_move_notify(abo->tbo.base.dma_buf); 1274 #endif 1275 1276 /* remember the eviction */ 1277 if (evict) 1278 atomic64_inc(&adev->num_evictions); 1279 1280 /* update statistics */ 1281 if (!new_mem) 1282 return; 1283 1284 /* move_notify is called before move happens */ 1285 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1286 } 1287 1288 void amdgpu_bo_get_memory(struct amdgpu_bo *bo, uint64_t *vram_mem, 1289 uint64_t *gtt_mem, uint64_t *cpu_mem) 1290 { 1291 unsigned int domain; 1292 1293 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1294 switch (domain) { 1295 case AMDGPU_GEM_DOMAIN_VRAM: 1296 *vram_mem += amdgpu_bo_size(bo); 1297 break; 1298 case AMDGPU_GEM_DOMAIN_GTT: 1299 *gtt_mem += amdgpu_bo_size(bo); 1300 break; 1301 case AMDGPU_GEM_DOMAIN_CPU: 1302 default: 1303 *cpu_mem += amdgpu_bo_size(bo); 1304 break; 1305 } 1306 } 1307 1308 /** 1309 * amdgpu_bo_release_notify - notification about a BO being released 1310 * @bo: pointer to a buffer object 1311 * 1312 * Wipes VRAM buffers whose contents should not be leaked before the 1313 * memory is released. 1314 */ 1315 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1316 { 1317 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1318 struct dma_fence *fence = NULL; 1319 struct amdgpu_bo *abo; 1320 int r; 1321 1322 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1323 return; 1324 1325 abo = ttm_to_amdgpu_bo(bo); 1326 1327 if (abo->kfd_bo) 1328 amdgpu_amdkfd_release_notify(abo); 1329 1330 /* We only remove the fence if the resv has individualized. */ 1331 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1332 && bo->base.resv != &bo->base._resv); 1333 if (bo->base.resv == &bo->base._resv) 1334 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1335 1336 if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM || 1337 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) || 1338 adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev))) 1339 return; 1340 1341 if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv))) 1342 return; 1343 1344 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1345 if (!WARN_ON(r)) { 1346 amdgpu_bo_fence(abo, fence, false); 1347 dma_fence_put(fence); 1348 } 1349 1350 dma_resv_unlock(bo->base.resv); 1351 } 1352 1353 /** 1354 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1355 * @bo: pointer to a buffer object 1356 * 1357 * Notifies the driver we are taking a fault on this BO and have reserved it, 1358 * also performs bookkeeping. 1359 * TTM driver callback for dealing with vm faults. 1360 * 1361 * Returns: 1362 * 0 for success or a negative error code on failure. 1363 */ 1364 vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1365 { 1366 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1367 struct ttm_operation_ctx ctx = { false, false }; 1368 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); 1369 unsigned long offset; 1370 int r; 1371 1372 /* Remember that this BO was accessed by the CPU */ 1373 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1374 1375 if (bo->resource->mem_type != TTM_PL_VRAM) 1376 return 0; 1377 1378 offset = bo->resource->start << PAGE_SHIFT; 1379 if ((offset + bo->base.size) <= adev->gmc.visible_vram_size) 1380 return 0; 1381 1382 /* Can't move a pinned BO to visible VRAM */ 1383 if (abo->tbo.pin_count > 0) 1384 return VM_FAULT_SIGBUS; 1385 1386 /* hurrah the memory is not visible ! */ 1387 atomic64_inc(&adev->num_vram_cpu_page_faults); 1388 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1389 AMDGPU_GEM_DOMAIN_GTT); 1390 1391 /* Avoid costly evictions; only set GTT as a busy placement */ 1392 abo->placement.num_busy_placement = 1; 1393 abo->placement.busy_placement = &abo->placements[1]; 1394 1395 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1396 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 1397 return VM_FAULT_NOPAGE; 1398 else if (unlikely(r)) 1399 return VM_FAULT_SIGBUS; 1400 1401 offset = bo->resource->start << PAGE_SHIFT; 1402 /* this should never happen */ 1403 if (bo->resource->mem_type == TTM_PL_VRAM && 1404 (offset + bo->base.size) > adev->gmc.visible_vram_size) 1405 return VM_FAULT_SIGBUS; 1406 1407 ttm_bo_move_to_lru_tail_unlocked(bo); 1408 return 0; 1409 } 1410 1411 /** 1412 * amdgpu_bo_fence - add fence to buffer object 1413 * 1414 * @bo: buffer object in question 1415 * @fence: fence to add 1416 * @shared: true if fence should be added shared 1417 * 1418 */ 1419 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1420 bool shared) 1421 { 1422 struct dma_resv *resv = bo->tbo.base.resv; 1423 int r; 1424 1425 r = dma_resv_reserve_fences(resv, 1); 1426 if (r) { 1427 /* As last resort on OOM we block for the fence */ 1428 dma_fence_wait(fence, false); 1429 return; 1430 } 1431 1432 dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ : 1433 DMA_RESV_USAGE_WRITE); 1434 } 1435 1436 /** 1437 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1438 * 1439 * @adev: amdgpu device pointer 1440 * @resv: reservation object to sync to 1441 * @sync_mode: synchronization mode 1442 * @owner: fence owner 1443 * @intr: Whether the wait is interruptible 1444 * 1445 * Extract the fences from the reservation object and waits for them to finish. 1446 * 1447 * Returns: 1448 * 0 on success, errno otherwise. 1449 */ 1450 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1451 enum amdgpu_sync_mode sync_mode, void *owner, 1452 bool intr) 1453 { 1454 struct amdgpu_sync sync; 1455 int r; 1456 1457 amdgpu_sync_create(&sync); 1458 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1459 r = amdgpu_sync_wait(&sync, intr); 1460 amdgpu_sync_free(&sync); 1461 return r; 1462 } 1463 1464 /** 1465 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1466 * @bo: buffer object to wait for 1467 * @owner: fence owner 1468 * @intr: Whether the wait is interruptible 1469 * 1470 * Wrapper to wait for fences in a BO. 1471 * Returns: 1472 * 0 on success, errno otherwise. 1473 */ 1474 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1475 { 1476 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1477 1478 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1479 AMDGPU_SYNC_NE_OWNER, owner, intr); 1480 } 1481 1482 /** 1483 * amdgpu_bo_gpu_offset - return GPU offset of bo 1484 * @bo: amdgpu object for which we query the offset 1485 * 1486 * Note: object should either be pinned or reserved when calling this 1487 * function, it might be useful to add check for this for debugging. 1488 * 1489 * Returns: 1490 * current GPU offset of the object. 1491 */ 1492 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1493 { 1494 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); 1495 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1496 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); 1497 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); 1498 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && 1499 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1500 1501 return amdgpu_bo_gpu_offset_no_check(bo); 1502 } 1503 1504 /** 1505 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo 1506 * @bo: amdgpu object for which we query the offset 1507 * 1508 * Returns: 1509 * current GPU offset of the object without raising warnings. 1510 */ 1511 u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo) 1512 { 1513 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1514 uint64_t offset; 1515 1516 offset = (bo->tbo.resource->start << PAGE_SHIFT) + 1517 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type); 1518 1519 return amdgpu_gmc_sign_extend(offset); 1520 } 1521 1522 /** 1523 * amdgpu_bo_get_preferred_domain - get preferred domain 1524 * @adev: amdgpu device object 1525 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1526 * 1527 * Returns: 1528 * Which of the allowed domains is preferred for allocating the BO. 1529 */ 1530 uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, 1531 uint32_t domain) 1532 { 1533 if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) && 1534 ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) { 1535 domain = AMDGPU_GEM_DOMAIN_VRAM; 1536 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1537 domain = AMDGPU_GEM_DOMAIN_GTT; 1538 } 1539 return domain; 1540 } 1541 1542 #if defined(CONFIG_DEBUG_FS) 1543 #define amdgpu_bo_print_flag(m, bo, flag) \ 1544 do { \ 1545 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \ 1546 seq_printf((m), " " #flag); \ 1547 } \ 1548 } while (0) 1549 1550 /** 1551 * amdgpu_bo_print_info - print BO info in debugfs file 1552 * 1553 * @id: Index or Id of the BO 1554 * @bo: Requested BO for printing info 1555 * @m: debugfs file 1556 * 1557 * Print BO information in debugfs file 1558 * 1559 * Returns: 1560 * Size of the BO in bytes. 1561 */ 1562 u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) 1563 { 1564 struct dma_buf_attachment *attachment; 1565 struct dma_buf *dma_buf; 1566 unsigned int domain; 1567 const char *placement; 1568 unsigned int pin_count; 1569 u64 size; 1570 1571 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type); 1572 switch (domain) { 1573 case AMDGPU_GEM_DOMAIN_VRAM: 1574 placement = "VRAM"; 1575 break; 1576 case AMDGPU_GEM_DOMAIN_GTT: 1577 placement = " GTT"; 1578 break; 1579 case AMDGPU_GEM_DOMAIN_CPU: 1580 default: 1581 placement = " CPU"; 1582 break; 1583 } 1584 1585 size = amdgpu_bo_size(bo); 1586 seq_printf(m, "\t\t0x%08x: %12lld byte %s", 1587 id, size, placement); 1588 1589 pin_count = READ_ONCE(bo->tbo.pin_count); 1590 if (pin_count) 1591 seq_printf(m, " pin count %d", pin_count); 1592 1593 dma_buf = READ_ONCE(bo->tbo.base.dma_buf); 1594 attachment = READ_ONCE(bo->tbo.base.import_attach); 1595 1596 if (attachment) 1597 seq_printf(m, " imported from %p", dma_buf); 1598 else if (dma_buf) 1599 seq_printf(m, " exported as %p", dma_buf); 1600 1601 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED); 1602 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS); 1603 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC); 1604 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED); 1605 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS); 1606 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID); 1607 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC); 1608 1609 seq_puts(m, "\n"); 1610 1611 return size; 1612 } 1613 #endif 1614