1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <linux/dma-buf.h> 35 36 #include <drm/amdgpu_drm.h> 37 #include <drm/drm_cache.h> 38 #include "amdgpu.h" 39 #include "amdgpu_trace.h" 40 #include "amdgpu_amdkfd.h" 41 42 /** 43 * DOC: amdgpu_object 44 * 45 * This defines the interfaces to operate on an &amdgpu_bo buffer object which 46 * represents memory used by driver (VRAM, system memory, etc.). The driver 47 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces 48 * to create/destroy/set buffer object which are then managed by the kernel TTM 49 * memory manager. 50 * The interfaces are also used internally by kernel clients, including gfx, 51 * uvd, etc. for kernel managed allocations used by the GPU. 52 * 53 */ 54 55 /** 56 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting 57 * 58 * @bo: &amdgpu_bo buffer object 59 * 60 * This function is called when a BO stops being pinned, and updates the 61 * &amdgpu_device pin_size values accordingly. 62 */ 63 static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo) 64 { 65 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 66 67 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) { 68 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); 69 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo), 70 &adev->visible_pin_size); 71 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) { 72 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size); 73 } 74 } 75 76 static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) 77 { 78 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); 79 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); 80 81 if (bo->pin_count > 0) 82 amdgpu_bo_subtract_pin_size(bo); 83 84 amdgpu_bo_kunmap(bo); 85 86 if (bo->tbo.base.import_attach) 87 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 88 drm_gem_object_release(&bo->tbo.base); 89 /* in case amdgpu_device_recover_vram got NULL of bo->parent */ 90 if (!list_empty(&bo->shadow_list)) { 91 mutex_lock(&adev->shadow_list_lock); 92 list_del_init(&bo->shadow_list); 93 mutex_unlock(&adev->shadow_list_lock); 94 } 95 amdgpu_bo_unref(&bo->parent); 96 97 kfree(bo->metadata); 98 pool_put(&bo->adev->ddev->objpl, bo); 99 } 100 101 /** 102 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo 103 * @bo: buffer object to be checked 104 * 105 * Uses destroy function associated with the object to determine if this is 106 * an &amdgpu_bo. 107 * 108 * Returns: 109 * true if the object belongs to &amdgpu_bo, false if not. 110 */ 111 bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 112 { 113 if (bo->destroy == &amdgpu_bo_destroy) 114 return true; 115 return false; 116 } 117 118 /** 119 * amdgpu_bo_placement_from_domain - set buffer's placement 120 * @abo: &amdgpu_bo buffer object whose placement is to be set 121 * @domain: requested domain 122 * 123 * Sets buffer's placement according to requested domain and the buffer's 124 * flags. 125 */ 126 void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 127 { 128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); 129 struct ttm_placement *placement = &abo->placement; 130 struct ttm_place *places = abo->placements; 131 u64 flags = abo->flags; 132 u32 c = 0; 133 134 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 135 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; 136 137 places[c].fpfn = 0; 138 places[c].lpfn = 0; 139 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 140 TTM_PL_FLAG_VRAM; 141 142 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 143 places[c].lpfn = visible_pfn; 144 else 145 places[c].flags |= TTM_PL_FLAG_TOPDOWN; 146 147 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) 148 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS; 149 c++; 150 } 151 152 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 153 places[c].fpfn = 0; 154 places[c].lpfn = 0; 155 places[c].flags = TTM_PL_FLAG_TT; 156 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 157 places[c].flags |= TTM_PL_FLAG_WC | 158 TTM_PL_FLAG_UNCACHED; 159 else 160 places[c].flags |= TTM_PL_FLAG_CACHED; 161 c++; 162 } 163 164 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 165 places[c].fpfn = 0; 166 places[c].lpfn = 0; 167 places[c].flags = TTM_PL_FLAG_SYSTEM; 168 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 169 places[c].flags |= TTM_PL_FLAG_WC | 170 TTM_PL_FLAG_UNCACHED; 171 else 172 places[c].flags |= TTM_PL_FLAG_CACHED; 173 c++; 174 } 175 176 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 177 places[c].fpfn = 0; 178 places[c].lpfn = 0; 179 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS; 180 c++; 181 } 182 183 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 184 places[c].fpfn = 0; 185 places[c].lpfn = 0; 186 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS; 187 c++; 188 } 189 190 if (domain & AMDGPU_GEM_DOMAIN_OA) { 191 places[c].fpfn = 0; 192 places[c].lpfn = 0; 193 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA; 194 c++; 195 } 196 197 if (!c) { 198 places[c].fpfn = 0; 199 places[c].lpfn = 0; 200 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 201 c++; 202 } 203 204 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS); 205 206 placement->num_placement = c; 207 placement->placement = places; 208 209 placement->num_busy_placement = c; 210 placement->busy_placement = places; 211 } 212 213 /** 214 * amdgpu_bo_create_reserved - create reserved BO for kernel use 215 * 216 * @adev: amdgpu device object 217 * @size: size for the new BO 218 * @align: alignment for the new BO 219 * @domain: where to place it 220 * @bo_ptr: used to initialize BOs in structures 221 * @gpu_addr: GPU addr of the pinned BO 222 * @cpu_addr: optional CPU address mapping 223 * 224 * Allocates and pins a BO for kernel internal use, and returns it still 225 * reserved. 226 * 227 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 228 * 229 * Returns: 230 * 0 on success, negative error code otherwise. 231 */ 232 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, 233 unsigned long size, int align, 234 u32 domain, struct amdgpu_bo **bo_ptr, 235 u64 *gpu_addr, void **cpu_addr) 236 { 237 struct amdgpu_bo_param bp; 238 bool free = false; 239 int r; 240 241 if (!size) { 242 amdgpu_bo_unref(bo_ptr); 243 return 0; 244 } 245 246 memset(&bp, 0, sizeof(bp)); 247 bp.size = size; 248 bp.byte_align = align; 249 bp.domain = domain; 250 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED 251 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 252 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 253 bp.type = ttm_bo_type_kernel; 254 bp.resv = NULL; 255 256 if (!*bo_ptr) { 257 r = amdgpu_bo_create(adev, &bp, bo_ptr); 258 if (r) { 259 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", 260 r); 261 return r; 262 } 263 free = true; 264 } 265 266 r = amdgpu_bo_reserve(*bo_ptr, false); 267 if (r) { 268 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r); 269 goto error_free; 270 } 271 272 r = amdgpu_bo_pin(*bo_ptr, domain); 273 if (r) { 274 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 275 goto error_unreserve; 276 } 277 278 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo); 279 if (r) { 280 dev_err(adev->dev, "%p bind failed\n", *bo_ptr); 281 goto error_unpin; 282 } 283 284 if (gpu_addr) 285 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr); 286 287 if (cpu_addr) { 288 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 289 if (r) { 290 dev_err(adev->dev, "(%d) kernel bo map failed\n", r); 291 goto error_unpin; 292 } 293 } 294 295 return 0; 296 297 error_unpin: 298 amdgpu_bo_unpin(*bo_ptr); 299 error_unreserve: 300 amdgpu_bo_unreserve(*bo_ptr); 301 302 error_free: 303 if (free) 304 amdgpu_bo_unref(bo_ptr); 305 306 return r; 307 } 308 309 /** 310 * amdgpu_bo_create_kernel - create BO for kernel use 311 * 312 * @adev: amdgpu device object 313 * @size: size for the new BO 314 * @align: alignment for the new BO 315 * @domain: where to place it 316 * @bo_ptr: used to initialize BOs in structures 317 * @gpu_addr: GPU addr of the pinned BO 318 * @cpu_addr: optional CPU address mapping 319 * 320 * Allocates and pins a BO for kernel internal use. 321 * 322 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL. 323 * 324 * Returns: 325 * 0 on success, negative error code otherwise. 326 */ 327 int amdgpu_bo_create_kernel(struct amdgpu_device *adev, 328 unsigned long size, int align, 329 u32 domain, struct amdgpu_bo **bo_ptr, 330 u64 *gpu_addr, void **cpu_addr) 331 { 332 int r; 333 334 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr, 335 gpu_addr, cpu_addr); 336 337 if (r) 338 return r; 339 340 if (*bo_ptr) 341 amdgpu_bo_unreserve(*bo_ptr); 342 343 return 0; 344 } 345 346 /** 347 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location 348 * 349 * @adev: amdgpu device object 350 * @offset: offset of the BO 351 * @size: size of the BO 352 * @domain: where to place it 353 * @bo_ptr: used to initialize BOs in structures 354 * @cpu_addr: optional CPU address mapping 355 * 356 * Creates a kernel BO at a specific offset in the address space of the domain. 357 * 358 * Returns: 359 * 0 on success, negative error code otherwise. 360 */ 361 int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev, 362 uint64_t offset, uint64_t size, uint32_t domain, 363 struct amdgpu_bo **bo_ptr, void **cpu_addr) 364 { 365 struct ttm_operation_ctx ctx = { false, false }; 366 unsigned int i; 367 int r; 368 369 offset &= ~PAGE_MASK; 370 size = roundup2(size, PAGE_SIZE); 371 372 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr, 373 NULL, cpu_addr); 374 if (r) 375 return r; 376 377 /* 378 * Remove the original mem node and create a new one at the request 379 * position. 380 */ 381 if (cpu_addr) 382 amdgpu_bo_kunmap(*bo_ptr); 383 384 ttm_bo_mem_put(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem); 385 386 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) { 387 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT; 388 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT; 389 } 390 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement, 391 &(*bo_ptr)->tbo.mem, &ctx); 392 if (r) 393 goto error; 394 395 if (cpu_addr) { 396 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 397 if (r) 398 goto error; 399 } 400 401 amdgpu_bo_unreserve(*bo_ptr); 402 return 0; 403 404 error: 405 amdgpu_bo_unreserve(*bo_ptr); 406 amdgpu_bo_unref(bo_ptr); 407 return r; 408 } 409 410 /** 411 * amdgpu_bo_free_kernel - free BO for kernel use 412 * 413 * @bo: amdgpu BO to free 414 * @gpu_addr: pointer to where the BO's GPU memory space address was stored 415 * @cpu_addr: pointer to where the BO's CPU memory space address was stored 416 * 417 * unmaps and unpin a BO for kernel internal use. 418 */ 419 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 420 void **cpu_addr) 421 { 422 if (*bo == NULL) 423 return; 424 425 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) { 426 if (cpu_addr) 427 amdgpu_bo_kunmap(*bo); 428 429 amdgpu_bo_unpin(*bo); 430 amdgpu_bo_unreserve(*bo); 431 } 432 amdgpu_bo_unref(bo); 433 434 if (gpu_addr) 435 *gpu_addr = 0; 436 437 if (cpu_addr) 438 *cpu_addr = NULL; 439 } 440 441 /* Validate bo size is bit bigger then the request domain */ 442 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 443 unsigned long size, u32 domain) 444 { 445 struct ttm_mem_type_manager *man = NULL; 446 447 /* 448 * If GTT is part of requested domains the check must succeed to 449 * allow fall back to GTT 450 */ 451 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 452 man = &adev->mman.bdev.man[TTM_PL_TT]; 453 454 if (size < (man->size << PAGE_SHIFT)) 455 return true; 456 else 457 goto fail; 458 } 459 460 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 461 man = &adev->mman.bdev.man[TTM_PL_VRAM]; 462 463 if (size < (man->size << PAGE_SHIFT)) 464 return true; 465 else 466 goto fail; 467 } 468 469 470 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */ 471 return true; 472 473 fail: 474 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, 475 man->size << PAGE_SHIFT); 476 return false; 477 } 478 479 bool amdgpu_bo_support_uswc(u64 bo_flags) 480 { 481 482 #ifdef CONFIG_X86_32 483 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 484 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 485 */ 486 return false; 487 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 488 /* Don't try to enable write-combining when it can't work, or things 489 * may be slow 490 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 491 */ 492 493 #ifndef CONFIG_COMPILE_TEST 494 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 495 thanks to write-combining 496 #endif 497 498 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) 499 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 500 "better performance thanks to write-combining\n"); 501 return false; 502 #else 503 /* For architectures that don't support WC memory, 504 * mask out the WC flag from the BO 505 */ 506 if (!drm_arch_can_wc_memory()) 507 return false; 508 509 return true; 510 #endif 511 } 512 513 static int amdgpu_bo_do_create(struct amdgpu_device *adev, 514 struct amdgpu_bo_param *bp, 515 struct amdgpu_bo **bo_ptr) 516 { 517 struct ttm_operation_ctx ctx = { 518 .interruptible = (bp->type != ttm_bo_type_kernel), 519 .no_wait_gpu = bp->no_wait_gpu, 520 .resv = bp->resv, 521 .flags = bp->type != ttm_bo_type_kernel ? 522 TTM_OPT_FLAG_ALLOW_RES_EVICT : 0 523 }; 524 struct amdgpu_bo *bo; 525 unsigned long page_align, size = bp->size; 526 size_t acc_size; 527 int r; 528 529 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */ 530 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 531 /* GWS and OA don't need any alignment. */ 532 page_align = bp->byte_align; 533 size <<= PAGE_SHIFT; 534 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) { 535 /* Both size and alignment must be a multiple of 4. */ 536 page_align = roundup2(bp->byte_align, 4); 537 size = roundup2(size, 4) << PAGE_SHIFT; 538 } else { 539 /* Memory should be aligned at least to a page size. */ 540 page_align = roundup2(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 541 size = roundup2(size, PAGE_SIZE); 542 } 543 544 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 545 return -ENOMEM; 546 547 *bo_ptr = NULL; 548 549 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 550 sizeof(struct amdgpu_bo)); 551 552 bo = pool_get(&adev->ddev->objpl, PR_WAITOK | PR_ZERO); 553 if (bo == NULL) 554 return -ENOMEM; 555 drm_gem_private_object_init(adev->ddev, &bo->tbo.base, size); 556 bo->adev = adev; 557 INIT_LIST_HEAD(&bo->shadow_list); 558 bo->vm_bo = NULL; 559 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain : 560 bp->domain; 561 bo->allowed_domains = bo->preferred_domains; 562 if (bp->type != ttm_bo_type_kernel && 563 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM) 564 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT; 565 566 bo->flags = bp->flags; 567 568 if (!amdgpu_bo_support_uswc(bo->flags)) 569 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 570 571 bo->tbo.bdev = &adev->mman.bdev; 572 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA | 573 AMDGPU_GEM_DOMAIN_GDS)) 574 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 575 else 576 amdgpu_bo_placement_from_domain(bo, bp->domain); 577 if (bp->type == ttm_bo_type_kernel) 578 bo->tbo.priority = 1; 579 580 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type, 581 &bo->placement, page_align, &ctx, acc_size, 582 NULL, bp->resv, &amdgpu_bo_destroy); 583 if (unlikely(r != 0)) 584 return r; 585 586 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) && 587 bo->tbo.mem.mem_type == TTM_PL_VRAM && 588 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) 589 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 590 ctx.bytes_moved); 591 else 592 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0); 593 594 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED && 595 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) { 596 struct dma_fence *fence; 597 598 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence); 599 if (unlikely(r)) 600 goto fail_unreserve; 601 602 amdgpu_bo_fence(bo, fence, false); 603 dma_fence_put(bo->tbo.moving); 604 bo->tbo.moving = dma_fence_get(fence); 605 dma_fence_put(fence); 606 } 607 if (!bp->resv) 608 amdgpu_bo_unreserve(bo); 609 *bo_ptr = bo; 610 611 trace_amdgpu_bo_create(bo); 612 613 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */ 614 if (bp->type == ttm_bo_type_device) 615 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 616 617 return 0; 618 619 fail_unreserve: 620 if (!bp->resv) 621 dma_resv_unlock(bo->tbo.base.resv); 622 amdgpu_bo_unref(&bo); 623 return r; 624 } 625 626 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev, 627 unsigned long size, 628 struct amdgpu_bo *bo) 629 { 630 struct amdgpu_bo_param bp; 631 int r; 632 633 if (bo->shadow) 634 return 0; 635 636 memset(&bp, 0, sizeof(bp)); 637 bp.size = size; 638 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 639 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC | 640 AMDGPU_GEM_CREATE_SHADOW; 641 bp.type = ttm_bo_type_kernel; 642 bp.resv = bo->tbo.base.resv; 643 644 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow); 645 if (!r) { 646 bo->shadow->parent = amdgpu_bo_ref(bo); 647 mutex_lock(&adev->shadow_list_lock); 648 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list); 649 mutex_unlock(&adev->shadow_list_lock); 650 } 651 652 return r; 653 } 654 655 /** 656 * amdgpu_bo_create - create an &amdgpu_bo buffer object 657 * @adev: amdgpu device object 658 * @bp: parameters to be used for the buffer object 659 * @bo_ptr: pointer to the buffer object pointer 660 * 661 * Creates an &amdgpu_bo buffer object; and if requested, also creates a 662 * shadow object. 663 * Shadow object is used to backup the original buffer object, and is always 664 * in GTT. 665 * 666 * Returns: 667 * 0 for success or a negative error code on failure. 668 */ 669 int amdgpu_bo_create(struct amdgpu_device *adev, 670 struct amdgpu_bo_param *bp, 671 struct amdgpu_bo **bo_ptr) 672 { 673 u64 flags = bp->flags; 674 int r; 675 676 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW; 677 r = amdgpu_bo_do_create(adev, bp, bo_ptr); 678 if (r) 679 return r; 680 681 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) { 682 if (!bp->resv) 683 WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv, 684 NULL)); 685 686 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr); 687 688 if (!bp->resv) 689 dma_resv_unlock((*bo_ptr)->tbo.base.resv); 690 691 if (r) 692 amdgpu_bo_unref(bo_ptr); 693 } 694 695 return r; 696 } 697 698 /** 699 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object 700 * @bo: pointer to the buffer object 701 * 702 * Sets placement according to domain; and changes placement and caching 703 * policy of the buffer object according to the placement. 704 * This is used for validating shadow bos. It calls ttm_bo_validate() to 705 * make sure the buffer is resident where it needs to be. 706 * 707 * Returns: 708 * 0 for success or a negative error code on failure. 709 */ 710 int amdgpu_bo_validate(struct amdgpu_bo *bo) 711 { 712 struct ttm_operation_ctx ctx = { false, false }; 713 uint32_t domain; 714 int r; 715 716 if (bo->pin_count) 717 return 0; 718 719 domain = bo->preferred_domains; 720 721 retry: 722 amdgpu_bo_placement_from_domain(bo, domain); 723 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 724 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { 725 domain = bo->allowed_domains; 726 goto retry; 727 } 728 729 return r; 730 } 731 732 /** 733 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow 734 * 735 * @shadow: &amdgpu_bo shadow to be restored 736 * @fence: dma_fence associated with the operation 737 * 738 * Copies a buffer object's shadow content back to the object. 739 * This is used for recovering a buffer from its shadow in case of a gpu 740 * reset where vram context may be lost. 741 * 742 * Returns: 743 * 0 for success or a negative error code on failure. 744 */ 745 int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) 746 747 { 748 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); 749 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 750 uint64_t shadow_addr, parent_addr; 751 752 shadow_addr = amdgpu_bo_gpu_offset(shadow); 753 parent_addr = amdgpu_bo_gpu_offset(shadow->parent); 754 755 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, 756 amdgpu_bo_size(shadow), NULL, fence, 757 true, false); 758 } 759 760 /** 761 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object 762 * @bo: &amdgpu_bo buffer object to be mapped 763 * @ptr: kernel virtual address to be returned 764 * 765 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls 766 * amdgpu_bo_kptr() to get the kernel virtual address. 767 * 768 * Returns: 769 * 0 for success or a negative error code on failure. 770 */ 771 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 772 { 773 void *kptr; 774 long r; 775 776 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 777 return -EPERM; 778 779 kptr = amdgpu_bo_kptr(bo); 780 if (kptr) { 781 if (ptr) 782 *ptr = kptr; 783 return 0; 784 } 785 786 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false, 787 MAX_SCHEDULE_TIMEOUT); 788 if (r < 0) 789 return r; 790 791 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 792 if (r) 793 return r; 794 795 if (ptr) 796 *ptr = amdgpu_bo_kptr(bo); 797 798 return 0; 799 } 800 801 /** 802 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object 803 * @bo: &amdgpu_bo buffer object 804 * 805 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address 806 * 807 * Returns: 808 * the virtual address of a buffer object area. 809 */ 810 void *amdgpu_bo_kptr(struct amdgpu_bo *bo) 811 { 812 bool is_iomem; 813 814 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 815 } 816 817 /** 818 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object 819 * @bo: &amdgpu_bo buffer object to be unmapped 820 * 821 * Unmaps a kernel map set up by amdgpu_bo_kmap(). 822 */ 823 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 824 { 825 if (bo->kmap.bo) 826 ttm_bo_kunmap(&bo->kmap); 827 } 828 829 /** 830 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object 831 * @bo: &amdgpu_bo buffer object 832 * 833 * References the contained &ttm_buffer_object. 834 * 835 * Returns: 836 * a refcounted pointer to the &amdgpu_bo buffer object. 837 */ 838 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 839 { 840 if (bo == NULL) 841 return NULL; 842 843 ttm_bo_get(&bo->tbo); 844 return bo; 845 } 846 847 /** 848 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object 849 * @bo: &amdgpu_bo buffer object 850 * 851 * Unreferences the contained &ttm_buffer_object and clear the pointer 852 */ 853 void amdgpu_bo_unref(struct amdgpu_bo **bo) 854 { 855 struct ttm_buffer_object *tbo; 856 857 if ((*bo) == NULL) 858 return; 859 860 tbo = &((*bo)->tbo); 861 ttm_bo_put(tbo); 862 *bo = NULL; 863 } 864 865 /** 866 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object 867 * @bo: &amdgpu_bo buffer object to be pinned 868 * @domain: domain to be pinned to 869 * @min_offset: the start of requested address range 870 * @max_offset: the end of requested address range 871 * 872 * Pins the buffer object according to requested domain and address range. If 873 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 874 * pin_count and pin_size accordingly. 875 * 876 * Pinning means to lock pages in memory along with keeping them at a fixed 877 * offset. It is required when a buffer can not be moved, for example, when 878 * a display buffer is being scanned out. 879 * 880 * Compared with amdgpu_bo_pin(), this function gives more flexibility on 881 * where to pin a buffer if there are specific restrictions on where a buffer 882 * must be located. 883 * 884 * Returns: 885 * 0 for success or a negative error code on failure. 886 */ 887 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 888 u64 min_offset, u64 max_offset) 889 { 890 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 891 struct ttm_operation_ctx ctx = { false, false }; 892 int r, i; 893 894 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) 895 return -EPERM; 896 897 if (WARN_ON_ONCE(min_offset > max_offset)) 898 return -EINVAL; 899 900 /* A shared bo cannot be migrated to VRAM */ 901 if (bo->prime_shared_count) { 902 if (domain & AMDGPU_GEM_DOMAIN_GTT) 903 domain = AMDGPU_GEM_DOMAIN_GTT; 904 else 905 return -EINVAL; 906 } 907 908 /* This assumes only APU display buffers are pinned with (VRAM|GTT). 909 * See function amdgpu_display_supported_domains() 910 */ 911 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain); 912 913 if (bo->pin_count) { 914 uint32_t mem_type = bo->tbo.mem.mem_type; 915 916 if (!(domain & amdgpu_mem_type_to_domain(mem_type))) 917 return -EINVAL; 918 919 bo->pin_count++; 920 921 if (max_offset != 0) { 922 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 923 WARN_ON_ONCE(max_offset < 924 (amdgpu_bo_gpu_offset(bo) - domain_start)); 925 } 926 927 return 0; 928 } 929 930 #ifdef notyet 931 if (bo->tbo.base.import_attach) 932 dma_buf_pin(bo->tbo.base.import_attach); 933 #endif 934 935 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; 936 /* force to pin into visible video ram */ 937 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) 938 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 939 amdgpu_bo_placement_from_domain(bo, domain); 940 for (i = 0; i < bo->placement.num_placement; i++) { 941 unsigned fpfn, lpfn; 942 943 fpfn = min_offset >> PAGE_SHIFT; 944 lpfn = max_offset >> PAGE_SHIFT; 945 946 if (fpfn > bo->placements[i].fpfn) 947 bo->placements[i].fpfn = fpfn; 948 if (!bo->placements[i].lpfn || 949 (lpfn && lpfn < bo->placements[i].lpfn)) 950 bo->placements[i].lpfn = lpfn; 951 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 952 } 953 954 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 955 if (unlikely(r)) { 956 dev_err(adev->dev, "%p pin failed\n", bo); 957 goto error; 958 } 959 960 bo->pin_count = 1; 961 962 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 963 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 964 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size); 965 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo), 966 &adev->visible_pin_size); 967 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) { 968 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size); 969 } 970 971 error: 972 return r; 973 } 974 975 /** 976 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 977 * @bo: &amdgpu_bo buffer object to be pinned 978 * @domain: domain to be pinned to 979 * 980 * A simple wrapper to amdgpu_bo_pin_restricted(). 981 * Provides a simpler API for buffers that do not have any strict restrictions 982 * on where a buffer must be located. 983 * 984 * Returns: 985 * 0 for success or a negative error code on failure. 986 */ 987 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) 988 { 989 return amdgpu_bo_pin_restricted(bo, domain, 0, 0); 990 } 991 992 /** 993 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object 994 * @bo: &amdgpu_bo buffer object to be unpinned 995 * 996 * Decreases the pin_count, and clears the flags if pin_count reaches 0. 997 * Changes placement and pin size accordingly. 998 * 999 * Returns: 1000 * 0 for success or a negative error code on failure. 1001 */ 1002 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 1003 { 1004 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1005 struct ttm_operation_ctx ctx = { false, false }; 1006 int r, i; 1007 1008 if (WARN_ON_ONCE(!bo->pin_count)) { 1009 dev_warn(adev->dev, "%p unpin not necessary\n", bo); 1010 return 0; 1011 } 1012 bo->pin_count--; 1013 if (bo->pin_count) 1014 return 0; 1015 1016 amdgpu_bo_subtract_pin_size(bo); 1017 1018 #ifdef notyet 1019 if (bo->tbo.base.import_attach) 1020 dma_buf_unpin(bo->tbo.base.import_attach); 1021 #endif 1022 1023 for (i = 0; i < bo->placement.num_placement; i++) { 1024 bo->placements[i].lpfn = 0; 1025 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 1026 } 1027 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1028 if (unlikely(r)) 1029 dev_err(adev->dev, "%p validate failed for unpin\n", bo); 1030 1031 return r; 1032 } 1033 1034 /** 1035 * amdgpu_bo_evict_vram - evict VRAM buffers 1036 * @adev: amdgpu device object 1037 * 1038 * Evicts all VRAM buffers on the lru list of the memory type. 1039 * Mainly used for evicting vram at suspend time. 1040 * 1041 * Returns: 1042 * 0 for success or a negative error code on failure. 1043 */ 1044 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 1045 { 1046 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 1047 #ifndef CONFIG_HIBERNATION 1048 if (adev->flags & AMD_IS_APU) { 1049 /* Useless to evict on IGP chips */ 1050 return 0; 1051 } 1052 #endif 1053 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 1054 } 1055 1056 static const char *amdgpu_vram_names[] = { 1057 "UNKNOWN", 1058 "GDDR1", 1059 "DDR2", 1060 "GDDR3", 1061 "GDDR4", 1062 "GDDR5", 1063 "HBM", 1064 "DDR3", 1065 "DDR4", 1066 "GDDR6", 1067 }; 1068 1069 /** 1070 * amdgpu_bo_init - initialize memory manager 1071 * @adev: amdgpu device object 1072 * 1073 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager. 1074 * 1075 * Returns: 1076 * 0 for success or a negative error code on failure. 1077 */ 1078 int amdgpu_bo_init(struct amdgpu_device *adev) 1079 { 1080 paddr_t start, end; 1081 1082 #ifdef __linux__ 1083 /* reserve PAT memory space to WC for VRAM */ 1084 arch_io_reserve_memtype_wc(adev->gmc.aper_base, 1085 adev->gmc.aper_size); 1086 1087 /* Add an MTRR for the VRAM */ 1088 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, 1089 adev->gmc.aper_size); 1090 #else 1091 drm_mtrr_add(adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC); 1092 1093 start = atop(bus_space_mmap(adev->memt, adev->gmc.aper_base, 0, 0, 0)); 1094 end = start + atop(adev->gmc.aper_size); 1095 uvm_page_physload(start, end, start, end, PHYSLOAD_DEVICE); 1096 #endif 1097 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 1098 adev->gmc.mc_vram_size >> 20, 1099 (unsigned long long)adev->gmc.aper_size >> 20); 1100 DRM_INFO("RAM width %dbits %s\n", 1101 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); 1102 return amdgpu_ttm_init(adev); 1103 } 1104 1105 /** 1106 * amdgpu_bo_late_init - late init 1107 * @adev: amdgpu device object 1108 * 1109 * Calls amdgpu_ttm_late_init() to free resources used earlier during 1110 * initialization. 1111 * 1112 * Returns: 1113 * 0 for success or a negative error code on failure. 1114 */ 1115 int amdgpu_bo_late_init(struct amdgpu_device *adev) 1116 { 1117 amdgpu_ttm_late_init(adev); 1118 1119 return 0; 1120 } 1121 1122 /** 1123 * amdgpu_bo_fini - tear down memory manager 1124 * @adev: amdgpu device object 1125 * 1126 * Reverses amdgpu_bo_init() to tear down memory manager. 1127 */ 1128 void amdgpu_bo_fini(struct amdgpu_device *adev) 1129 { 1130 amdgpu_ttm_fini(adev); 1131 #ifdef __linux__ 1132 arch_phys_wc_del(adev->gmc.vram_mtrr); 1133 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); 1134 #else 1135 drm_mtrr_del(0, adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC); 1136 #endif 1137 } 1138 1139 #ifdef notyet 1140 /** 1141 * amdgpu_bo_fbdev_mmap - mmap fbdev memory 1142 * @bo: &amdgpu_bo buffer object 1143 * @vma: vma as input from the fbdev mmap method 1144 * 1145 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo. 1146 * 1147 * Returns: 1148 * 0 for success or a negative error code on failure. 1149 */ 1150 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 1151 struct vm_area_struct *vma) 1152 { 1153 if (vma->vm_pgoff != 0) 1154 return -EACCES; 1155 1156 return ttm_bo_mmap_obj(vma, &bo->tbo); 1157 } 1158 #endif 1159 1160 /** 1161 * amdgpu_bo_set_tiling_flags - set tiling flags 1162 * @bo: &amdgpu_bo buffer object 1163 * @tiling_flags: new flags 1164 * 1165 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or 1166 * kernel driver to set the tiling flags on a buffer. 1167 * 1168 * Returns: 1169 * 0 for success or a negative error code on failure. 1170 */ 1171 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 1172 { 1173 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1174 1175 if (adev->family <= AMDGPU_FAMILY_CZ && 1176 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 1177 return -EINVAL; 1178 1179 bo->tiling_flags = tiling_flags; 1180 return 0; 1181 } 1182 1183 /** 1184 * amdgpu_bo_get_tiling_flags - get tiling flags 1185 * @bo: &amdgpu_bo buffer object 1186 * @tiling_flags: returned flags 1187 * 1188 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to 1189 * set the tiling flags on a buffer. 1190 */ 1191 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 1192 { 1193 dma_resv_assert_held(bo->tbo.base.resv); 1194 1195 if (tiling_flags) 1196 *tiling_flags = bo->tiling_flags; 1197 } 1198 1199 /** 1200 * amdgpu_bo_set_metadata - set metadata 1201 * @bo: &amdgpu_bo buffer object 1202 * @metadata: new metadata 1203 * @metadata_size: size of the new metadata 1204 * @flags: flags of the new metadata 1205 * 1206 * Sets buffer object's metadata, its size and flags. 1207 * Used via GEM ioctl. 1208 * 1209 * Returns: 1210 * 0 for success or a negative error code on failure. 1211 */ 1212 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 1213 uint32_t metadata_size, uint64_t flags) 1214 { 1215 void *buffer; 1216 1217 if (!metadata_size) { 1218 if (bo->metadata_size) { 1219 kfree(bo->metadata); 1220 bo->metadata = NULL; 1221 bo->metadata_size = 0; 1222 } 1223 return 0; 1224 } 1225 1226 if (metadata == NULL) 1227 return -EINVAL; 1228 1229 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 1230 if (buffer == NULL) 1231 return -ENOMEM; 1232 1233 kfree(bo->metadata); 1234 bo->metadata_flags = flags; 1235 bo->metadata = buffer; 1236 bo->metadata_size = metadata_size; 1237 1238 return 0; 1239 } 1240 1241 /** 1242 * amdgpu_bo_get_metadata - get metadata 1243 * @bo: &amdgpu_bo buffer object 1244 * @buffer: returned metadata 1245 * @buffer_size: size of the buffer 1246 * @metadata_size: size of the returned metadata 1247 * @flags: flags of the returned metadata 1248 * 1249 * Gets buffer object's metadata, its size and flags. buffer_size shall not be 1250 * less than metadata_size. 1251 * Used via GEM ioctl. 1252 * 1253 * Returns: 1254 * 0 for success or a negative error code on failure. 1255 */ 1256 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 1257 size_t buffer_size, uint32_t *metadata_size, 1258 uint64_t *flags) 1259 { 1260 if (!buffer && !metadata_size) 1261 return -EINVAL; 1262 1263 if (buffer) { 1264 if (buffer_size < bo->metadata_size) 1265 return -EINVAL; 1266 1267 if (bo->metadata_size) 1268 memcpy(buffer, bo->metadata, bo->metadata_size); 1269 } 1270 1271 if (metadata_size) 1272 *metadata_size = bo->metadata_size; 1273 if (flags) 1274 *flags = bo->metadata_flags; 1275 1276 return 0; 1277 } 1278 1279 /** 1280 * amdgpu_bo_move_notify - notification about a memory move 1281 * @bo: pointer to a buffer object 1282 * @evict: if this move is evicting the buffer from the graphics address space 1283 * @new_mem: new information of the bufer object 1284 * 1285 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs 1286 * bookkeeping. 1287 * TTM driver callback which is called when ttm moves a buffer. 1288 */ 1289 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 1290 bool evict, 1291 struct ttm_mem_reg *new_mem) 1292 { 1293 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1294 struct amdgpu_bo *abo; 1295 struct ttm_mem_reg *old_mem = &bo->mem; 1296 1297 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1298 return; 1299 1300 abo = ttm_to_amdgpu_bo(bo); 1301 amdgpu_vm_bo_invalidate(adev, abo, evict); 1302 1303 amdgpu_bo_kunmap(abo); 1304 1305 #ifdef notyet 1306 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && 1307 bo->mem.mem_type != TTM_PL_SYSTEM) 1308 dma_buf_move_notify(abo->tbo.base.dma_buf); 1309 #endif 1310 1311 /* remember the eviction */ 1312 if (evict) 1313 atomic64_inc(&adev->num_evictions); 1314 1315 /* update statistics */ 1316 if (!new_mem) 1317 return; 1318 1319 /* move_notify is called before move happens */ 1320 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type); 1321 } 1322 1323 /** 1324 * amdgpu_bo_move_notify - notification about a BO being released 1325 * @bo: pointer to a buffer object 1326 * 1327 * Wipes VRAM buffers whose contents should not be leaked before the 1328 * memory is released. 1329 */ 1330 void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) 1331 { 1332 struct dma_fence *fence = NULL; 1333 struct amdgpu_bo *abo; 1334 int r; 1335 1336 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1337 return; 1338 1339 abo = ttm_to_amdgpu_bo(bo); 1340 1341 if (abo->kfd_bo) 1342 amdgpu_amdkfd_unreserve_memory_limit(abo); 1343 1344 /* We only remove the fence if the resv has individualized. */ 1345 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel 1346 && bo->base.resv != &bo->base._resv); 1347 if (bo->base.resv == &bo->base._resv) 1348 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); 1349 1350 if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node || 1351 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) 1352 return; 1353 1354 dma_resv_lock(bo->base.resv, NULL); 1355 1356 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence); 1357 if (!WARN_ON(r)) { 1358 amdgpu_bo_fence(abo, fence, false); 1359 dma_fence_put(fence); 1360 } 1361 1362 dma_resv_unlock(bo->base.resv); 1363 } 1364 1365 /** 1366 * amdgpu_bo_fault_reserve_notify - notification about a memory fault 1367 * @bo: pointer to a buffer object 1368 * 1369 * Notifies the driver we are taking a fault on this BO and have reserved it, 1370 * also performs bookkeeping. 1371 * TTM driver callback for dealing with vm faults. 1372 * 1373 * Returns: 1374 * 0 for success or a negative error code on failure. 1375 */ 1376 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 1377 { 1378 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); 1379 struct ttm_operation_ctx ctx = { false, false }; 1380 struct amdgpu_bo *abo; 1381 unsigned long offset, size; 1382 int r; 1383 1384 if (!amdgpu_bo_is_amdgpu_bo(bo)) 1385 return 0; 1386 1387 abo = ttm_to_amdgpu_bo(bo); 1388 1389 /* Remember that this BO was accessed by the CPU */ 1390 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; 1391 1392 if (bo->mem.mem_type != TTM_PL_VRAM) 1393 return 0; 1394 1395 size = bo->mem.num_pages << PAGE_SHIFT; 1396 offset = bo->mem.start << PAGE_SHIFT; 1397 if ((offset + size) <= adev->gmc.visible_vram_size) 1398 return 0; 1399 1400 /* Can't move a pinned BO to visible VRAM */ 1401 if (abo->pin_count > 0) 1402 return -EINVAL; 1403 1404 /* hurrah the memory is not visible ! */ 1405 atomic64_inc(&adev->num_vram_cpu_page_faults); 1406 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | 1407 AMDGPU_GEM_DOMAIN_GTT); 1408 1409 /* Avoid costly evictions; only set GTT as a busy placement */ 1410 abo->placement.num_busy_placement = 1; 1411 abo->placement.busy_placement = &abo->placements[1]; 1412 1413 r = ttm_bo_validate(bo, &abo->placement, &ctx); 1414 if (unlikely(r != 0)) 1415 return r; 1416 1417 offset = bo->mem.start << PAGE_SHIFT; 1418 /* this should never happen */ 1419 if (bo->mem.mem_type == TTM_PL_VRAM && 1420 (offset + size) > adev->gmc.visible_vram_size) 1421 return -EINVAL; 1422 1423 return 0; 1424 } 1425 1426 /** 1427 * amdgpu_bo_fence - add fence to buffer object 1428 * 1429 * @bo: buffer object in question 1430 * @fence: fence to add 1431 * @shared: true if fence should be added shared 1432 * 1433 */ 1434 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, 1435 bool shared) 1436 { 1437 struct dma_resv *resv = bo->tbo.base.resv; 1438 1439 if (shared) 1440 dma_resv_add_shared_fence(resv, fence); 1441 else 1442 dma_resv_add_excl_fence(resv, fence); 1443 } 1444 1445 /** 1446 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences 1447 * 1448 * @adev: amdgpu device pointer 1449 * @resv: reservation object to sync to 1450 * @sync_mode: synchronization mode 1451 * @owner: fence owner 1452 * @intr: Whether the wait is interruptible 1453 * 1454 * Extract the fences from the reservation object and waits for them to finish. 1455 * 1456 * Returns: 1457 * 0 on success, errno otherwise. 1458 */ 1459 int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv, 1460 enum amdgpu_sync_mode sync_mode, void *owner, 1461 bool intr) 1462 { 1463 struct amdgpu_sync sync; 1464 int r; 1465 1466 amdgpu_sync_create(&sync); 1467 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner); 1468 r = amdgpu_sync_wait(&sync, intr); 1469 amdgpu_sync_free(&sync); 1470 return r; 1471 } 1472 1473 /** 1474 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv 1475 * @bo: buffer object to wait for 1476 * @owner: fence owner 1477 * @intr: Whether the wait is interruptible 1478 * 1479 * Wrapper to wait for fences in a BO. 1480 * Returns: 1481 * 0 on success, errno otherwise. 1482 */ 1483 int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) 1484 { 1485 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1486 1487 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, 1488 AMDGPU_SYNC_NE_OWNER, owner, intr); 1489 } 1490 1491 /** 1492 * amdgpu_bo_gpu_offset - return GPU offset of bo 1493 * @bo: amdgpu object for which we query the offset 1494 * 1495 * Note: object should either be pinned or reserved when calling this 1496 * function, it might be useful to add check for this for debugging. 1497 * 1498 * Returns: 1499 * current GPU offset of the object. 1500 */ 1501 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 1502 { 1503 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM); 1504 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && 1505 !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel); 1506 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET); 1507 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM && 1508 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); 1509 1510 return amdgpu_gmc_sign_extend(bo->tbo.offset); 1511 } 1512 1513 /** 1514 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout 1515 * @adev: amdgpu device object 1516 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>` 1517 * 1518 * Returns: 1519 * Which of the allowed domains is preferred for pinning the BO for scanout. 1520 */ 1521 uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev, 1522 uint32_t domain) 1523 { 1524 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) { 1525 domain = AMDGPU_GEM_DOMAIN_VRAM; 1526 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD) 1527 domain = AMDGPU_GEM_DOMAIN_GTT; 1528 } 1529 return domain; 1530 } 1531