1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include <linux/sched/mm.h> 31 32 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 33 #define AMDGPU_MES_MAX_GFX_PIPES 2 34 #define AMDGPU_MES_MAX_SDMA_PIPES 2 35 36 #define AMDGPU_MES_API_VERSION_SHIFT 12 37 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 38 39 #define AMDGPU_MES_VERSION_MASK 0x00000fff 40 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 41 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 42 43 enum amdgpu_mes_priority_level { 44 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 45 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 46 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 47 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 48 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 49 AMDGPU_MES_PRIORITY_NUM_LEVELS 50 }; 51 52 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 53 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 54 55 struct amdgpu_mes_funcs; 56 57 enum admgpu_mes_pipe { 58 AMDGPU_MES_SCHED_PIPE = 0, 59 AMDGPU_MES_KIQ_PIPE, 60 AMDGPU_MAX_MES_PIPES = 2, 61 }; 62 63 struct amdgpu_mes { 64 struct amdgpu_device *adev; 65 66 struct rwlock mutex_hidden; 67 68 struct idr pasid_idr; 69 struct idr gang_id_idr; 70 struct idr queue_id_idr; 71 struct ida doorbell_ida; 72 73 spinlock_t queue_id_lock; 74 75 uint32_t sched_version; 76 uint32_t kiq_version; 77 78 uint32_t total_max_queue; 79 uint32_t doorbell_id_offset; 80 uint32_t max_doorbell_slices; 81 82 uint64_t default_process_quantum; 83 uint64_t default_gang_quantum; 84 85 struct amdgpu_ring ring; 86 spinlock_t ring_lock; 87 88 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 89 90 /* mes ucode */ 91 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 92 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 93 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 94 uint32_t ucode_fw_version[AMDGPU_MAX_MES_PIPES]; 95 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 96 97 /* mes ucode data */ 98 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 99 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 100 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 101 uint32_t data_fw_version[AMDGPU_MAX_MES_PIPES]; 102 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 103 104 /* eop gpu obj */ 105 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 106 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 107 108 void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 109 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 110 111 uint32_t vmid_mask_gfxhub; 112 uint32_t vmid_mask_mmhub; 113 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 114 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 115 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 116 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 117 uint32_t sch_ctx_offs; 118 uint64_t sch_ctx_gpu_addr; 119 uint64_t *sch_ctx_ptr; 120 uint32_t query_status_fence_offs; 121 uint64_t query_status_fence_gpu_addr; 122 uint64_t *query_status_fence_ptr; 123 uint32_t read_val_offs; 124 uint64_t read_val_gpu_addr; 125 uint32_t *read_val_ptr; 126 127 #ifdef notyet 128 uint32_t saved_flags; 129 #endif 130 131 /* initialize kiq pipe */ 132 int (*kiq_hw_init)(struct amdgpu_device *adev); 133 int (*kiq_hw_fini)(struct amdgpu_device *adev); 134 135 /* ip specific functions */ 136 const struct amdgpu_mes_funcs *funcs; 137 }; 138 139 struct amdgpu_mes_process { 140 int pasid; 141 struct amdgpu_vm *vm; 142 uint64_t pd_gpu_addr; 143 struct amdgpu_bo *proc_ctx_bo; 144 uint64_t proc_ctx_gpu_addr; 145 void *proc_ctx_cpu_ptr; 146 uint64_t process_quantum; 147 struct list_head gang_list; 148 uint32_t doorbell_index; 149 unsigned long *doorbell_bitmap; 150 struct mutex doorbell_lock; 151 }; 152 153 struct amdgpu_mes_gang { 154 int gang_id; 155 int priority; 156 int inprocess_gang_priority; 157 int global_priority_level; 158 struct list_head list; 159 struct amdgpu_mes_process *process; 160 struct amdgpu_bo *gang_ctx_bo; 161 uint64_t gang_ctx_gpu_addr; 162 void *gang_ctx_cpu_ptr; 163 uint64_t gang_quantum; 164 struct list_head queue_list; 165 }; 166 167 struct amdgpu_mes_queue { 168 struct list_head list; 169 struct amdgpu_mes_gang *gang; 170 int queue_id; 171 uint64_t doorbell_off; 172 struct amdgpu_bo *mqd_obj; 173 void *mqd_cpu_ptr; 174 uint64_t mqd_gpu_addr; 175 uint64_t wptr_gpu_addr; 176 int queue_type; 177 int paging; 178 struct amdgpu_ring *ring; 179 }; 180 181 struct amdgpu_mes_queue_properties { 182 int queue_type; 183 uint64_t hqd_base_gpu_addr; 184 uint64_t rptr_gpu_addr; 185 uint64_t wptr_gpu_addr; 186 uint64_t wptr_mc_addr; 187 uint32_t queue_size; 188 uint64_t eop_gpu_addr; 189 uint32_t hqd_pipe_priority; 190 uint32_t hqd_queue_priority; 191 bool paging; 192 struct amdgpu_ring *ring; 193 /* out */ 194 uint64_t doorbell_off; 195 }; 196 197 struct amdgpu_mes_gang_properties { 198 uint32_t priority; 199 uint32_t gang_quantum; 200 uint32_t inprocess_gang_priority; 201 uint32_t priority_level; 202 int global_priority_level; 203 }; 204 205 struct mes_add_queue_input { 206 uint32_t process_id; 207 uint64_t page_table_base_addr; 208 uint64_t process_va_start; 209 uint64_t process_va_end; 210 uint64_t process_quantum; 211 uint64_t process_context_addr; 212 uint64_t gang_quantum; 213 uint64_t gang_context_addr; 214 uint32_t inprocess_gang_priority; 215 uint32_t gang_global_priority_level; 216 uint32_t doorbell_offset; 217 uint64_t mqd_addr; 218 uint64_t wptr_addr; 219 uint64_t wptr_mc_addr; 220 uint32_t queue_type; 221 uint32_t paging; 222 uint32_t gws_base; 223 uint32_t gws_size; 224 uint64_t tba_addr; 225 uint64_t tma_addr; 226 uint32_t is_kfd_process; 227 uint32_t is_aql_queue; 228 uint32_t queue_size; 229 }; 230 231 struct mes_remove_queue_input { 232 uint32_t doorbell_offset; 233 uint64_t gang_context_addr; 234 }; 235 236 struct mes_unmap_legacy_queue_input { 237 enum amdgpu_unmap_queues_action action; 238 uint32_t queue_type; 239 uint32_t doorbell_offset; 240 uint32_t pipe_id; 241 uint32_t queue_id; 242 uint64_t trail_fence_addr; 243 uint64_t trail_fence_data; 244 }; 245 246 struct mes_suspend_gang_input { 247 bool suspend_all_gangs; 248 uint64_t gang_context_addr; 249 uint64_t suspend_fence_addr; 250 uint32_t suspend_fence_value; 251 }; 252 253 struct mes_resume_gang_input { 254 bool resume_all_gangs; 255 uint64_t gang_context_addr; 256 }; 257 258 enum mes_misc_opcode { 259 MES_MISC_OP_WRITE_REG, 260 MES_MISC_OP_READ_REG, 261 MES_MISC_OP_WRM_REG_WAIT, 262 MES_MISC_OP_WRM_REG_WR_WAIT, 263 }; 264 265 struct mes_misc_op_input { 266 enum mes_misc_opcode op; 267 268 union { 269 struct { 270 uint32_t reg_offset; 271 uint64_t buffer_addr; 272 } read_reg; 273 274 struct { 275 uint32_t reg_offset; 276 uint32_t reg_value; 277 } write_reg; 278 279 struct { 280 uint32_t ref; 281 uint32_t mask; 282 uint32_t reg0; 283 uint32_t reg1; 284 } wrm_reg; 285 }; 286 }; 287 288 struct amdgpu_mes_funcs { 289 int (*add_hw_queue)(struct amdgpu_mes *mes, 290 struct mes_add_queue_input *input); 291 292 int (*remove_hw_queue)(struct amdgpu_mes *mes, 293 struct mes_remove_queue_input *input); 294 295 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 296 struct mes_unmap_legacy_queue_input *input); 297 298 int (*suspend_gang)(struct amdgpu_mes *mes, 299 struct mes_suspend_gang_input *input); 300 301 int (*resume_gang)(struct amdgpu_mes *mes, 302 struct mes_resume_gang_input *input); 303 304 int (*misc_op)(struct amdgpu_mes *mes, 305 struct mes_misc_op_input *input); 306 }; 307 308 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 309 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 310 311 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); 312 313 int amdgpu_mes_init(struct amdgpu_device *adev); 314 void amdgpu_mes_fini(struct amdgpu_device *adev); 315 316 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid, 317 struct amdgpu_vm *vm); 318 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid); 319 320 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid, 321 struct amdgpu_mes_gang_properties *gprops, 322 int *gang_id); 323 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id); 324 325 int amdgpu_mes_suspend(struct amdgpu_device *adev); 326 int amdgpu_mes_resume(struct amdgpu_device *adev); 327 328 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, 329 struct amdgpu_mes_queue_properties *qprops, 330 int *queue_id); 331 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); 332 333 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 334 struct amdgpu_ring *ring, 335 enum amdgpu_unmap_queues_action action, 336 u64 gpu_addr, u64 seq); 337 338 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 339 int amdgpu_mes_wreg(struct amdgpu_device *adev, 340 uint32_t reg, uint32_t val); 341 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, 342 uint32_t val, uint32_t mask); 343 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 344 uint32_t reg0, uint32_t reg1, 345 uint32_t ref, uint32_t mask); 346 347 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, 348 int queue_type, int idx, 349 struct amdgpu_mes_ctx_data *ctx_data, 350 struct amdgpu_ring **out); 351 void amdgpu_mes_remove_ring(struct amdgpu_device *adev, 352 struct amdgpu_ring *ring); 353 354 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 355 enum amdgpu_mes_priority_level prio); 356 357 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, 358 struct amdgpu_mes_ctx_data *ctx_data); 359 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data); 360 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev, 361 struct amdgpu_vm *vm, 362 struct amdgpu_mes_ctx_data *ctx_data); 363 int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev, 364 struct amdgpu_mes_ctx_data *ctx_data); 365 366 int amdgpu_mes_self_test(struct amdgpu_device *adev); 367 368 int amdgpu_mes_alloc_process_doorbells(struct amdgpu_device *adev, 369 unsigned int *doorbell_index); 370 void amdgpu_mes_free_process_doorbells(struct amdgpu_device *adev, 371 unsigned int doorbell_index); 372 unsigned int amdgpu_mes_get_doorbell_dw_offset_in_bar( 373 struct amdgpu_device *adev, 374 uint32_t doorbell_index, 375 unsigned int doorbell_id); 376 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 377 378 /* 379 * MES lock can be taken in MMU notifiers. 380 * 381 * A bit more detail about why to set no-FS reclaim with MES lock: 382 * 383 * The purpose of the MMU notifier is to stop GPU access to memory so 384 * that the Linux VM subsystem can move pages around safely. This is 385 * done by preempting user mode queues for the affected process. When 386 * MES is used, MES lock needs to be taken to preempt the queues. 387 * 388 * The MMU notifier callback entry point in the driver is 389 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 390 * there is: 391 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 392 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 393 * 394 * The last part of the chain is a function pointer where we take the 395 * MES lock. 396 * 397 * The problem with taking locks in the MMU notifier is, that MMU 398 * notifiers can be called in reclaim-FS context. That's where the 399 * kernel frees up pages to make room for new page allocations under 400 * memory pressure. While we are running in reclaim-FS context, we must 401 * not trigger another memory reclaim operation because that would 402 * recursively reenter the reclaim code and cause a deadlock. The 403 * memalloc_nofs_save/restore calls guarantee that. 404 * 405 * In addition we also need to avoid lock dependencies on other locks taken 406 * under the MES lock, for example reservation locks. Here is a possible 407 * scenario of a deadlock: 408 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 409 * MMU notifier | blocks trying to take MES lock 410 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 411 * 412 * In this scenario Thread B gets involved in a deadlock even without 413 * triggering a reclaim-FS operation itself. 414 * To fix this and break the lock dependency chain you'd need to either: 415 * 1. protect reservation locks with memalloc_nofs_save/restore, or 416 * 2. avoid taking reservation locks under the MES lock. 417 * 418 * Reservation locks are taken all over the kernel in different subsystems, we 419 * have no control over them and their lock dependencies.So the only workable 420 * solution is to avoid taking other locks under the MES lock. 421 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 422 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 423 */ 424 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 425 { 426 mutex_lock(&mes->mutex_hidden); 427 #ifdef notyet 428 mes->saved_flags = memalloc_noreclaim_save(); 429 #endif 430 } 431 432 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 433 { 434 #ifdef notyet 435 memalloc_noreclaim_restore(mes->saved_flags); 436 #endif 437 mutex_unlock(&mes->mutex_hidden); 438 } 439 #endif /* __AMDGPU_MES_H__ */ 440