1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include "amdgpu.h" 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include "amdgpu_uvd.h" 33 #include "amdgpu_vce.h" 34 #include "atom.h" 35 36 #include <linux/vga_switcheroo.h> 37 #include <linux/slab.h> 38 #include <linux/uaccess.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include "amdgpu_amdkfd.h" 42 #include "amdgpu_gem.h" 43 #include "amdgpu_display.h" 44 #include "amdgpu_ras.h" 45 46 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev) 47 { 48 struct amdgpu_gpu_instance *gpu_instance; 49 int i; 50 51 mutex_lock(&mgpu_info.mutex); 52 53 for (i = 0; i < mgpu_info.num_gpu; i++) { 54 gpu_instance = &(mgpu_info.gpu_ins[i]); 55 if (gpu_instance->adev == adev) { 56 mgpu_info.gpu_ins[i] = 57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1]; 58 mgpu_info.num_gpu--; 59 if (adev->flags & AMD_IS_APU) 60 mgpu_info.num_apu--; 61 else 62 mgpu_info.num_dgpu--; 63 break; 64 } 65 } 66 67 mutex_unlock(&mgpu_info.mutex); 68 } 69 70 #ifdef __linux__ 71 /** 72 * amdgpu_driver_unload_kms - Main unload function for KMS. 73 * 74 * @dev: drm dev pointer 75 * 76 * This is the main unload function for KMS (all asics). 77 * Returns 0 on success. 78 */ 79 void amdgpu_driver_unload_kms(struct drm_device *dev) 80 { 81 struct amdgpu_device *adev = drm_to_adev(dev); 82 83 if (adev == NULL) 84 return; 85 86 amdgpu_unregister_gpu_instance(adev); 87 88 if (adev->rmmio == NULL) 89 return; 90 91 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD)) 92 DRM_WARN("smart shift update failed\n"); 93 94 amdgpu_acpi_fini(adev); 95 amdgpu_device_fini_hw(adev); 96 } 97 #endif /* __linux__ */ 98 99 void amdgpu_register_gpu_instance(struct amdgpu_device *adev) 100 { 101 struct amdgpu_gpu_instance *gpu_instance; 102 103 mutex_lock(&mgpu_info.mutex); 104 105 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) { 106 DRM_ERROR("Cannot register more gpu instance\n"); 107 mutex_unlock(&mgpu_info.mutex); 108 return; 109 } 110 111 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]); 112 gpu_instance->adev = adev; 113 gpu_instance->mgpu_fan_enabled = 0; 114 115 mgpu_info.num_gpu++; 116 if (adev->flags & AMD_IS_APU) 117 mgpu_info.num_apu++; 118 else 119 mgpu_info.num_dgpu++; 120 121 mutex_unlock(&mgpu_info.mutex); 122 } 123 124 #ifdef __linux__ 125 /** 126 * amdgpu_driver_load_kms - Main load function for KMS. 127 * 128 * @adev: pointer to struct amdgpu_device 129 * @flags: device flags 130 * 131 * This is the main load function for KMS (all asics). 132 * Returns 0 on success, error on failure. 133 */ 134 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags) 135 { 136 struct drm_device *dev; 137 int r, acpi_status; 138 139 dev = adev_to_drm(adev); 140 141 /* amdgpu_device_init should report only fatal error 142 * like memory allocation failure or iomapping failure, 143 * or memory manager initialization failure, it must 144 * properly initialize the GPU MC controller and permit 145 * VRAM allocation 146 */ 147 r = amdgpu_device_init(adev, flags); 148 if (r) { 149 dev_err(dev->dev, "Fatal error during GPU init\n"); 150 goto out; 151 } 152 153 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; 154 if (amdgpu_device_supports_px(dev) && 155 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ 156 adev->pm.rpm_mode = AMDGPU_RUNPM_PX; 157 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 158 } else if (amdgpu_device_supports_boco(dev) && 159 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ 160 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; 161 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 162 } else if (amdgpu_device_supports_baco(dev) && 163 (amdgpu_runtime_pm != 0)) { 164 switch (adev->asic_type) { 165 case CHIP_VEGA20: 166 case CHIP_ARCTURUS: 167 /* enable BACO as runpm mode if runpm=1 */ 168 if (amdgpu_runtime_pm > 0) 169 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 170 break; 171 case CHIP_VEGA10: 172 /* enable BACO as runpm mode if noretry=0 */ 173 if (!adev->gmc.noretry) 174 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 175 break; 176 default: 177 /* enable BACO as runpm mode on CI+ */ 178 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 179 break; 180 } 181 182 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) 183 dev_info(adev->dev, "Using BACO for runtime pm\n"); 184 } 185 186 /* Call ACPI methods: require modeset init 187 * but failure is not fatal 188 */ 189 190 acpi_status = amdgpu_acpi_init(adev); 191 if (acpi_status) 192 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 193 194 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 195 DRM_WARN("smart shift update failed\n"); 196 197 out: 198 if (r) 199 amdgpu_driver_unload_kms(dev); 200 201 return r; 202 } 203 #endif /* __linux__ */ 204 205 static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, 206 struct drm_amdgpu_query_fw *query_fw, 207 struct amdgpu_device *adev) 208 { 209 switch (query_fw->fw_type) { 210 case AMDGPU_INFO_FW_VCE: 211 fw_info->ver = adev->vce.fw_version; 212 fw_info->feature = adev->vce.fb_version; 213 break; 214 case AMDGPU_INFO_FW_UVD: 215 fw_info->ver = adev->uvd.fw_version; 216 fw_info->feature = 0; 217 break; 218 case AMDGPU_INFO_FW_VCN: 219 fw_info->ver = adev->vcn.fw_version; 220 fw_info->feature = 0; 221 break; 222 case AMDGPU_INFO_FW_GMC: 223 fw_info->ver = adev->gmc.fw_version; 224 fw_info->feature = 0; 225 break; 226 case AMDGPU_INFO_FW_GFX_ME: 227 fw_info->ver = adev->gfx.me_fw_version; 228 fw_info->feature = adev->gfx.me_feature_version; 229 break; 230 case AMDGPU_INFO_FW_GFX_PFP: 231 fw_info->ver = adev->gfx.pfp_fw_version; 232 fw_info->feature = adev->gfx.pfp_feature_version; 233 break; 234 case AMDGPU_INFO_FW_GFX_CE: 235 fw_info->ver = adev->gfx.ce_fw_version; 236 fw_info->feature = adev->gfx.ce_feature_version; 237 break; 238 case AMDGPU_INFO_FW_GFX_RLC: 239 fw_info->ver = adev->gfx.rlc_fw_version; 240 fw_info->feature = adev->gfx.rlc_feature_version; 241 break; 242 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL: 243 fw_info->ver = adev->gfx.rlc_srlc_fw_version; 244 fw_info->feature = adev->gfx.rlc_srlc_feature_version; 245 break; 246 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM: 247 fw_info->ver = adev->gfx.rlc_srlg_fw_version; 248 fw_info->feature = adev->gfx.rlc_srlg_feature_version; 249 break; 250 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM: 251 fw_info->ver = adev->gfx.rlc_srls_fw_version; 252 fw_info->feature = adev->gfx.rlc_srls_feature_version; 253 break; 254 case AMDGPU_INFO_FW_GFX_RLCP: 255 fw_info->ver = adev->gfx.rlcp_ucode_version; 256 fw_info->feature = adev->gfx.rlcp_ucode_feature_version; 257 break; 258 case AMDGPU_INFO_FW_GFX_RLCV: 259 fw_info->ver = adev->gfx.rlcv_ucode_version; 260 fw_info->feature = adev->gfx.rlcv_ucode_feature_version; 261 break; 262 case AMDGPU_INFO_FW_GFX_MEC: 263 if (query_fw->index == 0) { 264 fw_info->ver = adev->gfx.mec_fw_version; 265 fw_info->feature = adev->gfx.mec_feature_version; 266 } else if (query_fw->index == 1) { 267 fw_info->ver = adev->gfx.mec2_fw_version; 268 fw_info->feature = adev->gfx.mec2_feature_version; 269 } else 270 return -EINVAL; 271 break; 272 case AMDGPU_INFO_FW_SMC: 273 fw_info->ver = adev->pm.fw_version; 274 fw_info->feature = 0; 275 break; 276 case AMDGPU_INFO_FW_TA: 277 switch (query_fw->index) { 278 case TA_FW_TYPE_PSP_XGMI: 279 fw_info->ver = adev->psp.xgmi_context.context.bin_desc.fw_version; 280 fw_info->feature = adev->psp.xgmi_context.context 281 .bin_desc.feature_version; 282 break; 283 case TA_FW_TYPE_PSP_RAS: 284 fw_info->ver = adev->psp.ras_context.context.bin_desc.fw_version; 285 fw_info->feature = adev->psp.ras_context.context 286 .bin_desc.feature_version; 287 break; 288 case TA_FW_TYPE_PSP_HDCP: 289 fw_info->ver = adev->psp.hdcp_context.context.bin_desc.fw_version; 290 fw_info->feature = adev->psp.hdcp_context.context 291 .bin_desc.feature_version; 292 break; 293 case TA_FW_TYPE_PSP_DTM: 294 fw_info->ver = adev->psp.dtm_context.context.bin_desc.fw_version; 295 fw_info->feature = adev->psp.dtm_context.context 296 .bin_desc.feature_version; 297 break; 298 case TA_FW_TYPE_PSP_RAP: 299 fw_info->ver = adev->psp.rap_context.context.bin_desc.fw_version; 300 fw_info->feature = adev->psp.rap_context.context 301 .bin_desc.feature_version; 302 break; 303 case TA_FW_TYPE_PSP_SECUREDISPLAY: 304 fw_info->ver = adev->psp.securedisplay_context.context.bin_desc.fw_version; 305 fw_info->feature = 306 adev->psp.securedisplay_context.context.bin_desc 307 .feature_version; 308 break; 309 default: 310 return -EINVAL; 311 } 312 break; 313 case AMDGPU_INFO_FW_SDMA: 314 if (query_fw->index >= adev->sdma.num_instances) 315 return -EINVAL; 316 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version; 317 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version; 318 break; 319 case AMDGPU_INFO_FW_SOS: 320 fw_info->ver = adev->psp.sos.fw_version; 321 fw_info->feature = adev->psp.sos.feature_version; 322 break; 323 case AMDGPU_INFO_FW_ASD: 324 fw_info->ver = adev->psp.asd_context.bin_desc.fw_version; 325 fw_info->feature = adev->psp.asd_context.bin_desc.feature_version; 326 break; 327 case AMDGPU_INFO_FW_DMCU: 328 fw_info->ver = adev->dm.dmcu_fw_version; 329 fw_info->feature = 0; 330 break; 331 case AMDGPU_INFO_FW_DMCUB: 332 fw_info->ver = adev->dm.dmcub_fw_version; 333 fw_info->feature = 0; 334 break; 335 case AMDGPU_INFO_FW_TOC: 336 fw_info->ver = adev->psp.toc.fw_version; 337 fw_info->feature = adev->psp.toc.feature_version; 338 break; 339 case AMDGPU_INFO_FW_CAP: 340 fw_info->ver = adev->psp.cap_fw_version; 341 fw_info->feature = adev->psp.cap_feature_version; 342 break; 343 case AMDGPU_INFO_FW_MES_KIQ: 344 fw_info->ver = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK; 345 fw_info->feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) 346 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 347 break; 348 case AMDGPU_INFO_FW_MES: 349 fw_info->ver = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 350 fw_info->feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) 351 >> AMDGPU_MES_FEAT_VERSION_SHIFT; 352 break; 353 case AMDGPU_INFO_FW_IMU: 354 fw_info->ver = adev->gfx.imu_fw_version; 355 fw_info->feature = 0; 356 break; 357 default: 358 return -EINVAL; 359 } 360 return 0; 361 } 362 363 static int amdgpu_hw_ip_info(struct amdgpu_device *adev, 364 struct drm_amdgpu_info *info, 365 struct drm_amdgpu_info_hw_ip *result) 366 { 367 uint32_t ib_start_alignment = 0; 368 uint32_t ib_size_alignment = 0; 369 enum amd_ip_block_type type; 370 unsigned int num_rings = 0; 371 unsigned int i, j; 372 373 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 374 return -EINVAL; 375 376 switch (info->query_hw_ip.type) { 377 case AMDGPU_HW_IP_GFX: 378 type = AMD_IP_BLOCK_TYPE_GFX; 379 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 380 if (adev->gfx.gfx_ring[i].sched.ready) 381 ++num_rings; 382 ib_start_alignment = 32; 383 ib_size_alignment = 32; 384 break; 385 case AMDGPU_HW_IP_COMPUTE: 386 type = AMD_IP_BLOCK_TYPE_GFX; 387 for (i = 0; i < adev->gfx.num_compute_rings; i++) 388 if (adev->gfx.compute_ring[i].sched.ready) 389 ++num_rings; 390 ib_start_alignment = 32; 391 ib_size_alignment = 32; 392 break; 393 case AMDGPU_HW_IP_DMA: 394 type = AMD_IP_BLOCK_TYPE_SDMA; 395 for (i = 0; i < adev->sdma.num_instances; i++) 396 if (adev->sdma.instance[i].ring.sched.ready) 397 ++num_rings; 398 ib_start_alignment = 256; 399 ib_size_alignment = 4; 400 break; 401 case AMDGPU_HW_IP_UVD: 402 type = AMD_IP_BLOCK_TYPE_UVD; 403 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 404 if (adev->uvd.harvest_config & (1 << i)) 405 continue; 406 407 if (adev->uvd.inst[i].ring.sched.ready) 408 ++num_rings; 409 } 410 ib_start_alignment = 64; 411 ib_size_alignment = 64; 412 break; 413 case AMDGPU_HW_IP_VCE: 414 type = AMD_IP_BLOCK_TYPE_VCE; 415 for (i = 0; i < adev->vce.num_rings; i++) 416 if (adev->vce.ring[i].sched.ready) 417 ++num_rings; 418 ib_start_alignment = 4; 419 ib_size_alignment = 1; 420 break; 421 case AMDGPU_HW_IP_UVD_ENC: 422 type = AMD_IP_BLOCK_TYPE_UVD; 423 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 424 if (adev->uvd.harvest_config & (1 << i)) 425 continue; 426 427 for (j = 0; j < adev->uvd.num_enc_rings; j++) 428 if (adev->uvd.inst[i].ring_enc[j].sched.ready) 429 ++num_rings; 430 } 431 ib_start_alignment = 64; 432 ib_size_alignment = 64; 433 break; 434 case AMDGPU_HW_IP_VCN_DEC: 435 type = AMD_IP_BLOCK_TYPE_VCN; 436 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 437 if (adev->uvd.harvest_config & (1 << i)) 438 continue; 439 440 if (adev->vcn.inst[i].ring_dec.sched.ready) 441 ++num_rings; 442 } 443 ib_start_alignment = 16; 444 ib_size_alignment = 16; 445 break; 446 case AMDGPU_HW_IP_VCN_ENC: 447 type = AMD_IP_BLOCK_TYPE_VCN; 448 for (i = 0; i < adev->vcn.num_vcn_inst; i++) { 449 if (adev->uvd.harvest_config & (1 << i)) 450 continue; 451 452 for (j = 0; j < adev->vcn.num_enc_rings; j++) 453 if (adev->vcn.inst[i].ring_enc[j].sched.ready) 454 ++num_rings; 455 } 456 ib_start_alignment = 64; 457 ib_size_alignment = 1; 458 break; 459 case AMDGPU_HW_IP_VCN_JPEG: 460 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 461 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 462 463 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) { 464 if (adev->jpeg.harvest_config & (1 << i)) 465 continue; 466 467 if (adev->jpeg.inst[i].ring_dec.sched.ready) 468 ++num_rings; 469 } 470 ib_start_alignment = 16; 471 ib_size_alignment = 16; 472 break; 473 default: 474 return -EINVAL; 475 } 476 477 for (i = 0; i < adev->num_ip_blocks; i++) 478 if (adev->ip_blocks[i].version->type == type && 479 adev->ip_blocks[i].status.valid) 480 break; 481 482 if (i == adev->num_ip_blocks) 483 return 0; 484 485 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type], 486 num_rings); 487 488 result->hw_ip_version_major = adev->ip_blocks[i].version->major; 489 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor; 490 491 if (adev->asic_type >= CHIP_VEGA10) { 492 switch (type) { 493 case AMD_IP_BLOCK_TYPE_GFX: 494 result->ip_discovery_version = adev->ip_versions[GC_HWIP][0]; 495 break; 496 case AMD_IP_BLOCK_TYPE_SDMA: 497 result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0]; 498 break; 499 case AMD_IP_BLOCK_TYPE_UVD: 500 case AMD_IP_BLOCK_TYPE_VCN: 501 case AMD_IP_BLOCK_TYPE_JPEG: 502 result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0]; 503 break; 504 case AMD_IP_BLOCK_TYPE_VCE: 505 result->ip_discovery_version = adev->ip_versions[VCE_HWIP][0]; 506 break; 507 default: 508 result->ip_discovery_version = 0; 509 break; 510 } 511 } else { 512 result->ip_discovery_version = 0; 513 } 514 result->capabilities_flags = 0; 515 result->available_rings = (1 << num_rings) - 1; 516 result->ib_start_alignment = ib_start_alignment; 517 result->ib_size_alignment = ib_size_alignment; 518 return 0; 519 } 520 521 /* 522 * Userspace get information ioctl 523 */ 524 /** 525 * amdgpu_info_ioctl - answer a device specific request. 526 * 527 * @dev: drm device pointer 528 * @data: request object 529 * @filp: drm filp 530 * 531 * This function is used to pass device specific parameters to the userspace 532 * drivers. Examples include: pci device id, pipeline parms, tiling params, 533 * etc. (all asics). 534 * Returns 0 on success, -EINVAL on failure. 535 */ 536 int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 537 { 538 struct amdgpu_device *adev = drm_to_adev(dev); 539 struct drm_amdgpu_info *info = data; 540 struct amdgpu_mode_info *minfo = &adev->mode_info; 541 void __user *out = (void __user *)(uintptr_t)info->return_pointer; 542 uint32_t size = info->return_size; 543 struct drm_crtc *crtc; 544 uint32_t ui32 = 0; 545 uint64_t ui64 = 0; 546 int i, found; 547 int ui32_size = sizeof(ui32); 548 549 if (!info->return_size || !info->return_pointer) 550 return -EINVAL; 551 552 switch (info->query) { 553 case AMDGPU_INFO_ACCEL_WORKING: 554 ui32 = adev->accel_working; 555 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 556 case AMDGPU_INFO_CRTC_FROM_ID: 557 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 558 crtc = (struct drm_crtc *)minfo->crtcs[i]; 559 if (crtc && crtc->base.id == info->mode_crtc.id) { 560 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 561 ui32 = amdgpu_crtc->crtc_id; 562 found = 1; 563 break; 564 } 565 } 566 if (!found) { 567 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 568 return -EINVAL; 569 } 570 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 571 case AMDGPU_INFO_HW_IP_INFO: { 572 struct drm_amdgpu_info_hw_ip ip = {}; 573 int ret; 574 575 ret = amdgpu_hw_ip_info(adev, info, &ip); 576 if (ret) 577 return ret; 578 579 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); 580 return ret ? -EFAULT : 0; 581 } 582 case AMDGPU_INFO_HW_IP_COUNT: { 583 enum amd_ip_block_type type; 584 uint32_t count = 0; 585 586 switch (info->query_hw_ip.type) { 587 case AMDGPU_HW_IP_GFX: 588 type = AMD_IP_BLOCK_TYPE_GFX; 589 break; 590 case AMDGPU_HW_IP_COMPUTE: 591 type = AMD_IP_BLOCK_TYPE_GFX; 592 break; 593 case AMDGPU_HW_IP_DMA: 594 type = AMD_IP_BLOCK_TYPE_SDMA; 595 break; 596 case AMDGPU_HW_IP_UVD: 597 type = AMD_IP_BLOCK_TYPE_UVD; 598 break; 599 case AMDGPU_HW_IP_VCE: 600 type = AMD_IP_BLOCK_TYPE_VCE; 601 break; 602 case AMDGPU_HW_IP_UVD_ENC: 603 type = AMD_IP_BLOCK_TYPE_UVD; 604 break; 605 case AMDGPU_HW_IP_VCN_DEC: 606 case AMDGPU_HW_IP_VCN_ENC: 607 type = AMD_IP_BLOCK_TYPE_VCN; 608 break; 609 case AMDGPU_HW_IP_VCN_JPEG: 610 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ? 611 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN; 612 break; 613 default: 614 return -EINVAL; 615 } 616 617 for (i = 0; i < adev->num_ip_blocks; i++) 618 if (adev->ip_blocks[i].version->type == type && 619 adev->ip_blocks[i].status.valid && 620 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 621 count++; 622 623 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 624 } 625 case AMDGPU_INFO_TIMESTAMP: 626 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev); 627 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 628 case AMDGPU_INFO_FW_VERSION: { 629 struct drm_amdgpu_info_firmware fw_info; 630 int ret; 631 632 /* We only support one instance of each IP block right now. */ 633 if (info->query_fw.ip_instance != 0) 634 return -EINVAL; 635 636 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev); 637 if (ret) 638 return ret; 639 640 return copy_to_user(out, &fw_info, 641 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 642 } 643 case AMDGPU_INFO_NUM_BYTES_MOVED: 644 ui64 = atomic64_read(&adev->num_bytes_moved); 645 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 646 case AMDGPU_INFO_NUM_EVICTIONS: 647 ui64 = atomic64_read(&adev->num_evictions); 648 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 649 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS: 650 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults); 651 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 652 case AMDGPU_INFO_VRAM_USAGE: 653 ui64 = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); 654 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 655 case AMDGPU_INFO_VIS_VRAM_USAGE: 656 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 657 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 658 case AMDGPU_INFO_GTT_USAGE: 659 ui64 = ttm_resource_manager_usage(&adev->mman.gtt_mgr.manager); 660 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 661 case AMDGPU_INFO_GDS_CONFIG: { 662 struct drm_amdgpu_info_gds gds_info; 663 664 memset(&gds_info, 0, sizeof(gds_info)); 665 gds_info.compute_partition_size = adev->gds.gds_size; 666 gds_info.gds_total_size = adev->gds.gds_size; 667 gds_info.gws_per_compute_partition = adev->gds.gws_size; 668 gds_info.oa_per_compute_partition = adev->gds.oa_size; 669 return copy_to_user(out, &gds_info, 670 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 671 } 672 case AMDGPU_INFO_VRAM_GTT: { 673 struct drm_amdgpu_info_vram_gtt vram_gtt; 674 675 vram_gtt.vram_size = adev->gmc.real_vram_size - 676 atomic64_read(&adev->vram_pin_size) - 677 AMDGPU_VM_RESERVED_VRAM; 678 vram_gtt.vram_cpu_accessible_size = 679 min(adev->gmc.visible_vram_size - 680 atomic64_read(&adev->visible_pin_size), 681 vram_gtt.vram_size); 682 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size; 683 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size); 684 return copy_to_user(out, &vram_gtt, 685 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 686 } 687 case AMDGPU_INFO_MEMORY: { 688 struct drm_amdgpu_memory_info mem; 689 struct ttm_resource_manager *gtt_man = 690 &adev->mman.gtt_mgr.manager; 691 struct ttm_resource_manager *vram_man = 692 &adev->mman.vram_mgr.manager; 693 694 memset(&mem, 0, sizeof(mem)); 695 mem.vram.total_heap_size = adev->gmc.real_vram_size; 696 mem.vram.usable_heap_size = adev->gmc.real_vram_size - 697 atomic64_read(&adev->vram_pin_size) - 698 AMDGPU_VM_RESERVED_VRAM; 699 mem.vram.heap_usage = 700 ttm_resource_manager_usage(vram_man); 701 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; 702 703 mem.cpu_accessible_vram.total_heap_size = 704 adev->gmc.visible_vram_size; 705 mem.cpu_accessible_vram.usable_heap_size = 706 min(adev->gmc.visible_vram_size - 707 atomic64_read(&adev->visible_pin_size), 708 mem.vram.usable_heap_size); 709 mem.cpu_accessible_vram.heap_usage = 710 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr); 711 mem.cpu_accessible_vram.max_allocation = 712 mem.cpu_accessible_vram.usable_heap_size * 3 / 4; 713 714 mem.gtt.total_heap_size = gtt_man->size; 715 mem.gtt.usable_heap_size = mem.gtt.total_heap_size - 716 atomic64_read(&adev->gart_pin_size); 717 mem.gtt.heap_usage = ttm_resource_manager_usage(gtt_man); 718 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4; 719 720 return copy_to_user(out, &mem, 721 min((size_t)size, sizeof(mem))) 722 ? -EFAULT : 0; 723 } 724 case AMDGPU_INFO_READ_MMR_REG: { 725 unsigned n, alloc_size; 726 uint32_t *regs; 727 unsigned se_num = (info->read_mmr_reg.instance >> 728 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 729 AMDGPU_INFO_MMR_SE_INDEX_MASK; 730 unsigned sh_num = (info->read_mmr_reg.instance >> 731 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 732 AMDGPU_INFO_MMR_SH_INDEX_MASK; 733 734 /* set full masks if the userspace set all bits 735 * in the bitfields */ 736 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 737 se_num = 0xffffffff; 738 else if (se_num >= AMDGPU_GFX_MAX_SE) 739 return -EINVAL; 740 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 741 sh_num = 0xffffffff; 742 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) 743 return -EINVAL; 744 745 if (info->read_mmr_reg.count > 128) 746 return -EINVAL; 747 748 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 749 if (!regs) 750 return -ENOMEM; 751 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 752 753 amdgpu_gfx_off_ctrl(adev, false); 754 for (i = 0; i < info->read_mmr_reg.count; i++) { 755 if (amdgpu_asic_read_register(adev, se_num, sh_num, 756 info->read_mmr_reg.dword_offset + i, 757 ®s[i])) { 758 DRM_DEBUG_KMS("unallowed offset %#x\n", 759 info->read_mmr_reg.dword_offset + i); 760 kfree(regs); 761 amdgpu_gfx_off_ctrl(adev, true); 762 return -EFAULT; 763 } 764 } 765 amdgpu_gfx_off_ctrl(adev, true); 766 n = copy_to_user(out, regs, min(size, alloc_size)); 767 kfree(regs); 768 return n ? -EFAULT : 0; 769 } 770 case AMDGPU_INFO_DEV_INFO: { 771 struct drm_amdgpu_info_device *dev_info; 772 uint64_t vm_size; 773 int ret; 774 775 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL); 776 if (!dev_info) 777 return -ENOMEM; 778 779 dev_info->device_id = adev->pdev->device; 780 dev_info->chip_rev = adev->rev_id; 781 dev_info->external_rev = adev->external_rev_id; 782 dev_info->pci_rev = adev->pdev->revision; 783 dev_info->family = adev->family; 784 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines; 785 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 786 /* return all clocks in KHz */ 787 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 788 if (adev->pm.dpm_enabled) { 789 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10; 790 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10; 791 } else { 792 dev_info->max_engine_clock = adev->clock.default_sclk * 10; 793 dev_info->max_memory_clock = adev->clock.default_mclk * 10; 794 } 795 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 796 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se * 797 adev->gfx.config.max_shader_engines; 798 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 799 dev_info->_pad = 0; 800 dev_info->ids_flags = 0; 801 if (adev->flags & AMD_IS_APU) 802 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 803 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) 804 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION; 805 if (amdgpu_is_tmz(adev)) 806 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ; 807 808 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 809 vm_size -= AMDGPU_VA_RESERVED_SIZE; 810 811 /* Older VCE FW versions are buggy and can handle only 40bits */ 812 if (adev->vce.fw_version && 813 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) 814 vm_size = min(vm_size, 1ULL << 40); 815 816 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 817 dev_info->virtual_address_max = 818 min(vm_size, AMDGPU_GMC_HOLE_START); 819 820 if (vm_size > AMDGPU_GMC_HOLE_START) { 821 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END; 822 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size; 823 } 824 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 825 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; 826 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 827 dev_info->cu_active_number = adev->gfx.cu_info.number; 828 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask; 829 dev_info->ce_ram_size = adev->gfx.ce_ram_size; 830 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0], 831 sizeof(adev->gfx.cu_info.ao_cu_bitmap)); 832 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], 833 sizeof(adev->gfx.cu_info.bitmap)); 834 dev_info->vram_type = adev->gmc.vram_type; 835 dev_info->vram_bit_width = adev->gmc.vram_width; 836 dev_info->vce_harvest_config = adev->vce.harvest_config; 837 dev_info->gc_double_offchip_lds_buf = 838 adev->gfx.config.double_offchip_lds_buf; 839 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size; 840 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs; 841 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 842 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches; 843 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth; 844 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth; 845 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads; 846 847 if (adev->family >= AMDGPU_FAMILY_NV) 848 dev_info->pa_sc_tile_steering_override = 849 adev->gfx.config.pa_sc_tile_steering_override; 850 851 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask; 852 853 ret = copy_to_user(out, dev_info, 854 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0; 855 kfree(dev_info); 856 return ret; 857 } 858 case AMDGPU_INFO_VCE_CLOCK_TABLE: { 859 unsigned i; 860 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {}; 861 struct amd_vce_state *vce_state; 862 863 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) { 864 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i); 865 if (vce_state) { 866 vce_clk_table.entries[i].sclk = vce_state->sclk; 867 vce_clk_table.entries[i].mclk = vce_state->mclk; 868 vce_clk_table.entries[i].eclk = vce_state->evclk; 869 vce_clk_table.num_valid_entries++; 870 } 871 } 872 873 return copy_to_user(out, &vce_clk_table, 874 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0; 875 } 876 case AMDGPU_INFO_VBIOS: { 877 uint32_t bios_size = adev->bios_size; 878 879 switch (info->vbios_info.type) { 880 case AMDGPU_INFO_VBIOS_SIZE: 881 return copy_to_user(out, &bios_size, 882 min((size_t)size, sizeof(bios_size))) 883 ? -EFAULT : 0; 884 case AMDGPU_INFO_VBIOS_IMAGE: { 885 uint8_t *bios; 886 uint32_t bios_offset = info->vbios_info.offset; 887 888 if (bios_offset >= bios_size) 889 return -EINVAL; 890 891 bios = adev->bios + bios_offset; 892 return copy_to_user(out, bios, 893 min((size_t)size, (size_t)(bios_size - bios_offset))) 894 ? -EFAULT : 0; 895 } 896 case AMDGPU_INFO_VBIOS_INFO: { 897 struct drm_amdgpu_info_vbios vbios_info = {}; 898 struct atom_context *atom_context; 899 900 atom_context = adev->mode_info.atom_context; 901 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name)); 902 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn)); 903 vbios_info.version = atom_context->version; 904 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str, 905 sizeof(atom_context->vbios_ver_str)); 906 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date)); 907 908 return copy_to_user(out, &vbios_info, 909 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0; 910 } 911 default: 912 DRM_DEBUG_KMS("Invalid request %d\n", 913 info->vbios_info.type); 914 return -EINVAL; 915 } 916 } 917 case AMDGPU_INFO_NUM_HANDLES: { 918 struct drm_amdgpu_info_num_handles handle; 919 920 switch (info->query_hw_ip.type) { 921 case AMDGPU_HW_IP_UVD: 922 /* Starting Polaris, we support unlimited UVD handles */ 923 if (adev->asic_type < CHIP_POLARIS10) { 924 handle.uvd_max_handles = adev->uvd.max_handles; 925 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev); 926 927 return copy_to_user(out, &handle, 928 min((size_t)size, sizeof(handle))) ? -EFAULT : 0; 929 } else { 930 return -ENODATA; 931 } 932 933 break; 934 default: 935 return -EINVAL; 936 } 937 } 938 case AMDGPU_INFO_SENSOR: { 939 if (!adev->pm.dpm_enabled) 940 return -ENOENT; 941 942 switch (info->sensor_info.type) { 943 case AMDGPU_INFO_SENSOR_GFX_SCLK: 944 /* get sclk in Mhz */ 945 if (amdgpu_dpm_read_sensor(adev, 946 AMDGPU_PP_SENSOR_GFX_SCLK, 947 (void *)&ui32, &ui32_size)) { 948 return -EINVAL; 949 } 950 ui32 /= 100; 951 break; 952 case AMDGPU_INFO_SENSOR_GFX_MCLK: 953 /* get mclk in Mhz */ 954 if (amdgpu_dpm_read_sensor(adev, 955 AMDGPU_PP_SENSOR_GFX_MCLK, 956 (void *)&ui32, &ui32_size)) { 957 return -EINVAL; 958 } 959 ui32 /= 100; 960 break; 961 case AMDGPU_INFO_SENSOR_GPU_TEMP: 962 /* get temperature in millidegrees C */ 963 if (amdgpu_dpm_read_sensor(adev, 964 AMDGPU_PP_SENSOR_GPU_TEMP, 965 (void *)&ui32, &ui32_size)) { 966 return -EINVAL; 967 } 968 break; 969 case AMDGPU_INFO_SENSOR_GPU_LOAD: 970 /* get GPU load */ 971 if (amdgpu_dpm_read_sensor(adev, 972 AMDGPU_PP_SENSOR_GPU_LOAD, 973 (void *)&ui32, &ui32_size)) { 974 return -EINVAL; 975 } 976 break; 977 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER: 978 /* get average GPU power */ 979 if (amdgpu_dpm_read_sensor(adev, 980 AMDGPU_PP_SENSOR_GPU_POWER, 981 (void *)&ui32, &ui32_size)) { 982 return -EINVAL; 983 } 984 ui32 >>= 8; 985 break; 986 case AMDGPU_INFO_SENSOR_VDDNB: 987 /* get VDDNB in millivolts */ 988 if (amdgpu_dpm_read_sensor(adev, 989 AMDGPU_PP_SENSOR_VDDNB, 990 (void *)&ui32, &ui32_size)) { 991 return -EINVAL; 992 } 993 break; 994 case AMDGPU_INFO_SENSOR_VDDGFX: 995 /* get VDDGFX in millivolts */ 996 if (amdgpu_dpm_read_sensor(adev, 997 AMDGPU_PP_SENSOR_VDDGFX, 998 (void *)&ui32, &ui32_size)) { 999 return -EINVAL; 1000 } 1001 break; 1002 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK: 1003 /* get stable pstate sclk in Mhz */ 1004 if (amdgpu_dpm_read_sensor(adev, 1005 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 1006 (void *)&ui32, &ui32_size)) { 1007 return -EINVAL; 1008 } 1009 ui32 /= 100; 1010 break; 1011 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK: 1012 /* get stable pstate mclk in Mhz */ 1013 if (amdgpu_dpm_read_sensor(adev, 1014 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 1015 (void *)&ui32, &ui32_size)) { 1016 return -EINVAL; 1017 } 1018 ui32 /= 100; 1019 break; 1020 default: 1021 DRM_DEBUG_KMS("Invalid request %d\n", 1022 info->sensor_info.type); 1023 return -EINVAL; 1024 } 1025 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1026 } 1027 case AMDGPU_INFO_VRAM_LOST_COUNTER: 1028 ui32 = atomic_read(&adev->vram_lost_counter); 1029 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 1030 case AMDGPU_INFO_RAS_ENABLED_FEATURES: { 1031 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); 1032 uint64_t ras_mask; 1033 1034 if (!ras) 1035 return -EINVAL; 1036 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features; 1037 1038 return copy_to_user(out, &ras_mask, 1039 min_t(u64, size, sizeof(ras_mask))) ? 1040 -EFAULT : 0; 1041 } 1042 case AMDGPU_INFO_VIDEO_CAPS: { 1043 const struct amdgpu_video_codecs *codecs; 1044 struct drm_amdgpu_info_video_caps *caps; 1045 int r; 1046 1047 switch (info->video_cap.type) { 1048 case AMDGPU_INFO_VIDEO_CAPS_DECODE: 1049 r = amdgpu_asic_query_video_codecs(adev, false, &codecs); 1050 if (r) 1051 return -EINVAL; 1052 break; 1053 case AMDGPU_INFO_VIDEO_CAPS_ENCODE: 1054 r = amdgpu_asic_query_video_codecs(adev, true, &codecs); 1055 if (r) 1056 return -EINVAL; 1057 break; 1058 default: 1059 DRM_DEBUG_KMS("Invalid request %d\n", 1060 info->video_cap.type); 1061 return -EINVAL; 1062 } 1063 1064 caps = kzalloc(sizeof(*caps), GFP_KERNEL); 1065 if (!caps) 1066 return -ENOMEM; 1067 1068 for (i = 0; i < codecs->codec_count; i++) { 1069 int idx = codecs->codec_array[i].codec_type; 1070 1071 switch (idx) { 1072 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2: 1073 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4: 1074 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1: 1075 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC: 1076 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC: 1077 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG: 1078 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9: 1079 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1: 1080 caps->codec_info[idx].valid = 1; 1081 caps->codec_info[idx].max_width = 1082 codecs->codec_array[i].max_width; 1083 caps->codec_info[idx].max_height = 1084 codecs->codec_array[i].max_height; 1085 caps->codec_info[idx].max_pixels_per_frame = 1086 codecs->codec_array[i].max_pixels_per_frame; 1087 caps->codec_info[idx].max_level = 1088 codecs->codec_array[i].max_level; 1089 break; 1090 default: 1091 break; 1092 } 1093 } 1094 r = copy_to_user(out, caps, 1095 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0; 1096 kfree(caps); 1097 return r; 1098 } 1099 default: 1100 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 1101 return -EINVAL; 1102 } 1103 return 0; 1104 } 1105 1106 1107 /* 1108 * Outdated mess for old drm with Xorg being in charge (void function now). 1109 */ 1110 /** 1111 * amdgpu_driver_lastclose_kms - drm callback for last close 1112 * 1113 * @dev: drm dev pointer 1114 * 1115 * Switch vga_switcheroo state after last close (all asics). 1116 */ 1117 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 1118 { 1119 drm_fb_helper_lastclose(dev); 1120 vga_switcheroo_process_delayed_switch(); 1121 } 1122 1123 /** 1124 * amdgpu_driver_open_kms - drm callback for open 1125 * 1126 * @dev: drm dev pointer 1127 * @file_priv: drm file 1128 * 1129 * On device open, init vm on cayman+ (all asics). 1130 * Returns 0 on success, error on failure. 1131 */ 1132 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1133 { 1134 struct amdgpu_device *adev = drm_to_adev(dev); 1135 struct amdgpu_fpriv *fpriv; 1136 int r, pasid; 1137 1138 /* Ensure IB tests are run on ring */ 1139 flush_delayed_work(&adev->delayed_init_work); 1140 1141 1142 if (amdgpu_ras_intr_triggered()) { 1143 DRM_ERROR("RAS Intr triggered, device disabled!!"); 1144 return -EHWPOISON; 1145 } 1146 1147 file_priv->driver_priv = NULL; 1148 1149 r = pm_runtime_get_sync(dev->dev); 1150 if (r < 0) 1151 goto pm_put; 1152 1153 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1154 if (unlikely(!fpriv)) { 1155 r = -ENOMEM; 1156 goto out_suspend; 1157 } 1158 1159 pasid = amdgpu_pasid_alloc(16); 1160 if (pasid < 0) { 1161 dev_warn(adev->dev, "No more PASIDs available!"); 1162 pasid = 0; 1163 } 1164 1165 r = amdgpu_vm_init(adev, &fpriv->vm); 1166 if (r) 1167 goto error_pasid; 1168 1169 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid); 1170 if (r) 1171 goto error_vm; 1172 1173 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL); 1174 if (!fpriv->prt_va) { 1175 r = -ENOMEM; 1176 goto error_vm; 1177 } 1178 1179 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1180 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK; 1181 1182 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj, 1183 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE); 1184 if (r) 1185 goto error_vm; 1186 } 1187 1188 rw_init(&fpriv->bo_list_lock, "agbo"); 1189 idr_init_base(&fpriv->bo_list_handles, 1); 1190 1191 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); 1192 1193 file_priv->driver_priv = fpriv; 1194 goto out_suspend; 1195 1196 error_vm: 1197 amdgpu_vm_fini(adev, &fpriv->vm); 1198 1199 error_pasid: 1200 if (pasid) { 1201 amdgpu_pasid_free(pasid); 1202 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0); 1203 } 1204 1205 kfree(fpriv); 1206 1207 out_suspend: 1208 pm_runtime_mark_last_busy(dev->dev); 1209 pm_put: 1210 pm_runtime_put_autosuspend(dev->dev); 1211 1212 return r; 1213 } 1214 1215 /** 1216 * amdgpu_driver_postclose_kms - drm callback for post close 1217 * 1218 * @dev: drm dev pointer 1219 * @file_priv: drm file 1220 * 1221 * On device post close, tear down vm on cayman+ (all asics). 1222 */ 1223 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1224 struct drm_file *file_priv) 1225 { 1226 struct amdgpu_device *adev = drm_to_adev(dev); 1227 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1228 struct amdgpu_bo_list *list; 1229 struct amdgpu_bo *pd; 1230 u32 pasid; 1231 int handle; 1232 1233 if (!fpriv) 1234 return; 1235 1236 pm_runtime_get_sync(dev->dev); 1237 1238 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL) 1239 amdgpu_uvd_free_handles(adev, file_priv); 1240 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL) 1241 amdgpu_vce_free_handles(adev, file_priv); 1242 1243 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { 1244 /* TODO: how to handle reserve failure */ 1245 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true)); 1246 amdgpu_vm_bo_del(adev, fpriv->csa_va); 1247 fpriv->csa_va = NULL; 1248 amdgpu_bo_unreserve(adev->virt.csa_obj); 1249 } 1250 1251 pasid = fpriv->vm.pasid; 1252 pd = amdgpu_bo_ref(fpriv->vm.root.bo); 1253 if (!WARN_ON(amdgpu_bo_reserve(pd, true))) { 1254 amdgpu_vm_bo_del(adev, fpriv->prt_va); 1255 amdgpu_bo_unreserve(pd); 1256 } 1257 1258 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 1259 amdgpu_vm_fini(adev, &fpriv->vm); 1260 1261 if (pasid) 1262 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); 1263 amdgpu_bo_unref(&pd); 1264 1265 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 1266 amdgpu_bo_list_put(list); 1267 1268 idr_destroy(&fpriv->bo_list_handles); 1269 mutex_destroy(&fpriv->bo_list_lock); 1270 1271 kfree(fpriv); 1272 file_priv->driver_priv = NULL; 1273 1274 pm_runtime_mark_last_busy(dev->dev); 1275 pm_runtime_put_autosuspend(dev->dev); 1276 } 1277 1278 1279 void amdgpu_driver_release_kms(struct drm_device *dev) 1280 { 1281 struct amdgpu_device *adev = drm_to_adev(dev); 1282 1283 amdgpu_device_fini_sw(adev); 1284 pci_set_drvdata(adev->pdev, NULL); 1285 } 1286 1287 /* 1288 * VBlank related functions. 1289 */ 1290 /** 1291 * amdgpu_get_vblank_counter_kms - get frame count 1292 * 1293 * @crtc: crtc to get the frame count from 1294 * 1295 * Gets the frame count on the requested crtc (all asics). 1296 * Returns frame count on success, -EINVAL on failure. 1297 */ 1298 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) 1299 { 1300 struct drm_device *dev = crtc->dev; 1301 unsigned int pipe = crtc->index; 1302 struct amdgpu_device *adev = drm_to_adev(dev); 1303 int vpos, hpos, stat; 1304 u32 count; 1305 1306 if (pipe >= adev->mode_info.num_crtc) { 1307 DRM_ERROR("Invalid crtc %u\n", pipe); 1308 return -EINVAL; 1309 } 1310 1311 /* The hw increments its frame counter at start of vsync, not at start 1312 * of vblank, as is required by DRM core vblank counter handling. 1313 * Cook the hw count here to make it appear to the caller as if it 1314 * incremented at start of vblank. We measure distance to start of 1315 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 1316 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 1317 * result by 1 to give the proper appearance to caller. 1318 */ 1319 if (adev->mode_info.crtcs[pipe]) { 1320 /* Repeat readout if needed to provide stable result if 1321 * we cross start of vsync during the queries. 1322 */ 1323 do { 1324 count = amdgpu_display_vblank_get_counter(adev, pipe); 1325 /* Ask amdgpu_display_get_crtc_scanoutpos to return 1326 * vpos as distance to start of vblank, instead of 1327 * regular vertical scanout pos. 1328 */ 1329 stat = amdgpu_display_get_crtc_scanoutpos( 1330 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 1331 &vpos, &hpos, NULL, NULL, 1332 &adev->mode_info.crtcs[pipe]->base.hwmode); 1333 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 1334 1335 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 1336 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 1337 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 1338 } else { 1339 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 1340 pipe, vpos); 1341 1342 /* Bump counter if we are at >= leading edge of vblank, 1343 * but before vsync where vpos would turn negative and 1344 * the hw counter really increments. 1345 */ 1346 if (vpos >= 0) 1347 count++; 1348 } 1349 } else { 1350 /* Fallback to use value as is. */ 1351 count = amdgpu_display_vblank_get_counter(adev, pipe); 1352 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 1353 } 1354 1355 return count; 1356 } 1357 1358 /** 1359 * amdgpu_enable_vblank_kms - enable vblank interrupt 1360 * 1361 * @crtc: crtc to enable vblank interrupt for 1362 * 1363 * Enable the interrupt on the requested crtc (all asics). 1364 * Returns 0 on success, -EINVAL on failure. 1365 */ 1366 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) 1367 { 1368 struct drm_device *dev = crtc->dev; 1369 unsigned int pipe = crtc->index; 1370 struct amdgpu_device *adev = drm_to_adev(dev); 1371 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1372 1373 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 1374 } 1375 1376 /** 1377 * amdgpu_disable_vblank_kms - disable vblank interrupt 1378 * 1379 * @crtc: crtc to disable vblank interrupt for 1380 * 1381 * Disable the interrupt on the requested crtc (all asics). 1382 */ 1383 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) 1384 { 1385 struct drm_device *dev = crtc->dev; 1386 unsigned int pipe = crtc->index; 1387 struct amdgpu_device *adev = drm_to_adev(dev); 1388 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); 1389 1390 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 1391 } 1392 1393 /* 1394 * Debugfs info 1395 */ 1396 #if defined(CONFIG_DEBUG_FS) 1397 1398 static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused) 1399 { 1400 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 1401 struct drm_amdgpu_info_firmware fw_info; 1402 struct drm_amdgpu_query_fw query_fw; 1403 struct atom_context *ctx = adev->mode_info.atom_context; 1404 uint8_t smu_program, smu_major, smu_minor, smu_debug; 1405 int ret, i; 1406 1407 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = { 1408 #define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type 1409 TA_FW_NAME(XGMI), 1410 TA_FW_NAME(RAS), 1411 TA_FW_NAME(HDCP), 1412 TA_FW_NAME(DTM), 1413 TA_FW_NAME(RAP), 1414 TA_FW_NAME(SECUREDISPLAY), 1415 #undef TA_FW_NAME 1416 }; 1417 1418 /* VCE */ 1419 query_fw.fw_type = AMDGPU_INFO_FW_VCE; 1420 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1421 if (ret) 1422 return ret; 1423 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n", 1424 fw_info.feature, fw_info.ver); 1425 1426 /* UVD */ 1427 query_fw.fw_type = AMDGPU_INFO_FW_UVD; 1428 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1429 if (ret) 1430 return ret; 1431 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n", 1432 fw_info.feature, fw_info.ver); 1433 1434 /* GMC */ 1435 query_fw.fw_type = AMDGPU_INFO_FW_GMC; 1436 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1437 if (ret) 1438 return ret; 1439 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n", 1440 fw_info.feature, fw_info.ver); 1441 1442 /* ME */ 1443 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME; 1444 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1445 if (ret) 1446 return ret; 1447 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n", 1448 fw_info.feature, fw_info.ver); 1449 1450 /* PFP */ 1451 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP; 1452 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1453 if (ret) 1454 return ret; 1455 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n", 1456 fw_info.feature, fw_info.ver); 1457 1458 /* CE */ 1459 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE; 1460 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1461 if (ret) 1462 return ret; 1463 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n", 1464 fw_info.feature, fw_info.ver); 1465 1466 /* RLC */ 1467 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC; 1468 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1469 if (ret) 1470 return ret; 1471 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n", 1472 fw_info.feature, fw_info.ver); 1473 1474 /* RLC SAVE RESTORE LIST CNTL */ 1475 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL; 1476 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1477 if (ret) 1478 return ret; 1479 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n", 1480 fw_info.feature, fw_info.ver); 1481 1482 /* RLC SAVE RESTORE LIST GPM MEM */ 1483 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM; 1484 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1485 if (ret) 1486 return ret; 1487 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n", 1488 fw_info.feature, fw_info.ver); 1489 1490 /* RLC SAVE RESTORE LIST SRM MEM */ 1491 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM; 1492 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1493 if (ret) 1494 return ret; 1495 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n", 1496 fw_info.feature, fw_info.ver); 1497 1498 /* RLCP */ 1499 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCP; 1500 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1501 if (ret) 1502 return ret; 1503 seq_printf(m, "RLCP feature version: %u, firmware version: 0x%08x\n", 1504 fw_info.feature, fw_info.ver); 1505 1506 /* RLCV */ 1507 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV; 1508 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1509 if (ret) 1510 return ret; 1511 seq_printf(m, "RLCV feature version: %u, firmware version: 0x%08x\n", 1512 fw_info.feature, fw_info.ver); 1513 1514 /* MEC */ 1515 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC; 1516 query_fw.index = 0; 1517 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1518 if (ret) 1519 return ret; 1520 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n", 1521 fw_info.feature, fw_info.ver); 1522 1523 /* MEC2 */ 1524 if (adev->gfx.mec2_fw) { 1525 query_fw.index = 1; 1526 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1527 if (ret) 1528 return ret; 1529 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n", 1530 fw_info.feature, fw_info.ver); 1531 } 1532 1533 /* IMU */ 1534 query_fw.fw_type = AMDGPU_INFO_FW_IMU; 1535 query_fw.index = 0; 1536 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1537 if (ret) 1538 return ret; 1539 seq_printf(m, "IMU feature version: %u, firmware version: 0x%08x\n", 1540 fw_info.feature, fw_info.ver); 1541 1542 /* PSP SOS */ 1543 query_fw.fw_type = AMDGPU_INFO_FW_SOS; 1544 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1545 if (ret) 1546 return ret; 1547 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n", 1548 fw_info.feature, fw_info.ver); 1549 1550 1551 /* PSP ASD */ 1552 query_fw.fw_type = AMDGPU_INFO_FW_ASD; 1553 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1554 if (ret) 1555 return ret; 1556 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n", 1557 fw_info.feature, fw_info.ver); 1558 1559 query_fw.fw_type = AMDGPU_INFO_FW_TA; 1560 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) { 1561 query_fw.index = i; 1562 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1563 if (ret) 1564 continue; 1565 1566 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n", 1567 ta_fw_name[i], fw_info.feature, fw_info.ver); 1568 } 1569 1570 /* SMC */ 1571 query_fw.fw_type = AMDGPU_INFO_FW_SMC; 1572 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1573 if (ret) 1574 return ret; 1575 smu_program = (fw_info.ver >> 24) & 0xff; 1576 smu_major = (fw_info.ver >> 16) & 0xff; 1577 smu_minor = (fw_info.ver >> 8) & 0xff; 1578 smu_debug = (fw_info.ver >> 0) & 0xff; 1579 seq_printf(m, "SMC feature version: %u, program: %d, firmware version: 0x%08x (%d.%d.%d)\n", 1580 fw_info.feature, smu_program, fw_info.ver, smu_major, smu_minor, smu_debug); 1581 1582 /* SDMA */ 1583 query_fw.fw_type = AMDGPU_INFO_FW_SDMA; 1584 for (i = 0; i < adev->sdma.num_instances; i++) { 1585 query_fw.index = i; 1586 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1587 if (ret) 1588 return ret; 1589 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n", 1590 i, fw_info.feature, fw_info.ver); 1591 } 1592 1593 /* VCN */ 1594 query_fw.fw_type = AMDGPU_INFO_FW_VCN; 1595 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1596 if (ret) 1597 return ret; 1598 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n", 1599 fw_info.feature, fw_info.ver); 1600 1601 /* DMCU */ 1602 query_fw.fw_type = AMDGPU_INFO_FW_DMCU; 1603 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1604 if (ret) 1605 return ret; 1606 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n", 1607 fw_info.feature, fw_info.ver); 1608 1609 /* DMCUB */ 1610 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB; 1611 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1612 if (ret) 1613 return ret; 1614 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n", 1615 fw_info.feature, fw_info.ver); 1616 1617 /* TOC */ 1618 query_fw.fw_type = AMDGPU_INFO_FW_TOC; 1619 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1620 if (ret) 1621 return ret; 1622 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n", 1623 fw_info.feature, fw_info.ver); 1624 1625 /* CAP */ 1626 if (adev->psp.cap_fw) { 1627 query_fw.fw_type = AMDGPU_INFO_FW_CAP; 1628 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1629 if (ret) 1630 return ret; 1631 seq_printf(m, "CAP feature version: %u, firmware version: 0x%08x\n", 1632 fw_info.feature, fw_info.ver); 1633 } 1634 1635 /* MES_KIQ */ 1636 query_fw.fw_type = AMDGPU_INFO_FW_MES_KIQ; 1637 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1638 if (ret) 1639 return ret; 1640 seq_printf(m, "MES_KIQ feature version: %u, firmware version: 0x%08x\n", 1641 fw_info.feature, fw_info.ver); 1642 1643 /* MES */ 1644 query_fw.fw_type = AMDGPU_INFO_FW_MES; 1645 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev); 1646 if (ret) 1647 return ret; 1648 seq_printf(m, "MES feature version: %u, firmware version: 0x%08x\n", 1649 fw_info.feature, fw_info.ver); 1650 1651 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version); 1652 1653 return 0; 1654 } 1655 1656 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info); 1657 1658 #endif 1659 1660 void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev) 1661 { 1662 #if defined(CONFIG_DEBUG_FS) 1663 struct drm_minor *minor = adev_to_drm(adev)->primary; 1664 struct dentry *root = minor->debugfs_root; 1665 1666 debugfs_create_file("amdgpu_firmware_info", 0444, root, 1667 adev, &amdgpu_debugfs_firmware_info_fops); 1668 1669 #endif 1670 } 1671