xref: /openbsd-src/sys/dev/pci/drm/amd/amdgpu/amdgpu_irq.c (revision 7350f337b9e3eb4461d99580e625c7ef148d107c)
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 
29 /**
30  * DOC: Interrupt Handling
31  *
32  * Interrupts generated within GPU hardware raise interrupt requests that are
33  * passed to amdgpu IRQ handler which is responsible for detecting source and
34  * type of the interrupt and dispatching matching handlers. If handling an
35  * interrupt requires calling kernel functions that may sleep processing is
36  * dispatched to work handlers.
37  *
38  * If MSI functionality is not disabled by module parameter then MSI
39  * support will be enabled.
40  *
41  * For GPU interrupt sources that may be driven by another driver, IRQ domain
42  * support is used (with mapping between virtual and hardware IRQs).
43  */
44 
45 #include <linux/irq.h>
46 #include <drm/drmP.h>
47 #include <drm/drm_crtc_helper.h>
48 #include <drm/amdgpu_drm.h>
49 #include "amdgpu.h"
50 #include "amdgpu_ih.h"
51 #include "atom.h"
52 #include "amdgpu_connectors.h"
53 #include "amdgpu_trace.h"
54 
55 #include <linux/pm_runtime.h>
56 
57 #ifdef CONFIG_DRM_AMD_DC
58 #include "amdgpu_dm_irq.h"
59 #endif
60 
61 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
62 
63 /**
64  * amdgpu_hotplug_work_func - work handler for display hotplug event
65  *
66  * @work: work struct pointer
67  *
68  * This is the hotplug event work handler (all ASICs).
69  * The work gets scheduled from the IRQ handler if there
70  * was a hotplug interrupt.  It walks through the connector table
71  * and calls hotplug handler for each connector. After this, it sends
72  * a DRM hotplug event to alert userspace.
73  *
74  * This design approach is required in order to defer hotplug event handling
75  * from the IRQ handler to a work handler because hotplug handler has to use
76  * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
77  * sleep).
78  */
79 static void amdgpu_hotplug_work_func(struct work_struct *work)
80 {
81 	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
82 						  hotplug_work);
83 	struct drm_device *dev = adev->ddev;
84 	struct drm_mode_config *mode_config = &dev->mode_config;
85 	struct drm_connector *connector;
86 
87 	mutex_lock(&mode_config->mutex);
88 	list_for_each_entry(connector, &mode_config->connector_list, head)
89 		amdgpu_connector_hotplug(connector);
90 	mutex_unlock(&mode_config->mutex);
91 	/* Just fire off a uevent and let userspace tell us what to do */
92 	drm_helper_hpd_irq_event(dev);
93 }
94 
95 /**
96  * amdgpu_irq_reset_work_func - execute GPU reset
97  *
98  * @work: work struct pointer
99  *
100  * Execute scheduled GPU reset (Cayman+).
101  * This function is called when the IRQ handler thinks we need a GPU reset.
102  */
103 static void amdgpu_irq_reset_work_func(struct work_struct *work)
104 {
105 	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
106 						  reset_work);
107 
108 	if (!amdgpu_sriov_vf(adev))
109 		amdgpu_device_gpu_recover(adev, NULL, false);
110 }
111 
112 /**
113  * amdgpu_irq_disable_all - disable *all* interrupts
114  *
115  * @adev: amdgpu device pointer
116  *
117  * Disable all types of interrupts from all sources.
118  */
119 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
120 {
121 	unsigned long irqflags;
122 	unsigned i, j, k;
123 	int r;
124 
125 	spin_lock_irqsave(&adev->irq.lock, irqflags);
126 	for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
127 		if (!adev->irq.client[i].sources)
128 			continue;
129 
130 		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
131 			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
132 
133 			if (!src || !src->funcs->set || !src->num_types)
134 				continue;
135 
136 			for (k = 0; k < src->num_types; ++k) {
137 				atomic_set(&src->enabled_types[k], 0);
138 				r = src->funcs->set(adev, src, k,
139 						    AMDGPU_IRQ_STATE_DISABLE);
140 				if (r)
141 					DRM_ERROR("error disabling interrupt (%d)\n",
142 						  r);
143 			}
144 		}
145 	}
146 	spin_unlock_irqrestore(&adev->irq.lock, irqflags);
147 }
148 
149 /**
150  * amdgpu_irq_handler - IRQ handler
151  *
152  * @irq: IRQ number (unused)
153  * @arg: pointer to DRM device
154  *
155  * IRQ handler for amdgpu driver (all ASICs).
156  *
157  * Returns:
158  * result of handling the IRQ, as defined by &irqreturn_t
159  */
160 irqreturn_t amdgpu_irq_handler(void *arg)
161 {
162 	struct drm_device *dev = (struct drm_device *) arg;
163 	struct amdgpu_device *adev = dev->dev_private;
164 	irqreturn_t ret;
165 
166 	if (!adev->irq.installed)
167 		return 0;
168 
169 	ret = amdgpu_ih_process(adev);
170 	if (ret == IRQ_HANDLED)
171 		pm_runtime_mark_last_busy(dev->dev);
172 	return ret;
173 }
174 
175 /**
176  * amdgpu_msi_ok - check whether MSI functionality is enabled
177  *
178  * @adev: amdgpu device pointer (unused)
179  *
180  * Checks whether MSI functionality has been disabled via module parameter
181  * (all ASICs).
182  *
183  * Returns:
184  * *true* if MSIs are allowed to be enabled or *false* otherwise
185  */
186 bool amdgpu_msi_ok(struct amdgpu_device *adev)
187 {
188 	if (amdgpu_msi == 1)
189 		return true;
190 	else if (amdgpu_msi == 0)
191 		return false;
192 
193 	return true;
194 }
195 
196 /**
197  * amdgpu_irq_init - initialize interrupt handling
198  *
199  * @adev: amdgpu device pointer
200  *
201  * Sets up work functions for hotplug and reset interrupts, enables MSI
202  * functionality, initializes vblank, hotplug and reset interrupt handling.
203  *
204  * Returns:
205  * 0 on success or error code on failure
206  */
207 int amdgpu_irq_init(struct amdgpu_device *adev)
208 {
209 	int r = 0;
210 
211 	mtx_init(&adev->irq.lock, IPL_TTY);
212 
213 #ifdef notyet
214 	/* Enable MSI if not disabled by module parameter */
215 	adev->irq.msi_enabled = false;
216 
217 	if (amdgpu_msi_ok(adev)) {
218 		int ret = pci_enable_msi(adev->pdev);
219 		if (!ret) {
220 			adev->irq.msi_enabled = true;
221 			dev_dbg(adev->dev, "amdgpu: using MSI.\n");
222 		}
223 	}
224 #endif
225 
226 	if (!amdgpu_device_has_dc_support(adev)) {
227 		if (!adev->enable_virtual_display)
228 			/* Disable vblank IRQs aggressively for power-saving */
229 			/* XXX: can this be enabled for DC? */
230 			adev->ddev->vblank_disable_immediate = true;
231 
232 		r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
233 		if (r)
234 			return r;
235 
236 		/* Pre-DCE11 */
237 		INIT_WORK(&adev->hotplug_work,
238 				amdgpu_hotplug_work_func);
239 	}
240 
241 	INIT_WORK(&adev->reset_work, amdgpu_irq_reset_work_func);
242 
243 	adev->irq.installed = true;
244 	r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq);
245 	if (r) {
246 		adev->irq.installed = false;
247 		if (!amdgpu_device_has_dc_support(adev))
248 			flush_work(&adev->hotplug_work);
249 		cancel_work_sync(&adev->reset_work);
250 		return r;
251 	}
252 	adev->ddev->max_vblank_count = 0x00ffffff;
253 
254 	DRM_DEBUG("amdgpu: irq initialized.\n");
255 	return 0;
256 }
257 
258 /**
259  * amdgpu_irq_fini - shut down interrupt handling
260  *
261  * @adev: amdgpu device pointer
262  *
263  * Tears down work functions for hotplug and reset interrupts, disables MSI
264  * functionality, shuts down vblank, hotplug and reset interrupt handling,
265  * turns off interrupts from all sources (all ASICs).
266  */
267 void amdgpu_irq_fini(struct amdgpu_device *adev)
268 {
269 	unsigned i, j;
270 
271 	if (adev->irq.installed) {
272 		drm_irq_uninstall(adev->ddev);
273 		adev->irq.installed = false;
274 		if (adev->irq.msi_enabled)
275 			pci_disable_msi(adev->pdev);
276 		if (!amdgpu_device_has_dc_support(adev))
277 			flush_work(&adev->hotplug_work);
278 		cancel_work_sync(&adev->reset_work);
279 	}
280 
281 	for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
282 		if (!adev->irq.client[i].sources)
283 			continue;
284 
285 		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
286 			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
287 
288 			if (!src)
289 				continue;
290 
291 			kfree(src->enabled_types);
292 			src->enabled_types = NULL;
293 			if (src->data) {
294 				kfree(src->data);
295 				kfree(src);
296 				adev->irq.client[i].sources[j] = NULL;
297 			}
298 		}
299 		kfree(adev->irq.client[i].sources);
300 		adev->irq.client[i].sources = NULL;
301 	}
302 }
303 
304 /**
305  * amdgpu_irq_add_id - register IRQ source
306  *
307  * @adev: amdgpu device pointer
308  * @client_id: client id
309  * @src_id: source id
310  * @source: IRQ source pointer
311  *
312  * Registers IRQ source on a client.
313  *
314  * Returns:
315  * 0 on success or error code otherwise
316  */
317 int amdgpu_irq_add_id(struct amdgpu_device *adev,
318 		      unsigned client_id, unsigned src_id,
319 		      struct amdgpu_irq_src *source)
320 {
321 	if (client_id >= AMDGPU_IH_CLIENTID_MAX)
322 		return -EINVAL;
323 
324 	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
325 		return -EINVAL;
326 
327 	if (!source->funcs)
328 		return -EINVAL;
329 
330 	if (!adev->irq.client[client_id].sources) {
331 		adev->irq.client[client_id].sources =
332 			kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
333 				sizeof(struct amdgpu_irq_src *),
334 				GFP_KERNEL);
335 		if (!adev->irq.client[client_id].sources)
336 			return -ENOMEM;
337 	}
338 
339 	if (adev->irq.client[client_id].sources[src_id] != NULL)
340 		return -EINVAL;
341 
342 	if (source->num_types && !source->enabled_types) {
343 		atomic_t *types;
344 
345 		types = kcalloc(source->num_types, sizeof(atomic_t),
346 				GFP_KERNEL);
347 		if (!types)
348 			return -ENOMEM;
349 
350 		source->enabled_types = types;
351 	}
352 
353 	adev->irq.client[client_id].sources[src_id] = source;
354 	return 0;
355 }
356 
357 /**
358  * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
359  *
360  * @adev: amdgpu device pointer
361  * @entry: interrupt vector pointer
362  *
363  * Dispatches IRQ to IP blocks.
364  */
365 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
366 			 struct amdgpu_iv_entry *entry)
367 {
368 	unsigned client_id = entry->client_id;
369 	unsigned src_id = entry->src_id;
370 	struct amdgpu_irq_src *src;
371 	int r;
372 
373 	trace_amdgpu_iv(entry);
374 
375 	if (client_id >= AMDGPU_IH_CLIENTID_MAX) {
376 		DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
377 		return;
378 	}
379 
380 	if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
381 		DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
382 		return;
383 	}
384 
385 	if (adev->irq.virq[src_id]) {
386 		STUB();
387 #ifdef notyet
388 		generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
389 #endif
390 	} else {
391 		if (!adev->irq.client[client_id].sources) {
392 			DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
393 				  client_id, src_id);
394 			return;
395 		}
396 
397 		src = adev->irq.client[client_id].sources[src_id];
398 		if (!src) {
399 			DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
400 			return;
401 		}
402 
403 		r = src->funcs->process(adev, src, entry);
404 		if (r)
405 			DRM_ERROR("error processing interrupt (%d)\n", r);
406 	}
407 }
408 
409 /**
410  * amdgpu_irq_update - update hardware interrupt state
411  *
412  * @adev: amdgpu device pointer
413  * @src: interrupt source pointer
414  * @type: type of interrupt
415  *
416  * Updates interrupt state for the specific source (all ASICs).
417  */
418 int amdgpu_irq_update(struct amdgpu_device *adev,
419 			     struct amdgpu_irq_src *src, unsigned type)
420 {
421 	unsigned long irqflags;
422 	enum amdgpu_interrupt_state state;
423 	int r;
424 
425 	spin_lock_irqsave(&adev->irq.lock, irqflags);
426 
427 	/* We need to determine after taking the lock, otherwise
428 	   we might disable just enabled interrupts again */
429 	if (amdgpu_irq_enabled(adev, src, type))
430 		state = AMDGPU_IRQ_STATE_ENABLE;
431 	else
432 		state = AMDGPU_IRQ_STATE_DISABLE;
433 
434 	r = src->funcs->set(adev, src, type, state);
435 	spin_unlock_irqrestore(&adev->irq.lock, irqflags);
436 	return r;
437 }
438 
439 /**
440  * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
441  *
442  * @adev: amdgpu device pointer
443  *
444  * Updates state of all types of interrupts on all sources on resume after
445  * reset.
446  */
447 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
448 {
449 	int i, j, k;
450 
451 	for (i = 0; i < AMDGPU_IH_CLIENTID_MAX; ++i) {
452 		if (!adev->irq.client[i].sources)
453 			continue;
454 
455 		for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
456 			struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
457 
458 			if (!src)
459 				continue;
460 			for (k = 0; k < src->num_types; k++)
461 				amdgpu_irq_update(adev, src, k);
462 		}
463 	}
464 }
465 
466 /**
467  * amdgpu_irq_get - enable interrupt
468  *
469  * @adev: amdgpu device pointer
470  * @src: interrupt source pointer
471  * @type: type of interrupt
472  *
473  * Enables specified type of interrupt on the specified source (all ASICs).
474  *
475  * Returns:
476  * 0 on success or error code otherwise
477  */
478 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
479 		   unsigned type)
480 {
481 	if (!adev->ddev->irq_enabled)
482 		return -ENOENT;
483 
484 	if (type >= src->num_types)
485 		return -EINVAL;
486 
487 	if (!src->enabled_types || !src->funcs->set)
488 		return -EINVAL;
489 
490 	if (atomic_inc_return(&src->enabled_types[type]) == 1)
491 		return amdgpu_irq_update(adev, src, type);
492 
493 	return 0;
494 }
495 
496 /**
497  * amdgpu_irq_put - disable interrupt
498  *
499  * @adev: amdgpu device pointer
500  * @src: interrupt source pointer
501  * @type: type of interrupt
502  *
503  * Enables specified type of interrupt on the specified source (all ASICs).
504  *
505  * Returns:
506  * 0 on success or error code otherwise
507  */
508 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
509 		   unsigned type)
510 {
511 	if (!adev->ddev->irq_enabled)
512 		return -ENOENT;
513 
514 	if (type >= src->num_types)
515 		return -EINVAL;
516 
517 	if (!src->enabled_types || !src->funcs->set)
518 		return -EINVAL;
519 
520 	if (atomic_dec_and_test(&src->enabled_types[type]))
521 		return amdgpu_irq_update(adev, src, type);
522 
523 	return 0;
524 }
525 
526 /**
527  * amdgpu_irq_enabled - check whether interrupt is enabled or not
528  *
529  * @adev: amdgpu device pointer
530  * @src: interrupt source pointer
531  * @type: type of interrupt
532  *
533  * Checks whether the given type of interrupt is enabled on the given source.
534  *
535  * Returns:
536  * *true* if interrupt is enabled, *false* if interrupt is disabled or on
537  * invalid parameters
538  */
539 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
540 			unsigned type)
541 {
542 	if (!adev->ddev->irq_enabled)
543 		return false;
544 
545 	if (type >= src->num_types)
546 		return false;
547 
548 	if (!src->enabled_types || !src->funcs->set)
549 		return false;
550 
551 	return !!atomic_read(&src->enabled_types[type]);
552 }
553 
554 #ifdef __linux__
555 /* XXX: Generic IRQ handling */
556 static void amdgpu_irq_mask(struct irq_data *irqd)
557 {
558 	/* XXX */
559 }
560 
561 static void amdgpu_irq_unmask(struct irq_data *irqd)
562 {
563 	/* XXX */
564 }
565 
566 /* amdgpu hardware interrupt chip descriptor */
567 static struct irq_chip amdgpu_irq_chip = {
568 	.name = "amdgpu-ih",
569 	.irq_mask = amdgpu_irq_mask,
570 	.irq_unmask = amdgpu_irq_unmask,
571 };
572 #endif
573 
574 #ifdef __linux__
575 /**
576  * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
577  *
578  * @d: amdgpu IRQ domain pointer (unused)
579  * @irq: virtual IRQ number
580  * @hwirq: hardware irq number
581  *
582  * Current implementation assigns simple interrupt handler to the given virtual
583  * IRQ.
584  *
585  * Returns:
586  * 0 on success or error code otherwise
587  */
588 static int amdgpu_irqdomain_map(struct irq_domain *d,
589 				unsigned int irq, irq_hw_number_t hwirq)
590 {
591 	if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
592 		return -EPERM;
593 
594 	irq_set_chip_and_handler(irq,
595 				 &amdgpu_irq_chip, handle_simple_irq);
596 	return 0;
597 }
598 
599 /* Implementation of methods for amdgpu IRQ domain */
600 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
601 	.map = amdgpu_irqdomain_map,
602 };
603 #endif
604 
605 /**
606  * amdgpu_irq_add_domain - create a linear IRQ domain
607  *
608  * @adev: amdgpu device pointer
609  *
610  * Creates an IRQ domain for GPU interrupt sources
611  * that may be driven by another driver (e.g., ACP).
612  *
613  * Returns:
614  * 0 on success or error code otherwise
615  */
616 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
617 {
618 	STUB();
619 	return 0;
620 #if 0
621 	adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
622 						 &amdgpu_hw_irqdomain_ops, adev);
623 	if (!adev->irq.domain) {
624 		DRM_ERROR("GPU irq add domain failed\n");
625 		return -ENODEV;
626 	}
627 
628 	return 0;
629 #endif
630 }
631 
632 /**
633  * amdgpu_irq_remove_domain - remove the IRQ domain
634  *
635  * @adev: amdgpu device pointer
636  *
637  * Removes the IRQ domain for GPU interrupt sources
638  * that may be driven by another driver (e.g., ACP).
639  */
640 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
641 {
642 	STUB();
643 #if 0
644 	if (adev->irq.domain) {
645 		irq_domain_remove(adev->irq.domain);
646 		adev->irq.domain = NULL;
647 	}
648 #endif
649 }
650 
651 /**
652  * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
653  *
654  * @adev: amdgpu device pointer
655  * @src_id: IH source id
656  *
657  * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
658  * Use this for components that generate a GPU interrupt, but are driven
659  * by a different driver (e.g., ACP).
660  *
661  * Returns:
662  * Linux IRQ
663  */
664 unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
665 {
666 	STUB();
667 	return 0;
668 #if 0
669 	adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
670 
671 	return adev->irq.virq[src_id];
672 #endif
673 }
674