1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <linux/export.h> 27 28 #include <drm/drmP.h> 29 #include <drm/drm_edid.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "amdgpu_i2c.h" 33 #include "amdgpu_atombios.h" 34 #include "atom.h" 35 #include "atombios_dp.h" 36 #include "atombios_i2c.h" 37 38 #include <dev/i2c/i2cvar.h> 39 #include <dev/i2c/i2c_bitbang.h> 40 41 /* bit banging i2c */ 42 static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap) 43 { 44 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 45 struct amdgpu_device *adev = i2c->dev->dev_private; 46 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 47 uint32_t temp; 48 49 mutex_lock(&i2c->mutex); 50 51 /* switch the pads to ddc mode */ 52 if (rec->hw_capable) { 53 temp = RREG32(rec->mask_clk_reg); 54 temp &= ~(1 << 16); 55 WREG32(rec->mask_clk_reg, temp); 56 } 57 58 /* clear the output pin values */ 59 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 60 WREG32(rec->a_clk_reg, temp); 61 62 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 63 WREG32(rec->a_data_reg, temp); 64 65 /* set the pins to input */ 66 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 67 WREG32(rec->en_clk_reg, temp); 68 69 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 70 WREG32(rec->en_data_reg, temp); 71 72 /* mask the gpio pins for software use */ 73 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 74 WREG32(rec->mask_clk_reg, temp); 75 temp = RREG32(rec->mask_clk_reg); 76 77 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 78 WREG32(rec->mask_data_reg, temp); 79 temp = RREG32(rec->mask_data_reg); 80 81 return 0; 82 } 83 84 static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap) 85 { 86 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 87 struct amdgpu_device *adev = i2c->dev->dev_private; 88 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 89 uint32_t temp; 90 91 /* unmask the gpio pins for software use */ 92 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 93 WREG32(rec->mask_clk_reg, temp); 94 temp = RREG32(rec->mask_clk_reg); 95 96 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 97 WREG32(rec->mask_data_reg, temp); 98 temp = RREG32(rec->mask_data_reg); 99 100 mutex_unlock(&i2c->mutex); 101 } 102 103 static int amdgpu_i2c_get_clock(void *i2c_priv) 104 { 105 struct amdgpu_i2c_chan *i2c = i2c_priv; 106 struct amdgpu_device *adev = i2c->dev->dev_private; 107 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 108 uint32_t val; 109 110 /* read the value off the pin */ 111 val = RREG32(rec->y_clk_reg); 112 val &= rec->y_clk_mask; 113 114 return (val != 0); 115 } 116 117 118 static int amdgpu_i2c_get_data(void *i2c_priv) 119 { 120 struct amdgpu_i2c_chan *i2c = i2c_priv; 121 struct amdgpu_device *adev = i2c->dev->dev_private; 122 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 123 uint32_t val; 124 125 /* read the value off the pin */ 126 val = RREG32(rec->y_data_reg); 127 val &= rec->y_data_mask; 128 129 return (val != 0); 130 } 131 132 static void amdgpu_i2c_set_clock(void *i2c_priv, int clock) 133 { 134 struct amdgpu_i2c_chan *i2c = i2c_priv; 135 struct amdgpu_device *adev = i2c->dev->dev_private; 136 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 137 uint32_t val; 138 139 /* set pin direction */ 140 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 141 val |= clock ? 0 : rec->en_clk_mask; 142 WREG32(rec->en_clk_reg, val); 143 } 144 145 static void amdgpu_i2c_set_data(void *i2c_priv, int data) 146 { 147 struct amdgpu_i2c_chan *i2c = i2c_priv; 148 struct amdgpu_device *adev = i2c->dev->dev_private; 149 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 150 uint32_t val; 151 152 /* set pin direction */ 153 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 154 val |= data ? 0 : rec->en_data_mask; 155 WREG32(rec->en_data_reg, val); 156 } 157 158 void amdgpu_bb_set_bits(void *, uint32_t); 159 void amdgpu_bb_set_dir(void *, uint32_t); 160 uint32_t amdgpu_bb_read_bits(void *); 161 162 int amdgpu_acquire_bus(void *, int); 163 void amdgpu_release_bus(void *, int); 164 int amdgpu_send_start(void *, int); 165 int amdgpu_send_stop(void *, int); 166 int amdgpu_initiate_xfer(void *, i2c_addr_t, int); 167 int amdgpu_read_byte(void *, u_int8_t *, int); 168 int amdgpu_write_byte(void *, u_int8_t, int); 169 170 #define AMDGPU_BB_SDA (1 << I2C_BIT_SDA) 171 #define AMDGPU_BB_SCL (1 << I2C_BIT_SCL) 172 173 struct i2c_bitbang_ops amdgpu_bbops = { 174 amdgpu_bb_set_bits, 175 amdgpu_bb_set_dir, 176 amdgpu_bb_read_bits, 177 { AMDGPU_BB_SDA, AMDGPU_BB_SCL, 0, 0 } 178 }; 179 180 void 181 amdgpu_bb_set_bits(void *cookie, uint32_t bits) 182 { 183 amdgpu_i2c_set_clock(cookie, bits & AMDGPU_BB_SCL); 184 amdgpu_i2c_set_data(cookie, bits & AMDGPU_BB_SDA); 185 } 186 187 void 188 amdgpu_bb_set_dir(void *cookie, uint32_t bits) 189 { 190 } 191 192 uint32_t 193 amdgpu_bb_read_bits(void *cookie) 194 { 195 uint32_t bits = 0; 196 197 if (amdgpu_i2c_get_clock(cookie)) 198 bits |= AMDGPU_BB_SCL; 199 if (amdgpu_i2c_get_data(cookie)) 200 bits |= AMDGPU_BB_SDA; 201 202 return bits; 203 } 204 205 int 206 amdgpu_acquire_bus(void *cookie, int flags) 207 { 208 struct amdgpu_i2c_chan *i2c = cookie; 209 amdgpu_i2c_pre_xfer(&i2c->adapter); 210 return (0); 211 } 212 213 void 214 amdgpu_release_bus(void *cookie, int flags) 215 { 216 struct amdgpu_i2c_chan *i2c = cookie; 217 amdgpu_i2c_post_xfer(&i2c->adapter); 218 } 219 220 int 221 amdgpu_send_start(void *cookie, int flags) 222 { 223 return (i2c_bitbang_send_start(cookie, flags, &amdgpu_bbops)); 224 } 225 226 int 227 amdgpu_send_stop(void *cookie, int flags) 228 { 229 return (i2c_bitbang_send_stop(cookie, flags, &amdgpu_bbops)); 230 } 231 232 int 233 amdgpu_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) 234 { 235 return (i2c_bitbang_initiate_xfer(cookie, addr, flags, &amdgpu_bbops)); 236 } 237 238 int 239 amdgpu_read_byte(void *cookie, u_int8_t *bytep, int flags) 240 { 241 return (i2c_bitbang_read_byte(cookie, bytep, flags, &amdgpu_bbops)); 242 } 243 244 int 245 amdgpu_write_byte(void *cookie, u_int8_t byte, int flags) 246 { 247 return (i2c_bitbang_write_byte(cookie, byte, flags, &amdgpu_bbops)); 248 } 249 250 static const struct i2c_algorithm amdgpu_atombios_i2c_algo = { 251 .master_xfer = amdgpu_atombios_i2c_xfer, 252 .functionality = amdgpu_atombios_i2c_func, 253 }; 254 255 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, 256 const struct amdgpu_i2c_bus_rec *rec, 257 const char *name) 258 { 259 struct amdgpu_i2c_chan *i2c; 260 int ret; 261 262 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 263 if (rec->mm_i2c && (amdgpu_hw_i2c == 0)) 264 return NULL; 265 266 i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL); 267 if (i2c == NULL) 268 return NULL; 269 270 i2c->rec = *rec; 271 #ifdef __linux__ 272 i2c->adapter.owner = THIS_MODULE; 273 i2c->adapter.class = I2C_CLASS_DDC; 274 i2c->adapter.dev.parent = &dev->pdev->dev; 275 #endif 276 i2c->dev = dev; 277 i2c_set_adapdata(&i2c->adapter, i2c); 278 rw_init(&i2c->mutex, "agiic"); 279 if (rec->hw_capable && 280 amdgpu_hw_i2c) { 281 /* hw i2c using atom */ 282 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 283 "AMDGPU i2c hw bus %s", name); 284 i2c->adapter.algo = &amdgpu_atombios_i2c_algo; 285 ret = i2c_add_adapter(&i2c->adapter); 286 if (ret) 287 goto out_free; 288 } else { 289 /* set the amdgpu bit adapter */ 290 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 291 "AMDGPU i2c bit bus %s", name); 292 i2c->adapter.algo_data = &i2c->bit; 293 #ifdef notyet 294 i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer; 295 i2c->bit.post_xfer = amdgpu_i2c_post_xfer; 296 i2c->bit.setsda = amdgpu_i2c_set_data; 297 i2c->bit.setscl = amdgpu_i2c_set_clock; 298 i2c->bit.getsda = amdgpu_i2c_get_data; 299 i2c->bit.getscl = amdgpu_i2c_get_clock; 300 i2c->bit.udelay = 10; 301 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 302 i2c->bit.data = i2c; 303 #else 304 i2c->bit.ic.ic_cookie = i2c; 305 i2c->bit.ic.ic_acquire_bus = amdgpu_acquire_bus; 306 i2c->bit.ic.ic_release_bus = amdgpu_release_bus; 307 i2c->bit.ic.ic_send_start = amdgpu_send_start; 308 i2c->bit.ic.ic_send_stop = amdgpu_send_stop; 309 i2c->bit.ic.ic_initiate_xfer = amdgpu_initiate_xfer; 310 i2c->bit.ic.ic_read_byte = amdgpu_read_byte; 311 i2c->bit.ic.ic_write_byte = amdgpu_write_byte; 312 #endif 313 ret = i2c_bit_add_bus(&i2c->adapter); 314 if (ret) { 315 DRM_ERROR("Failed to register bit i2c %s\n", name); 316 goto out_free; 317 } 318 } 319 320 return i2c; 321 out_free: 322 kfree(i2c); 323 return NULL; 324 325 } 326 327 void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c) 328 { 329 if (!i2c) 330 return; 331 WARN_ON(i2c->has_aux); 332 i2c_del_adapter(&i2c->adapter); 333 kfree(i2c); 334 } 335 336 /* Add the default buses */ 337 void amdgpu_i2c_init(struct amdgpu_device *adev) 338 { 339 if (amdgpu_hw_i2c) 340 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 341 342 amdgpu_atombios_i2c_init(adev); 343 } 344 345 /* remove all the buses */ 346 void amdgpu_i2c_fini(struct amdgpu_device *adev) 347 { 348 int i; 349 350 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 351 if (adev->i2c_bus[i]) { 352 amdgpu_i2c_destroy(adev->i2c_bus[i]); 353 adev->i2c_bus[i] = NULL; 354 } 355 } 356 } 357 358 /* Add additional buses */ 359 void amdgpu_i2c_add(struct amdgpu_device *adev, 360 const struct amdgpu_i2c_bus_rec *rec, 361 const char *name) 362 { 363 struct drm_device *dev = adev->ddev; 364 int i; 365 366 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 367 if (!adev->i2c_bus[i]) { 368 adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name); 369 return; 370 } 371 } 372 } 373 374 /* looks up bus based on id */ 375 struct amdgpu_i2c_chan * 376 amdgpu_i2c_lookup(struct amdgpu_device *adev, 377 const struct amdgpu_i2c_bus_rec *i2c_bus) 378 { 379 int i; 380 381 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 382 if (adev->i2c_bus[i] && 383 (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 384 return adev->i2c_bus[i]; 385 } 386 } 387 return NULL; 388 } 389 390 static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus, 391 u8 slave_addr, 392 u8 addr, 393 u8 *val) 394 { 395 u8 out_buf[2]; 396 u8 in_buf[2]; 397 struct i2c_msg msgs[] = { 398 { 399 .addr = slave_addr, 400 .flags = 0, 401 .len = 1, 402 .buf = out_buf, 403 }, 404 { 405 .addr = slave_addr, 406 .flags = I2C_M_RD, 407 .len = 1, 408 .buf = in_buf, 409 } 410 }; 411 412 out_buf[0] = addr; 413 out_buf[1] = 0; 414 415 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 416 *val = in_buf[0]; 417 DRM_DEBUG("val = 0x%02x\n", *val); 418 } else { 419 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 420 addr, *val); 421 } 422 } 423 424 static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus, 425 u8 slave_addr, 426 u8 addr, 427 u8 val) 428 { 429 uint8_t out_buf[2]; 430 struct i2c_msg msg = { 431 .addr = slave_addr, 432 .flags = 0, 433 .len = 2, 434 .buf = out_buf, 435 }; 436 437 out_buf[0] = addr; 438 out_buf[1] = val; 439 440 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 441 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 442 addr, val); 443 } 444 445 /* ddc router switching */ 446 void 447 amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector) 448 { 449 u8 val; 450 451 if (!amdgpu_connector->router.ddc_valid) 452 return; 453 454 if (!amdgpu_connector->router_bus) 455 return; 456 457 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 458 amdgpu_connector->router.i2c_addr, 459 0x3, &val); 460 val &= ~amdgpu_connector->router.ddc_mux_control_pin; 461 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 462 amdgpu_connector->router.i2c_addr, 463 0x3, val); 464 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 465 amdgpu_connector->router.i2c_addr, 466 0x1, &val); 467 val &= ~amdgpu_connector->router.ddc_mux_control_pin; 468 val |= amdgpu_connector->router.ddc_mux_state; 469 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 470 amdgpu_connector->router.i2c_addr, 471 0x1, val); 472 } 473 474 /* clock/data router switching */ 475 void 476 amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector) 477 { 478 u8 val; 479 480 if (!amdgpu_connector->router.cd_valid) 481 return; 482 483 if (!amdgpu_connector->router_bus) 484 return; 485 486 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 487 amdgpu_connector->router.i2c_addr, 488 0x3, &val); 489 val &= ~amdgpu_connector->router.cd_mux_control_pin; 490 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 491 amdgpu_connector->router.i2c_addr, 492 0x3, val); 493 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 494 amdgpu_connector->router.i2c_addr, 495 0x1, &val); 496 val &= ~amdgpu_connector->router.cd_mux_control_pin; 497 val |= amdgpu_connector->router.cd_mux_state; 498 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 499 amdgpu_connector->router.i2c_addr, 500 0x1, val); 501 } 502