1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <linux/firmware.h> 27 #include "amdgpu.h" 28 #include "amdgpu_gfx.h" 29 #include "amdgpu_rlc.h" 30 #include "amdgpu_ras.h" 31 32 /* delay 0.1 second to enable gfx off feature */ 33 #define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100) 34 35 #define GFX_OFF_NO_DELAY 0 36 37 /* 38 * GPU GFX IP block helpers function. 39 */ 40 41 int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 42 int pipe, int queue) 43 { 44 int bit = 0; 45 46 bit += mec * adev->gfx.mec.num_pipe_per_mec 47 * adev->gfx.mec.num_queue_per_pipe; 48 bit += pipe * adev->gfx.mec.num_queue_per_pipe; 49 bit += queue; 50 51 return bit; 52 } 53 54 void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 55 int *mec, int *pipe, int *queue) 56 { 57 *queue = bit % adev->gfx.mec.num_queue_per_pipe; 58 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) 59 % adev->gfx.mec.num_pipe_per_mec; 60 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) 61 / adev->gfx.mec.num_pipe_per_mec; 62 63 } 64 65 bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, 66 int mec, int pipe, int queue) 67 { 68 return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue), 69 adev->gfx.mec.queue_bitmap); 70 } 71 72 int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, 73 int me, int pipe, int queue) 74 { 75 int bit = 0; 76 77 bit += me * adev->gfx.me.num_pipe_per_me 78 * adev->gfx.me.num_queue_per_pipe; 79 bit += pipe * adev->gfx.me.num_queue_per_pipe; 80 bit += queue; 81 82 return bit; 83 } 84 85 void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 86 int *me, int *pipe, int *queue) 87 { 88 *queue = bit % adev->gfx.me.num_queue_per_pipe; 89 *pipe = (bit / adev->gfx.me.num_queue_per_pipe) 90 % adev->gfx.me.num_pipe_per_me; 91 *me = (bit / adev->gfx.me.num_queue_per_pipe) 92 / adev->gfx.me.num_pipe_per_me; 93 } 94 95 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, 96 int me, int pipe, int queue) 97 { 98 return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue), 99 adev->gfx.me.queue_bitmap); 100 } 101 102 /** 103 * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter 104 * 105 * @mask: array in which the per-shader array disable masks will be stored 106 * @max_se: number of SEs 107 * @max_sh: number of SHs 108 * 109 * The bitmask of CUs to be disabled in the shader array determined by se and 110 * sh is stored in mask[se * max_sh + sh]. 111 */ 112 void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se, unsigned max_sh) 113 { 114 unsigned se, sh, cu; 115 const char *p; 116 117 memset(mask, 0, sizeof(*mask) * max_se * max_sh); 118 119 if (!amdgpu_disable_cu || !*amdgpu_disable_cu) 120 return; 121 122 #ifdef notyet 123 p = amdgpu_disable_cu; 124 for (;;) { 125 char *next; 126 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu); 127 if (ret < 3) { 128 DRM_ERROR("amdgpu: could not parse disable_cu\n"); 129 return; 130 } 131 132 if (se < max_se && sh < max_sh && cu < 16) { 133 DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu); 134 mask[se * max_sh + sh] |= 1u << cu; 135 } else { 136 DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n", 137 se, sh, cu); 138 } 139 140 next = strchr(p, ','); 141 if (!next) 142 break; 143 p = next + 1; 144 } 145 #endif 146 } 147 148 static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev) 149 { 150 return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1; 151 } 152 153 static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev) 154 { 155 if (amdgpu_compute_multipipe != -1) { 156 DRM_INFO("amdgpu: forcing compute pipe policy %d\n", 157 amdgpu_compute_multipipe); 158 return amdgpu_compute_multipipe == 1; 159 } 160 161 if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0)) 162 return true; 163 164 /* FIXME: spreading the queues across pipes causes perf regressions 165 * on POLARIS11 compute workloads */ 166 if (adev->asic_type == CHIP_POLARIS11) 167 return false; 168 169 return adev->gfx.mec.num_mec > 1; 170 } 171 172 bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, 173 struct amdgpu_ring *ring) 174 { 175 int queue = ring->queue; 176 int pipe = ring->pipe; 177 178 /* Policy: use pipe1 queue0 as high priority graphics queue if we 179 * have more than one gfx pipe. 180 */ 181 if (amdgpu_gfx_is_graphics_multipipe_capable(adev) && 182 adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) { 183 int me = ring->me; 184 int bit; 185 186 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue); 187 if (ring == &adev->gfx.gfx_ring[bit]) 188 return true; 189 } 190 191 return false; 192 } 193 194 bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 195 struct amdgpu_ring *ring) 196 { 197 /* Policy: use 1st queue as high priority compute queue if we 198 * have more than one compute queue. 199 */ 200 if (adev->gfx.num_compute_rings > 1 && 201 ring == &adev->gfx.compute_ring[0]) 202 return true; 203 204 return false; 205 } 206 207 void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) 208 { 209 int i, queue, pipe; 210 bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev); 211 int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec * 212 adev->gfx.mec.num_queue_per_pipe, 213 adev->gfx.num_compute_rings); 214 215 if (multipipe_policy) { 216 /* policy: make queues evenly cross all pipes on MEC1 only */ 217 for (i = 0; i < max_queues_per_mec; i++) { 218 pipe = i % adev->gfx.mec.num_pipe_per_mec; 219 queue = (i / adev->gfx.mec.num_pipe_per_mec) % 220 adev->gfx.mec.num_queue_per_pipe; 221 222 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue, 223 adev->gfx.mec.queue_bitmap); 224 } 225 } else { 226 /* policy: amdgpu owns all queues in the given pipe */ 227 for (i = 0; i < max_queues_per_mec; ++i) 228 set_bit(i, adev->gfx.mec.queue_bitmap); 229 } 230 231 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n", bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)); 232 } 233 234 void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev) 235 { 236 int i, queue, pipe; 237 bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev); 238 int max_queues_per_me = adev->gfx.me.num_pipe_per_me * 239 adev->gfx.me.num_queue_per_pipe; 240 241 if (multipipe_policy) { 242 /* policy: amdgpu owns the first queue per pipe at this stage 243 * will extend to mulitple queues per pipe later */ 244 for (i = 0; i < max_queues_per_me; i++) { 245 pipe = i % adev->gfx.me.num_pipe_per_me; 246 queue = (i / adev->gfx.me.num_pipe_per_me) % 247 adev->gfx.me.num_queue_per_pipe; 248 249 set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue, 250 adev->gfx.me.queue_bitmap); 251 } 252 } else { 253 for (i = 0; i < max_queues_per_me; ++i) 254 set_bit(i, adev->gfx.me.queue_bitmap); 255 } 256 257 /* update the number of active graphics rings */ 258 adev->gfx.num_gfx_rings = 259 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 260 } 261 262 static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, 263 struct amdgpu_ring *ring) 264 { 265 int queue_bit; 266 int mec, pipe, queue; 267 268 queue_bit = adev->gfx.mec.num_mec 269 * adev->gfx.mec.num_pipe_per_mec 270 * adev->gfx.mec.num_queue_per_pipe; 271 272 while (--queue_bit >= 0) { 273 if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap)) 274 continue; 275 276 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); 277 278 /* 279 * 1. Using pipes 2/3 from MEC 2 seems cause problems. 280 * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN 281 * only can be issued on queue 0. 282 */ 283 if ((mec == 1 && pipe > 1) || queue != 0) 284 continue; 285 286 ring->me = mec + 1; 287 ring->pipe = pipe; 288 ring->queue = queue; 289 290 return 0; 291 } 292 293 dev_err(adev->dev, "Failed to find a queue for KIQ\n"); 294 return -EINVAL; 295 } 296 297 int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 298 struct amdgpu_ring *ring, 299 struct amdgpu_irq_src *irq) 300 { 301 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 302 int r = 0; 303 304 mtx_init(&kiq->ring_lock, IPL_TTY); 305 306 ring->adev = NULL; 307 ring->ring_obj = NULL; 308 ring->use_doorbell = true; 309 ring->doorbell_index = adev->doorbell_index.kiq; 310 311 r = amdgpu_gfx_kiq_acquire(adev, ring); 312 if (r) 313 return r; 314 315 ring->eop_gpu_addr = kiq->eop_gpu_addr; 316 ring->no_scheduler = true; 317 snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d", ring->me, ring->pipe, ring->queue); 318 r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0, 319 AMDGPU_RING_PRIO_DEFAULT, NULL); 320 if (r) 321 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); 322 323 return r; 324 } 325 326 void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring) 327 { 328 amdgpu_ring_fini(ring); 329 } 330 331 void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev) 332 { 333 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 334 335 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); 336 } 337 338 int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 339 unsigned hpd_size) 340 { 341 int r; 342 u32 *hpd; 343 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 344 345 r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE, 346 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, 347 &kiq->eop_gpu_addr, (void **)&hpd); 348 if (r) { 349 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); 350 return r; 351 } 352 353 memset(hpd, 0, hpd_size); 354 355 r = amdgpu_bo_reserve(kiq->eop_obj, true); 356 if (unlikely(r != 0)) 357 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); 358 amdgpu_bo_kunmap(kiq->eop_obj); 359 amdgpu_bo_unreserve(kiq->eop_obj); 360 361 return 0; 362 } 363 364 /* create MQD for each compute/gfx queue */ 365 int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 366 unsigned mqd_size) 367 { 368 struct amdgpu_ring *ring = NULL; 369 int r, i; 370 371 /* create MQD for KIQ */ 372 ring = &adev->gfx.kiq.ring; 373 if (!adev->enable_mes_kiq && !ring->mqd_obj) { 374 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must 375 * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD 376 * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for 377 * KIQ MQD no matter SRIOV or Bare-metal 378 */ 379 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 380 AMDGPU_GEM_DOMAIN_VRAM, &ring->mqd_obj, 381 &ring->mqd_gpu_addr, &ring->mqd_ptr); 382 if (r) { 383 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); 384 return r; 385 } 386 387 /* prepare MQD backup */ 388 adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS] = kmalloc(mqd_size, GFP_KERNEL); 389 if (!adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]) 390 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 391 } 392 393 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { 394 /* create MQD for each KGQ */ 395 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 396 ring = &adev->gfx.gfx_ring[i]; 397 if (!ring->mqd_obj) { 398 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 399 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 400 &ring->mqd_gpu_addr, &ring->mqd_ptr); 401 if (r) { 402 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 403 return r; 404 } 405 406 /* prepare MQD backup */ 407 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL); 408 if (!adev->gfx.me.mqd_backup[i]) 409 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 410 } 411 } 412 } 413 414 /* create MQD for each KCQ */ 415 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 416 ring = &adev->gfx.compute_ring[i]; 417 if (!ring->mqd_obj) { 418 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 419 AMDGPU_GEM_DOMAIN_GTT, &ring->mqd_obj, 420 &ring->mqd_gpu_addr, &ring->mqd_ptr); 421 if (r) { 422 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 423 return r; 424 } 425 426 /* prepare MQD backup */ 427 adev->gfx.mec.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL); 428 if (!adev->gfx.mec.mqd_backup[i]) 429 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 430 } 431 } 432 433 return 0; 434 } 435 436 void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev) 437 { 438 struct amdgpu_ring *ring = NULL; 439 int i; 440 441 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { 442 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 443 ring = &adev->gfx.gfx_ring[i]; 444 kfree(adev->gfx.me.mqd_backup[i]); 445 amdgpu_bo_free_kernel(&ring->mqd_obj, 446 &ring->mqd_gpu_addr, 447 &ring->mqd_ptr); 448 } 449 } 450 451 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 452 ring = &adev->gfx.compute_ring[i]; 453 kfree(adev->gfx.mec.mqd_backup[i]); 454 amdgpu_bo_free_kernel(&ring->mqd_obj, 455 &ring->mqd_gpu_addr, 456 &ring->mqd_ptr); 457 } 458 459 ring = &adev->gfx.kiq.ring; 460 kfree(adev->gfx.mec.mqd_backup[AMDGPU_MAX_COMPUTE_RINGS]); 461 amdgpu_bo_free_kernel(&ring->mqd_obj, 462 &ring->mqd_gpu_addr, 463 &ring->mqd_ptr); 464 } 465 466 int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev) 467 { 468 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 469 struct amdgpu_ring *kiq_ring = &kiq->ring; 470 int i, r = 0; 471 472 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 473 return -EINVAL; 474 475 spin_lock(&adev->gfx.kiq.ring_lock); 476 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 477 adev->gfx.num_compute_rings)) { 478 spin_unlock(&adev->gfx.kiq.ring_lock); 479 return -ENOMEM; 480 } 481 482 for (i = 0; i < adev->gfx.num_compute_rings; i++) 483 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.compute_ring[i], 484 RESET_QUEUES, 0, 0); 485 486 if (adev->gfx.kiq.ring.sched.ready && !adev->job_hang) 487 r = amdgpu_ring_test_helper(kiq_ring); 488 spin_unlock(&adev->gfx.kiq.ring_lock); 489 490 return r; 491 } 492 493 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, 494 int queue_bit) 495 { 496 int mec, pipe, queue; 497 int set_resource_bit = 0; 498 499 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); 500 501 set_resource_bit = mec * 4 * 8 + pipe * 8 + queue; 502 503 return set_resource_bit; 504 } 505 506 int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev) 507 { 508 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 509 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 510 uint64_t queue_mask = 0; 511 int r, i; 512 513 if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources) 514 return -EINVAL; 515 516 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { 517 if (!test_bit(i, adev->gfx.mec.queue_bitmap)) 518 continue; 519 520 /* This situation may be hit in the future if a new HW 521 * generation exposes more than 64 queues. If so, the 522 * definition of queue_mask needs updating */ 523 if (WARN_ON(i > (sizeof(queue_mask)*8))) { 524 DRM_ERROR("Invalid KCQ enabled: %d\n", i); 525 break; 526 } 527 528 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i)); 529 } 530 531 DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe, 532 kiq_ring->queue); 533 spin_lock(&adev->gfx.kiq.ring_lock); 534 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 535 adev->gfx.num_compute_rings + 536 kiq->pmf->set_resources_size); 537 if (r) { 538 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 539 spin_unlock(&adev->gfx.kiq.ring_lock); 540 return r; 541 } 542 543 if (adev->enable_mes) 544 queue_mask = ~0ULL; 545 546 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask); 547 for (i = 0; i < adev->gfx.num_compute_rings; i++) 548 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.compute_ring[i]); 549 550 r = amdgpu_ring_test_helper(kiq_ring); 551 spin_unlock(&adev->gfx.kiq.ring_lock); 552 if (r) 553 DRM_ERROR("KCQ enable failed\n"); 554 555 return r; 556 } 557 558 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable 559 * 560 * @adev: amdgpu_device pointer 561 * @bool enable true: enable gfx off feature, false: disable gfx off feature 562 * 563 * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled. 564 * 2. other client can send request to disable gfx off feature, the request should be honored. 565 * 3. other client can cancel their request of disable gfx off feature 566 * 4. other client should not send request to enable gfx off feature before disable gfx off feature. 567 */ 568 569 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) 570 { 571 unsigned long delay = GFX_OFF_DELAY_ENABLE; 572 573 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 574 return; 575 576 mutex_lock(&adev->gfx.gfx_off_mutex); 577 578 if (enable) { 579 /* If the count is already 0, it means there's an imbalance bug somewhere. 580 * Note that the bug may be in a different caller than the one which triggers the 581 * WARN_ON_ONCE. 582 */ 583 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0)) 584 goto unlock; 585 586 adev->gfx.gfx_off_req_count--; 587 588 if (adev->gfx.gfx_off_req_count == 0 && 589 !adev->gfx.gfx_off_state) { 590 /* If going to s2idle, no need to wait */ 591 if (adev->in_s0ix) { 592 if (!amdgpu_dpm_set_powergating_by_smu(adev, 593 AMD_IP_BLOCK_TYPE_GFX, true)) 594 adev->gfx.gfx_off_state = true; 595 } else { 596 schedule_delayed_work(&adev->gfx.gfx_off_delay_work, 597 delay); 598 } 599 } 600 } else { 601 if (adev->gfx.gfx_off_req_count == 0) { 602 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 603 604 if (adev->gfx.gfx_off_state && 605 !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) { 606 adev->gfx.gfx_off_state = false; 607 608 if (adev->gfx.funcs->init_spm_golden) { 609 dev_dbg(adev->dev, 610 "GFXOFF is disabled, re-init SPM golden settings\n"); 611 amdgpu_gfx_init_spm_golden(adev); 612 } 613 } 614 } 615 616 adev->gfx.gfx_off_req_count++; 617 } 618 619 unlock: 620 mutex_unlock(&adev->gfx.gfx_off_mutex); 621 } 622 623 int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value) 624 { 625 int r = 0; 626 627 mutex_lock(&adev->gfx.gfx_off_mutex); 628 629 r = amdgpu_dpm_set_residency_gfxoff(adev, value); 630 631 mutex_unlock(&adev->gfx.gfx_off_mutex); 632 633 return r; 634 } 635 636 int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value) 637 { 638 int r = 0; 639 640 mutex_lock(&adev->gfx.gfx_off_mutex); 641 642 r = amdgpu_dpm_get_residency_gfxoff(adev, value); 643 644 mutex_unlock(&adev->gfx.gfx_off_mutex); 645 646 return r; 647 } 648 649 int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value) 650 { 651 int r = 0; 652 653 mutex_lock(&adev->gfx.gfx_off_mutex); 654 655 r = amdgpu_dpm_get_entrycount_gfxoff(adev, value); 656 657 mutex_unlock(&adev->gfx.gfx_off_mutex); 658 659 return r; 660 } 661 662 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value) 663 { 664 665 int r = 0; 666 667 mutex_lock(&adev->gfx.gfx_off_mutex); 668 669 r = amdgpu_dpm_get_status_gfxoff(adev, value); 670 671 mutex_unlock(&adev->gfx.gfx_off_mutex); 672 673 return r; 674 } 675 676 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 677 { 678 int r; 679 680 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 681 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 682 amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX); 683 684 r = amdgpu_ras_block_late_init(adev, ras_block); 685 if (r) 686 return r; 687 688 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); 689 if (r) 690 goto late_fini; 691 } else { 692 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); 693 } 694 695 return 0; 696 late_fini: 697 amdgpu_ras_block_late_fini(adev, ras_block); 698 return r; 699 } 700 701 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 702 void *err_data, 703 struct amdgpu_iv_entry *entry) 704 { 705 /* TODO ue will trigger an interrupt. 706 * 707 * When “Full RAS” is enabled, the per-IP interrupt sources should 708 * be disabled and the driver should only look for the aggregated 709 * interrupt via sync flood 710 */ 711 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) { 712 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 713 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops && 714 adev->gfx.ras->ras_block.hw_ops->query_ras_error_count) 715 adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); 716 amdgpu_ras_reset_gpu(adev); 717 } 718 return AMDGPU_RAS_SUCCESS; 719 } 720 721 int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 722 struct amdgpu_irq_src *source, 723 struct amdgpu_iv_entry *entry) 724 { 725 struct ras_common_if *ras_if = adev->gfx.ras_if; 726 struct ras_dispatch_if ih_data = { 727 .entry = entry, 728 }; 729 730 if (!ras_if) 731 return 0; 732 733 ih_data.head = *ras_if; 734 735 DRM_ERROR("CP ECC ERROR IRQ\n"); 736 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 737 return 0; 738 } 739 740 uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) 741 { 742 signed long r, cnt = 0; 743 unsigned long flags; 744 uint32_t seq, reg_val_offs = 0, value = 0; 745 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 746 struct amdgpu_ring *ring = &kiq->ring; 747 748 if (amdgpu_device_skip_hw_access(adev)) 749 return 0; 750 751 if (adev->mes.ring.sched.ready) 752 return amdgpu_mes_rreg(adev, reg); 753 754 BUG_ON(!ring->funcs->emit_rreg); 755 756 spin_lock_irqsave(&kiq->ring_lock, flags); 757 if (amdgpu_device_wb_get(adev, ®_val_offs)) { 758 pr_err("critical bug! too many kiq readers\n"); 759 goto failed_unlock; 760 } 761 amdgpu_ring_alloc(ring, 32); 762 amdgpu_ring_emit_rreg(ring, reg, reg_val_offs); 763 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 764 if (r) 765 goto failed_undo; 766 767 amdgpu_ring_commit(ring); 768 spin_unlock_irqrestore(&kiq->ring_lock, flags); 769 770 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 771 772 /* don't wait anymore for gpu reset case because this way may 773 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 774 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 775 * never return if we keep waiting in virt_kiq_rreg, which cause 776 * gpu_recover() hang there. 777 * 778 * also don't wait anymore for IRQ context 779 * */ 780 if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt())) 781 goto failed_kiq_read; 782 783 might_sleep(); 784 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 785 drm_msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 786 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 787 } 788 789 if (cnt > MAX_KIQ_REG_TRY) 790 goto failed_kiq_read; 791 792 mb(); 793 value = adev->wb.wb[reg_val_offs]; 794 amdgpu_device_wb_free(adev, reg_val_offs); 795 return value; 796 797 failed_undo: 798 amdgpu_ring_undo(ring); 799 failed_unlock: 800 spin_unlock_irqrestore(&kiq->ring_lock, flags); 801 failed_kiq_read: 802 if (reg_val_offs) 803 amdgpu_device_wb_free(adev, reg_val_offs); 804 dev_err(adev->dev, "failed to read reg:%x\n", reg); 805 return ~0; 806 } 807 808 void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) 809 { 810 signed long r, cnt = 0; 811 unsigned long flags; 812 uint32_t seq; 813 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 814 struct amdgpu_ring *ring = &kiq->ring; 815 816 BUG_ON(!ring->funcs->emit_wreg); 817 818 if (amdgpu_device_skip_hw_access(adev)) 819 return; 820 821 if (adev->mes.ring.sched.ready) { 822 amdgpu_mes_wreg(adev, reg, v); 823 return; 824 } 825 826 spin_lock_irqsave(&kiq->ring_lock, flags); 827 amdgpu_ring_alloc(ring, 32); 828 amdgpu_ring_emit_wreg(ring, reg, v); 829 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 830 if (r) 831 goto failed_undo; 832 833 amdgpu_ring_commit(ring); 834 spin_unlock_irqrestore(&kiq->ring_lock, flags); 835 836 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 837 838 /* don't wait anymore for gpu reset case because this way may 839 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 840 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 841 * never return if we keep waiting in virt_kiq_rreg, which cause 842 * gpu_recover() hang there. 843 * 844 * also don't wait anymore for IRQ context 845 * */ 846 if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt())) 847 goto failed_kiq_write; 848 849 might_sleep(); 850 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 851 852 drm_msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 853 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 854 } 855 856 if (cnt > MAX_KIQ_REG_TRY) 857 goto failed_kiq_write; 858 859 return; 860 861 failed_undo: 862 amdgpu_ring_undo(ring); 863 spin_unlock_irqrestore(&kiq->ring_lock, flags); 864 failed_kiq_write: 865 dev_err(adev->dev, "failed to write reg:%x\n", reg); 866 } 867 868 int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev) 869 { 870 if (amdgpu_num_kcq == -1) { 871 return 8; 872 } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) { 873 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n"); 874 return 8; 875 } 876 return amdgpu_num_kcq; 877 } 878 879 void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, 880 uint32_t ucode_id) 881 { 882 const struct gfx_firmware_header_v1_0 *cp_hdr; 883 const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0; 884 struct amdgpu_firmware_info *info = NULL; 885 const struct firmware *ucode_fw; 886 unsigned int fw_size; 887 888 switch (ucode_id) { 889 case AMDGPU_UCODE_ID_CP_PFP: 890 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 891 adev->gfx.pfp_fw->data; 892 adev->gfx.pfp_fw_version = 893 le32_to_cpu(cp_hdr->header.ucode_version); 894 adev->gfx.pfp_feature_version = 895 le32_to_cpu(cp_hdr->ucode_feature_version); 896 ucode_fw = adev->gfx.pfp_fw; 897 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 898 break; 899 case AMDGPU_UCODE_ID_CP_RS64_PFP: 900 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) 901 adev->gfx.pfp_fw->data; 902 adev->gfx.pfp_fw_version = 903 le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 904 adev->gfx.pfp_feature_version = 905 le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 906 ucode_fw = adev->gfx.pfp_fw; 907 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes); 908 break; 909 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 910 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 911 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) 912 adev->gfx.pfp_fw->data; 913 ucode_fw = adev->gfx.pfp_fw; 914 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes); 915 break; 916 case AMDGPU_UCODE_ID_CP_ME: 917 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 918 adev->gfx.me_fw->data; 919 adev->gfx.me_fw_version = 920 le32_to_cpu(cp_hdr->header.ucode_version); 921 adev->gfx.me_feature_version = 922 le32_to_cpu(cp_hdr->ucode_feature_version); 923 ucode_fw = adev->gfx.me_fw; 924 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 925 break; 926 case AMDGPU_UCODE_ID_CP_RS64_ME: 927 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) 928 adev->gfx.me_fw->data; 929 adev->gfx.me_fw_version = 930 le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 931 adev->gfx.me_feature_version = 932 le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 933 ucode_fw = adev->gfx.me_fw; 934 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes); 935 break; 936 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 937 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 938 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) 939 adev->gfx.me_fw->data; 940 ucode_fw = adev->gfx.me_fw; 941 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes); 942 break; 943 case AMDGPU_UCODE_ID_CP_CE: 944 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 945 adev->gfx.ce_fw->data; 946 adev->gfx.ce_fw_version = 947 le32_to_cpu(cp_hdr->header.ucode_version); 948 adev->gfx.ce_feature_version = 949 le32_to_cpu(cp_hdr->ucode_feature_version); 950 ucode_fw = adev->gfx.ce_fw; 951 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 952 break; 953 case AMDGPU_UCODE_ID_CP_MEC1: 954 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 955 adev->gfx.mec_fw->data; 956 adev->gfx.mec_fw_version = 957 le32_to_cpu(cp_hdr->header.ucode_version); 958 adev->gfx.mec_feature_version = 959 le32_to_cpu(cp_hdr->ucode_feature_version); 960 ucode_fw = adev->gfx.mec_fw; 961 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 962 le32_to_cpu(cp_hdr->jt_size) * 4; 963 break; 964 case AMDGPU_UCODE_ID_CP_MEC1_JT: 965 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 966 adev->gfx.mec_fw->data; 967 ucode_fw = adev->gfx.mec_fw; 968 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4; 969 break; 970 case AMDGPU_UCODE_ID_CP_MEC2: 971 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 972 adev->gfx.mec2_fw->data; 973 adev->gfx.mec2_fw_version = 974 le32_to_cpu(cp_hdr->header.ucode_version); 975 adev->gfx.mec2_feature_version = 976 le32_to_cpu(cp_hdr->ucode_feature_version); 977 ucode_fw = adev->gfx.mec2_fw; 978 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 979 le32_to_cpu(cp_hdr->jt_size) * 4; 980 break; 981 case AMDGPU_UCODE_ID_CP_MEC2_JT: 982 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 983 adev->gfx.mec2_fw->data; 984 ucode_fw = adev->gfx.mec2_fw; 985 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4; 986 break; 987 case AMDGPU_UCODE_ID_CP_RS64_MEC: 988 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) 989 adev->gfx.mec_fw->data; 990 adev->gfx.mec_fw_version = 991 le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 992 adev->gfx.mec_feature_version = 993 le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 994 ucode_fw = adev->gfx.mec_fw; 995 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes); 996 break; 997 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 998 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 999 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 1000 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 1001 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) 1002 adev->gfx.mec_fw->data; 1003 ucode_fw = adev->gfx.mec_fw; 1004 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes); 1005 break; 1006 default: 1007 break; 1008 } 1009 1010 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1011 info = &adev->firmware.ucode[ucode_id]; 1012 info->ucode_id = ucode_id; 1013 info->fw = ucode_fw; 1014 adev->firmware.fw_size += roundup2(fw_size, PAGE_SIZE); 1015 } 1016 } 1017