1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include <drm/drm_managed.h> 30 #include "amdgpu_drv.h" 31 32 #include <drm/drm_pciids.h> 33 #include <linux/module.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/vga_switcheroo.h> 36 #include <drm/drm_probe_helper.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/suspend.h> 39 #include <linux/cc_platform.h> 40 #include <linux/fb.h> 41 #include <linux/dynamic_debug.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 * - 3.43.0 - Add device hot plug/unplug support 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 102 * - 3.45.0 - Add context ioctl stable pstate interface 103 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 104 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 105 * - 3.48.0 - Add IP discovery version info to HW INFO 106 * 3.49.0 - Add gang submit into CS IOCTL 107 */ 108 #define KMS_DRIVER_MAJOR 3 109 #define KMS_DRIVER_MINOR 49 110 #define KMS_DRIVER_PATCHLEVEL 0 111 112 int amdgpu_vram_limit; 113 int amdgpu_vis_vram_limit; 114 int amdgpu_gart_size = -1; /* auto */ 115 int amdgpu_gtt_size = -1; /* auto */ 116 int amdgpu_moverate = -1; /* auto */ 117 int amdgpu_audio = -1; 118 int amdgpu_disp_priority; 119 int amdgpu_hw_i2c; 120 int amdgpu_pcie_gen2 = -1; 121 int amdgpu_msi = -1; 122 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 123 int amdgpu_dpm = -1; 124 int amdgpu_fw_load_type = -1; 125 int amdgpu_aspm = -1; 126 int amdgpu_runtime_pm = -1; 127 uint amdgpu_ip_block_mask = 0xffffffff; 128 int amdgpu_bapm = -1; 129 int amdgpu_deep_color; 130 int amdgpu_vm_size = -1; 131 int amdgpu_vm_fragment_size = -1; 132 int amdgpu_vm_block_size = -1; 133 int amdgpu_vm_fault_stop; 134 int amdgpu_vm_debug; 135 int amdgpu_vm_update_mode = -1; 136 int amdgpu_exp_hw_support; 137 int amdgpu_dc = -1; 138 int amdgpu_sched_jobs = 32; 139 int amdgpu_sched_hw_submission = 2; 140 uint amdgpu_pcie_gen_cap; 141 uint amdgpu_pcie_lane_cap; 142 u64 amdgpu_cg_mask = 0xffffffffffffffff; 143 uint amdgpu_pg_mask = 0xffffffff; 144 uint amdgpu_sdma_phase_quantum = 32; 145 char *amdgpu_disable_cu = NULL; 146 char *amdgpu_virtual_display = NULL; 147 148 /* 149 * OverDrive(bit 14) disabled by default 150 * GFX DCS(bit 19) disabled by default 151 */ 152 uint amdgpu_pp_feature_mask = 0xfff7bfff; 153 uint amdgpu_force_long_training; 154 int amdgpu_job_hang_limit; 155 int amdgpu_lbpw = -1; 156 int amdgpu_compute_multipipe = -1; 157 int amdgpu_gpu_recovery = -1; /* auto */ 158 int amdgpu_emu_mode; 159 uint amdgpu_smu_memory_pool_size; 160 int amdgpu_smu_pptable_id = -1; 161 /* 162 * FBC (bit 0) disabled by default 163 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 164 * - With this, for multiple monitors in sync(e.g. with the same model), 165 * mclk switching will be allowed. And the mclk will be not foced to the 166 * highest. That helps saving some idle power. 167 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 168 * PSR (bit 3) disabled by default 169 * EDP NO POWER SEQUENCING (bit 4) disabled by default 170 */ 171 uint amdgpu_dc_feature_mask = 2; 172 uint amdgpu_dc_debug_mask; 173 uint amdgpu_dc_visual_confirm; 174 int amdgpu_async_gfx_ring = 1; 175 int amdgpu_mcbp; 176 int amdgpu_discovery = -1; 177 int amdgpu_mes; 178 int amdgpu_mes_kiq; 179 int amdgpu_noretry = -1; 180 int amdgpu_force_asic_type = -1; 181 int amdgpu_tmz = -1; /* auto */ 182 uint amdgpu_freesync_vid_mode; 183 int amdgpu_reset_method = -1; /* auto */ 184 int amdgpu_num_kcq = -1; 185 int amdgpu_smartshift_bias; 186 int amdgpu_use_xgmi_p2p = 1; 187 int amdgpu_vcnfw_log; 188 189 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 190 191 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 192 "DRM_UT_CORE", 193 "DRM_UT_DRIVER", 194 "DRM_UT_KMS", 195 "DRM_UT_PRIME", 196 "DRM_UT_ATOMIC", 197 "DRM_UT_VBL", 198 "DRM_UT_STATE", 199 "DRM_UT_LEASE", 200 "DRM_UT_DP", 201 "DRM_UT_DRMRES"); 202 203 struct amdgpu_mgpu_info mgpu_info = { 204 .mutex = RWLOCK_INITIALIZER("mgpu_info"), 205 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 206 mgpu_info.delayed_reset_work, 207 amdgpu_drv_delayed_reset_work_handler, 0), 208 }; 209 int amdgpu_ras_enable = -1; 210 uint amdgpu_ras_mask = 0xffffffff; 211 int amdgpu_bad_page_threshold = -1; 212 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 213 .timeout_fatal_disable = false, 214 .period = 0x0, /* default to 0x0 (timeout disable) */ 215 }; 216 217 /** 218 * DOC: vramlimit (int) 219 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 220 */ 221 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 222 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 223 224 /** 225 * DOC: vis_vramlimit (int) 226 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 227 */ 228 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 229 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 230 231 /** 232 * DOC: gartsize (uint) 233 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 234 */ 235 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 236 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 237 238 /** 239 * DOC: gttsize (int) 240 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 241 * otherwise 3/4 RAM size). 242 */ 243 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 244 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 245 246 /** 247 * DOC: moverate (int) 248 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 249 */ 250 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 251 module_param_named(moverate, amdgpu_moverate, int, 0600); 252 253 /** 254 * DOC: audio (int) 255 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 256 */ 257 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 258 module_param_named(audio, amdgpu_audio, int, 0444); 259 260 /** 261 * DOC: disp_priority (int) 262 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 263 */ 264 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 265 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 266 267 /** 268 * DOC: hw_i2c (int) 269 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 270 */ 271 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 272 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 273 274 /** 275 * DOC: pcie_gen2 (int) 276 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 277 */ 278 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 279 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 280 281 /** 282 * DOC: msi (int) 283 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 284 */ 285 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 286 module_param_named(msi, amdgpu_msi, int, 0444); 287 288 /** 289 * DOC: lockup_timeout (string) 290 * Set GPU scheduler timeout value in ms. 291 * 292 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 293 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 294 * to the default timeout. 295 * 296 * - With one value specified, the setting will apply to all non-compute jobs. 297 * - With multiple values specified, the first one will be for GFX. 298 * The second one is for Compute. The third and fourth ones are 299 * for SDMA and Video. 300 * 301 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 302 * jobs is 10000. The timeout for compute is 60000. 303 */ 304 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 305 "for passthrough or sriov, 10000 for all jobs." 306 " 0: keep default value. negative: infinity timeout), " 307 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 308 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 309 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 310 311 /** 312 * DOC: dpm (int) 313 * Override for dynamic power management setting 314 * (0 = disable, 1 = enable) 315 * The default is -1 (auto). 316 */ 317 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 318 module_param_named(dpm, amdgpu_dpm, int, 0444); 319 320 /** 321 * DOC: fw_load_type (int) 322 * Set different firmware loading type for debugging, if supported. 323 * Set to 0 to force direct loading if supported by the ASIC. Set 324 * to -1 to select the default loading mode for the ASIC, as defined 325 * by the driver. The default is -1 (auto). 326 */ 327 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 328 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 329 330 /** 331 * DOC: aspm (int) 332 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 333 */ 334 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 335 module_param_named(aspm, amdgpu_aspm, int, 0444); 336 337 /** 338 * DOC: runpm (int) 339 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 340 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 341 * Setting the value to 0 disables this functionality. 342 */ 343 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 344 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 345 346 /** 347 * DOC: ip_block_mask (uint) 348 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 349 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 350 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 351 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 352 */ 353 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 354 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 355 356 /** 357 * DOC: bapm (int) 358 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 359 * The default -1 (auto, enabled) 360 */ 361 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 362 module_param_named(bapm, amdgpu_bapm, int, 0444); 363 364 /** 365 * DOC: deep_color (int) 366 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 367 */ 368 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 369 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 370 371 /** 372 * DOC: vm_size (int) 373 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 374 */ 375 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 376 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 377 378 /** 379 * DOC: vm_fragment_size (int) 380 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 381 */ 382 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 383 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 384 385 /** 386 * DOC: vm_block_size (int) 387 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 388 */ 389 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 390 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 391 392 /** 393 * DOC: vm_fault_stop (int) 394 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 395 */ 396 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 397 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 398 399 /** 400 * DOC: vm_debug (int) 401 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 402 */ 403 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 404 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 405 406 /** 407 * DOC: vm_update_mode (int) 408 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 409 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 410 */ 411 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 412 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 413 414 /** 415 * DOC: exp_hw_support (int) 416 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 417 */ 418 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 419 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 420 421 /** 422 * DOC: dc (int) 423 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 424 */ 425 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 426 module_param_named(dc, amdgpu_dc, int, 0444); 427 428 /** 429 * DOC: sched_jobs (int) 430 * Override the max number of jobs supported in the sw queue. The default is 32. 431 */ 432 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 433 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 434 435 /** 436 * DOC: sched_hw_submission (int) 437 * Override the max number of HW submissions. The default is 2. 438 */ 439 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 440 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 441 442 /** 443 * DOC: ppfeaturemask (hexint) 444 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 445 * The default is the current set of stable power features. 446 */ 447 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 448 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 449 450 /** 451 * DOC: forcelongtraining (uint) 452 * Force long memory training in resume. 453 * The default is zero, indicates short training in resume. 454 */ 455 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 456 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 457 458 /** 459 * DOC: pcie_gen_cap (uint) 460 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 461 * The default is 0 (automatic for each asic). 462 */ 463 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 464 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 465 466 /** 467 * DOC: pcie_lane_cap (uint) 468 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 469 * The default is 0 (automatic for each asic). 470 */ 471 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 472 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 473 474 /** 475 * DOC: cg_mask (ullong) 476 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 477 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 478 */ 479 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 480 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 481 482 /** 483 * DOC: pg_mask (uint) 484 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 485 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 486 */ 487 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 488 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 489 490 /** 491 * DOC: sdma_phase_quantum (uint) 492 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 493 */ 494 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 495 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 496 497 /** 498 * DOC: disable_cu (charp) 499 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 500 */ 501 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 502 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 503 504 /** 505 * DOC: virtual_display (charp) 506 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 507 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 508 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 509 * device at 26:00.0. The default is NULL. 510 */ 511 MODULE_PARM_DESC(virtual_display, 512 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 513 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 514 515 /** 516 * DOC: job_hang_limit (int) 517 * Set how much time allow a job hang and not drop it. The default is 0. 518 */ 519 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 520 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 521 522 /** 523 * DOC: lbpw (int) 524 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 525 */ 526 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 527 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 528 529 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 530 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 531 532 /** 533 * DOC: gpu_recovery (int) 534 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 535 */ 536 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 537 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 538 539 /** 540 * DOC: emu_mode (int) 541 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 542 */ 543 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 544 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 545 546 /** 547 * DOC: ras_enable (int) 548 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 549 */ 550 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 551 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 552 553 /** 554 * DOC: ras_mask (uint) 555 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 556 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 557 */ 558 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 559 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 560 561 /** 562 * DOC: timeout_fatal_disable (bool) 563 * Disable Watchdog timeout fatal error event 564 */ 565 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 566 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 567 568 /** 569 * DOC: timeout_period (uint) 570 * Modify the watchdog timeout max_cycles as (1 << period) 571 */ 572 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 573 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 574 575 /** 576 * DOC: si_support (int) 577 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 578 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 579 * otherwise using amdgpu driver. 580 */ 581 #ifdef CONFIG_DRM_AMDGPU_SI 582 583 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 584 int amdgpu_si_support = 0; 585 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 586 #else 587 int amdgpu_si_support = 1; 588 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 589 #endif 590 591 module_param_named(si_support, amdgpu_si_support, int, 0444); 592 #endif 593 594 /** 595 * DOC: cik_support (int) 596 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 597 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 598 * otherwise using amdgpu driver. 599 */ 600 #ifdef CONFIG_DRM_AMDGPU_CIK 601 602 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 603 int amdgpu_cik_support = 0; 604 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 605 #else 606 int amdgpu_cik_support = 1; 607 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 608 #endif 609 610 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 611 #endif 612 613 /** 614 * DOC: smu_memory_pool_size (uint) 615 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 616 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 617 */ 618 MODULE_PARM_DESC(smu_memory_pool_size, 619 "reserve gtt for smu debug usage, 0 = disable," 620 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 621 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 622 623 /** 624 * DOC: async_gfx_ring (int) 625 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 626 */ 627 MODULE_PARM_DESC(async_gfx_ring, 628 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 629 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 630 631 /** 632 * DOC: mcbp (int) 633 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 634 */ 635 MODULE_PARM_DESC(mcbp, 636 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 637 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 638 639 /** 640 * DOC: discovery (int) 641 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 642 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 643 */ 644 MODULE_PARM_DESC(discovery, 645 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 646 module_param_named(discovery, amdgpu_discovery, int, 0444); 647 648 /** 649 * DOC: mes (int) 650 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 651 * (0 = disabled (default), 1 = enabled) 652 */ 653 MODULE_PARM_DESC(mes, 654 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 655 module_param_named(mes, amdgpu_mes, int, 0444); 656 657 /** 658 * DOC: mes_kiq (int) 659 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 660 * (0 = disabled (default), 1 = enabled) 661 */ 662 MODULE_PARM_DESC(mes_kiq, 663 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 664 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 665 666 /** 667 * DOC: noretry (int) 668 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 669 * do not support per-process XNACK this also disables retry page faults. 670 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 671 */ 672 MODULE_PARM_DESC(noretry, 673 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 674 module_param_named(noretry, amdgpu_noretry, int, 0644); 675 676 /** 677 * DOC: force_asic_type (int) 678 * A non negative value used to specify the asic type for all supported GPUs. 679 */ 680 MODULE_PARM_DESC(force_asic_type, 681 "A non negative value used to specify the asic type for all supported GPUs"); 682 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 683 684 /** 685 * DOC: use_xgmi_p2p (int) 686 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 687 */ 688 MODULE_PARM_DESC(use_xgmi_p2p, 689 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 690 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 691 692 693 #ifdef CONFIG_HSA_AMD 694 /** 695 * DOC: sched_policy (int) 696 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 697 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 698 * assigns queues to HQDs. 699 */ 700 int sched_policy = KFD_SCHED_POLICY_HWS; 701 module_param(sched_policy, int, 0444); 702 MODULE_PARM_DESC(sched_policy, 703 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 704 705 /** 706 * DOC: hws_max_conc_proc (int) 707 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 708 * number of VMIDs assigned to the HWS, which is also the default. 709 */ 710 int hws_max_conc_proc = -1; 711 module_param(hws_max_conc_proc, int, 0444); 712 MODULE_PARM_DESC(hws_max_conc_proc, 713 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 714 715 /** 716 * DOC: cwsr_enable (int) 717 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 718 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 719 * disables it. 720 */ 721 int cwsr_enable = 1; 722 module_param(cwsr_enable, int, 0444); 723 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 724 725 /** 726 * DOC: max_num_of_queues_per_device (int) 727 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 728 * is 4096. 729 */ 730 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 731 module_param(max_num_of_queues_per_device, int, 0444); 732 MODULE_PARM_DESC(max_num_of_queues_per_device, 733 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 734 735 /** 736 * DOC: send_sigterm (int) 737 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 738 * but just print errors on dmesg. Setting 1 enables sending sigterm. 739 */ 740 int send_sigterm; 741 module_param(send_sigterm, int, 0444); 742 MODULE_PARM_DESC(send_sigterm, 743 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 744 745 /** 746 * DOC: debug_largebar (int) 747 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 748 * system. This limits the VRAM size reported to ROCm applications to the visible 749 * size, usually 256MB. 750 * Default value is 0, diabled. 751 */ 752 int debug_largebar; 753 module_param(debug_largebar, int, 0444); 754 MODULE_PARM_DESC(debug_largebar, 755 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 756 757 /** 758 * DOC: ignore_crat (int) 759 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 760 * table to get information about AMD APUs. This option can serve as a workaround on 761 * systems with a broken CRAT table. 762 * 763 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 764 * whether use CRAT) 765 */ 766 int ignore_crat; 767 module_param(ignore_crat, int, 0444); 768 MODULE_PARM_DESC(ignore_crat, 769 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 770 771 /** 772 * DOC: halt_if_hws_hang (int) 773 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 774 * Setting 1 enables halt on hang. 775 */ 776 int halt_if_hws_hang; 777 module_param(halt_if_hws_hang, int, 0644); 778 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 779 780 /** 781 * DOC: hws_gws_support(bool) 782 * Assume that HWS supports GWS barriers regardless of what firmware version 783 * check says. Default value: false (rely on MEC2 firmware version check). 784 */ 785 bool hws_gws_support; 786 module_param(hws_gws_support, bool, 0444); 787 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 788 789 /** 790 * DOC: queue_preemption_timeout_ms (int) 791 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 792 */ 793 int queue_preemption_timeout_ms = 9000; 794 module_param(queue_preemption_timeout_ms, int, 0644); 795 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 796 797 /** 798 * DOC: debug_evictions(bool) 799 * Enable extra debug messages to help determine the cause of evictions 800 */ 801 bool debug_evictions; 802 module_param(debug_evictions, bool, 0644); 803 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 804 805 /** 806 * DOC: no_system_mem_limit(bool) 807 * Disable system memory limit, to support multiple process shared memory 808 */ 809 bool no_system_mem_limit; 810 module_param(no_system_mem_limit, bool, 0644); 811 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 812 813 /** 814 * DOC: no_queue_eviction_on_vm_fault (int) 815 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 816 */ 817 int amdgpu_no_queue_eviction_on_vm_fault = 0; 818 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 819 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 820 #endif 821 822 /** 823 * DOC: pcie_p2p (bool) 824 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 825 */ 826 #ifdef CONFIG_HSA_AMD_P2P 827 bool pcie_p2p = true; 828 module_param(pcie_p2p, bool, 0444); 829 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 830 #endif 831 832 /** 833 * DOC: dcfeaturemask (uint) 834 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 835 * The default is the current set of stable display features. 836 */ 837 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 838 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 839 840 /** 841 * DOC: dcdebugmask (uint) 842 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 843 */ 844 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 845 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 846 847 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 848 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 849 850 /** 851 * DOC: abmlevel (uint) 852 * Override the default ABM (Adaptive Backlight Management) level used for DC 853 * enabled hardware. Requires DMCU to be supported and loaded. 854 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 855 * default. Values 1-4 control the maximum allowable brightness reduction via 856 * the ABM algorithm, with 1 being the least reduction and 4 being the most 857 * reduction. 858 * 859 * Defaults to 0, or disabled. Userspace can still override this level later 860 * after boot. 861 */ 862 uint amdgpu_dm_abm_level; 863 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 864 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 865 866 int amdgpu_backlight = -1; 867 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 868 module_param_named(backlight, amdgpu_backlight, bint, 0444); 869 870 /** 871 * DOC: tmz (int) 872 * Trusted Memory Zone (TMZ) is a method to protect data being written 873 * to or read from memory. 874 * 875 * The default value: 0 (off). TODO: change to auto till it is completed. 876 */ 877 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 878 module_param_named(tmz, amdgpu_tmz, int, 0444); 879 880 /** 881 * DOC: freesync_video (uint) 882 * Enable the optimization to adjust front porch timing to achieve seamless 883 * mode change experience when setting a freesync supported mode for which full 884 * modeset is not needed. 885 * 886 * The Display Core will add a set of modes derived from the base FreeSync 887 * video mode into the corresponding connector's mode list based on commonly 888 * used refresh rates and VRR range of the connected display, when users enable 889 * this feature. From the userspace perspective, they can see a seamless mode 890 * change experience when the change between different refresh rates under the 891 * same resolution. Additionally, userspace applications such as Video playback 892 * can read this modeset list and change the refresh rate based on the video 893 * frame rate. Finally, the userspace can also derive an appropriate mode for a 894 * particular refresh rate based on the FreeSync Mode and add it to the 895 * connector's mode list. 896 * 897 * Note: This is an experimental feature. 898 * 899 * The default value: 0 (off). 900 */ 901 MODULE_PARM_DESC( 902 freesync_video, 903 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 904 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 905 906 /** 907 * DOC: reset_method (int) 908 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 909 */ 910 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 911 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 912 913 /** 914 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 915 * threshold value of faulty pages detected by RAS ECC, which may 916 * result in the GPU entering bad status when the number of total 917 * faulty pages by ECC exceeds the threshold value. 918 */ 919 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 920 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 921 922 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 923 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 924 925 /** 926 * DOC: vcnfw_log (int) 927 * Enable vcnfw log output for debugging, the default is disabled. 928 */ 929 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 930 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 931 932 /** 933 * DOC: smu_pptable_id (int) 934 * Used to override pptable id. id = 0 use VBIOS pptable. 935 * id > 0 use the soft pptable with specicfied id. 936 */ 937 MODULE_PARM_DESC(smu_pptable_id, 938 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 939 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 940 941 /* These devices are not supported by amdgpu. 942 * They are supported by the mach64, r128, radeon drivers 943 */ 944 static const u16 amdgpu_unsupported_pciidlist[] = { 945 /* mach64 */ 946 0x4354, 947 0x4358, 948 0x4554, 949 0x4742, 950 0x4744, 951 0x4749, 952 0x474C, 953 0x474D, 954 0x474E, 955 0x474F, 956 0x4750, 957 0x4751, 958 0x4752, 959 0x4753, 960 0x4754, 961 0x4755, 962 0x4756, 963 0x4757, 964 0x4758, 965 0x4759, 966 0x475A, 967 0x4C42, 968 0x4C44, 969 0x4C47, 970 0x4C49, 971 0x4C4D, 972 0x4C4E, 973 0x4C50, 974 0x4C51, 975 0x4C52, 976 0x4C53, 977 0x5654, 978 0x5655, 979 0x5656, 980 /* r128 */ 981 0x4c45, 982 0x4c46, 983 0x4d46, 984 0x4d4c, 985 0x5041, 986 0x5042, 987 0x5043, 988 0x5044, 989 0x5045, 990 0x5046, 991 0x5047, 992 0x5048, 993 0x5049, 994 0x504A, 995 0x504B, 996 0x504C, 997 0x504D, 998 0x504E, 999 0x504F, 1000 0x5050, 1001 0x5051, 1002 0x5052, 1003 0x5053, 1004 0x5054, 1005 0x5055, 1006 0x5056, 1007 0x5057, 1008 0x5058, 1009 0x5245, 1010 0x5246, 1011 0x5247, 1012 0x524b, 1013 0x524c, 1014 0x534d, 1015 0x5446, 1016 0x544C, 1017 0x5452, 1018 /* radeon */ 1019 0x3150, 1020 0x3151, 1021 0x3152, 1022 0x3154, 1023 0x3155, 1024 0x3E50, 1025 0x3E54, 1026 0x4136, 1027 0x4137, 1028 0x4144, 1029 0x4145, 1030 0x4146, 1031 0x4147, 1032 0x4148, 1033 0x4149, 1034 0x414A, 1035 0x414B, 1036 0x4150, 1037 0x4151, 1038 0x4152, 1039 0x4153, 1040 0x4154, 1041 0x4155, 1042 0x4156, 1043 0x4237, 1044 0x4242, 1045 0x4336, 1046 0x4337, 1047 0x4437, 1048 0x4966, 1049 0x4967, 1050 0x4A48, 1051 0x4A49, 1052 0x4A4A, 1053 0x4A4B, 1054 0x4A4C, 1055 0x4A4D, 1056 0x4A4E, 1057 0x4A4F, 1058 0x4A50, 1059 0x4A54, 1060 0x4B48, 1061 0x4B49, 1062 0x4B4A, 1063 0x4B4B, 1064 0x4B4C, 1065 0x4C57, 1066 0x4C58, 1067 0x4C59, 1068 0x4C5A, 1069 0x4C64, 1070 0x4C66, 1071 0x4C67, 1072 0x4E44, 1073 0x4E45, 1074 0x4E46, 1075 0x4E47, 1076 0x4E48, 1077 0x4E49, 1078 0x4E4A, 1079 0x4E4B, 1080 0x4E50, 1081 0x4E51, 1082 0x4E52, 1083 0x4E53, 1084 0x4E54, 1085 0x4E56, 1086 0x5144, 1087 0x5145, 1088 0x5146, 1089 0x5147, 1090 0x5148, 1091 0x514C, 1092 0x514D, 1093 0x5157, 1094 0x5158, 1095 0x5159, 1096 0x515A, 1097 0x515E, 1098 0x5460, 1099 0x5462, 1100 0x5464, 1101 0x5548, 1102 0x5549, 1103 0x554A, 1104 0x554B, 1105 0x554C, 1106 0x554D, 1107 0x554E, 1108 0x554F, 1109 0x5550, 1110 0x5551, 1111 0x5552, 1112 0x5554, 1113 0x564A, 1114 0x564B, 1115 0x564F, 1116 0x5652, 1117 0x5653, 1118 0x5657, 1119 0x5834, 1120 0x5835, 1121 0x5954, 1122 0x5955, 1123 0x5974, 1124 0x5975, 1125 0x5960, 1126 0x5961, 1127 0x5962, 1128 0x5964, 1129 0x5965, 1130 0x5969, 1131 0x5a41, 1132 0x5a42, 1133 0x5a61, 1134 0x5a62, 1135 0x5b60, 1136 0x5b62, 1137 0x5b63, 1138 0x5b64, 1139 0x5b65, 1140 0x5c61, 1141 0x5c63, 1142 0x5d48, 1143 0x5d49, 1144 0x5d4a, 1145 0x5d4c, 1146 0x5d4d, 1147 0x5d4e, 1148 0x5d4f, 1149 0x5d50, 1150 0x5d52, 1151 0x5d57, 1152 0x5e48, 1153 0x5e4a, 1154 0x5e4b, 1155 0x5e4c, 1156 0x5e4d, 1157 0x5e4f, 1158 0x6700, 1159 0x6701, 1160 0x6702, 1161 0x6703, 1162 0x6704, 1163 0x6705, 1164 0x6706, 1165 0x6707, 1166 0x6708, 1167 0x6709, 1168 0x6718, 1169 0x6719, 1170 0x671c, 1171 0x671d, 1172 0x671f, 1173 0x6720, 1174 0x6721, 1175 0x6722, 1176 0x6723, 1177 0x6724, 1178 0x6725, 1179 0x6726, 1180 0x6727, 1181 0x6728, 1182 0x6729, 1183 0x6738, 1184 0x6739, 1185 0x673e, 1186 0x6740, 1187 0x6741, 1188 0x6742, 1189 0x6743, 1190 0x6744, 1191 0x6745, 1192 0x6746, 1193 0x6747, 1194 0x6748, 1195 0x6749, 1196 0x674A, 1197 0x6750, 1198 0x6751, 1199 0x6758, 1200 0x6759, 1201 0x675B, 1202 0x675D, 1203 0x675F, 1204 0x6760, 1205 0x6761, 1206 0x6762, 1207 0x6763, 1208 0x6764, 1209 0x6765, 1210 0x6766, 1211 0x6767, 1212 0x6768, 1213 0x6770, 1214 0x6771, 1215 0x6772, 1216 0x6778, 1217 0x6779, 1218 0x677B, 1219 0x6840, 1220 0x6841, 1221 0x6842, 1222 0x6843, 1223 0x6849, 1224 0x684C, 1225 0x6850, 1226 0x6858, 1227 0x6859, 1228 0x6880, 1229 0x6888, 1230 0x6889, 1231 0x688A, 1232 0x688C, 1233 0x688D, 1234 0x6898, 1235 0x6899, 1236 0x689b, 1237 0x689c, 1238 0x689d, 1239 0x689e, 1240 0x68a0, 1241 0x68a1, 1242 0x68a8, 1243 0x68a9, 1244 0x68b0, 1245 0x68b8, 1246 0x68b9, 1247 0x68ba, 1248 0x68be, 1249 0x68bf, 1250 0x68c0, 1251 0x68c1, 1252 0x68c7, 1253 0x68c8, 1254 0x68c9, 1255 0x68d8, 1256 0x68d9, 1257 0x68da, 1258 0x68de, 1259 0x68e0, 1260 0x68e1, 1261 0x68e4, 1262 0x68e5, 1263 0x68e8, 1264 0x68e9, 1265 0x68f1, 1266 0x68f2, 1267 0x68f8, 1268 0x68f9, 1269 0x68fa, 1270 0x68fe, 1271 0x7100, 1272 0x7101, 1273 0x7102, 1274 0x7103, 1275 0x7104, 1276 0x7105, 1277 0x7106, 1278 0x7108, 1279 0x7109, 1280 0x710A, 1281 0x710B, 1282 0x710C, 1283 0x710E, 1284 0x710F, 1285 0x7140, 1286 0x7141, 1287 0x7142, 1288 0x7143, 1289 0x7144, 1290 0x7145, 1291 0x7146, 1292 0x7147, 1293 0x7149, 1294 0x714A, 1295 0x714B, 1296 0x714C, 1297 0x714D, 1298 0x714E, 1299 0x714F, 1300 0x7151, 1301 0x7152, 1302 0x7153, 1303 0x715E, 1304 0x715F, 1305 0x7180, 1306 0x7181, 1307 0x7183, 1308 0x7186, 1309 0x7187, 1310 0x7188, 1311 0x718A, 1312 0x718B, 1313 0x718C, 1314 0x718D, 1315 0x718F, 1316 0x7193, 1317 0x7196, 1318 0x719B, 1319 0x719F, 1320 0x71C0, 1321 0x71C1, 1322 0x71C2, 1323 0x71C3, 1324 0x71C4, 1325 0x71C5, 1326 0x71C6, 1327 0x71C7, 1328 0x71CD, 1329 0x71CE, 1330 0x71D2, 1331 0x71D4, 1332 0x71D5, 1333 0x71D6, 1334 0x71DA, 1335 0x71DE, 1336 0x7200, 1337 0x7210, 1338 0x7211, 1339 0x7240, 1340 0x7243, 1341 0x7244, 1342 0x7245, 1343 0x7246, 1344 0x7247, 1345 0x7248, 1346 0x7249, 1347 0x724A, 1348 0x724B, 1349 0x724C, 1350 0x724D, 1351 0x724E, 1352 0x724F, 1353 0x7280, 1354 0x7281, 1355 0x7283, 1356 0x7284, 1357 0x7287, 1358 0x7288, 1359 0x7289, 1360 0x728B, 1361 0x728C, 1362 0x7290, 1363 0x7291, 1364 0x7293, 1365 0x7297, 1366 0x7834, 1367 0x7835, 1368 0x791e, 1369 0x791f, 1370 0x793f, 1371 0x7941, 1372 0x7942, 1373 0x796c, 1374 0x796d, 1375 0x796e, 1376 0x796f, 1377 0x9400, 1378 0x9401, 1379 0x9402, 1380 0x9403, 1381 0x9405, 1382 0x940A, 1383 0x940B, 1384 0x940F, 1385 0x94A0, 1386 0x94A1, 1387 0x94A3, 1388 0x94B1, 1389 0x94B3, 1390 0x94B4, 1391 0x94B5, 1392 0x94B9, 1393 0x9440, 1394 0x9441, 1395 0x9442, 1396 0x9443, 1397 0x9444, 1398 0x9446, 1399 0x944A, 1400 0x944B, 1401 0x944C, 1402 0x944E, 1403 0x9450, 1404 0x9452, 1405 0x9456, 1406 0x945A, 1407 0x945B, 1408 0x945E, 1409 0x9460, 1410 0x9462, 1411 0x946A, 1412 0x946B, 1413 0x947A, 1414 0x947B, 1415 0x9480, 1416 0x9487, 1417 0x9488, 1418 0x9489, 1419 0x948A, 1420 0x948F, 1421 0x9490, 1422 0x9491, 1423 0x9495, 1424 0x9498, 1425 0x949C, 1426 0x949E, 1427 0x949F, 1428 0x94C0, 1429 0x94C1, 1430 0x94C3, 1431 0x94C4, 1432 0x94C5, 1433 0x94C6, 1434 0x94C7, 1435 0x94C8, 1436 0x94C9, 1437 0x94CB, 1438 0x94CC, 1439 0x94CD, 1440 0x9500, 1441 0x9501, 1442 0x9504, 1443 0x9505, 1444 0x9506, 1445 0x9507, 1446 0x9508, 1447 0x9509, 1448 0x950F, 1449 0x9511, 1450 0x9515, 1451 0x9517, 1452 0x9519, 1453 0x9540, 1454 0x9541, 1455 0x9542, 1456 0x954E, 1457 0x954F, 1458 0x9552, 1459 0x9553, 1460 0x9555, 1461 0x9557, 1462 0x955f, 1463 0x9580, 1464 0x9581, 1465 0x9583, 1466 0x9586, 1467 0x9587, 1468 0x9588, 1469 0x9589, 1470 0x958A, 1471 0x958B, 1472 0x958C, 1473 0x958D, 1474 0x958E, 1475 0x958F, 1476 0x9590, 1477 0x9591, 1478 0x9593, 1479 0x9595, 1480 0x9596, 1481 0x9597, 1482 0x9598, 1483 0x9599, 1484 0x959B, 1485 0x95C0, 1486 0x95C2, 1487 0x95C4, 1488 0x95C5, 1489 0x95C6, 1490 0x95C7, 1491 0x95C9, 1492 0x95CC, 1493 0x95CD, 1494 0x95CE, 1495 0x95CF, 1496 0x9610, 1497 0x9611, 1498 0x9612, 1499 0x9613, 1500 0x9614, 1501 0x9615, 1502 0x9616, 1503 0x9640, 1504 0x9641, 1505 0x9642, 1506 0x9643, 1507 0x9644, 1508 0x9645, 1509 0x9647, 1510 0x9648, 1511 0x9649, 1512 0x964a, 1513 0x964b, 1514 0x964c, 1515 0x964e, 1516 0x964f, 1517 0x9710, 1518 0x9711, 1519 0x9712, 1520 0x9713, 1521 0x9714, 1522 0x9715, 1523 0x9802, 1524 0x9803, 1525 0x9804, 1526 0x9805, 1527 0x9806, 1528 0x9807, 1529 0x9808, 1530 0x9809, 1531 0x980A, 1532 0x9900, 1533 0x9901, 1534 0x9903, 1535 0x9904, 1536 0x9905, 1537 0x9906, 1538 0x9907, 1539 0x9908, 1540 0x9909, 1541 0x990A, 1542 0x990B, 1543 0x990C, 1544 0x990D, 1545 0x990E, 1546 0x990F, 1547 0x9910, 1548 0x9913, 1549 0x9917, 1550 0x9918, 1551 0x9919, 1552 0x9990, 1553 0x9991, 1554 0x9992, 1555 0x9993, 1556 0x9994, 1557 0x9995, 1558 0x9996, 1559 0x9997, 1560 0x9998, 1561 0x9999, 1562 0x999A, 1563 0x999B, 1564 0x999C, 1565 0x999D, 1566 0x99A0, 1567 0x99A2, 1568 0x99A4, 1569 /* radeon secondary ids */ 1570 0x3171, 1571 0x3e70, 1572 0x4164, 1573 0x4165, 1574 0x4166, 1575 0x4168, 1576 0x4170, 1577 0x4171, 1578 0x4172, 1579 0x4173, 1580 0x496e, 1581 0x4a69, 1582 0x4a6a, 1583 0x4a6b, 1584 0x4a70, 1585 0x4a74, 1586 0x4b69, 1587 0x4b6b, 1588 0x4b6c, 1589 0x4c6e, 1590 0x4e64, 1591 0x4e65, 1592 0x4e66, 1593 0x4e67, 1594 0x4e68, 1595 0x4e69, 1596 0x4e6a, 1597 0x4e71, 1598 0x4f73, 1599 0x5569, 1600 0x556b, 1601 0x556d, 1602 0x556f, 1603 0x5571, 1604 0x5854, 1605 0x5874, 1606 0x5940, 1607 0x5941, 1608 0x5b72, 1609 0x5b73, 1610 0x5b74, 1611 0x5b75, 1612 0x5d44, 1613 0x5d45, 1614 0x5d6d, 1615 0x5d6f, 1616 0x5d72, 1617 0x5d77, 1618 0x5e6b, 1619 0x5e6d, 1620 0x7120, 1621 0x7124, 1622 0x7129, 1623 0x712e, 1624 0x712f, 1625 0x7162, 1626 0x7163, 1627 0x7166, 1628 0x7167, 1629 0x7172, 1630 0x7173, 1631 0x71a0, 1632 0x71a1, 1633 0x71a3, 1634 0x71a7, 1635 0x71bb, 1636 0x71e0, 1637 0x71e1, 1638 0x71e2, 1639 0x71e6, 1640 0x71e7, 1641 0x71f2, 1642 0x7269, 1643 0x726b, 1644 0x726e, 1645 0x72a0, 1646 0x72a8, 1647 0x72b1, 1648 0x72b3, 1649 0x793f, 1650 }; 1651 1652 static const struct pci_device_id pciidlist[] = { 1653 #ifdef CONFIG_DRM_AMDGPU_SI 1654 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1655 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1656 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1657 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1658 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1659 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1660 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1661 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1662 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1663 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1664 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1665 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1666 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1667 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1668 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1669 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1670 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1671 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1672 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1673 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1674 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1675 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1676 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1677 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1678 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1679 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1680 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1681 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1682 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1683 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1684 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1685 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1686 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1687 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1688 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1689 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1690 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1691 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1692 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1693 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1694 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1695 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1696 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1697 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1698 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1699 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1700 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1701 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1702 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1703 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1704 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1705 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1706 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1707 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1708 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1709 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1710 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1711 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1712 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1713 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1714 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1715 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1716 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1717 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1718 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1719 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1720 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1721 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1722 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1723 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1724 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1725 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1726 #endif 1727 #ifdef CONFIG_DRM_AMDGPU_CIK 1728 /* Kaveri */ 1729 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1730 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1731 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1732 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1733 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1734 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1735 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1736 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1737 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1738 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1739 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1740 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1741 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1742 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1743 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1744 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1745 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1746 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1747 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1748 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1749 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1750 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1751 /* Bonaire */ 1752 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1753 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1754 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1755 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1756 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1757 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1758 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1759 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1760 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1761 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1762 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1763 /* Hawaii */ 1764 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1765 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1766 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1767 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1768 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1769 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1770 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1771 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1772 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1773 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1774 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1775 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1776 /* Kabini */ 1777 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1778 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1779 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1780 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1781 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1782 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1783 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1784 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1785 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1786 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1787 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1788 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1789 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1790 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1791 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1792 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1793 /* mullins */ 1794 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1795 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1796 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1797 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1798 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1799 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1800 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1801 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1802 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1803 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1804 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1805 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1806 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1807 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1808 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1809 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1810 #endif 1811 /* topaz */ 1812 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1813 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1814 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1815 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1816 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1817 /* tonga */ 1818 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1819 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1820 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1821 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1822 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1823 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1824 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1825 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1826 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1827 /* fiji */ 1828 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1829 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1830 /* carrizo */ 1831 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1832 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1833 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1834 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1835 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1836 /* stoney */ 1837 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1838 /* Polaris11 */ 1839 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1840 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1841 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1842 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1843 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1844 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1845 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1846 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1847 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1848 /* Polaris10 */ 1849 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1850 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1851 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1852 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1853 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1854 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1855 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1856 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1857 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1858 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1859 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1860 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1861 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1862 /* Polaris12 */ 1863 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1864 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1865 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1866 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1867 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1868 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1869 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1870 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1871 /* VEGAM */ 1872 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1873 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1874 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1875 /* Vega 10 */ 1876 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1877 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1878 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1879 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1880 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1881 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1882 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1883 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1884 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1885 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1886 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1887 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1888 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1889 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1890 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1891 /* Vega 12 */ 1892 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1893 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1894 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1895 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1896 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1897 /* Vega 20 */ 1898 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1899 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1900 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1901 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1902 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1903 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1904 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1905 /* Raven */ 1906 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1907 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1908 /* Arcturus */ 1909 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1910 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1911 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1912 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1913 /* Navi10 */ 1914 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1915 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1916 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1917 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1918 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1919 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1920 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1921 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1922 /* Navi14 */ 1923 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1924 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1925 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1926 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1927 1928 /* Renoir */ 1929 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1930 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1931 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1932 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1933 1934 /* Navi12 */ 1935 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1936 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1937 1938 /* Sienna_Cichlid */ 1939 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1940 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1941 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1942 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1943 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1944 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1945 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1946 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1947 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1948 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1949 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1950 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1951 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1952 1953 /* Van Gogh */ 1954 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1955 1956 /* Yellow Carp */ 1957 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1958 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1959 1960 /* Navy_Flounder */ 1961 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1962 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1963 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1964 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1965 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1966 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1967 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1968 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1969 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1970 1971 /* DIMGREY_CAVEFISH */ 1972 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1973 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1974 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1975 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1976 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1977 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1978 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1979 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1980 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1981 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1982 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1983 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1984 1985 /* Aldebaran */ 1986 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1987 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1988 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1989 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1990 1991 /* CYAN_SKILLFISH */ 1992 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1993 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1994 1995 /* BEIGE_GOBY */ 1996 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1997 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1998 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1999 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2000 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2001 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2002 2003 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2004 .class = PCI_CLASS_DISPLAY_VGA << 8, 2005 .class_mask = 0xffffff, 2006 .driver_data = CHIP_IP_DISCOVERY }, 2007 2008 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2009 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2010 .class_mask = 0xffffff, 2011 .driver_data = CHIP_IP_DISCOVERY }, 2012 2013 {0, 0, 0} 2014 }; 2015 2016 MODULE_DEVICE_TABLE(pci, pciidlist); 2017 2018 static const struct drm_driver amdgpu_kms_driver; 2019 2020 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2021 { 2022 STUB(); 2023 #ifdef notyet 2024 struct pci_dev *p = NULL; 2025 int i; 2026 2027 /* 0 - GPU 2028 * 1 - audio 2029 * 2 - USB 2030 * 3 - UCSI 2031 */ 2032 for (i = 1; i < 4; i++) { 2033 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2034 adev->pdev->bus->number, i); 2035 if (p) { 2036 pm_runtime_get_sync(&p->dev); 2037 pm_runtime_mark_last_busy(&p->dev); 2038 pm_runtime_put_autosuspend(&p->dev); 2039 pci_dev_put(p); 2040 } 2041 } 2042 #endif 2043 } 2044 2045 #ifdef notyet 2046 static int amdgpu_pci_probe(struct pci_dev *pdev, 2047 const struct pci_device_id *ent) 2048 { 2049 struct drm_device *ddev; 2050 struct amdgpu_device *adev; 2051 unsigned long flags = ent->driver_data; 2052 int ret, retry = 0, i; 2053 bool supports_atomic = false; 2054 2055 /* skip devices which are owned by radeon */ 2056 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2057 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2058 return -ENODEV; 2059 } 2060 2061 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2062 amdgpu_aspm = 0; 2063 2064 if (amdgpu_virtual_display || 2065 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2066 supports_atomic = true; 2067 2068 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2069 DRM_INFO("This hardware requires experimental hardware support.\n" 2070 "See modparam exp_hw_support\n"); 2071 return -ENODEV; 2072 } 2073 /* differentiate between P10 and P11 asics with the same DID */ 2074 if (pdev->device == 0x67FF && 2075 (pdev->revision == 0xE3 || 2076 pdev->revision == 0xE7 || 2077 pdev->revision == 0xF3 || 2078 pdev->revision == 0xF7)) { 2079 flags &= ~AMD_ASIC_MASK; 2080 flags |= CHIP_POLARIS10; 2081 } 2082 2083 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2084 * however, SME requires an indirect IOMMU mapping because the encryption 2085 * bit is beyond the DMA mask of the chip. 2086 */ 2087 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2088 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2089 dev_info(&pdev->dev, 2090 "SME is not compatible with RAVEN\n"); 2091 return -ENOTSUPP; 2092 } 2093 2094 #ifdef CONFIG_DRM_AMDGPU_SI 2095 if (!amdgpu_si_support) { 2096 switch (flags & AMD_ASIC_MASK) { 2097 case CHIP_TAHITI: 2098 case CHIP_PITCAIRN: 2099 case CHIP_VERDE: 2100 case CHIP_OLAND: 2101 case CHIP_HAINAN: 2102 dev_info(&pdev->dev, 2103 "SI support provided by radeon.\n"); 2104 dev_info(&pdev->dev, 2105 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2106 ); 2107 return -ENODEV; 2108 } 2109 } 2110 #endif 2111 #ifdef CONFIG_DRM_AMDGPU_CIK 2112 if (!amdgpu_cik_support) { 2113 switch (flags & AMD_ASIC_MASK) { 2114 case CHIP_KAVERI: 2115 case CHIP_BONAIRE: 2116 case CHIP_HAWAII: 2117 case CHIP_KABINI: 2118 case CHIP_MULLINS: 2119 dev_info(&pdev->dev, 2120 "CIK support provided by radeon.\n"); 2121 dev_info(&pdev->dev, 2122 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2123 ); 2124 return -ENODEV; 2125 } 2126 } 2127 #endif 2128 2129 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2130 if (IS_ERR(adev)) 2131 return PTR_ERR(adev); 2132 2133 adev->dev = &pdev->dev; 2134 adev->pdev = pdev; 2135 ddev = adev_to_drm(adev); 2136 2137 if (!supports_atomic) 2138 ddev->driver_features &= ~DRIVER_ATOMIC; 2139 2140 ret = pci_enable_device(pdev); 2141 if (ret) 2142 return ret; 2143 2144 pci_set_drvdata(pdev, ddev); 2145 2146 ret = amdgpu_driver_load_kms(adev, flags); 2147 if (ret) 2148 goto err_pci; 2149 2150 retry_init: 2151 ret = drm_dev_register(ddev, flags); 2152 if (ret == -EAGAIN && ++retry <= 3) { 2153 DRM_INFO("retry init %d\n", retry); 2154 /* Don't request EX mode too frequently which is attacking */ 2155 drm_msleep(5000); 2156 goto retry_init; 2157 } else if (ret) { 2158 goto err_pci; 2159 } 2160 2161 /* 2162 * 1. don't init fbdev on hw without DCE 2163 * 2. don't init fbdev if there are no connectors 2164 */ 2165 if (adev->mode_info.mode_config_initialized && 2166 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2167 /* select 8 bpp console on low vram cards */ 2168 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2169 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2170 else 2171 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2172 } 2173 2174 ret = amdgpu_debugfs_init(adev); 2175 if (ret) 2176 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2177 2178 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2179 /* only need to skip on ATPX */ 2180 if (amdgpu_device_supports_px(ddev)) 2181 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2182 /* we want direct complete for BOCO */ 2183 if (amdgpu_device_supports_boco(ddev)) 2184 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2185 DPM_FLAG_SMART_SUSPEND | 2186 DPM_FLAG_MAY_SKIP_RESUME); 2187 pm_runtime_use_autosuspend(ddev->dev); 2188 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2189 2190 pm_runtime_allow(ddev->dev); 2191 2192 pm_runtime_mark_last_busy(ddev->dev); 2193 pm_runtime_put_autosuspend(ddev->dev); 2194 2195 /* 2196 * For runpm implemented via BACO, PMFW will handle the 2197 * timing for BACO in and out: 2198 * - put ASIC into BACO state only when both video and 2199 * audio functions are in D3 state. 2200 * - pull ASIC out of BACO state when either video or 2201 * audio function is in D0 state. 2202 * Also, at startup, PMFW assumes both functions are in 2203 * D0 state. 2204 * 2205 * So if snd driver was loaded prior to amdgpu driver 2206 * and audio function was put into D3 state, there will 2207 * be no PMFW-aware D-state transition(D0->D3) on runpm 2208 * suspend. Thus the BACO will be not correctly kicked in. 2209 * 2210 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2211 * into D0 state. Then there will be a PMFW-aware D-state 2212 * transition(D0->D3) on runpm suspend. 2213 */ 2214 if (amdgpu_device_supports_baco(ddev) && 2215 !(adev->flags & AMD_IS_APU) && 2216 (adev->asic_type >= CHIP_NAVI10)) 2217 amdgpu_get_secondary_funcs(adev); 2218 } 2219 2220 return 0; 2221 2222 err_pci: 2223 pci_disable_device(pdev); 2224 return ret; 2225 } 2226 2227 static void 2228 amdgpu_pci_remove(struct pci_dev *pdev) 2229 { 2230 struct drm_device *dev = pci_get_drvdata(pdev); 2231 struct amdgpu_device *adev = drm_to_adev(dev); 2232 2233 drm_dev_unplug(dev); 2234 2235 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2236 pm_runtime_get_sync(dev->dev); 2237 pm_runtime_forbid(dev->dev); 2238 } 2239 2240 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2241 !amdgpu_sriov_vf(adev)) { 2242 bool need_to_reset_gpu = false; 2243 2244 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2245 struct amdgpu_hive_info *hive; 2246 2247 hive = amdgpu_get_xgmi_hive(adev); 2248 if (hive->device_remove_count == 0) 2249 need_to_reset_gpu = true; 2250 hive->device_remove_count++; 2251 amdgpu_put_xgmi_hive(hive); 2252 } else { 2253 need_to_reset_gpu = true; 2254 } 2255 2256 /* Workaround for ASICs need to reset SMU. 2257 * Called only when the first device is removed. 2258 */ 2259 if (need_to_reset_gpu) { 2260 struct amdgpu_reset_context reset_context; 2261 2262 adev->shutdown = true; 2263 memset(&reset_context, 0, sizeof(reset_context)); 2264 reset_context.method = AMD_RESET_METHOD_NONE; 2265 reset_context.reset_req_dev = adev; 2266 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2267 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2268 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2269 } 2270 } 2271 2272 amdgpu_driver_unload_kms(dev); 2273 2274 /* 2275 * Flush any in flight DMA operations from device. 2276 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2277 * StatusTransactions Pending bit. 2278 */ 2279 pci_disable_device(pdev); 2280 pci_wait_for_pending_transaction(pdev); 2281 } 2282 2283 static void 2284 amdgpu_pci_shutdown(struct pci_dev *pdev) 2285 { 2286 struct drm_device *dev = pci_get_drvdata(pdev); 2287 struct amdgpu_device *adev = drm_to_adev(dev); 2288 2289 if (amdgpu_ras_intr_triggered()) 2290 return; 2291 2292 /* if we are running in a VM, make sure the device 2293 * torn down properly on reboot/shutdown. 2294 * unfortunately we can't detect certain 2295 * hypervisors so just do this all the time. 2296 */ 2297 if (!amdgpu_passthrough(adev)) 2298 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2299 amdgpu_device_ip_suspend(adev); 2300 adev->mp1_state = PP_MP1_STATE_NONE; 2301 } 2302 #endif 2303 2304 /** 2305 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2306 * 2307 * @work: work_struct. 2308 */ 2309 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2310 { 2311 struct list_head device_list; 2312 struct amdgpu_device *adev; 2313 int i, r; 2314 struct amdgpu_reset_context reset_context; 2315 2316 memset(&reset_context, 0, sizeof(reset_context)); 2317 2318 mutex_lock(&mgpu_info.mutex); 2319 if (mgpu_info.pending_reset == true) { 2320 mutex_unlock(&mgpu_info.mutex); 2321 return; 2322 } 2323 mgpu_info.pending_reset = true; 2324 mutex_unlock(&mgpu_info.mutex); 2325 2326 /* Use a common context, just need to make sure full reset is done */ 2327 reset_context.method = AMD_RESET_METHOD_NONE; 2328 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2329 2330 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2331 adev = mgpu_info.gpu_ins[i].adev; 2332 reset_context.reset_req_dev = adev; 2333 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2334 if (r) { 2335 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2336 r, adev_to_drm(adev)->unique); 2337 } 2338 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2339 r = -EALREADY; 2340 } 2341 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2342 adev = mgpu_info.gpu_ins[i].adev; 2343 flush_work(&adev->xgmi_reset_work); 2344 adev->gmc.xgmi.pending_reset = false; 2345 } 2346 2347 /* reset function will rebuild the xgmi hive info , clear it now */ 2348 for (i = 0; i < mgpu_info.num_dgpu; i++) 2349 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2350 2351 INIT_LIST_HEAD(&device_list); 2352 2353 for (i = 0; i < mgpu_info.num_dgpu; i++) 2354 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2355 2356 /* unregister the GPU first, reset function will add them back */ 2357 list_for_each_entry(adev, &device_list, reset_list) 2358 amdgpu_unregister_gpu_instance(adev); 2359 2360 /* Use a common context, just need to make sure full reset is done */ 2361 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2362 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2363 2364 if (r) { 2365 DRM_ERROR("reinit gpus failure"); 2366 return; 2367 } 2368 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2369 adev = mgpu_info.gpu_ins[i].adev; 2370 if (!adev->kfd.init_complete) 2371 amdgpu_amdkfd_device_init(adev); 2372 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2373 } 2374 return; 2375 } 2376 2377 #ifdef notyet 2378 2379 static int amdgpu_pmops_prepare(struct device *dev) 2380 { 2381 struct drm_device *drm_dev = dev_get_drvdata(dev); 2382 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2383 2384 /* Return a positive number here so 2385 * DPM_FLAG_SMART_SUSPEND works properly 2386 */ 2387 if (amdgpu_device_supports_boco(drm_dev)) 2388 return pm_runtime_suspended(dev); 2389 2390 /* if we will not support s3 or s2i for the device 2391 * then skip suspend 2392 */ 2393 if (!amdgpu_acpi_is_s0ix_active(adev) && 2394 !amdgpu_acpi_is_s3_active(adev)) 2395 return 1; 2396 2397 return 0; 2398 } 2399 2400 static void amdgpu_pmops_complete(struct device *dev) 2401 { 2402 /* nothing to do */ 2403 } 2404 2405 static int amdgpu_pmops_suspend(struct device *dev) 2406 { 2407 struct drm_device *drm_dev = dev_get_drvdata(dev); 2408 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2409 2410 if (amdgpu_acpi_is_s0ix_active(adev)) 2411 adev->in_s0ix = true; 2412 else 2413 adev->in_s3 = true; 2414 return amdgpu_device_suspend(drm_dev, true); 2415 } 2416 2417 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2418 { 2419 struct drm_device *drm_dev = dev_get_drvdata(dev); 2420 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2421 2422 if (amdgpu_acpi_should_gpu_reset(adev)) 2423 return amdgpu_asic_reset(adev); 2424 2425 return 0; 2426 } 2427 2428 static int amdgpu_pmops_resume(struct device *dev) 2429 { 2430 struct drm_device *drm_dev = dev_get_drvdata(dev); 2431 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2432 int r; 2433 2434 /* Avoids registers access if device is physically gone */ 2435 if (!pci_device_is_present(adev->pdev)) 2436 adev->no_hw_access = true; 2437 2438 r = amdgpu_device_resume(drm_dev, true); 2439 if (amdgpu_acpi_is_s0ix_active(adev)) 2440 adev->in_s0ix = false; 2441 else 2442 adev->in_s3 = false; 2443 return r; 2444 } 2445 2446 static int amdgpu_pmops_freeze(struct device *dev) 2447 { 2448 struct drm_device *drm_dev = dev_get_drvdata(dev); 2449 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2450 int r; 2451 2452 adev->in_s4 = true; 2453 r = amdgpu_device_suspend(drm_dev, true); 2454 adev->in_s4 = false; 2455 if (r) 2456 return r; 2457 2458 if (amdgpu_acpi_should_gpu_reset(adev)) 2459 return amdgpu_asic_reset(adev); 2460 return 0; 2461 } 2462 2463 static int amdgpu_pmops_thaw(struct device *dev) 2464 { 2465 struct drm_device *drm_dev = dev_get_drvdata(dev); 2466 2467 return amdgpu_device_resume(drm_dev, true); 2468 } 2469 2470 static int amdgpu_pmops_poweroff(struct device *dev) 2471 { 2472 struct drm_device *drm_dev = dev_get_drvdata(dev); 2473 2474 return amdgpu_device_suspend(drm_dev, true); 2475 } 2476 2477 static int amdgpu_pmops_restore(struct device *dev) 2478 { 2479 struct drm_device *drm_dev = dev_get_drvdata(dev); 2480 2481 return amdgpu_device_resume(drm_dev, true); 2482 } 2483 2484 static int amdgpu_runtime_idle_check_display(struct device *dev) 2485 { 2486 struct pci_dev *pdev = to_pci_dev(dev); 2487 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2488 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2489 2490 if (adev->mode_info.num_crtc) { 2491 struct drm_connector *list_connector; 2492 struct drm_connector_list_iter iter; 2493 int ret = 0; 2494 2495 /* XXX: Return busy if any displays are connected to avoid 2496 * possible display wakeups after runtime resume due to 2497 * hotplug events in case any displays were connected while 2498 * the GPU was in suspend. Remove this once that is fixed. 2499 */ 2500 mutex_lock(&drm_dev->mode_config.mutex); 2501 drm_connector_list_iter_begin(drm_dev, &iter); 2502 drm_for_each_connector_iter(list_connector, &iter) { 2503 if (list_connector->status == connector_status_connected) { 2504 ret = -EBUSY; 2505 break; 2506 } 2507 } 2508 drm_connector_list_iter_end(&iter); 2509 mutex_unlock(&drm_dev->mode_config.mutex); 2510 2511 if (ret) 2512 return ret; 2513 2514 if (amdgpu_device_has_dc_support(adev)) { 2515 struct drm_crtc *crtc; 2516 2517 drm_for_each_crtc(crtc, drm_dev) { 2518 drm_modeset_lock(&crtc->mutex, NULL); 2519 if (crtc->state->active) 2520 ret = -EBUSY; 2521 drm_modeset_unlock(&crtc->mutex); 2522 if (ret < 0) 2523 break; 2524 } 2525 } else { 2526 mutex_lock(&drm_dev->mode_config.mutex); 2527 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2528 2529 drm_connector_list_iter_begin(drm_dev, &iter); 2530 drm_for_each_connector_iter(list_connector, &iter) { 2531 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2532 ret = -EBUSY; 2533 break; 2534 } 2535 } 2536 2537 drm_connector_list_iter_end(&iter); 2538 2539 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2540 mutex_unlock(&drm_dev->mode_config.mutex); 2541 } 2542 if (ret) 2543 return ret; 2544 } 2545 2546 return 0; 2547 } 2548 2549 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2550 { 2551 struct pci_dev *pdev = to_pci_dev(dev); 2552 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2553 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2554 int ret, i; 2555 2556 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2557 pm_runtime_forbid(dev); 2558 return -EBUSY; 2559 } 2560 2561 ret = amdgpu_runtime_idle_check_display(dev); 2562 if (ret) 2563 return ret; 2564 2565 /* wait for all rings to drain before suspending */ 2566 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2567 struct amdgpu_ring *ring = adev->rings[i]; 2568 if (ring && ring->sched.ready) { 2569 ret = amdgpu_fence_wait_empty(ring); 2570 if (ret) 2571 return -EBUSY; 2572 } 2573 } 2574 2575 adev->in_runpm = true; 2576 if (amdgpu_device_supports_px(drm_dev)) 2577 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2578 2579 /* 2580 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2581 * proper cleanups and put itself into a state ready for PNP. That 2582 * can address some random resuming failure observed on BOCO capable 2583 * platforms. 2584 * TODO: this may be also needed for PX capable platform. 2585 */ 2586 if (amdgpu_device_supports_boco(drm_dev)) 2587 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2588 2589 ret = amdgpu_device_suspend(drm_dev, false); 2590 if (ret) { 2591 adev->in_runpm = false; 2592 if (amdgpu_device_supports_boco(drm_dev)) 2593 adev->mp1_state = PP_MP1_STATE_NONE; 2594 return ret; 2595 } 2596 2597 if (amdgpu_device_supports_boco(drm_dev)) 2598 adev->mp1_state = PP_MP1_STATE_NONE; 2599 2600 if (amdgpu_device_supports_px(drm_dev)) { 2601 /* Only need to handle PCI state in the driver for ATPX 2602 * PCI core handles it for _PR3. 2603 */ 2604 amdgpu_device_cache_pci_state(pdev); 2605 pci_disable_device(pdev); 2606 pci_ignore_hotplug(pdev); 2607 pci_set_power_state(pdev, PCI_D3cold); 2608 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2609 } else if (amdgpu_device_supports_boco(drm_dev)) { 2610 /* nothing to do */ 2611 } else if (amdgpu_device_supports_baco(drm_dev)) { 2612 amdgpu_device_baco_enter(drm_dev); 2613 } 2614 2615 return 0; 2616 } 2617 2618 static int amdgpu_pmops_runtime_resume(struct device *dev) 2619 { 2620 struct pci_dev *pdev = to_pci_dev(dev); 2621 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2622 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2623 int ret; 2624 2625 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2626 return -EINVAL; 2627 2628 /* Avoids registers access if device is physically gone */ 2629 if (!pci_device_is_present(adev->pdev)) 2630 adev->no_hw_access = true; 2631 2632 if (amdgpu_device_supports_px(drm_dev)) { 2633 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2634 2635 /* Only need to handle PCI state in the driver for ATPX 2636 * PCI core handles it for _PR3. 2637 */ 2638 pci_set_power_state(pdev, PCI_D0); 2639 amdgpu_device_load_pci_state(pdev); 2640 ret = pci_enable_device(pdev); 2641 if (ret) 2642 return ret; 2643 pci_set_master(pdev); 2644 } else if (amdgpu_device_supports_boco(drm_dev)) { 2645 /* Only need to handle PCI state in the driver for ATPX 2646 * PCI core handles it for _PR3. 2647 */ 2648 pci_set_master(pdev); 2649 } else if (amdgpu_device_supports_baco(drm_dev)) { 2650 amdgpu_device_baco_exit(drm_dev); 2651 } 2652 ret = amdgpu_device_resume(drm_dev, false); 2653 if (ret) { 2654 if (amdgpu_device_supports_px(drm_dev)) 2655 pci_disable_device(pdev); 2656 return ret; 2657 } 2658 2659 if (amdgpu_device_supports_px(drm_dev)) 2660 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2661 adev->in_runpm = false; 2662 return 0; 2663 } 2664 2665 static int amdgpu_pmops_runtime_idle(struct device *dev) 2666 { 2667 struct drm_device *drm_dev = dev_get_drvdata(dev); 2668 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2669 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2670 int ret = 1; 2671 2672 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2673 pm_runtime_forbid(dev); 2674 return -EBUSY; 2675 } 2676 2677 ret = amdgpu_runtime_idle_check_display(dev); 2678 2679 pm_runtime_mark_last_busy(dev); 2680 pm_runtime_autosuspend(dev); 2681 return ret; 2682 } 2683 #endif /* notyet */ 2684 2685 #ifdef __linux__ 2686 long amdgpu_drm_ioctl(struct file *filp, 2687 unsigned int cmd, unsigned long arg) 2688 { 2689 struct drm_file *file_priv = filp->private_data; 2690 struct drm_device *dev; 2691 long ret; 2692 dev = file_priv->minor->dev; 2693 ret = pm_runtime_get_sync(dev->dev); 2694 if (ret < 0) 2695 goto out; 2696 2697 ret = drm_ioctl(filp, cmd, arg); 2698 2699 pm_runtime_mark_last_busy(dev->dev); 2700 out: 2701 pm_runtime_put_autosuspend(dev->dev); 2702 return ret; 2703 } 2704 2705 static const struct dev_pm_ops amdgpu_pm_ops = { 2706 .prepare = amdgpu_pmops_prepare, 2707 .complete = amdgpu_pmops_complete, 2708 .suspend = amdgpu_pmops_suspend, 2709 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2710 .resume = amdgpu_pmops_resume, 2711 .freeze = amdgpu_pmops_freeze, 2712 .thaw = amdgpu_pmops_thaw, 2713 .poweroff = amdgpu_pmops_poweroff, 2714 .restore = amdgpu_pmops_restore, 2715 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2716 .runtime_resume = amdgpu_pmops_runtime_resume, 2717 .runtime_idle = amdgpu_pmops_runtime_idle, 2718 }; 2719 2720 static int amdgpu_flush(struct file *f, fl_owner_t id) 2721 { 2722 struct drm_file *file_priv = f->private_data; 2723 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2724 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2725 2726 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2727 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2728 2729 return timeout >= 0 ? 0 : timeout; 2730 } 2731 2732 static const struct file_operations amdgpu_driver_kms_fops = { 2733 .owner = THIS_MODULE, 2734 .open = drm_open, 2735 .flush = amdgpu_flush, 2736 .release = drm_release, 2737 .unlocked_ioctl = amdgpu_drm_ioctl, 2738 .mmap = drm_gem_mmap, 2739 .poll = drm_poll, 2740 .read = drm_read, 2741 #ifdef CONFIG_COMPAT 2742 .compat_ioctl = amdgpu_kms_compat_ioctl, 2743 #endif 2744 #ifdef CONFIG_PROC_FS 2745 .show_fdinfo = amdgpu_show_fdinfo 2746 #endif 2747 }; 2748 2749 #endif /* __linux__ */ 2750 2751 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2752 { 2753 STUB(); 2754 return -ENOSYS; 2755 #ifdef notyet 2756 struct drm_file *file; 2757 2758 if (!filp) 2759 return -EINVAL; 2760 2761 if (filp->f_op != &amdgpu_driver_kms_fops) { 2762 return -EINVAL; 2763 } 2764 2765 file = filp->private_data; 2766 *fpriv = file->driver_priv; 2767 return 0; 2768 #endif 2769 } 2770 2771 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2772 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2773 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2774 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2775 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2776 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2777 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2778 /* KMS */ 2779 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2780 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2781 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2782 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2783 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2784 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2785 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2786 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2787 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2788 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2789 }; 2790 2791 static const struct drm_driver amdgpu_kms_driver = { 2792 .driver_features = 2793 DRIVER_ATOMIC | 2794 DRIVER_GEM | 2795 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2796 DRIVER_SYNCOBJ_TIMELINE, 2797 .open = amdgpu_driver_open_kms, 2798 #ifdef __OpenBSD__ 2799 .mmap = drm_gem_mmap, 2800 #endif 2801 .postclose = amdgpu_driver_postclose_kms, 2802 .lastclose = amdgpu_driver_lastclose_kms, 2803 .ioctls = amdgpu_ioctls_kms, 2804 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2805 .dumb_create = amdgpu_mode_dumb_create, 2806 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2807 #ifdef __linux__ 2808 .fops = &amdgpu_driver_kms_fops, 2809 #endif 2810 .release = &amdgpu_driver_release_kms, 2811 2812 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2813 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2814 .gem_prime_import = amdgpu_gem_prime_import, 2815 #ifdef notyet 2816 .gem_prime_mmap = drm_gem_prime_mmap, 2817 #endif 2818 2819 .name = DRIVER_NAME, 2820 .desc = DRIVER_DESC, 2821 .date = DRIVER_DATE, 2822 .major = KMS_DRIVER_MAJOR, 2823 .minor = KMS_DRIVER_MINOR, 2824 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2825 }; 2826 2827 #ifdef __linux__ 2828 static struct pci_error_handlers amdgpu_pci_err_handler = { 2829 .error_detected = amdgpu_pci_error_detected, 2830 .mmio_enabled = amdgpu_pci_mmio_enabled, 2831 .slot_reset = amdgpu_pci_slot_reset, 2832 .resume = amdgpu_pci_resume, 2833 }; 2834 2835 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2836 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2837 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2838 2839 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2840 &amdgpu_vram_mgr_attr_group, 2841 &amdgpu_gtt_mgr_attr_group, 2842 &amdgpu_vbios_version_attr_group, 2843 NULL, 2844 }; 2845 2846 2847 static struct pci_driver amdgpu_kms_pci_driver = { 2848 .name = DRIVER_NAME, 2849 .id_table = pciidlist, 2850 .probe = amdgpu_pci_probe, 2851 .remove = amdgpu_pci_remove, 2852 .shutdown = amdgpu_pci_shutdown, 2853 .driver.pm = &amdgpu_pm_ops, 2854 .err_handler = &amdgpu_pci_err_handler, 2855 .dev_groups = amdgpu_sysfs_groups, 2856 }; 2857 2858 static int __init amdgpu_init(void) 2859 { 2860 int r; 2861 2862 if (drm_firmware_drivers_only()) 2863 return -EINVAL; 2864 2865 r = amdgpu_sync_init(); 2866 if (r) 2867 goto error_sync; 2868 2869 r = amdgpu_fence_slab_init(); 2870 if (r) 2871 goto error_fence; 2872 2873 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2874 amdgpu_register_atpx_handler(); 2875 amdgpu_acpi_detect(); 2876 2877 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2878 amdgpu_amdkfd_init(); 2879 2880 /* let modprobe override vga console setting */ 2881 return pci_register_driver(&amdgpu_kms_pci_driver); 2882 2883 error_fence: 2884 amdgpu_sync_fini(); 2885 2886 error_sync: 2887 return r; 2888 } 2889 2890 static void __exit amdgpu_exit(void) 2891 { 2892 amdgpu_amdkfd_fini(); 2893 pci_unregister_driver(&amdgpu_kms_pci_driver); 2894 amdgpu_unregister_atpx_handler(); 2895 amdgpu_sync_fini(); 2896 amdgpu_fence_slab_fini(); 2897 mmu_notifier_synchronize(); 2898 } 2899 2900 module_init(amdgpu_init); 2901 module_exit(amdgpu_exit); 2902 2903 MODULE_AUTHOR(DRIVER_AUTHOR); 2904 MODULE_DESCRIPTION(DRIVER_DESC); 2905 MODULE_LICENSE("GPL and additional rights"); 2906 #endif /* __linux__ */ 2907 2908 #include <drm/drm_drv.h> 2909 #include <drm/drm_utils.h> 2910 2911 #include "vga.h" 2912 2913 #if NVGA > 0 2914 #include <dev/ic/mc6845reg.h> 2915 #include <dev/ic/pcdisplayvar.h> 2916 #include <dev/ic/vgareg.h> 2917 #include <dev/ic/vgavar.h> 2918 2919 extern int vga_console_attached; 2920 #endif 2921 2922 #ifdef __amd64__ 2923 #include "efifb.h" 2924 #include <machine/biosvar.h> 2925 #endif 2926 2927 #if NEFIFB > 0 2928 #include <machine/efifbvar.h> 2929 #endif 2930 2931 int amdgpu_probe(struct device *, void *, void *); 2932 void amdgpu_attach(struct device *, struct device *, void *); 2933 int amdgpu_detach(struct device *, int); 2934 int amdgpu_activate(struct device *, int); 2935 void amdgpu_attachhook(struct device *); 2936 int amdgpu_forcedetach(struct amdgpu_device *); 2937 2938 bool amdgpu_msi_ok(struct amdgpu_device *); 2939 2940 /* 2941 * set if the mountroot hook has a fatal error 2942 * such as not being able to find the firmware 2943 */ 2944 int amdgpu_fatal_error; 2945 2946 const struct cfattach amdgpu_ca = { 2947 sizeof (struct amdgpu_device), amdgpu_probe, amdgpu_attach, 2948 amdgpu_detach, amdgpu_activate 2949 }; 2950 2951 struct cfdriver amdgpu_cd = { 2952 NULL, "amdgpu", DV_DULL 2953 }; 2954 2955 int 2956 amdgpu_probe(struct device *parent, void *match, void *aux) 2957 { 2958 struct pci_attach_args *pa = aux; 2959 const struct pci_device_id *id_entry; 2960 unsigned long flags = 0; 2961 int i; 2962 2963 if (amdgpu_fatal_error) 2964 return 0; 2965 2966 id_entry = drm_find_description(PCI_VENDOR(pa->pa_id), 2967 PCI_PRODUCT(pa->pa_id), pciidlist); 2968 if (id_entry != NULL) { 2969 flags = id_entry->driver_data; 2970 2971 if (id_entry->device == PCI_ANY_ID) { 2972 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY) 2973 return 0; 2974 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA && 2975 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_MISC) 2976 return 0; 2977 } 2978 2979 /* skip devices which are owned by radeon */ 2980 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2981 if (amdgpu_unsupported_pciidlist[i] == 2982 PCI_PRODUCT(pa->pa_id)) 2983 return 0; 2984 } 2985 2986 if (flags & AMD_EXP_HW_SUPPORT) 2987 return 0; 2988 else 2989 return 20; 2990 } 2991 2992 return 0; 2993 } 2994 2995 /* 2996 * some functions are only called once on init regardless of how many times 2997 * amdgpu attaches in linux this is handled via module_init()/module_exit() 2998 */ 2999 int amdgpu_refcnt; 3000 3001 int __init drm_sched_fence_slab_init(void); 3002 void __exit drm_sched_fence_slab_fini(void); 3003 irqreturn_t amdgpu_irq_handler(void *); 3004 3005 void 3006 amdgpu_attach(struct device *parent, struct device *self, void *aux) 3007 { 3008 struct amdgpu_device *adev = (struct amdgpu_device *)self; 3009 struct drm_device *dev; 3010 struct pci_attach_args *pa = aux; 3011 const struct pci_device_id *id_entry; 3012 pcireg_t type; 3013 int i; 3014 uint8_t rmmio_bar; 3015 paddr_t fb_aper; 3016 pcireg_t addr, mask; 3017 int s; 3018 bool supports_atomic = false; 3019 3020 id_entry = drm_find_description(PCI_VENDOR(pa->pa_id), 3021 PCI_PRODUCT(pa->pa_id), pciidlist); 3022 adev->flags = id_entry->driver_data; 3023 adev->family = adev->flags & AMD_ASIC_MASK; 3024 adev->pc = pa->pa_pc; 3025 adev->pa_tag = pa->pa_tag; 3026 adev->iot = pa->pa_iot; 3027 adev->memt = pa->pa_memt; 3028 adev->dmat = pa->pa_dmat; 3029 3030 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && 3031 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA && 3032 (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) 3033 & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 3034 == (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) { 3035 adev->primary = 1; 3036 #if NVGA > 0 3037 adev->console = vga_is_console(pa->pa_iot, -1); 3038 vga_console_attached = 1; 3039 #endif 3040 } 3041 #if NEFIFB > 0 3042 if (efifb_is_primary(pa)) { 3043 adev->primary = 1; 3044 adev->console = efifb_is_console(pa); 3045 efifb_detach(); 3046 } 3047 #endif 3048 3049 #define AMDGPU_PCI_MEM 0x10 3050 3051 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM); 3052 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 3053 pci_mapreg_info(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM, 3054 type, &adev->fb_aper_offset, &adev->fb_aper_size, NULL)) { 3055 printf(": can't get frambuffer info\n"); 3056 return; 3057 } 3058 3059 if (adev->fb_aper_offset == 0) { 3060 bus_size_t start, end, pci_mem_end; 3061 bus_addr_t base; 3062 3063 KASSERT(pa->pa_memex != NULL); 3064 3065 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 3066 if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT) 3067 pci_mem_end = PCI_MEM64_END; 3068 else 3069 pci_mem_end = PCI_MEM_END; 3070 end = min(pci_mem_end, pa->pa_memex->ex_end); 3071 if (extent_alloc_subregion(pa->pa_memex, start, end, 3072 adev->fb_aper_size, adev->fb_aper_size, 0, 0, 0, &base)) { 3073 printf(": can't reserve framebuffer space\n"); 3074 return; 3075 } 3076 pci_conf_write(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM, base); 3077 if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT) 3078 pci_conf_write(pa->pa_pc, pa->pa_tag, 3079 AMDGPU_PCI_MEM + 4, (uint64_t)base >> 32); 3080 adev->fb_aper_offset = base; 3081 } 3082 3083 if (adev->family >= CHIP_BONAIRE) { 3084 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x18); 3085 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 3086 pci_mapreg_map(pa, 0x18, type, BUS_SPACE_MAP_LINEAR, 3087 &adev->doorbell.bst, &adev->doorbell.bsh, 3088 &adev->doorbell.base, &adev->doorbell.size, 0)) { 3089 printf(": can't map doorbell space\n"); 3090 return; 3091 } 3092 adev->doorbell.ptr = bus_space_vaddr(adev->doorbell.bst, 3093 adev->doorbell.bsh); 3094 } 3095 3096 if (adev->family >= CHIP_BONAIRE) 3097 rmmio_bar = 0x24; 3098 else 3099 rmmio_bar = 0x18; 3100 3101 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, rmmio_bar); 3102 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 3103 pci_mapreg_map(pa, rmmio_bar, type, BUS_SPACE_MAP_LINEAR, 3104 &adev->rmmio_bst, &adev->rmmio_bsh, &adev->rmmio_base, 3105 &adev->rmmio_size, 0)) { 3106 printf(": can't map rmmio space\n"); 3107 return; 3108 } 3109 adev->rmmio = bus_space_vaddr(adev->rmmio_bst, adev->rmmio_bsh); 3110 3111 /* 3112 * Make sure we have a base address for the ROM such that we 3113 * can map it later. 3114 */ 3115 s = splhigh(); 3116 addr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 3117 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 3118 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 3119 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, addr); 3120 splx(s); 3121 3122 if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) { 3123 bus_size_t size, start, end; 3124 bus_addr_t base; 3125 3126 size = PCI_ROM_SIZE(mask); 3127 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 3128 end = min(PCI_MEM_END, pa->pa_memex->ex_end); 3129 if (extent_alloc_subregion(pa->pa_memex, start, end, size, 3130 size, 0, 0, 0, &base) == 0) 3131 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, base); 3132 } 3133 3134 printf("\n"); 3135 3136 /* from amdgpu_pci_probe(), aspm test done later */ 3137 3138 if (!amdgpu_virtual_display && 3139 amdgpu_device_asic_has_dc_support(adev->family)) 3140 supports_atomic = true; 3141 3142 if ((adev->flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 3143 DRM_INFO("This hardware requires experimental hardware support.\n"); 3144 return; 3145 } 3146 3147 /* 3148 * Initialize amdkfd before starting radeon. 3149 */ 3150 amdgpu_amdkfd_init(); 3151 3152 dev = drm_attach_pci(&amdgpu_kms_driver, pa, 0, adev->primary, 3153 self, &adev->ddev); 3154 if (dev == NULL) { 3155 printf("%s: drm attach failed\n", adev->self.dv_xname); 3156 return; 3157 } 3158 adev->pdev = dev->pdev; 3159 3160 /* from amdgpu_pci_probe() */ 3161 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(adev->pdev)) 3162 amdgpu_aspm = 0; 3163 3164 if (!supports_atomic) 3165 dev->driver_features &= ~DRIVER_ATOMIC; 3166 3167 if (!amdgpu_msi_ok(adev)) 3168 pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 3169 3170 /* from amdgpu_init() */ 3171 if (amdgpu_refcnt == 0) { 3172 drm_sched_fence_slab_init(); 3173 3174 if (amdgpu_sync_init()) { 3175 printf("%s: amdgpu_sync_init failed\n", 3176 adev->self.dv_xname); 3177 return; 3178 } 3179 3180 if (amdgpu_fence_slab_init()) { 3181 amdgpu_sync_fini(); 3182 printf("%s: amdgpu_fence_slab_init failed\n", 3183 adev->self.dv_xname); 3184 return; 3185 } 3186 3187 amdgpu_register_atpx_handler(); 3188 amdgpu_acpi_detect(); 3189 } 3190 amdgpu_refcnt++; 3191 3192 adev->irq.msi_enabled = false; 3193 if (pci_intr_map_msi(pa, &adev->intrh) == 0) 3194 adev->irq.msi_enabled = true; 3195 else if (pci_intr_map(pa, &adev->intrh) != 0) { 3196 printf("%s: couldn't map interrupt\n", adev->self.dv_xname); 3197 return; 3198 } 3199 printf("%s: %s\n", adev->self.dv_xname, 3200 pci_intr_string(pa->pa_pc, adev->intrh)); 3201 3202 adev->irqh = pci_intr_establish(pa->pa_pc, adev->intrh, IPL_TTY, 3203 amdgpu_irq_handler, &adev->ddev, adev->self.dv_xname); 3204 if (adev->irqh == NULL) { 3205 printf("%s: couldn't establish interrupt\n", 3206 adev->self.dv_xname); 3207 return; 3208 } 3209 adev->pdev->irq = 0; 3210 3211 fb_aper = bus_space_mmap(adev->memt, adev->fb_aper_offset, 0, 0, 0); 3212 if (fb_aper != -1) 3213 rasops_claim_framebuffer(fb_aper, adev->fb_aper_size, self); 3214 3215 3216 adev->shutdown = true; 3217 config_mountroot(self, amdgpu_attachhook); 3218 } 3219 3220 int 3221 amdgpu_forcedetach(struct amdgpu_device *adev) 3222 { 3223 struct pci_softc *sc = (struct pci_softc *)adev->self.dv_parent; 3224 pcitag_t tag = adev->pa_tag; 3225 3226 #if NVGA > 0 3227 if (adev->primary) 3228 vga_console_attached = 0; 3229 #endif 3230 3231 /* reprobe pci device for non efi systems */ 3232 #if NEFIFB > 0 3233 if (bios_efiinfo == NULL && !efifb_cb_found()) { 3234 #endif 3235 config_detach(&adev->self, 0); 3236 return pci_probe_device(sc, tag, NULL, NULL); 3237 #if NEFIFB > 0 3238 } else if (adev->primary) { 3239 efifb_reattach(); 3240 } 3241 #endif 3242 3243 return 0; 3244 } 3245 3246 void amdgpu_burner(void *, u_int, u_int); 3247 void amdgpu_burner_cb(void *); 3248 int amdgpu_wsioctl(void *, u_long, caddr_t, int, struct proc *); 3249 paddr_t amdgpu_wsmmap(void *, off_t, int); 3250 int amdgpu_alloc_screen(void *, const struct wsscreen_descr *, 3251 void **, int *, int *, uint32_t *); 3252 void amdgpu_free_screen(void *, void *); 3253 int amdgpu_show_screen(void *, void *, int, 3254 void (*)(void *, int, int), void *); 3255 void amdgpu_doswitch(void *); 3256 void amdgpu_enter_ddb(void *, void *); 3257 3258 struct wsscreen_descr amdgpu_stdscreen = { 3259 "std", 3260 0, 0, 3261 0, 3262 0, 0, 3263 WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 3264 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS 3265 }; 3266 3267 const struct wsscreen_descr *amdgpu_scrlist[] = { 3268 &amdgpu_stdscreen, 3269 }; 3270 3271 struct wsscreen_list amdgpu_screenlist = { 3272 nitems(amdgpu_scrlist), amdgpu_scrlist 3273 }; 3274 3275 struct wsdisplay_accessops amdgpu_accessops = { 3276 .ioctl = amdgpu_wsioctl, 3277 .mmap = amdgpu_wsmmap, 3278 .alloc_screen = amdgpu_alloc_screen, 3279 .free_screen = amdgpu_free_screen, 3280 .show_screen = amdgpu_show_screen, 3281 .enter_ddb = amdgpu_enter_ddb, 3282 .getchar = rasops_getchar, 3283 .load_font = rasops_load_font, 3284 .list_font = rasops_list_font, 3285 .scrollback = rasops_scrollback, 3286 .burn_screen = amdgpu_burner 3287 }; 3288 3289 int 3290 amdgpu_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 3291 { 3292 struct rasops_info *ri = v; 3293 struct amdgpu_device *adev = ri->ri_hw; 3294 struct backlight_device *bd = adev->dm.backlight_dev[0]; 3295 struct wsdisplay_param *dp = (struct wsdisplay_param *)data; 3296 struct wsdisplay_fbinfo *wdf; 3297 3298 switch (cmd) { 3299 case WSDISPLAYIO_GTYPE: 3300 *(u_int *)data = WSDISPLAY_TYPE_RADEONDRM; 3301 return 0; 3302 case WSDISPLAYIO_GINFO: 3303 wdf = (struct wsdisplay_fbinfo *)data; 3304 wdf->width = ri->ri_width; 3305 wdf->height = ri->ri_height; 3306 wdf->depth = ri->ri_depth; 3307 wdf->stride = ri->ri_stride; 3308 wdf->offset = 0; 3309 wdf->cmsize = 0; 3310 return 0; 3311 case WSDISPLAYIO_GETPARAM: 3312 if (bd == NULL) 3313 return -1; 3314 3315 switch (dp->param) { 3316 case WSDISPLAYIO_PARAM_BRIGHTNESS: 3317 dp->min = 0; 3318 dp->max = bd->props.max_brightness; 3319 dp->curval = bd->props.brightness; 3320 return (dp->max > dp->min) ? 0 : -1; 3321 } 3322 break; 3323 case WSDISPLAYIO_SETPARAM: 3324 if (bd == NULL || dp->curval > bd->props.max_brightness) 3325 return -1; 3326 3327 switch (dp->param) { 3328 case WSDISPLAYIO_PARAM_BRIGHTNESS: 3329 bd->props.brightness = dp->curval; 3330 backlight_update_status(bd); 3331 knote_locked(&adev->ddev.note, NOTE_CHANGE); 3332 return 0; 3333 } 3334 break; 3335 } 3336 3337 return (-1); 3338 } 3339 3340 paddr_t 3341 amdgpu_wsmmap(void *v, off_t off, int prot) 3342 { 3343 return (-1); 3344 } 3345 3346 int 3347 amdgpu_alloc_screen(void *v, const struct wsscreen_descr *type, 3348 void **cookiep, int *curxp, int *curyp, uint32_t *attrp) 3349 { 3350 return rasops_alloc_screen(v, cookiep, curxp, curyp, attrp); 3351 } 3352 3353 void 3354 amdgpu_free_screen(void *v, void *cookie) 3355 { 3356 return rasops_free_screen(v, cookie); 3357 } 3358 3359 int 3360 amdgpu_show_screen(void *v, void *cookie, int waitok, 3361 void (*cb)(void *, int, int), void *cbarg) 3362 { 3363 struct rasops_info *ri = v; 3364 struct amdgpu_device *adev = ri->ri_hw; 3365 3366 if (cookie == ri->ri_active) 3367 return (0); 3368 3369 adev->switchcb = cb; 3370 adev->switchcbarg = cbarg; 3371 adev->switchcookie = cookie; 3372 if (cb) { 3373 task_add(systq, &adev->switchtask); 3374 return (EAGAIN); 3375 } 3376 3377 amdgpu_doswitch(v); 3378 3379 return (0); 3380 } 3381 3382 void 3383 amdgpu_doswitch(void *v) 3384 { 3385 struct rasops_info *ri = v; 3386 struct amdgpu_device *adev = ri->ri_hw; 3387 struct amdgpu_crtc *amdgpu_crtc; 3388 int i, crtc; 3389 3390 rasops_show_screen(ri, adev->switchcookie, 0, NULL, NULL); 3391 drm_fb_helper_restore_fbdev_mode_unlocked(adev_to_drm(adev)->fb_helper); 3392 3393 if (adev->switchcb) 3394 (adev->switchcb)(adev->switchcbarg, 0, 0); 3395 } 3396 3397 void 3398 amdgpu_enter_ddb(void *v, void *cookie) 3399 { 3400 struct rasops_info *ri = v; 3401 struct amdgpu_device *adev = ri->ri_hw; 3402 struct drm_fb_helper *fb_helper = adev_to_drm(adev)->fb_helper; 3403 3404 if (cookie == ri->ri_active) 3405 return; 3406 3407 rasops_show_screen(ri, cookie, 0, NULL, NULL); 3408 drm_fb_helper_debug_enter(fb_helper->fbdev); 3409 } 3410 3411 void 3412 amdgpu_init_backlight(struct amdgpu_device *adev) 3413 { 3414 struct drm_device *dev = &adev->ddev; 3415 struct backlight_device *bd = adev->dm.backlight_dev[0]; 3416 struct drm_connector_list_iter conn_iter; 3417 struct drm_connector *connector; 3418 3419 if (bd == NULL) 3420 return; 3421 3422 drm_connector_list_iter_begin(dev, &conn_iter); 3423 drm_for_each_connector_iter(connector, &conn_iter) { 3424 if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS && 3425 connector->connector_type != DRM_MODE_CONNECTOR_eDP && 3426 connector->connector_type != DRM_MODE_CONNECTOR_DSI) 3427 continue; 3428 3429 connector->backlight_device = bd; 3430 connector->backlight_property = drm_property_create_range(dev, 3431 0, "Backlight", 0, bd->props.max_brightness); 3432 drm_object_attach_property(&connector->base, 3433 connector->backlight_property, bd->props.brightness); 3434 } 3435 drm_connector_list_iter_end(&conn_iter); 3436 } 3437 3438 void 3439 amdgpu_attachhook(struct device *self) 3440 { 3441 struct amdgpu_device *adev = (struct amdgpu_device *)self; 3442 struct drm_device *dev = &adev->ddev; 3443 int r, acpi_status; 3444 struct rasops_info *ri = &adev->ro; 3445 struct drm_fb_helper *fb_helper; 3446 struct drm_framebuffer *fb; 3447 struct drm_gem_object *obj; 3448 struct amdgpu_bo *rbo; 3449 3450 /* from amdgpu_driver_load_kms() */ 3451 3452 /* amdgpu_device_init should report only fatal error 3453 * like memory allocation failure or iomapping failure, 3454 * or memory manager initialization failure, it must 3455 * properly initialize the GPU MC controller and permit 3456 * VRAM allocation 3457 */ 3458 r = amdgpu_device_init(adev, adev->flags); 3459 if (r) { 3460 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 3461 goto out; 3462 } 3463 3464 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; 3465 if (amdgpu_device_supports_px(dev) && 3466 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ 3467 adev->pm.rpm_mode = AMDGPU_RUNPM_PX; 3468 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 3469 } else if (amdgpu_device_supports_boco(dev) && 3470 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ 3471 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; 3472 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 3473 } else if (amdgpu_device_supports_baco(dev) && 3474 (amdgpu_runtime_pm != 0)) { 3475 switch (adev->asic_type) { 3476 case CHIP_VEGA20: 3477 case CHIP_ARCTURUS: 3478 /* enable BACO as runpm mode if runpm=1 */ 3479 if (amdgpu_runtime_pm > 0) 3480 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 3481 break; 3482 case CHIP_VEGA10: 3483 /* enable BACO as runpm mode if noretry=0 */ 3484 if (!adev->gmc.noretry) 3485 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 3486 break; 3487 default: 3488 /* enable BACO as runpm mode on CI+ */ 3489 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 3490 break; 3491 } 3492 3493 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) 3494 dev_info(adev->dev, "Using BACO for runtime pm\n"); 3495 } 3496 3497 /* Call ACPI methods: require modeset init 3498 * but failure is not fatal 3499 */ 3500 3501 acpi_status = amdgpu_acpi_init(adev); 3502 if (acpi_status) 3503 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 3504 3505 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 3506 DRM_WARN("smart shift update failed\n"); 3507 3508 /* 3509 * 1. don't init fbdev on hw without DCE 3510 * 2. don't init fbdev if there are no connectors 3511 */ 3512 if (adev->mode_info.mode_config_initialized && 3513 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 3514 3515 /* OpenBSD specific backlight property on connector */ 3516 amdgpu_init_backlight(adev); 3517 3518 /* 3519 * in linux via amdgpu_pci_probe -> drm_dev_register 3520 * must be after (local) backlight property added not before 3521 * and before drm_fbdev_generic_setup() 3522 */ 3523 drm_dev_register(dev, adev->flags); 3524 3525 /* select 8 bpp console on low vram cards */ 3526 if (adev->gmc.real_vram_size <= (32*1024*1024)) 3527 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 3528 else 3529 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 3530 3531 fb_helper = adev_to_drm(adev)->fb_helper; 3532 if (fb_helper == NULL) { 3533 printf("fb_helper NULL\n"); 3534 return; 3535 } 3536 fb = fb_helper->fb; 3537 obj = fb->obj[0]; 3538 rbo = gem_to_amdgpu_bo(obj); 3539 amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM); 3540 amdgpu_bo_kmap(rbo, (void **)(&ri->ri_bits)); 3541 3542 ri->ri_depth = fb->format->cpp[0] * 8; 3543 ri->ri_stride = fb->pitches[0]; 3544 ri->ri_width = fb_helper->fbdev->var.xres; 3545 ri->ri_height = fb_helper->fbdev->var.yres; 3546 3547 switch (fb->format->format) { 3548 case DRM_FORMAT_XRGB8888: 3549 ri->ri_rnum = 8; 3550 ri->ri_rpos = 16; 3551 ri->ri_gnum = 8; 3552 ri->ri_gpos = 8; 3553 ri->ri_bnum = 8; 3554 ri->ri_bpos = 0; 3555 break; 3556 case DRM_FORMAT_RGB565: 3557 ri->ri_rnum = 5; 3558 ri->ri_rpos = 11; 3559 ri->ri_gnum = 6; 3560 ri->ri_gpos = 5; 3561 ri->ri_bnum = 5; 3562 ri->ri_bpos = 0; 3563 break; 3564 } 3565 } 3566 { 3567 struct wsemuldisplaydev_attach_args aa; 3568 int orientation_quirk; 3569 3570 task_set(&adev->switchtask, amdgpu_doswitch, ri); 3571 task_set(&adev->burner_task, amdgpu_burner_cb, adev); 3572 3573 if (ri->ri_bits == NULL) 3574 return; 3575 3576 ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY; 3577 3578 orientation_quirk = drm_get_panel_orientation_quirk(ri->ri_width, 3579 ri->ri_height); 3580 if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_LEFT_UP) 3581 ri->ri_flg |= RI_ROTATE_CCW; 3582 else if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_RIGHT_UP) 3583 ri->ri_flg |= RI_ROTATE_CW; 3584 3585 rasops_init(ri, 160, 160); 3586 3587 ri->ri_hw = adev; 3588 3589 amdgpu_stdscreen.capabilities = ri->ri_caps; 3590 amdgpu_stdscreen.nrows = ri->ri_rows; 3591 amdgpu_stdscreen.ncols = ri->ri_cols; 3592 amdgpu_stdscreen.textops = &ri->ri_ops; 3593 amdgpu_stdscreen.fontwidth = ri->ri_font->fontwidth; 3594 amdgpu_stdscreen.fontheight = ri->ri_font->fontheight; 3595 3596 aa.console = adev->console; 3597 aa.primary = adev->primary; 3598 aa.scrdata = &amdgpu_screenlist; 3599 aa.accessops = &amdgpu_accessops; 3600 aa.accesscookie = ri; 3601 aa.defaultscreens = 0; 3602 3603 if (adev->console) { 3604 uint32_t defattr; 3605 3606 ri->ri_ops.pack_attr(ri->ri_active, 0, 0, 0, &defattr); 3607 wsdisplay_cnattach(&amdgpu_stdscreen, ri->ri_active, 3608 ri->ri_ccol, ri->ri_crow, defattr); 3609 } 3610 3611 /* 3612 * Now that we've taken over the console, disable decoding of 3613 * VGA legacy addresses, and opt out of arbitration. 3614 */ 3615 amdgpu_asic_set_vga_state(adev, false); 3616 pci_disable_legacy_vga(&adev->self); 3617 3618 printf("%s: %dx%d, %dbpp\n", adev->self.dv_xname, 3619 ri->ri_width, ri->ri_height, ri->ri_depth); 3620 3621 config_found_sm(&adev->self, &aa, wsemuldisplaydevprint, 3622 wsemuldisplaydevsubmatch); 3623 } 3624 3625 out: 3626 if (r) { 3627 amdgpu_fatal_error = 1; 3628 amdgpu_forcedetach(adev); 3629 } 3630 } 3631 3632 /* from amdgpu_exit amdgpu_driver_unload_kms */ 3633 int 3634 amdgpu_detach(struct device *self, int flags) 3635 { 3636 struct amdgpu_device *adev = (struct amdgpu_device *)self; 3637 struct drm_device *dev = &adev->ddev; 3638 3639 if (adev == NULL) 3640 return 0; 3641 3642 amdgpu_refcnt--; 3643 3644 if (amdgpu_refcnt == 0) 3645 amdgpu_amdkfd_fini(); 3646 3647 pci_intr_disestablish(adev->pc, adev->irqh); 3648 3649 amdgpu_unregister_gpu_instance(adev); 3650 3651 amdgpu_acpi_fini(adev); 3652 amdgpu_device_fini_hw(adev); 3653 3654 if (amdgpu_refcnt == 0) { 3655 amdgpu_unregister_atpx_handler(); 3656 amdgpu_sync_fini(); 3657 amdgpu_fence_slab_fini(); 3658 3659 drm_sched_fence_slab_fini(); 3660 } 3661 3662 config_detach(adev->ddev.dev, flags); 3663 3664 return 0; 3665 } 3666 3667 int 3668 amdgpu_activate(struct device *self, int act) 3669 { 3670 struct amdgpu_device *adev = (struct amdgpu_device *)self; 3671 struct drm_device *dev = &adev->ddev; 3672 int rv = 0; 3673 3674 if (dev->dev == NULL || amdgpu_fatal_error) 3675 return (0); 3676 3677 switch (act) { 3678 case DVACT_QUIESCE: 3679 rv = config_activate_children(self, act); 3680 amdgpu_device_suspend(dev, true); 3681 break; 3682 case DVACT_SUSPEND: 3683 break; 3684 case DVACT_RESUME: 3685 break; 3686 case DVACT_WAKEUP: 3687 amdgpu_device_resume(dev, true); 3688 rv = config_activate_children(self, act); 3689 break; 3690 } 3691 3692 return (rv); 3693 } 3694 3695 void 3696 amdgpu_burner(void *v, u_int on, u_int flags) 3697 { 3698 struct rasops_info *ri = v; 3699 struct amdgpu_device *adev = ri->ri_hw; 3700 3701 task_del(systq, &adev->burner_task); 3702 3703 if (on) 3704 adev->burner_fblank = FB_BLANK_UNBLANK; 3705 else { 3706 if (flags & WSDISPLAY_BURN_VBLANK) 3707 adev->burner_fblank = FB_BLANK_VSYNC_SUSPEND; 3708 else 3709 adev->burner_fblank = FB_BLANK_NORMAL; 3710 } 3711 3712 /* 3713 * Setting the DPMS mode may sleep while waiting for vblank so 3714 * hand things off to a taskq. 3715 */ 3716 task_add(systq, &adev->burner_task); 3717 } 3718 3719 void 3720 amdgpu_burner_cb(void *arg1) 3721 { 3722 struct amdgpu_device *adev = arg1; 3723 struct drm_fb_helper *helper = adev_to_drm(adev)->fb_helper; 3724 3725 drm_fb_helper_blank(adev->burner_fblank, helper->fbdev); 3726 } 3727