1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_aperture.h> 27 #include <drm/drm_drv.h> 28 #include <drm/drm_gem.h> 29 #include <drm/drm_vblank.h> 30 #include <drm/drm_managed.h> 31 #include "amdgpu_drv.h" 32 33 #include <drm/drm_pciids.h> 34 #include <linux/console.h> 35 #include <linux/module.h> 36 #include <linux/pm_runtime.h> 37 #include <linux/vga_switcheroo.h> 38 #include <drm/drm_probe_helper.h> 39 #include <linux/mmu_notifier.h> 40 #include <linux/suspend.h> 41 #include <linux/fb.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 */ 101 #define KMS_DRIVER_MAJOR 3 102 #define KMS_DRIVER_MINOR 42 103 #define KMS_DRIVER_PATCHLEVEL 0 104 105 int amdgpu_vram_limit; 106 int amdgpu_vis_vram_limit; 107 int amdgpu_gart_size = -1; /* auto */ 108 int amdgpu_gtt_size = -1; /* auto */ 109 int amdgpu_moverate = -1; /* auto */ 110 int amdgpu_benchmarking; 111 int amdgpu_testing; 112 int amdgpu_audio = -1; 113 int amdgpu_disp_priority; 114 int amdgpu_hw_i2c; 115 int amdgpu_pcie_gen2 = -1; 116 int amdgpu_msi = -1; 117 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 118 int amdgpu_dpm = -1; 119 int amdgpu_fw_load_type = -1; 120 int amdgpu_aspm = -1; 121 int amdgpu_runtime_pm = -1; 122 uint amdgpu_ip_block_mask = 0xffffffff; 123 int amdgpu_bapm = -1; 124 int amdgpu_deep_color; 125 int amdgpu_vm_size = -1; 126 int amdgpu_vm_fragment_size = -1; 127 int amdgpu_vm_block_size = -1; 128 int amdgpu_vm_fault_stop; 129 int amdgpu_vm_debug; 130 int amdgpu_vm_update_mode = -1; 131 int amdgpu_exp_hw_support; 132 int amdgpu_dc = -1; 133 int amdgpu_sched_jobs = 32; 134 int amdgpu_sched_hw_submission = 2; 135 uint amdgpu_pcie_gen_cap; 136 uint amdgpu_pcie_lane_cap; 137 uint amdgpu_cg_mask = 0xffffffff; 138 uint amdgpu_pg_mask = 0xffffffff; 139 uint amdgpu_sdma_phase_quantum = 32; 140 char *amdgpu_disable_cu = NULL; 141 char *amdgpu_virtual_display = NULL; 142 143 /* 144 * OverDrive(bit 14) disabled by default 145 * GFX DCS(bit 19) disabled by default 146 */ 147 uint amdgpu_pp_feature_mask = 0xfff7bfff; 148 uint amdgpu_force_long_training; 149 int amdgpu_job_hang_limit; 150 int amdgpu_lbpw = -1; 151 int amdgpu_compute_multipipe = -1; 152 int amdgpu_gpu_recovery = -1; /* auto */ 153 int amdgpu_emu_mode; 154 uint amdgpu_smu_memory_pool_size; 155 int amdgpu_smu_pptable_id = -1; 156 /* 157 * FBC (bit 0) disabled by default 158 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 159 * - With this, for multiple monitors in sync(e.g. with the same model), 160 * mclk switching will be allowed. And the mclk will be not foced to the 161 * highest. That helps saving some idle power. 162 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 163 * PSR (bit 3) disabled by default 164 * EDP NO POWER SEQUENCING (bit 4) disabled by default 165 */ 166 uint amdgpu_dc_feature_mask = 2; 167 uint amdgpu_dc_debug_mask; 168 int amdgpu_async_gfx_ring = 1; 169 int amdgpu_mcbp; 170 int amdgpu_discovery = -1; 171 int amdgpu_mes; 172 int amdgpu_noretry = -1; 173 int amdgpu_force_asic_type = -1; 174 int amdgpu_tmz = -1; /* auto */ 175 uint amdgpu_freesync_vid_mode; 176 int amdgpu_reset_method = -1; /* auto */ 177 int amdgpu_num_kcq = -1; 178 int amdgpu_smartshift_bias; 179 180 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 181 182 struct amdgpu_mgpu_info mgpu_info = { 183 .mutex = RWLOCK_INITIALIZER("mgpu_info"), 184 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 185 mgpu_info.delayed_reset_work, 186 amdgpu_drv_delayed_reset_work_handler, 0), 187 }; 188 int amdgpu_ras_enable = -1; 189 uint amdgpu_ras_mask = 0xffffffff; 190 int amdgpu_bad_page_threshold = -1; 191 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 192 .timeout_fatal_disable = false, 193 .period = 0x0, /* default to 0x0 (timeout disable) */ 194 }; 195 196 /** 197 * DOC: vramlimit (int) 198 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 199 */ 200 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 201 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 202 203 /** 204 * DOC: vis_vramlimit (int) 205 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 206 */ 207 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 208 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 209 210 /** 211 * DOC: gartsize (uint) 212 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 213 */ 214 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 215 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 216 217 /** 218 * DOC: gttsize (int) 219 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 220 * otherwise 3/4 RAM size). 221 */ 222 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 223 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 224 225 /** 226 * DOC: moverate (int) 227 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 228 */ 229 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 230 module_param_named(moverate, amdgpu_moverate, int, 0600); 231 232 /** 233 * DOC: benchmark (int) 234 * Run benchmarks. The default is 0 (Skip benchmarks). 235 */ 236 MODULE_PARM_DESC(benchmark, "Run benchmark"); 237 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 238 239 /** 240 * DOC: test (int) 241 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 242 */ 243 MODULE_PARM_DESC(test, "Run tests"); 244 module_param_named(test, amdgpu_testing, int, 0444); 245 246 /** 247 * DOC: audio (int) 248 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 249 */ 250 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 251 module_param_named(audio, amdgpu_audio, int, 0444); 252 253 /** 254 * DOC: disp_priority (int) 255 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 256 */ 257 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 258 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 259 260 /** 261 * DOC: hw_i2c (int) 262 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 263 */ 264 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 265 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 266 267 /** 268 * DOC: pcie_gen2 (int) 269 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 270 */ 271 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 272 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 273 274 /** 275 * DOC: msi (int) 276 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 277 */ 278 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 279 module_param_named(msi, amdgpu_msi, int, 0444); 280 281 /** 282 * DOC: lockup_timeout (string) 283 * Set GPU scheduler timeout value in ms. 284 * 285 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 286 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 287 * to the default timeout. 288 * 289 * - With one value specified, the setting will apply to all non-compute jobs. 290 * - With multiple values specified, the first one will be for GFX. 291 * The second one is for Compute. The third and fourth ones are 292 * for SDMA and Video. 293 * 294 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 295 * jobs is 10000. The timeout for compute is 60000. 296 */ 297 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 298 "for passthrough or sriov, 10000 for all jobs." 299 " 0: keep default value. negative: infinity timeout), " 300 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 301 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 302 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 303 304 /** 305 * DOC: dpm (int) 306 * Override for dynamic power management setting 307 * (0 = disable, 1 = enable) 308 * The default is -1 (auto). 309 */ 310 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 311 module_param_named(dpm, amdgpu_dpm, int, 0444); 312 313 /** 314 * DOC: fw_load_type (int) 315 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 316 */ 317 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 318 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 319 320 /** 321 * DOC: aspm (int) 322 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 323 */ 324 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 325 module_param_named(aspm, amdgpu_aspm, int, 0444); 326 327 /** 328 * DOC: runpm (int) 329 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 330 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 331 */ 332 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)"); 333 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 334 335 /** 336 * DOC: ip_block_mask (uint) 337 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 338 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 339 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 340 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 341 */ 342 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 343 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 344 345 /** 346 * DOC: bapm (int) 347 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 348 * The default -1 (auto, enabled) 349 */ 350 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 351 module_param_named(bapm, amdgpu_bapm, int, 0444); 352 353 /** 354 * DOC: deep_color (int) 355 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 356 */ 357 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 358 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 359 360 /** 361 * DOC: vm_size (int) 362 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 363 */ 364 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 365 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 366 367 /** 368 * DOC: vm_fragment_size (int) 369 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 370 */ 371 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 372 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 373 374 /** 375 * DOC: vm_block_size (int) 376 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 377 */ 378 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 379 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 380 381 /** 382 * DOC: vm_fault_stop (int) 383 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 384 */ 385 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 386 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 387 388 /** 389 * DOC: vm_debug (int) 390 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 391 */ 392 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 393 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 394 395 /** 396 * DOC: vm_update_mode (int) 397 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 398 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 399 */ 400 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 401 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 402 403 /** 404 * DOC: exp_hw_support (int) 405 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 406 */ 407 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 408 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 409 410 /** 411 * DOC: dc (int) 412 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 413 */ 414 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 415 module_param_named(dc, amdgpu_dc, int, 0444); 416 417 /** 418 * DOC: sched_jobs (int) 419 * Override the max number of jobs supported in the sw queue. The default is 32. 420 */ 421 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 422 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 423 424 /** 425 * DOC: sched_hw_submission (int) 426 * Override the max number of HW submissions. The default is 2. 427 */ 428 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 429 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 430 431 /** 432 * DOC: ppfeaturemask (hexint) 433 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 434 * The default is the current set of stable power features. 435 */ 436 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 437 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 438 439 /** 440 * DOC: forcelongtraining (uint) 441 * Force long memory training in resume. 442 * The default is zero, indicates short training in resume. 443 */ 444 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 445 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 446 447 /** 448 * DOC: pcie_gen_cap (uint) 449 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 450 * The default is 0 (automatic for each asic). 451 */ 452 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 453 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 454 455 /** 456 * DOC: pcie_lane_cap (uint) 457 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 458 * The default is 0 (automatic for each asic). 459 */ 460 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 461 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 462 463 /** 464 * DOC: cg_mask (uint) 465 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 466 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 467 */ 468 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 469 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 470 471 /** 472 * DOC: pg_mask (uint) 473 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 474 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 475 */ 476 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 477 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 478 479 /** 480 * DOC: sdma_phase_quantum (uint) 481 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 482 */ 483 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 484 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 485 486 /** 487 * DOC: disable_cu (charp) 488 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 489 */ 490 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 491 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 492 493 /** 494 * DOC: virtual_display (charp) 495 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 496 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 497 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 498 * device at 26:00.0. The default is NULL. 499 */ 500 MODULE_PARM_DESC(virtual_display, 501 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 502 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 503 504 /** 505 * DOC: job_hang_limit (int) 506 * Set how much time allow a job hang and not drop it. The default is 0. 507 */ 508 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 509 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 510 511 /** 512 * DOC: lbpw (int) 513 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 514 */ 515 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 516 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 517 518 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 519 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 520 521 /** 522 * DOC: gpu_recovery (int) 523 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 524 */ 525 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 526 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 527 528 /** 529 * DOC: emu_mode (int) 530 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 531 */ 532 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 533 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 534 535 /** 536 * DOC: ras_enable (int) 537 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 538 */ 539 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 540 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 541 542 /** 543 * DOC: ras_mask (uint) 544 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 545 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 546 */ 547 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 548 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 549 550 /** 551 * DOC: timeout_fatal_disable (bool) 552 * Disable Watchdog timeout fatal error event 553 */ 554 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 555 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 556 557 /** 558 * DOC: timeout_period (uint) 559 * Modify the watchdog timeout max_cycles as (1 << period) 560 */ 561 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 562 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 563 564 /** 565 * DOC: si_support (int) 566 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 567 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 568 * otherwise using amdgpu driver. 569 */ 570 #ifdef CONFIG_DRM_AMDGPU_SI 571 572 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 573 int amdgpu_si_support = 0; 574 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 575 #else 576 int amdgpu_si_support = 1; 577 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 578 #endif 579 580 module_param_named(si_support, amdgpu_si_support, int, 0444); 581 #endif 582 583 /** 584 * DOC: cik_support (int) 585 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 586 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 587 * otherwise using amdgpu driver. 588 */ 589 #ifdef CONFIG_DRM_AMDGPU_CIK 590 591 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 592 int amdgpu_cik_support = 0; 593 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 594 #else 595 int amdgpu_cik_support = 1; 596 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 597 #endif 598 599 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 600 #endif 601 602 /** 603 * DOC: smu_memory_pool_size (uint) 604 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 605 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 606 */ 607 MODULE_PARM_DESC(smu_memory_pool_size, 608 "reserve gtt for smu debug usage, 0 = disable," 609 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 610 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 611 612 /** 613 * DOC: async_gfx_ring (int) 614 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 615 */ 616 MODULE_PARM_DESC(async_gfx_ring, 617 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 618 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 619 620 /** 621 * DOC: mcbp (int) 622 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 623 */ 624 MODULE_PARM_DESC(mcbp, 625 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 626 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 627 628 /** 629 * DOC: discovery (int) 630 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 631 * (-1 = auto (default), 0 = disabled, 1 = enabled) 632 */ 633 MODULE_PARM_DESC(discovery, 634 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 635 module_param_named(discovery, amdgpu_discovery, int, 0444); 636 637 /** 638 * DOC: mes (int) 639 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 640 * (0 = disabled (default), 1 = enabled) 641 */ 642 MODULE_PARM_DESC(mes, 643 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 644 module_param_named(mes, amdgpu_mes, int, 0444); 645 646 /** 647 * DOC: noretry (int) 648 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 649 * do not support per-process XNACK this also disables retry page faults. 650 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 651 */ 652 MODULE_PARM_DESC(noretry, 653 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 654 module_param_named(noretry, amdgpu_noretry, int, 0644); 655 656 /** 657 * DOC: force_asic_type (int) 658 * A non negative value used to specify the asic type for all supported GPUs. 659 */ 660 MODULE_PARM_DESC(force_asic_type, 661 "A non negative value used to specify the asic type for all supported GPUs"); 662 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 663 664 665 666 #ifdef CONFIG_HSA_AMD 667 /** 668 * DOC: sched_policy (int) 669 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 670 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 671 * assigns queues to HQDs. 672 */ 673 int sched_policy = KFD_SCHED_POLICY_HWS; 674 module_param(sched_policy, int, 0444); 675 MODULE_PARM_DESC(sched_policy, 676 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 677 678 /** 679 * DOC: hws_max_conc_proc (int) 680 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 681 * number of VMIDs assigned to the HWS, which is also the default. 682 */ 683 int hws_max_conc_proc = -1; 684 module_param(hws_max_conc_proc, int, 0444); 685 MODULE_PARM_DESC(hws_max_conc_proc, 686 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 687 688 /** 689 * DOC: cwsr_enable (int) 690 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 691 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 692 * disables it. 693 */ 694 int cwsr_enable = 1; 695 module_param(cwsr_enable, int, 0444); 696 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 697 698 /** 699 * DOC: max_num_of_queues_per_device (int) 700 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 701 * is 4096. 702 */ 703 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 704 module_param(max_num_of_queues_per_device, int, 0444); 705 MODULE_PARM_DESC(max_num_of_queues_per_device, 706 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 707 708 /** 709 * DOC: send_sigterm (int) 710 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 711 * but just print errors on dmesg. Setting 1 enables sending sigterm. 712 */ 713 int send_sigterm; 714 module_param(send_sigterm, int, 0444); 715 MODULE_PARM_DESC(send_sigterm, 716 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 717 718 /** 719 * DOC: debug_largebar (int) 720 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 721 * system. This limits the VRAM size reported to ROCm applications to the visible 722 * size, usually 256MB. 723 * Default value is 0, diabled. 724 */ 725 int debug_largebar; 726 module_param(debug_largebar, int, 0444); 727 MODULE_PARM_DESC(debug_largebar, 728 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 729 730 /** 731 * DOC: ignore_crat (int) 732 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 733 * table to get information about AMD APUs. This option can serve as a workaround on 734 * systems with a broken CRAT table. 735 * 736 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 737 * whehter use CRAT) 738 */ 739 int ignore_crat; 740 module_param(ignore_crat, int, 0444); 741 MODULE_PARM_DESC(ignore_crat, 742 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 743 744 /** 745 * DOC: halt_if_hws_hang (int) 746 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 747 * Setting 1 enables halt on hang. 748 */ 749 int halt_if_hws_hang; 750 module_param(halt_if_hws_hang, int, 0644); 751 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 752 753 /** 754 * DOC: hws_gws_support(bool) 755 * Assume that HWS supports GWS barriers regardless of what firmware version 756 * check says. Default value: false (rely on MEC2 firmware version check). 757 */ 758 bool hws_gws_support; 759 module_param(hws_gws_support, bool, 0444); 760 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 761 762 /** 763 * DOC: queue_preemption_timeout_ms (int) 764 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 765 */ 766 int queue_preemption_timeout_ms = 9000; 767 module_param(queue_preemption_timeout_ms, int, 0644); 768 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 769 770 /** 771 * DOC: debug_evictions(bool) 772 * Enable extra debug messages to help determine the cause of evictions 773 */ 774 bool debug_evictions; 775 module_param(debug_evictions, bool, 0644); 776 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 777 778 /** 779 * DOC: no_system_mem_limit(bool) 780 * Disable system memory limit, to support multiple process shared memory 781 */ 782 bool no_system_mem_limit; 783 module_param(no_system_mem_limit, bool, 0644); 784 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 785 786 /** 787 * DOC: no_queue_eviction_on_vm_fault (int) 788 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 789 */ 790 int amdgpu_no_queue_eviction_on_vm_fault = 0; 791 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 792 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 793 #endif 794 795 /** 796 * DOC: dcfeaturemask (uint) 797 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 798 * The default is the current set of stable display features. 799 */ 800 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 801 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 802 803 /** 804 * DOC: dcdebugmask (uint) 805 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 806 */ 807 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 808 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 809 810 /** 811 * DOC: abmlevel (uint) 812 * Override the default ABM (Adaptive Backlight Management) level used for DC 813 * enabled hardware. Requires DMCU to be supported and loaded. 814 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 815 * default. Values 1-4 control the maximum allowable brightness reduction via 816 * the ABM algorithm, with 1 being the least reduction and 4 being the most 817 * reduction. 818 * 819 * Defaults to 0, or disabled. Userspace can still override this level later 820 * after boot. 821 */ 822 uint amdgpu_dm_abm_level; 823 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 824 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 825 826 int amdgpu_backlight = -1; 827 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 828 module_param_named(backlight, amdgpu_backlight, bint, 0444); 829 830 /** 831 * DOC: tmz (int) 832 * Trusted Memory Zone (TMZ) is a method to protect data being written 833 * to or read from memory. 834 * 835 * The default value: 0 (off). TODO: change to auto till it is completed. 836 */ 837 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 838 module_param_named(tmz, amdgpu_tmz, int, 0444); 839 840 /** 841 * DOC: freesync_video (uint) 842 * Enable the optimization to adjust front porch timing to achieve seamless 843 * mode change experience when setting a freesync supported mode for which full 844 * modeset is not needed. 845 * 846 * The Display Core will add a set of modes derived from the base FreeSync 847 * video mode into the corresponding connector's mode list based on commonly 848 * used refresh rates and VRR range of the connected display, when users enable 849 * this feature. From the userspace perspective, they can see a seamless mode 850 * change experience when the change between different refresh rates under the 851 * same resolution. Additionally, userspace applications such as Video playback 852 * can read this modeset list and change the refresh rate based on the video 853 * frame rate. Finally, the userspace can also derive an appropriate mode for a 854 * particular refresh rate based on the FreeSync Mode and add it to the 855 * connector's mode list. 856 * 857 * Note: This is an experimental feature. 858 * 859 * The default value: 0 (off). 860 */ 861 MODULE_PARM_DESC( 862 freesync_video, 863 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 864 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 865 866 /** 867 * DOC: reset_method (int) 868 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco, 5 = pci) 869 */ 870 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)"); 871 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 872 873 /** 874 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 875 * threshold value of faulty pages detected by RAS ECC, which may 876 * result in the GPU entering bad status when the number of total 877 * faulty pages by ECC exceeds the threshold value. 878 */ 879 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)"); 880 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 881 882 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 883 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 884 885 /** 886 * DOC: smu_pptable_id (int) 887 * Used to override pptable id. id = 0 use VBIOS pptable. 888 * id > 0 use the soft pptable with specicfied id. 889 */ 890 MODULE_PARM_DESC(smu_pptable_id, 891 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 892 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 893 894 /* These devices are not supported by amdgpu. 895 * They are supported by the mach64, r128, radeon drivers 896 */ 897 static const u16 amdgpu_unsupported_pciidlist[] = { 898 /* mach64 */ 899 0x4354, 900 0x4358, 901 0x4554, 902 0x4742, 903 0x4744, 904 0x4749, 905 0x474C, 906 0x474D, 907 0x474E, 908 0x474F, 909 0x4750, 910 0x4751, 911 0x4752, 912 0x4753, 913 0x4754, 914 0x4755, 915 0x4756, 916 0x4757, 917 0x4758, 918 0x4759, 919 0x475A, 920 0x4C42, 921 0x4C44, 922 0x4C47, 923 0x4C49, 924 0x4C4D, 925 0x4C4E, 926 0x4C50, 927 0x4C51, 928 0x4C52, 929 0x4C53, 930 0x5654, 931 0x5655, 932 0x5656, 933 /* r128 */ 934 0x4c45, 935 0x4c46, 936 0x4d46, 937 0x4d4c, 938 0x5041, 939 0x5042, 940 0x5043, 941 0x5044, 942 0x5045, 943 0x5046, 944 0x5047, 945 0x5048, 946 0x5049, 947 0x504A, 948 0x504B, 949 0x504C, 950 0x504D, 951 0x504E, 952 0x504F, 953 0x5050, 954 0x5051, 955 0x5052, 956 0x5053, 957 0x5054, 958 0x5055, 959 0x5056, 960 0x5057, 961 0x5058, 962 0x5245, 963 0x5246, 964 0x5247, 965 0x524b, 966 0x524c, 967 0x534d, 968 0x5446, 969 0x544C, 970 0x5452, 971 /* radeon */ 972 0x3150, 973 0x3151, 974 0x3152, 975 0x3154, 976 0x3155, 977 0x3E50, 978 0x3E54, 979 0x4136, 980 0x4137, 981 0x4144, 982 0x4145, 983 0x4146, 984 0x4147, 985 0x4148, 986 0x4149, 987 0x414A, 988 0x414B, 989 0x4150, 990 0x4151, 991 0x4152, 992 0x4153, 993 0x4154, 994 0x4155, 995 0x4156, 996 0x4237, 997 0x4242, 998 0x4336, 999 0x4337, 1000 0x4437, 1001 0x4966, 1002 0x4967, 1003 0x4A48, 1004 0x4A49, 1005 0x4A4A, 1006 0x4A4B, 1007 0x4A4C, 1008 0x4A4D, 1009 0x4A4E, 1010 0x4A4F, 1011 0x4A50, 1012 0x4A54, 1013 0x4B48, 1014 0x4B49, 1015 0x4B4A, 1016 0x4B4B, 1017 0x4B4C, 1018 0x4C57, 1019 0x4C58, 1020 0x4C59, 1021 0x4C5A, 1022 0x4C64, 1023 0x4C66, 1024 0x4C67, 1025 0x4E44, 1026 0x4E45, 1027 0x4E46, 1028 0x4E47, 1029 0x4E48, 1030 0x4E49, 1031 0x4E4A, 1032 0x4E4B, 1033 0x4E50, 1034 0x4E51, 1035 0x4E52, 1036 0x4E53, 1037 0x4E54, 1038 0x4E56, 1039 0x5144, 1040 0x5145, 1041 0x5146, 1042 0x5147, 1043 0x5148, 1044 0x514C, 1045 0x514D, 1046 0x5157, 1047 0x5158, 1048 0x5159, 1049 0x515A, 1050 0x515E, 1051 0x5460, 1052 0x5462, 1053 0x5464, 1054 0x5548, 1055 0x5549, 1056 0x554A, 1057 0x554B, 1058 0x554C, 1059 0x554D, 1060 0x554E, 1061 0x554F, 1062 0x5550, 1063 0x5551, 1064 0x5552, 1065 0x5554, 1066 0x564A, 1067 0x564B, 1068 0x564F, 1069 0x5652, 1070 0x5653, 1071 0x5657, 1072 0x5834, 1073 0x5835, 1074 0x5954, 1075 0x5955, 1076 0x5974, 1077 0x5975, 1078 0x5960, 1079 0x5961, 1080 0x5962, 1081 0x5964, 1082 0x5965, 1083 0x5969, 1084 0x5a41, 1085 0x5a42, 1086 0x5a61, 1087 0x5a62, 1088 0x5b60, 1089 0x5b62, 1090 0x5b63, 1091 0x5b64, 1092 0x5b65, 1093 0x5c61, 1094 0x5c63, 1095 0x5d48, 1096 0x5d49, 1097 0x5d4a, 1098 0x5d4c, 1099 0x5d4d, 1100 0x5d4e, 1101 0x5d4f, 1102 0x5d50, 1103 0x5d52, 1104 0x5d57, 1105 0x5e48, 1106 0x5e4a, 1107 0x5e4b, 1108 0x5e4c, 1109 0x5e4d, 1110 0x5e4f, 1111 0x6700, 1112 0x6701, 1113 0x6702, 1114 0x6703, 1115 0x6704, 1116 0x6705, 1117 0x6706, 1118 0x6707, 1119 0x6708, 1120 0x6709, 1121 0x6718, 1122 0x6719, 1123 0x671c, 1124 0x671d, 1125 0x671f, 1126 0x6720, 1127 0x6721, 1128 0x6722, 1129 0x6723, 1130 0x6724, 1131 0x6725, 1132 0x6726, 1133 0x6727, 1134 0x6728, 1135 0x6729, 1136 0x6738, 1137 0x6739, 1138 0x673e, 1139 0x6740, 1140 0x6741, 1141 0x6742, 1142 0x6743, 1143 0x6744, 1144 0x6745, 1145 0x6746, 1146 0x6747, 1147 0x6748, 1148 0x6749, 1149 0x674A, 1150 0x6750, 1151 0x6751, 1152 0x6758, 1153 0x6759, 1154 0x675B, 1155 0x675D, 1156 0x675F, 1157 0x6760, 1158 0x6761, 1159 0x6762, 1160 0x6763, 1161 0x6764, 1162 0x6765, 1163 0x6766, 1164 0x6767, 1165 0x6768, 1166 0x6770, 1167 0x6771, 1168 0x6772, 1169 0x6778, 1170 0x6779, 1171 0x677B, 1172 0x6840, 1173 0x6841, 1174 0x6842, 1175 0x6843, 1176 0x6849, 1177 0x684C, 1178 0x6850, 1179 0x6858, 1180 0x6859, 1181 0x6880, 1182 0x6888, 1183 0x6889, 1184 0x688A, 1185 0x688C, 1186 0x688D, 1187 0x6898, 1188 0x6899, 1189 0x689b, 1190 0x689c, 1191 0x689d, 1192 0x689e, 1193 0x68a0, 1194 0x68a1, 1195 0x68a8, 1196 0x68a9, 1197 0x68b0, 1198 0x68b8, 1199 0x68b9, 1200 0x68ba, 1201 0x68be, 1202 0x68bf, 1203 0x68c0, 1204 0x68c1, 1205 0x68c7, 1206 0x68c8, 1207 0x68c9, 1208 0x68d8, 1209 0x68d9, 1210 0x68da, 1211 0x68de, 1212 0x68e0, 1213 0x68e1, 1214 0x68e4, 1215 0x68e5, 1216 0x68e8, 1217 0x68e9, 1218 0x68f1, 1219 0x68f2, 1220 0x68f8, 1221 0x68f9, 1222 0x68fa, 1223 0x68fe, 1224 0x7100, 1225 0x7101, 1226 0x7102, 1227 0x7103, 1228 0x7104, 1229 0x7105, 1230 0x7106, 1231 0x7108, 1232 0x7109, 1233 0x710A, 1234 0x710B, 1235 0x710C, 1236 0x710E, 1237 0x710F, 1238 0x7140, 1239 0x7141, 1240 0x7142, 1241 0x7143, 1242 0x7144, 1243 0x7145, 1244 0x7146, 1245 0x7147, 1246 0x7149, 1247 0x714A, 1248 0x714B, 1249 0x714C, 1250 0x714D, 1251 0x714E, 1252 0x714F, 1253 0x7151, 1254 0x7152, 1255 0x7153, 1256 0x715E, 1257 0x715F, 1258 0x7180, 1259 0x7181, 1260 0x7183, 1261 0x7186, 1262 0x7187, 1263 0x7188, 1264 0x718A, 1265 0x718B, 1266 0x718C, 1267 0x718D, 1268 0x718F, 1269 0x7193, 1270 0x7196, 1271 0x719B, 1272 0x719F, 1273 0x71C0, 1274 0x71C1, 1275 0x71C2, 1276 0x71C3, 1277 0x71C4, 1278 0x71C5, 1279 0x71C6, 1280 0x71C7, 1281 0x71CD, 1282 0x71CE, 1283 0x71D2, 1284 0x71D4, 1285 0x71D5, 1286 0x71D6, 1287 0x71DA, 1288 0x71DE, 1289 0x7200, 1290 0x7210, 1291 0x7211, 1292 0x7240, 1293 0x7243, 1294 0x7244, 1295 0x7245, 1296 0x7246, 1297 0x7247, 1298 0x7248, 1299 0x7249, 1300 0x724A, 1301 0x724B, 1302 0x724C, 1303 0x724D, 1304 0x724E, 1305 0x724F, 1306 0x7280, 1307 0x7281, 1308 0x7283, 1309 0x7284, 1310 0x7287, 1311 0x7288, 1312 0x7289, 1313 0x728B, 1314 0x728C, 1315 0x7290, 1316 0x7291, 1317 0x7293, 1318 0x7297, 1319 0x7834, 1320 0x7835, 1321 0x791e, 1322 0x791f, 1323 0x793f, 1324 0x7941, 1325 0x7942, 1326 0x796c, 1327 0x796d, 1328 0x796e, 1329 0x796f, 1330 0x9400, 1331 0x9401, 1332 0x9402, 1333 0x9403, 1334 0x9405, 1335 0x940A, 1336 0x940B, 1337 0x940F, 1338 0x94A0, 1339 0x94A1, 1340 0x94A3, 1341 0x94B1, 1342 0x94B3, 1343 0x94B4, 1344 0x94B5, 1345 0x94B9, 1346 0x9440, 1347 0x9441, 1348 0x9442, 1349 0x9443, 1350 0x9444, 1351 0x9446, 1352 0x944A, 1353 0x944B, 1354 0x944C, 1355 0x944E, 1356 0x9450, 1357 0x9452, 1358 0x9456, 1359 0x945A, 1360 0x945B, 1361 0x945E, 1362 0x9460, 1363 0x9462, 1364 0x946A, 1365 0x946B, 1366 0x947A, 1367 0x947B, 1368 0x9480, 1369 0x9487, 1370 0x9488, 1371 0x9489, 1372 0x948A, 1373 0x948F, 1374 0x9490, 1375 0x9491, 1376 0x9495, 1377 0x9498, 1378 0x949C, 1379 0x949E, 1380 0x949F, 1381 0x94C0, 1382 0x94C1, 1383 0x94C3, 1384 0x94C4, 1385 0x94C5, 1386 0x94C6, 1387 0x94C7, 1388 0x94C8, 1389 0x94C9, 1390 0x94CB, 1391 0x94CC, 1392 0x94CD, 1393 0x9500, 1394 0x9501, 1395 0x9504, 1396 0x9505, 1397 0x9506, 1398 0x9507, 1399 0x9508, 1400 0x9509, 1401 0x950F, 1402 0x9511, 1403 0x9515, 1404 0x9517, 1405 0x9519, 1406 0x9540, 1407 0x9541, 1408 0x9542, 1409 0x954E, 1410 0x954F, 1411 0x9552, 1412 0x9553, 1413 0x9555, 1414 0x9557, 1415 0x955f, 1416 0x9580, 1417 0x9581, 1418 0x9583, 1419 0x9586, 1420 0x9587, 1421 0x9588, 1422 0x9589, 1423 0x958A, 1424 0x958B, 1425 0x958C, 1426 0x958D, 1427 0x958E, 1428 0x958F, 1429 0x9590, 1430 0x9591, 1431 0x9593, 1432 0x9595, 1433 0x9596, 1434 0x9597, 1435 0x9598, 1436 0x9599, 1437 0x959B, 1438 0x95C0, 1439 0x95C2, 1440 0x95C4, 1441 0x95C5, 1442 0x95C6, 1443 0x95C7, 1444 0x95C9, 1445 0x95CC, 1446 0x95CD, 1447 0x95CE, 1448 0x95CF, 1449 0x9610, 1450 0x9611, 1451 0x9612, 1452 0x9613, 1453 0x9614, 1454 0x9615, 1455 0x9616, 1456 0x9640, 1457 0x9641, 1458 0x9642, 1459 0x9643, 1460 0x9644, 1461 0x9645, 1462 0x9647, 1463 0x9648, 1464 0x9649, 1465 0x964a, 1466 0x964b, 1467 0x964c, 1468 0x964e, 1469 0x964f, 1470 0x9710, 1471 0x9711, 1472 0x9712, 1473 0x9713, 1474 0x9714, 1475 0x9715, 1476 0x9802, 1477 0x9803, 1478 0x9804, 1479 0x9805, 1480 0x9806, 1481 0x9807, 1482 0x9808, 1483 0x9809, 1484 0x980A, 1485 0x9900, 1486 0x9901, 1487 0x9903, 1488 0x9904, 1489 0x9905, 1490 0x9906, 1491 0x9907, 1492 0x9908, 1493 0x9909, 1494 0x990A, 1495 0x990B, 1496 0x990C, 1497 0x990D, 1498 0x990E, 1499 0x990F, 1500 0x9910, 1501 0x9913, 1502 0x9917, 1503 0x9918, 1504 0x9919, 1505 0x9990, 1506 0x9991, 1507 0x9992, 1508 0x9993, 1509 0x9994, 1510 0x9995, 1511 0x9996, 1512 0x9997, 1513 0x9998, 1514 0x9999, 1515 0x999A, 1516 0x999B, 1517 0x999C, 1518 0x999D, 1519 0x99A0, 1520 0x99A2, 1521 0x99A4, 1522 /* radeon secondary ids */ 1523 0x3171, 1524 0x3e70, 1525 0x4164, 1526 0x4165, 1527 0x4166, 1528 0x4168, 1529 0x4170, 1530 0x4171, 1531 0x4172, 1532 0x4173, 1533 0x496e, 1534 0x4a69, 1535 0x4a6a, 1536 0x4a6b, 1537 0x4a70, 1538 0x4a74, 1539 0x4b69, 1540 0x4b6b, 1541 0x4b6c, 1542 0x4c6e, 1543 0x4e64, 1544 0x4e65, 1545 0x4e66, 1546 0x4e67, 1547 0x4e68, 1548 0x4e69, 1549 0x4e6a, 1550 0x4e71, 1551 0x4f73, 1552 0x5569, 1553 0x556b, 1554 0x556d, 1555 0x556f, 1556 0x5571, 1557 0x5854, 1558 0x5874, 1559 0x5940, 1560 0x5941, 1561 0x5b72, 1562 0x5b73, 1563 0x5b74, 1564 0x5b75, 1565 0x5d44, 1566 0x5d45, 1567 0x5d6d, 1568 0x5d6f, 1569 0x5d72, 1570 0x5d77, 1571 0x5e6b, 1572 0x5e6d, 1573 0x7120, 1574 0x7124, 1575 0x7129, 1576 0x712e, 1577 0x712f, 1578 0x7162, 1579 0x7163, 1580 0x7166, 1581 0x7167, 1582 0x7172, 1583 0x7173, 1584 0x71a0, 1585 0x71a1, 1586 0x71a3, 1587 0x71a7, 1588 0x71bb, 1589 0x71e0, 1590 0x71e1, 1591 0x71e2, 1592 0x71e6, 1593 0x71e7, 1594 0x71f2, 1595 0x7269, 1596 0x726b, 1597 0x726e, 1598 0x72a0, 1599 0x72a8, 1600 0x72b1, 1601 0x72b3, 1602 0x793f, 1603 }; 1604 1605 const struct pci_device_id amdgpu_pciidlist[] = { 1606 #ifdef CONFIG_DRM_AMDGPU_SI 1607 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1608 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1609 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1610 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1611 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1612 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1613 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1614 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1615 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1616 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1617 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1618 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1619 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1620 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1621 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1622 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1623 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1624 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1625 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1626 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1627 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1628 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1629 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1630 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1631 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1632 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1633 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1634 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1635 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1636 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1637 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1638 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1639 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1640 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1641 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1642 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1643 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1644 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1645 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1646 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1647 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1648 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1649 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1650 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1651 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1652 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1653 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1654 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1655 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1656 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1657 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1658 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1659 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1660 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1661 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1662 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1663 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1664 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1665 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1666 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1667 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1668 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1669 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1670 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1671 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1672 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1673 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1674 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1675 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1676 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1677 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1678 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1679 #endif 1680 #ifdef CONFIG_DRM_AMDGPU_CIK 1681 /* Kaveri */ 1682 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1683 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1684 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1685 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1686 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1687 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1688 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1689 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1690 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1691 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1692 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1693 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1694 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1695 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1696 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1697 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1698 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1699 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1700 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1701 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1702 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1703 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1704 /* Bonaire */ 1705 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1706 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1707 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1708 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1709 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1710 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1711 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1712 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1713 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1714 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1715 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1716 /* Hawaii */ 1717 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1718 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1719 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1720 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1721 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1722 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1723 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1724 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1725 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1726 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1727 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1728 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1729 /* Kabini */ 1730 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1731 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1732 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1733 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1734 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1735 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1736 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1737 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1738 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1739 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1740 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1741 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1742 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1743 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1744 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1745 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1746 /* mullins */ 1747 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1748 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1749 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1750 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1751 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1752 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1753 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1754 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1755 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1756 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1757 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1758 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1759 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1760 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1761 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1762 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1763 #endif 1764 /* topaz */ 1765 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1766 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1767 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1768 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1769 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1770 /* tonga */ 1771 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1772 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1773 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1774 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1775 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1776 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1777 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1778 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1779 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1780 /* fiji */ 1781 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1782 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1783 /* carrizo */ 1784 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1785 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1786 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1787 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1788 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1789 /* stoney */ 1790 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1791 /* Polaris11 */ 1792 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1793 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1794 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1795 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1796 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1797 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1798 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1799 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1800 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1801 /* Polaris10 */ 1802 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1803 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1804 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1805 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1806 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1807 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1808 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1809 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1810 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1811 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1812 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1813 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1814 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1815 /* Polaris12 */ 1816 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1817 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1818 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1819 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1820 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1821 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1822 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1823 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1824 /* VEGAM */ 1825 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1826 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1827 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1828 /* Vega 10 */ 1829 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1830 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1831 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1832 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1833 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1834 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1835 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1836 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1837 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1838 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1839 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1840 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1841 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1842 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1843 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1844 /* Vega 12 */ 1845 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1846 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1847 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1848 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1849 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1850 /* Vega 20 */ 1851 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1852 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1853 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1854 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1855 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1856 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1857 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1858 /* Raven */ 1859 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1860 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1861 /* Arcturus */ 1862 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1863 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1864 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1865 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1866 /* Navi10 */ 1867 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1868 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1869 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1870 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1871 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1872 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1873 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1874 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1875 /* Navi14 */ 1876 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1877 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1878 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1879 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1880 1881 /* Renoir */ 1882 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1883 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1884 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1885 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1886 1887 /* Navi12 */ 1888 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1889 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1890 1891 /* Sienna_Cichlid */ 1892 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1893 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1894 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1895 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1896 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1897 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1898 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1899 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1900 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1901 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1902 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1903 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1904 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1905 1906 /* Van Gogh */ 1907 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1908 1909 /* Yellow Carp */ 1910 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1911 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1912 1913 /* Navy_Flounder */ 1914 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1915 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1916 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1917 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1918 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1919 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1920 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1921 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1922 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1923 1924 /* DIMGREY_CAVEFISH */ 1925 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1926 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1927 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1928 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1929 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1930 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1931 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1932 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1933 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1934 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1935 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1936 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1937 1938 /* Aldebaran */ 1939 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1940 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1941 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1942 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT}, 1943 1944 /* CYAN_SKILLFISH */ 1945 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 1946 1947 /* BEIGE_GOBY */ 1948 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1949 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1950 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1951 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1952 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 1953 1954 {0, 0, 0} 1955 }; 1956 1957 MODULE_DEVICE_TABLE(pci, pciidlist); 1958 1959 const struct drm_driver amdgpu_kms_driver; 1960 1961 static bool amdgpu_is_fw_framebuffer(resource_size_t base, 1962 resource_size_t size) 1963 { 1964 bool found = false; 1965 #if IS_REACHABLE(CONFIG_FB) 1966 struct apertures_struct *a; 1967 1968 a = alloc_apertures(1); 1969 if (!a) 1970 return false; 1971 1972 a->ranges[0].base = base; 1973 a->ranges[0].size = size; 1974 1975 found = is_firmware_framebuffer(a); 1976 kfree(a); 1977 #endif 1978 return found; 1979 } 1980 1981 #ifdef notyet 1982 static int amdgpu_pci_probe(struct pci_dev *pdev, 1983 const struct pci_device_id *ent) 1984 { 1985 struct drm_device *ddev; 1986 struct amdgpu_device *adev; 1987 unsigned long flags = ent->driver_data; 1988 int ret, retry = 0, i; 1989 bool supports_atomic = false; 1990 bool is_fw_fb; 1991 resource_size_t base, size; 1992 1993 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 1994 amdgpu_aspm = 0; 1995 1996 /* skip devices which are owned by radeon */ 1997 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 1998 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 1999 return -ENODEV; 2000 } 2001 2002 if (amdgpu_virtual_display || 2003 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2004 supports_atomic = true; 2005 2006 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2007 DRM_INFO("This hardware requires experimental hardware support.\n" 2008 "See modparam exp_hw_support\n"); 2009 return -ENODEV; 2010 } 2011 2012 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2013 * however, SME requires an indirect IOMMU mapping because the encryption 2014 * bit is beyond the DMA mask of the chip. 2015 */ 2016 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2017 dev_info(&pdev->dev, 2018 "SME is not compatible with RAVEN\n"); 2019 return -ENOTSUPP; 2020 } 2021 2022 #ifdef CONFIG_DRM_AMDGPU_SI 2023 if (!amdgpu_si_support) { 2024 switch (flags & AMD_ASIC_MASK) { 2025 case CHIP_TAHITI: 2026 case CHIP_PITCAIRN: 2027 case CHIP_VERDE: 2028 case CHIP_OLAND: 2029 case CHIP_HAINAN: 2030 dev_info(&pdev->dev, 2031 "SI support provided by radeon.\n"); 2032 dev_info(&pdev->dev, 2033 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2034 ); 2035 return -ENODEV; 2036 } 2037 } 2038 #endif 2039 #ifdef CONFIG_DRM_AMDGPU_CIK 2040 if (!amdgpu_cik_support) { 2041 switch (flags & AMD_ASIC_MASK) { 2042 case CHIP_KAVERI: 2043 case CHIP_BONAIRE: 2044 case CHIP_HAWAII: 2045 case CHIP_KABINI: 2046 case CHIP_MULLINS: 2047 dev_info(&pdev->dev, 2048 "CIK support provided by radeon.\n"); 2049 dev_info(&pdev->dev, 2050 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2051 ); 2052 return -ENODEV; 2053 } 2054 } 2055 #endif 2056 2057 base = pci_resource_start(pdev, 0); 2058 size = pci_resource_len(pdev, 0); 2059 is_fw_fb = amdgpu_is_fw_framebuffer(base, size); 2060 2061 /* Get rid of things like offb */ 2062 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver); 2063 if (ret) 2064 return ret; 2065 2066 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2067 if (IS_ERR(adev)) 2068 return PTR_ERR(adev); 2069 2070 adev->dev = &pdev->dev; 2071 adev->pdev = pdev; 2072 ddev = adev_to_drm(adev); 2073 adev->is_fw_fb = is_fw_fb; 2074 2075 if (!supports_atomic) 2076 ddev->driver_features &= ~DRIVER_ATOMIC; 2077 2078 ret = pci_enable_device(pdev); 2079 if (ret) 2080 return ret; 2081 2082 pci_set_drvdata(pdev, ddev); 2083 2084 ret = amdgpu_driver_load_kms(adev, ent->driver_data); 2085 if (ret) 2086 goto err_pci; 2087 2088 retry_init: 2089 ret = drm_dev_register(ddev, ent->driver_data); 2090 if (ret == -EAGAIN && ++retry <= 3) { 2091 DRM_INFO("retry init %d\n", retry); 2092 /* Don't request EX mode too frequently which is attacking */ 2093 drm_msleep(5000); 2094 goto retry_init; 2095 } else if (ret) { 2096 goto err_pci; 2097 } 2098 2099 ret = amdgpu_debugfs_init(adev); 2100 if (ret) 2101 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2102 2103 return 0; 2104 2105 err_pci: 2106 pci_disable_device(pdev); 2107 return ret; 2108 } 2109 2110 static void 2111 amdgpu_pci_remove(struct pci_dev *pdev) 2112 { 2113 struct drm_device *dev = pci_get_drvdata(pdev); 2114 2115 drm_dev_unplug(dev); 2116 amdgpu_driver_unload_kms(dev); 2117 2118 /* 2119 * Flush any in flight DMA operations from device. 2120 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2121 * StatusTransactions Pending bit. 2122 */ 2123 pci_disable_device(pdev); 2124 pci_wait_for_pending_transaction(pdev); 2125 } 2126 2127 static void 2128 amdgpu_pci_shutdown(struct pci_dev *pdev) 2129 { 2130 struct drm_device *dev = pci_get_drvdata(pdev); 2131 struct amdgpu_device *adev = drm_to_adev(dev); 2132 2133 if (amdgpu_ras_intr_triggered()) 2134 return; 2135 2136 /* if we are running in a VM, make sure the device 2137 * torn down properly on reboot/shutdown. 2138 * unfortunately we can't detect certain 2139 * hypervisors so just do this all the time. 2140 */ 2141 if (!amdgpu_passthrough(adev)) 2142 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2143 amdgpu_device_ip_suspend(adev); 2144 adev->mp1_state = PP_MP1_STATE_NONE; 2145 } 2146 #endif 2147 2148 /** 2149 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2150 * 2151 * @work: work_struct. 2152 */ 2153 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2154 { 2155 struct list_head device_list; 2156 struct amdgpu_device *adev; 2157 int i, r; 2158 struct amdgpu_reset_context reset_context; 2159 2160 memset(&reset_context, 0, sizeof(reset_context)); 2161 2162 mutex_lock(&mgpu_info.mutex); 2163 if (mgpu_info.pending_reset == true) { 2164 mutex_unlock(&mgpu_info.mutex); 2165 return; 2166 } 2167 mgpu_info.pending_reset = true; 2168 mutex_unlock(&mgpu_info.mutex); 2169 2170 /* Use a common context, just need to make sure full reset is done */ 2171 reset_context.method = AMD_RESET_METHOD_NONE; 2172 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2173 2174 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2175 adev = mgpu_info.gpu_ins[i].adev; 2176 reset_context.reset_req_dev = adev; 2177 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2178 if (r) { 2179 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2180 r, adev_to_drm(adev)->unique); 2181 } 2182 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2183 r = -EALREADY; 2184 } 2185 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2186 adev = mgpu_info.gpu_ins[i].adev; 2187 flush_work(&adev->xgmi_reset_work); 2188 adev->gmc.xgmi.pending_reset = false; 2189 } 2190 2191 /* reset function will rebuild the xgmi hive info , clear it now */ 2192 for (i = 0; i < mgpu_info.num_dgpu; i++) 2193 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2194 2195 INIT_LIST_HEAD(&device_list); 2196 2197 for (i = 0; i < mgpu_info.num_dgpu; i++) 2198 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2199 2200 /* unregister the GPU first, reset function will add them back */ 2201 list_for_each_entry(adev, &device_list, reset_list) 2202 amdgpu_unregister_gpu_instance(adev); 2203 2204 /* Use a common context, just need to make sure full reset is done */ 2205 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2206 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2207 2208 if (r) { 2209 DRM_ERROR("reinit gpus failure"); 2210 return; 2211 } 2212 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2213 adev = mgpu_info.gpu_ins[i].adev; 2214 if (!adev->kfd.init_complete) 2215 amdgpu_amdkfd_device_init(adev); 2216 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2217 } 2218 return; 2219 } 2220 2221 #ifdef notyet 2222 2223 static int amdgpu_pmops_prepare(struct device *dev) 2224 { 2225 struct drm_device *drm_dev = dev_get_drvdata(dev); 2226 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2227 2228 /* Return a positive number here so 2229 * DPM_FLAG_SMART_SUSPEND works properly 2230 */ 2231 if (amdgpu_device_supports_boco(drm_dev)) 2232 return pm_runtime_suspended(dev); 2233 2234 /* if we will not support s3 or s2i for the device 2235 * then skip suspend 2236 */ 2237 if (!amdgpu_acpi_is_s0ix_active(adev) && 2238 !amdgpu_acpi_is_s3_active(adev)) 2239 return 1; 2240 2241 return 0; 2242 } 2243 2244 static void amdgpu_pmops_complete(struct device *dev) 2245 { 2246 /* nothing to do */ 2247 } 2248 2249 static int amdgpu_pmops_suspend(struct device *dev) 2250 { 2251 struct drm_device *drm_dev = dev_get_drvdata(dev); 2252 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2253 int r; 2254 2255 if (amdgpu_acpi_is_s0ix_active(adev)) 2256 adev->in_s0ix = true; 2257 adev->in_s3 = true; 2258 r = amdgpu_device_suspend(drm_dev, true); 2259 adev->in_s3 = false; 2260 if (r) 2261 return r; 2262 if (!adev->in_s0ix) 2263 r = amdgpu_asic_reset(adev); 2264 return r; 2265 } 2266 2267 static int amdgpu_pmops_resume(struct device *dev) 2268 { 2269 struct drm_device *drm_dev = dev_get_drvdata(dev); 2270 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2271 int r; 2272 2273 r = amdgpu_device_resume(drm_dev, true); 2274 if (amdgpu_acpi_is_s0ix_active(adev)) 2275 adev->in_s0ix = false; 2276 return r; 2277 } 2278 2279 static int amdgpu_pmops_freeze(struct device *dev) 2280 { 2281 struct drm_device *drm_dev = dev_get_drvdata(dev); 2282 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2283 int r; 2284 2285 adev->in_s4 = true; 2286 r = amdgpu_device_suspend(drm_dev, true); 2287 adev->in_s4 = false; 2288 if (r) 2289 return r; 2290 return amdgpu_asic_reset(adev); 2291 } 2292 2293 static int amdgpu_pmops_thaw(struct device *dev) 2294 { 2295 struct drm_device *drm_dev = dev_get_drvdata(dev); 2296 2297 return amdgpu_device_resume(drm_dev, true); 2298 } 2299 2300 static int amdgpu_pmops_poweroff(struct device *dev) 2301 { 2302 struct drm_device *drm_dev = dev_get_drvdata(dev); 2303 2304 return amdgpu_device_suspend(drm_dev, true); 2305 } 2306 2307 static int amdgpu_pmops_restore(struct device *dev) 2308 { 2309 struct drm_device *drm_dev = dev_get_drvdata(dev); 2310 2311 return amdgpu_device_resume(drm_dev, true); 2312 } 2313 2314 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2315 { 2316 struct pci_dev *pdev = to_pci_dev(dev); 2317 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2318 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2319 int ret, i; 2320 2321 if (!adev->runpm) { 2322 pm_runtime_forbid(dev); 2323 return -EBUSY; 2324 } 2325 2326 /* wait for all rings to drain before suspending */ 2327 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2328 struct amdgpu_ring *ring = adev->rings[i]; 2329 if (ring && ring->sched.ready) { 2330 ret = amdgpu_fence_wait_empty(ring); 2331 if (ret) 2332 return -EBUSY; 2333 } 2334 } 2335 2336 adev->in_runpm = true; 2337 if (amdgpu_device_supports_px(drm_dev)) 2338 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2339 2340 /* 2341 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2342 * proper cleanups and put itself into a state ready for PNP. That 2343 * can address some random resuming failure observed on BOCO capable 2344 * platforms. 2345 * TODO: this may be also needed for PX capable platform. 2346 */ 2347 if (amdgpu_device_supports_boco(drm_dev)) 2348 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2349 2350 ret = amdgpu_device_suspend(drm_dev, false); 2351 if (ret) { 2352 adev->in_runpm = false; 2353 if (amdgpu_device_supports_boco(drm_dev)) 2354 adev->mp1_state = PP_MP1_STATE_NONE; 2355 return ret; 2356 } 2357 2358 if (amdgpu_device_supports_boco(drm_dev)) 2359 adev->mp1_state = PP_MP1_STATE_NONE; 2360 2361 if (amdgpu_device_supports_px(drm_dev)) { 2362 /* Only need to handle PCI state in the driver for ATPX 2363 * PCI core handles it for _PR3. 2364 */ 2365 amdgpu_device_cache_pci_state(pdev); 2366 pci_disable_device(pdev); 2367 pci_ignore_hotplug(pdev); 2368 pci_set_power_state(pdev, PCI_D3cold); 2369 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2370 } else if (amdgpu_device_supports_boco(drm_dev)) { 2371 /* nothing to do */ 2372 } else if (amdgpu_device_supports_baco(drm_dev)) { 2373 amdgpu_device_baco_enter(drm_dev); 2374 } 2375 2376 return 0; 2377 } 2378 2379 static int amdgpu_pmops_runtime_resume(struct device *dev) 2380 { 2381 struct pci_dev *pdev = to_pci_dev(dev); 2382 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2383 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2384 int ret; 2385 2386 if (!adev->runpm) 2387 return -EINVAL; 2388 2389 /* Avoids registers access if device is physically gone */ 2390 if (!pci_device_is_present(adev->pdev)) 2391 adev->no_hw_access = true; 2392 2393 if (amdgpu_device_supports_px(drm_dev)) { 2394 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2395 2396 /* Only need to handle PCI state in the driver for ATPX 2397 * PCI core handles it for _PR3. 2398 */ 2399 pci_set_power_state(pdev, PCI_D0); 2400 amdgpu_device_load_pci_state(pdev); 2401 ret = pci_enable_device(pdev); 2402 if (ret) 2403 return ret; 2404 pci_set_master(pdev); 2405 } else if (amdgpu_device_supports_boco(drm_dev)) { 2406 /* Only need to handle PCI state in the driver for ATPX 2407 * PCI core handles it for _PR3. 2408 */ 2409 pci_set_master(pdev); 2410 } else if (amdgpu_device_supports_baco(drm_dev)) { 2411 amdgpu_device_baco_exit(drm_dev); 2412 } 2413 ret = amdgpu_device_resume(drm_dev, false); 2414 if (ret) 2415 return ret; 2416 2417 if (amdgpu_device_supports_px(drm_dev)) 2418 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2419 adev->in_runpm = false; 2420 return 0; 2421 } 2422 2423 static int amdgpu_pmops_runtime_idle(struct device *dev) 2424 { 2425 struct drm_device *drm_dev = dev_get_drvdata(dev); 2426 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2427 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2428 int ret = 1; 2429 2430 if (!adev->runpm) { 2431 pm_runtime_forbid(dev); 2432 return -EBUSY; 2433 } 2434 2435 if (amdgpu_device_has_dc_support(adev)) { 2436 struct drm_crtc *crtc; 2437 2438 drm_for_each_crtc(crtc, drm_dev) { 2439 drm_modeset_lock(&crtc->mutex, NULL); 2440 if (crtc->state->active) 2441 ret = -EBUSY; 2442 drm_modeset_unlock(&crtc->mutex); 2443 if (ret < 0) 2444 break; 2445 } 2446 2447 } else { 2448 struct drm_connector *list_connector; 2449 struct drm_connector_list_iter iter; 2450 2451 mutex_lock(&drm_dev->mode_config.mutex); 2452 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2453 2454 drm_connector_list_iter_begin(drm_dev, &iter); 2455 drm_for_each_connector_iter(list_connector, &iter) { 2456 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2457 ret = -EBUSY; 2458 break; 2459 } 2460 } 2461 2462 drm_connector_list_iter_end(&iter); 2463 2464 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2465 mutex_unlock(&drm_dev->mode_config.mutex); 2466 } 2467 2468 if (ret == -EBUSY) 2469 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 2470 2471 pm_runtime_mark_last_busy(dev); 2472 pm_runtime_autosuspend(dev); 2473 return ret; 2474 } 2475 #endif /* notyet */ 2476 2477 #ifdef __linux__ 2478 long amdgpu_drm_ioctl(struct file *filp, 2479 unsigned int cmd, unsigned long arg) 2480 { 2481 struct drm_file *file_priv = filp->private_data; 2482 struct drm_device *dev; 2483 long ret; 2484 dev = file_priv->minor->dev; 2485 ret = pm_runtime_get_sync(dev->dev); 2486 if (ret < 0) 2487 goto out; 2488 2489 ret = drm_ioctl(filp, cmd, arg); 2490 2491 pm_runtime_mark_last_busy(dev->dev); 2492 out: 2493 pm_runtime_put_autosuspend(dev->dev); 2494 return ret; 2495 } 2496 2497 static const struct dev_pm_ops amdgpu_pm_ops = { 2498 .prepare = amdgpu_pmops_prepare, 2499 .complete = amdgpu_pmops_complete, 2500 .suspend = amdgpu_pmops_suspend, 2501 .resume = amdgpu_pmops_resume, 2502 .freeze = amdgpu_pmops_freeze, 2503 .thaw = amdgpu_pmops_thaw, 2504 .poweroff = amdgpu_pmops_poweroff, 2505 .restore = amdgpu_pmops_restore, 2506 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2507 .runtime_resume = amdgpu_pmops_runtime_resume, 2508 .runtime_idle = amdgpu_pmops_runtime_idle, 2509 }; 2510 2511 static int amdgpu_flush(struct file *f, fl_owner_t id) 2512 { 2513 struct drm_file *file_priv = f->private_data; 2514 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2515 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2516 2517 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2518 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2519 2520 return timeout >= 0 ? 0 : timeout; 2521 } 2522 2523 static const struct file_operations amdgpu_driver_kms_fops = { 2524 .owner = THIS_MODULE, 2525 .open = drm_open, 2526 .flush = amdgpu_flush, 2527 .release = drm_release, 2528 .unlocked_ioctl = amdgpu_drm_ioctl, 2529 .mmap = drm_gem_mmap, 2530 .poll = drm_poll, 2531 .read = drm_read, 2532 #ifdef CONFIG_COMPAT 2533 .compat_ioctl = amdgpu_kms_compat_ioctl, 2534 #endif 2535 #ifdef CONFIG_PROC_FS 2536 .show_fdinfo = amdgpu_show_fdinfo 2537 #endif 2538 }; 2539 2540 #endif /* __linux__ */ 2541 2542 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2543 { 2544 STUB(); 2545 return -ENOSYS; 2546 #ifdef notyet 2547 struct drm_file *file; 2548 2549 if (!filp) 2550 return -EINVAL; 2551 2552 if (filp->f_op != &amdgpu_driver_kms_fops) { 2553 return -EINVAL; 2554 } 2555 2556 file = filp->private_data; 2557 *fpriv = file->driver_priv; 2558 return 0; 2559 #endif 2560 } 2561 2562 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2563 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2564 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2565 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2566 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2567 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2568 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2569 /* KMS */ 2570 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2571 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2572 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2573 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2574 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2575 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2576 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2577 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2578 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2579 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2580 }; 2581 2582 const struct drm_driver amdgpu_kms_driver = { 2583 .driver_features = 2584 DRIVER_ATOMIC | 2585 DRIVER_GEM | 2586 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2587 DRIVER_SYNCOBJ_TIMELINE, 2588 .open = amdgpu_driver_open_kms, 2589 #ifdef __OpenBSD__ 2590 .mmap = drm_gem_mmap, 2591 #endif 2592 .postclose = amdgpu_driver_postclose_kms, 2593 .lastclose = amdgpu_driver_lastclose_kms, 2594 .ioctls = amdgpu_ioctls_kms, 2595 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2596 .dumb_create = amdgpu_mode_dumb_create, 2597 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2598 #ifdef __linux__ 2599 .fops = &amdgpu_driver_kms_fops, 2600 #endif 2601 .release = &amdgpu_driver_release_kms, 2602 2603 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2604 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2605 .gem_prime_import = amdgpu_gem_prime_import, 2606 #ifdef notyet 2607 .gem_prime_mmap = drm_gem_prime_mmap, 2608 #endif 2609 2610 .name = DRIVER_NAME, 2611 .desc = DRIVER_DESC, 2612 .date = DRIVER_DATE, 2613 .major = KMS_DRIVER_MAJOR, 2614 .minor = KMS_DRIVER_MINOR, 2615 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2616 }; 2617 2618 #ifdef __linux__ 2619 static struct pci_error_handlers amdgpu_pci_err_handler = { 2620 .error_detected = amdgpu_pci_error_detected, 2621 .mmio_enabled = amdgpu_pci_mmio_enabled, 2622 .slot_reset = amdgpu_pci_slot_reset, 2623 .resume = amdgpu_pci_resume, 2624 }; 2625 2626 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2627 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2628 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2629 2630 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2631 &amdgpu_vram_mgr_attr_group, 2632 &amdgpu_gtt_mgr_attr_group, 2633 &amdgpu_vbios_version_attr_group, 2634 NULL, 2635 }; 2636 2637 2638 static struct pci_driver amdgpu_kms_pci_driver = { 2639 .name = DRIVER_NAME, 2640 .id_table = pciidlist, 2641 .probe = amdgpu_pci_probe, 2642 .remove = amdgpu_pci_remove, 2643 .shutdown = amdgpu_pci_shutdown, 2644 .driver.pm = &amdgpu_pm_ops, 2645 .err_handler = &amdgpu_pci_err_handler, 2646 .dev_groups = amdgpu_sysfs_groups, 2647 }; 2648 2649 static int __init amdgpu_init(void) 2650 { 2651 int r; 2652 2653 if (vgacon_text_force()) { 2654 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 2655 return -EINVAL; 2656 } 2657 2658 r = amdgpu_sync_init(); 2659 if (r) 2660 goto error_sync; 2661 2662 r = amdgpu_fence_slab_init(); 2663 if (r) 2664 goto error_fence; 2665 2666 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2667 amdgpu_register_atpx_handler(); 2668 amdgpu_acpi_detect(); 2669 2670 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2671 amdgpu_amdkfd_init(); 2672 2673 /* let modprobe override vga console setting */ 2674 return pci_register_driver(&amdgpu_kms_pci_driver); 2675 2676 error_fence: 2677 amdgpu_sync_fini(); 2678 2679 error_sync: 2680 return r; 2681 } 2682 2683 static void __exit amdgpu_exit(void) 2684 { 2685 amdgpu_amdkfd_fini(); 2686 pci_unregister_driver(&amdgpu_kms_pci_driver); 2687 amdgpu_unregister_atpx_handler(); 2688 amdgpu_sync_fini(); 2689 amdgpu_fence_slab_fini(); 2690 mmu_notifier_synchronize(); 2691 } 2692 2693 module_init(amdgpu_init); 2694 module_exit(amdgpu_exit); 2695 2696 MODULE_AUTHOR(DRIVER_AUTHOR); 2697 MODULE_DESCRIPTION(DRIVER_DESC); 2698 MODULE_LICENSE("GPL and additional rights"); 2699 #endif /* __linux__ */ 2700