1 /* 2 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #include <drm/amdgpu_drm.h> 26 #include <drm/drm_drv.h> 27 #include <drm/drm_gem.h> 28 #include <drm/drm_vblank.h> 29 #include <drm/drm_managed.h> 30 #include "amdgpu_drv.h" 31 32 #include <drm/drm_pciids.h> 33 #include <linux/module.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/vga_switcheroo.h> 36 #include <drm/drm_probe_helper.h> 37 #include <linux/mmu_notifier.h> 38 #include <linux/suspend.h> 39 #include <linux/cc_platform.h> 40 #include <linux/fb.h> 41 #include <linux/dynamic_debug.h> 42 43 #include "amdgpu.h" 44 #include "amdgpu_irq.h" 45 #include "amdgpu_dma_buf.h" 46 #include "amdgpu_sched.h" 47 #include "amdgpu_fdinfo.h" 48 #include "amdgpu_amdkfd.h" 49 50 #include "amdgpu_ras.h" 51 #include "amdgpu_xgmi.h" 52 #include "amdgpu_reset.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 59 * at the end of IBs. 60 * - 3.3.0 - Add VM support for UVD on supported hardware. 61 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 62 * - 3.5.0 - Add support for new UVD_NO_OP register. 63 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 64 * - 3.7.0 - Add support for VCE clock list packet 65 * - 3.8.0 - Add support raster config init in the kernel 66 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 67 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 68 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 69 * - 3.12.0 - Add query for double offchip LDS buffers 70 * - 3.13.0 - Add PRT support 71 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 72 * - 3.15.0 - Export more gpu info for gfx9 73 * - 3.16.0 - Add reserved vmid support 74 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 75 * - 3.18.0 - Export gpu always on cu bitmap 76 * - 3.19.0 - Add support for UVD MJPEG decode 77 * - 3.20.0 - Add support for local BOs 78 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 79 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 80 * - 3.23.0 - Add query for VRAM lost counter 81 * - 3.24.0 - Add high priority compute support for gfx9 82 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 83 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 84 * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. 85 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 86 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 87 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 88 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 89 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 90 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 91 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 92 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 93 * - 3.36.0 - Allow reading more status registers on si/cik 94 * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness 95 * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC 96 * - 3.39.0 - DMABUF implicit sync does a full pipeline sync 97 * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ 98 * - 3.41.0 - Add video codec query 99 * - 3.42.0 - Add 16bpc fixed point display support 100 * - 3.43.0 - Add device hot plug/unplug support 101 * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B 102 * - 3.45.0 - Add context ioctl stable pstate interface 103 * - 3.46.0 - To enable hot plug amdgpu tests in libdrm 104 * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags 105 * - 3.48.0 - Add IP discovery version info to HW INFO 106 * 3.49.0 - Add gang submit into CS IOCTL 107 */ 108 #define KMS_DRIVER_MAJOR 3 109 #define KMS_DRIVER_MINOR 49 110 #define KMS_DRIVER_PATCHLEVEL 0 111 112 int amdgpu_vram_limit; 113 int amdgpu_vis_vram_limit; 114 int amdgpu_gart_size = -1; /* auto */ 115 int amdgpu_gtt_size = -1; /* auto */ 116 int amdgpu_moverate = -1; /* auto */ 117 int amdgpu_audio = -1; 118 int amdgpu_disp_priority; 119 int amdgpu_hw_i2c; 120 int amdgpu_pcie_gen2 = -1; 121 int amdgpu_msi = -1; 122 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 123 int amdgpu_dpm = -1; 124 int amdgpu_fw_load_type = -1; 125 int amdgpu_aspm = -1; 126 int amdgpu_runtime_pm = -1; 127 uint amdgpu_ip_block_mask = 0xffffffff; 128 int amdgpu_bapm = -1; 129 int amdgpu_deep_color; 130 int amdgpu_vm_size = -1; 131 int amdgpu_vm_fragment_size = -1; 132 int amdgpu_vm_block_size = -1; 133 int amdgpu_vm_fault_stop; 134 int amdgpu_vm_debug; 135 int amdgpu_vm_update_mode = -1; 136 int amdgpu_exp_hw_support; 137 int amdgpu_dc = -1; 138 int amdgpu_sched_jobs = 32; 139 int amdgpu_sched_hw_submission = 2; 140 uint amdgpu_pcie_gen_cap; 141 uint amdgpu_pcie_lane_cap; 142 u64 amdgpu_cg_mask = 0xffffffffffffffff; 143 uint amdgpu_pg_mask = 0xffffffff; 144 uint amdgpu_sdma_phase_quantum = 32; 145 char *amdgpu_disable_cu = NULL; 146 char *amdgpu_virtual_display = NULL; 147 148 /* 149 * OverDrive(bit 14) disabled by default 150 * GFX DCS(bit 19) disabled by default 151 */ 152 uint amdgpu_pp_feature_mask = 0xfff7bfff; 153 uint amdgpu_force_long_training; 154 int amdgpu_job_hang_limit; 155 int amdgpu_lbpw = -1; 156 int amdgpu_compute_multipipe = -1; 157 int amdgpu_gpu_recovery = -1; /* auto */ 158 int amdgpu_emu_mode; 159 uint amdgpu_smu_memory_pool_size; 160 int amdgpu_smu_pptable_id = -1; 161 /* 162 * FBC (bit 0) disabled by default 163 * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default 164 * - With this, for multiple monitors in sync(e.g. with the same model), 165 * mclk switching will be allowed. And the mclk will be not foced to the 166 * highest. That helps saving some idle power. 167 * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default 168 * PSR (bit 3) disabled by default 169 * EDP NO POWER SEQUENCING (bit 4) disabled by default 170 */ 171 uint amdgpu_dc_feature_mask = 2; 172 uint amdgpu_dc_debug_mask; 173 uint amdgpu_dc_visual_confirm; 174 int amdgpu_async_gfx_ring = 1; 175 int amdgpu_mcbp; 176 int amdgpu_discovery = -1; 177 int amdgpu_mes; 178 int amdgpu_mes_kiq; 179 int amdgpu_noretry = -1; 180 int amdgpu_force_asic_type = -1; 181 int amdgpu_tmz = -1; /* auto */ 182 uint amdgpu_freesync_vid_mode; 183 int amdgpu_reset_method = -1; /* auto */ 184 int amdgpu_num_kcq = -1; 185 int amdgpu_smartshift_bias; 186 int amdgpu_use_xgmi_p2p = 1; 187 int amdgpu_vcnfw_log; 188 int amdgpu_sg_display = -1; /* auto */ 189 190 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); 191 192 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 193 "DRM_UT_CORE", 194 "DRM_UT_DRIVER", 195 "DRM_UT_KMS", 196 "DRM_UT_PRIME", 197 "DRM_UT_ATOMIC", 198 "DRM_UT_VBL", 199 "DRM_UT_STATE", 200 "DRM_UT_LEASE", 201 "DRM_UT_DP", 202 "DRM_UT_DRMRES"); 203 204 struct amdgpu_mgpu_info mgpu_info = { 205 .mutex = RWLOCK_INITIALIZER("mgpu_info"), 206 .delayed_reset_work = __DELAYED_WORK_INITIALIZER( 207 mgpu_info.delayed_reset_work, 208 amdgpu_drv_delayed_reset_work_handler, 0), 209 }; 210 int amdgpu_ras_enable = -1; 211 uint amdgpu_ras_mask = 0xffffffff; 212 int amdgpu_bad_page_threshold = -1; 213 struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { 214 .timeout_fatal_disable = false, 215 .period = 0x0, /* default to 0x0 (timeout disable) */ 216 }; 217 218 /** 219 * DOC: vramlimit (int) 220 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 221 */ 222 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 223 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 224 225 /** 226 * DOC: vis_vramlimit (int) 227 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 228 */ 229 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 230 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 231 232 /** 233 * DOC: gartsize (uint) 234 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 235 */ 236 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 237 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 238 239 /** 240 * DOC: gttsize (int) 241 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 242 * otherwise 3/4 RAM size). 243 */ 244 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 245 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 246 247 /** 248 * DOC: moverate (int) 249 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 250 */ 251 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 252 module_param_named(moverate, amdgpu_moverate, int, 0600); 253 254 /** 255 * DOC: audio (int) 256 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 257 */ 258 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 259 module_param_named(audio, amdgpu_audio, int, 0444); 260 261 /** 262 * DOC: disp_priority (int) 263 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 264 */ 265 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 266 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 267 268 /** 269 * DOC: hw_i2c (int) 270 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 271 */ 272 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 273 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 274 275 /** 276 * DOC: pcie_gen2 (int) 277 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 278 */ 279 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 280 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 281 282 /** 283 * DOC: msi (int) 284 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 285 */ 286 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 287 module_param_named(msi, amdgpu_msi, int, 0444); 288 289 /** 290 * DOC: lockup_timeout (string) 291 * Set GPU scheduler timeout value in ms. 292 * 293 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 294 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 295 * to the default timeout. 296 * 297 * - With one value specified, the setting will apply to all non-compute jobs. 298 * - With multiple values specified, the first one will be for GFX. 299 * The second one is for Compute. The third and fourth ones are 300 * for SDMA and Video. 301 * 302 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 303 * jobs is 10000. The timeout for compute is 60000. 304 */ 305 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " 306 "for passthrough or sriov, 10000 for all jobs." 307 " 0: keep default value. negative: infinity timeout), " 308 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 309 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 310 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 311 312 /** 313 * DOC: dpm (int) 314 * Override for dynamic power management setting 315 * (0 = disable, 1 = enable) 316 * The default is -1 (auto). 317 */ 318 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 319 module_param_named(dpm, amdgpu_dpm, int, 0444); 320 321 /** 322 * DOC: fw_load_type (int) 323 * Set different firmware loading type for debugging, if supported. 324 * Set to 0 to force direct loading if supported by the ASIC. Set 325 * to -1 to select the default loading mode for the ASIC, as defined 326 * by the driver. The default is -1 (auto). 327 */ 328 MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); 329 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 330 331 /** 332 * DOC: aspm (int) 333 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 334 */ 335 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 336 module_param_named(aspm, amdgpu_aspm, int, 0444); 337 338 /** 339 * DOC: runpm (int) 340 * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down 341 * the dGPUs when they are idle if supported. The default is -1 (auto enable). 342 * Setting the value to 0 disables this functionality. 343 */ 344 MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); 345 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 346 347 /** 348 * DOC: ip_block_mask (uint) 349 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 350 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 351 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 352 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 353 */ 354 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 355 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 356 357 /** 358 * DOC: bapm (int) 359 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 360 * The default -1 (auto, enabled) 361 */ 362 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 363 module_param_named(bapm, amdgpu_bapm, int, 0444); 364 365 /** 366 * DOC: deep_color (int) 367 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 368 */ 369 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 370 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 371 372 /** 373 * DOC: vm_size (int) 374 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 375 */ 376 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 377 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 378 379 /** 380 * DOC: vm_fragment_size (int) 381 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 382 */ 383 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 384 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 385 386 /** 387 * DOC: vm_block_size (int) 388 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 389 */ 390 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 391 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 392 393 /** 394 * DOC: vm_fault_stop (int) 395 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 396 */ 397 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 398 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 399 400 /** 401 * DOC: vm_debug (int) 402 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 403 */ 404 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 405 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 406 407 /** 408 * DOC: vm_update_mode (int) 409 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 410 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 411 */ 412 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 413 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 414 415 /** 416 * DOC: exp_hw_support (int) 417 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 418 */ 419 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 420 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 421 422 /** 423 * DOC: dc (int) 424 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 425 */ 426 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 427 module_param_named(dc, amdgpu_dc, int, 0444); 428 429 /** 430 * DOC: sched_jobs (int) 431 * Override the max number of jobs supported in the sw queue. The default is 32. 432 */ 433 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 434 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 435 436 /** 437 * DOC: sched_hw_submission (int) 438 * Override the max number of HW submissions. The default is 2. 439 */ 440 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 441 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 442 443 /** 444 * DOC: ppfeaturemask (hexint) 445 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 446 * The default is the current set of stable power features. 447 */ 448 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 449 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); 450 451 /** 452 * DOC: forcelongtraining (uint) 453 * Force long memory training in resume. 454 * The default is zero, indicates short training in resume. 455 */ 456 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 457 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 458 459 /** 460 * DOC: pcie_gen_cap (uint) 461 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 462 * The default is 0 (automatic for each asic). 463 */ 464 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 465 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 466 467 /** 468 * DOC: pcie_lane_cap (uint) 469 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 470 * The default is 0 (automatic for each asic). 471 */ 472 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 473 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 474 475 /** 476 * DOC: cg_mask (ullong) 477 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 478 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). 479 */ 480 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 481 module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); 482 483 /** 484 * DOC: pg_mask (uint) 485 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 486 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 487 */ 488 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 489 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 490 491 /** 492 * DOC: sdma_phase_quantum (uint) 493 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 494 */ 495 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 496 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 497 498 /** 499 * DOC: disable_cu (charp) 500 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 501 */ 502 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 503 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 504 505 /** 506 * DOC: virtual_display (charp) 507 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 508 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 509 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 510 * device at 26:00.0. The default is NULL. 511 */ 512 MODULE_PARM_DESC(virtual_display, 513 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 514 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 515 516 /** 517 * DOC: job_hang_limit (int) 518 * Set how much time allow a job hang and not drop it. The default is 0. 519 */ 520 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 521 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 522 523 /** 524 * DOC: lbpw (int) 525 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 526 */ 527 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 528 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 529 530 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 531 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 532 533 /** 534 * DOC: gpu_recovery (int) 535 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 536 */ 537 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); 538 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 539 540 /** 541 * DOC: emu_mode (int) 542 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 543 */ 544 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 545 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 546 547 /** 548 * DOC: ras_enable (int) 549 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 550 */ 551 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 552 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 553 554 /** 555 * DOC: ras_mask (uint) 556 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 557 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 558 */ 559 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 560 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 561 562 /** 563 * DOC: timeout_fatal_disable (bool) 564 * Disable Watchdog timeout fatal error event 565 */ 566 MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); 567 module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); 568 569 /** 570 * DOC: timeout_period (uint) 571 * Modify the watchdog timeout max_cycles as (1 << period) 572 */ 573 MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); 574 module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); 575 576 /** 577 * DOC: si_support (int) 578 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 579 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 580 * otherwise using amdgpu driver. 581 */ 582 #ifdef CONFIG_DRM_AMDGPU_SI 583 584 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 585 int amdgpu_si_support = 0; 586 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 587 #else 588 int amdgpu_si_support = 1; 589 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 590 #endif 591 592 module_param_named(si_support, amdgpu_si_support, int, 0444); 593 #endif 594 595 /** 596 * DOC: cik_support (int) 597 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 598 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 599 * otherwise using amdgpu driver. 600 */ 601 #ifdef CONFIG_DRM_AMDGPU_CIK 602 603 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 604 int amdgpu_cik_support = 0; 605 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 606 #else 607 int amdgpu_cik_support = 1; 608 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 609 #endif 610 611 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 612 #endif 613 614 /** 615 * DOC: smu_memory_pool_size (uint) 616 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 617 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 618 */ 619 MODULE_PARM_DESC(smu_memory_pool_size, 620 "reserve gtt for smu debug usage, 0 = disable," 621 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 622 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 623 624 /** 625 * DOC: async_gfx_ring (int) 626 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 627 */ 628 MODULE_PARM_DESC(async_gfx_ring, 629 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 630 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 631 632 /** 633 * DOC: mcbp (int) 634 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 635 */ 636 MODULE_PARM_DESC(mcbp, 637 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 638 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 639 640 /** 641 * DOC: discovery (int) 642 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 643 * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) 644 */ 645 MODULE_PARM_DESC(discovery, 646 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 647 module_param_named(discovery, amdgpu_discovery, int, 0444); 648 649 /** 650 * DOC: mes (int) 651 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 652 * (0 = disabled (default), 1 = enabled) 653 */ 654 MODULE_PARM_DESC(mes, 655 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 656 module_param_named(mes, amdgpu_mes, int, 0444); 657 658 /** 659 * DOC: mes_kiq (int) 660 * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. 661 * (0 = disabled (default), 1 = enabled) 662 */ 663 MODULE_PARM_DESC(mes_kiq, 664 "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); 665 module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); 666 667 /** 668 * DOC: noretry (int) 669 * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that 670 * do not support per-process XNACK this also disables retry page faults. 671 * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) 672 */ 673 MODULE_PARM_DESC(noretry, 674 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); 675 module_param_named(noretry, amdgpu_noretry, int, 0644); 676 677 /** 678 * DOC: force_asic_type (int) 679 * A non negative value used to specify the asic type for all supported GPUs. 680 */ 681 MODULE_PARM_DESC(force_asic_type, 682 "A non negative value used to specify the asic type for all supported GPUs"); 683 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 684 685 /** 686 * DOC: use_xgmi_p2p (int) 687 * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). 688 */ 689 MODULE_PARM_DESC(use_xgmi_p2p, 690 "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); 691 module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); 692 693 694 #ifdef CONFIG_HSA_AMD 695 /** 696 * DOC: sched_policy (int) 697 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 698 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 699 * assigns queues to HQDs. 700 */ 701 int sched_policy = KFD_SCHED_POLICY_HWS; 702 module_param(sched_policy, int, 0444); 703 MODULE_PARM_DESC(sched_policy, 704 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 705 706 /** 707 * DOC: hws_max_conc_proc (int) 708 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 709 * number of VMIDs assigned to the HWS, which is also the default. 710 */ 711 int hws_max_conc_proc = -1; 712 module_param(hws_max_conc_proc, int, 0444); 713 MODULE_PARM_DESC(hws_max_conc_proc, 714 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 715 716 /** 717 * DOC: cwsr_enable (int) 718 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 719 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 720 * disables it. 721 */ 722 int cwsr_enable = 1; 723 module_param(cwsr_enable, int, 0444); 724 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 725 726 /** 727 * DOC: max_num_of_queues_per_device (int) 728 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 729 * is 4096. 730 */ 731 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 732 module_param(max_num_of_queues_per_device, int, 0444); 733 MODULE_PARM_DESC(max_num_of_queues_per_device, 734 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 735 736 /** 737 * DOC: send_sigterm (int) 738 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 739 * but just print errors on dmesg. Setting 1 enables sending sigterm. 740 */ 741 int send_sigterm; 742 module_param(send_sigterm, int, 0444); 743 MODULE_PARM_DESC(send_sigterm, 744 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 745 746 /** 747 * DOC: debug_largebar (int) 748 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 749 * system. This limits the VRAM size reported to ROCm applications to the visible 750 * size, usually 256MB. 751 * Default value is 0, diabled. 752 */ 753 int debug_largebar; 754 module_param(debug_largebar, int, 0444); 755 MODULE_PARM_DESC(debug_largebar, 756 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 757 758 /** 759 * DOC: ignore_crat (int) 760 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 761 * table to get information about AMD APUs. This option can serve as a workaround on 762 * systems with a broken CRAT table. 763 * 764 * Default is auto (according to asic type, iommu_v2, and crat table, to decide 765 * whether use CRAT) 766 */ 767 int ignore_crat; 768 module_param(ignore_crat, int, 0444); 769 MODULE_PARM_DESC(ignore_crat, 770 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); 771 772 /** 773 * DOC: halt_if_hws_hang (int) 774 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 775 * Setting 1 enables halt on hang. 776 */ 777 int halt_if_hws_hang; 778 module_param(halt_if_hws_hang, int, 0644); 779 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 780 781 /** 782 * DOC: hws_gws_support(bool) 783 * Assume that HWS supports GWS barriers regardless of what firmware version 784 * check says. Default value: false (rely on MEC2 firmware version check). 785 */ 786 bool hws_gws_support; 787 module_param(hws_gws_support, bool, 0444); 788 MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); 789 790 /** 791 * DOC: queue_preemption_timeout_ms (int) 792 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 793 */ 794 int queue_preemption_timeout_ms = 9000; 795 module_param(queue_preemption_timeout_ms, int, 0644); 796 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 797 798 /** 799 * DOC: debug_evictions(bool) 800 * Enable extra debug messages to help determine the cause of evictions 801 */ 802 bool debug_evictions; 803 module_param(debug_evictions, bool, 0644); 804 MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); 805 806 /** 807 * DOC: no_system_mem_limit(bool) 808 * Disable system memory limit, to support multiple process shared memory 809 */ 810 bool no_system_mem_limit; 811 module_param(no_system_mem_limit, bool, 0644); 812 MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); 813 814 /** 815 * DOC: no_queue_eviction_on_vm_fault (int) 816 * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). 817 */ 818 int amdgpu_no_queue_eviction_on_vm_fault = 0; 819 MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); 820 module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); 821 #endif 822 823 /** 824 * DOC: pcie_p2p (bool) 825 * Enable PCIe P2P (requires large-BAR). Default value: true (on) 826 */ 827 #ifdef CONFIG_HSA_AMD_P2P 828 bool pcie_p2p = true; 829 module_param(pcie_p2p, bool, 0444); 830 MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); 831 #endif 832 833 /** 834 * DOC: dcfeaturemask (uint) 835 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 836 * The default is the current set of stable display features. 837 */ 838 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 839 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 840 841 /** 842 * DOC: dcdebugmask (uint) 843 * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 844 */ 845 MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); 846 module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); 847 848 MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); 849 module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); 850 851 /** 852 * DOC: abmlevel (uint) 853 * Override the default ABM (Adaptive Backlight Management) level used for DC 854 * enabled hardware. Requires DMCU to be supported and loaded. 855 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 856 * default. Values 1-4 control the maximum allowable brightness reduction via 857 * the ABM algorithm, with 1 being the least reduction and 4 being the most 858 * reduction. 859 * 860 * Defaults to 0, or disabled. Userspace can still override this level later 861 * after boot. 862 */ 863 uint amdgpu_dm_abm_level; 864 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 865 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 866 867 int amdgpu_backlight = -1; 868 MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); 869 module_param_named(backlight, amdgpu_backlight, bint, 0444); 870 871 /** 872 * DOC: tmz (int) 873 * Trusted Memory Zone (TMZ) is a method to protect data being written 874 * to or read from memory. 875 * 876 * The default value: 0 (off). TODO: change to auto till it is completed. 877 */ 878 MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); 879 module_param_named(tmz, amdgpu_tmz, int, 0444); 880 881 /** 882 * DOC: freesync_video (uint) 883 * Enable the optimization to adjust front porch timing to achieve seamless 884 * mode change experience when setting a freesync supported mode for which full 885 * modeset is not needed. 886 * 887 * The Display Core will add a set of modes derived from the base FreeSync 888 * video mode into the corresponding connector's mode list based on commonly 889 * used refresh rates and VRR range of the connected display, when users enable 890 * this feature. From the userspace perspective, they can see a seamless mode 891 * change experience when the change between different refresh rates under the 892 * same resolution. Additionally, userspace applications such as Video playback 893 * can read this modeset list and change the refresh rate based on the video 894 * frame rate. Finally, the userspace can also derive an appropriate mode for a 895 * particular refresh rate based on the FreeSync Mode and add it to the 896 * connector's mode list. 897 * 898 * Note: This is an experimental feature. 899 * 900 * The default value: 0 (off). 901 */ 902 MODULE_PARM_DESC( 903 freesync_video, 904 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); 905 module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); 906 907 /** 908 * DOC: reset_method (int) 909 * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) 910 */ 911 MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); 912 module_param_named(reset_method, amdgpu_reset_method, int, 0444); 913 914 /** 915 * DOC: bad_page_threshold (int) Bad page threshold is specifies the 916 * threshold value of faulty pages detected by RAS ECC, which may 917 * result in the GPU entering bad status when the number of total 918 * faulty pages by ECC exceeds the threshold value. 919 */ 920 MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); 921 module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); 922 923 MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); 924 module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); 925 926 /** 927 * DOC: vcnfw_log (int) 928 * Enable vcnfw log output for debugging, the default is disabled. 929 */ 930 MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); 931 module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); 932 933 /** 934 * DOC: sg_display (int) 935 * Disable S/G (scatter/gather) display (i.e., display from system memory). 936 * This option is only relevant on APUs. Set this option to 0 to disable 937 * S/G display if you experience flickering or other issues under memory 938 * pressure and report the issue. 939 */ 940 MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); 941 module_param_named(sg_display, amdgpu_sg_display, int, 0444); 942 943 /** 944 * DOC: smu_pptable_id (int) 945 * Used to override pptable id. id = 0 use VBIOS pptable. 946 * id > 0 use the soft pptable with specicfied id. 947 */ 948 MODULE_PARM_DESC(smu_pptable_id, 949 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); 950 module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); 951 952 /* These devices are not supported by amdgpu. 953 * They are supported by the mach64, r128, radeon drivers 954 */ 955 static const u16 amdgpu_unsupported_pciidlist[] = { 956 /* mach64 */ 957 0x4354, 958 0x4358, 959 0x4554, 960 0x4742, 961 0x4744, 962 0x4749, 963 0x474C, 964 0x474D, 965 0x474E, 966 0x474F, 967 0x4750, 968 0x4751, 969 0x4752, 970 0x4753, 971 0x4754, 972 0x4755, 973 0x4756, 974 0x4757, 975 0x4758, 976 0x4759, 977 0x475A, 978 0x4C42, 979 0x4C44, 980 0x4C47, 981 0x4C49, 982 0x4C4D, 983 0x4C4E, 984 0x4C50, 985 0x4C51, 986 0x4C52, 987 0x4C53, 988 0x5654, 989 0x5655, 990 0x5656, 991 /* r128 */ 992 0x4c45, 993 0x4c46, 994 0x4d46, 995 0x4d4c, 996 0x5041, 997 0x5042, 998 0x5043, 999 0x5044, 1000 0x5045, 1001 0x5046, 1002 0x5047, 1003 0x5048, 1004 0x5049, 1005 0x504A, 1006 0x504B, 1007 0x504C, 1008 0x504D, 1009 0x504E, 1010 0x504F, 1011 0x5050, 1012 0x5051, 1013 0x5052, 1014 0x5053, 1015 0x5054, 1016 0x5055, 1017 0x5056, 1018 0x5057, 1019 0x5058, 1020 0x5245, 1021 0x5246, 1022 0x5247, 1023 0x524b, 1024 0x524c, 1025 0x534d, 1026 0x5446, 1027 0x544C, 1028 0x5452, 1029 /* radeon */ 1030 0x3150, 1031 0x3151, 1032 0x3152, 1033 0x3154, 1034 0x3155, 1035 0x3E50, 1036 0x3E54, 1037 0x4136, 1038 0x4137, 1039 0x4144, 1040 0x4145, 1041 0x4146, 1042 0x4147, 1043 0x4148, 1044 0x4149, 1045 0x414A, 1046 0x414B, 1047 0x4150, 1048 0x4151, 1049 0x4152, 1050 0x4153, 1051 0x4154, 1052 0x4155, 1053 0x4156, 1054 0x4237, 1055 0x4242, 1056 0x4336, 1057 0x4337, 1058 0x4437, 1059 0x4966, 1060 0x4967, 1061 0x4A48, 1062 0x4A49, 1063 0x4A4A, 1064 0x4A4B, 1065 0x4A4C, 1066 0x4A4D, 1067 0x4A4E, 1068 0x4A4F, 1069 0x4A50, 1070 0x4A54, 1071 0x4B48, 1072 0x4B49, 1073 0x4B4A, 1074 0x4B4B, 1075 0x4B4C, 1076 0x4C57, 1077 0x4C58, 1078 0x4C59, 1079 0x4C5A, 1080 0x4C64, 1081 0x4C66, 1082 0x4C67, 1083 0x4E44, 1084 0x4E45, 1085 0x4E46, 1086 0x4E47, 1087 0x4E48, 1088 0x4E49, 1089 0x4E4A, 1090 0x4E4B, 1091 0x4E50, 1092 0x4E51, 1093 0x4E52, 1094 0x4E53, 1095 0x4E54, 1096 0x4E56, 1097 0x5144, 1098 0x5145, 1099 0x5146, 1100 0x5147, 1101 0x5148, 1102 0x514C, 1103 0x514D, 1104 0x5157, 1105 0x5158, 1106 0x5159, 1107 0x515A, 1108 0x515E, 1109 0x5460, 1110 0x5462, 1111 0x5464, 1112 0x5548, 1113 0x5549, 1114 0x554A, 1115 0x554B, 1116 0x554C, 1117 0x554D, 1118 0x554E, 1119 0x554F, 1120 0x5550, 1121 0x5551, 1122 0x5552, 1123 0x5554, 1124 0x564A, 1125 0x564B, 1126 0x564F, 1127 0x5652, 1128 0x5653, 1129 0x5657, 1130 0x5834, 1131 0x5835, 1132 0x5954, 1133 0x5955, 1134 0x5974, 1135 0x5975, 1136 0x5960, 1137 0x5961, 1138 0x5962, 1139 0x5964, 1140 0x5965, 1141 0x5969, 1142 0x5a41, 1143 0x5a42, 1144 0x5a61, 1145 0x5a62, 1146 0x5b60, 1147 0x5b62, 1148 0x5b63, 1149 0x5b64, 1150 0x5b65, 1151 0x5c61, 1152 0x5c63, 1153 0x5d48, 1154 0x5d49, 1155 0x5d4a, 1156 0x5d4c, 1157 0x5d4d, 1158 0x5d4e, 1159 0x5d4f, 1160 0x5d50, 1161 0x5d52, 1162 0x5d57, 1163 0x5e48, 1164 0x5e4a, 1165 0x5e4b, 1166 0x5e4c, 1167 0x5e4d, 1168 0x5e4f, 1169 0x6700, 1170 0x6701, 1171 0x6702, 1172 0x6703, 1173 0x6704, 1174 0x6705, 1175 0x6706, 1176 0x6707, 1177 0x6708, 1178 0x6709, 1179 0x6718, 1180 0x6719, 1181 0x671c, 1182 0x671d, 1183 0x671f, 1184 0x6720, 1185 0x6721, 1186 0x6722, 1187 0x6723, 1188 0x6724, 1189 0x6725, 1190 0x6726, 1191 0x6727, 1192 0x6728, 1193 0x6729, 1194 0x6738, 1195 0x6739, 1196 0x673e, 1197 0x6740, 1198 0x6741, 1199 0x6742, 1200 0x6743, 1201 0x6744, 1202 0x6745, 1203 0x6746, 1204 0x6747, 1205 0x6748, 1206 0x6749, 1207 0x674A, 1208 0x6750, 1209 0x6751, 1210 0x6758, 1211 0x6759, 1212 0x675B, 1213 0x675D, 1214 0x675F, 1215 0x6760, 1216 0x6761, 1217 0x6762, 1218 0x6763, 1219 0x6764, 1220 0x6765, 1221 0x6766, 1222 0x6767, 1223 0x6768, 1224 0x6770, 1225 0x6771, 1226 0x6772, 1227 0x6778, 1228 0x6779, 1229 0x677B, 1230 0x6840, 1231 0x6841, 1232 0x6842, 1233 0x6843, 1234 0x6849, 1235 0x684C, 1236 0x6850, 1237 0x6858, 1238 0x6859, 1239 0x6880, 1240 0x6888, 1241 0x6889, 1242 0x688A, 1243 0x688C, 1244 0x688D, 1245 0x6898, 1246 0x6899, 1247 0x689b, 1248 0x689c, 1249 0x689d, 1250 0x689e, 1251 0x68a0, 1252 0x68a1, 1253 0x68a8, 1254 0x68a9, 1255 0x68b0, 1256 0x68b8, 1257 0x68b9, 1258 0x68ba, 1259 0x68be, 1260 0x68bf, 1261 0x68c0, 1262 0x68c1, 1263 0x68c7, 1264 0x68c8, 1265 0x68c9, 1266 0x68d8, 1267 0x68d9, 1268 0x68da, 1269 0x68de, 1270 0x68e0, 1271 0x68e1, 1272 0x68e4, 1273 0x68e5, 1274 0x68e8, 1275 0x68e9, 1276 0x68f1, 1277 0x68f2, 1278 0x68f8, 1279 0x68f9, 1280 0x68fa, 1281 0x68fe, 1282 0x7100, 1283 0x7101, 1284 0x7102, 1285 0x7103, 1286 0x7104, 1287 0x7105, 1288 0x7106, 1289 0x7108, 1290 0x7109, 1291 0x710A, 1292 0x710B, 1293 0x710C, 1294 0x710E, 1295 0x710F, 1296 0x7140, 1297 0x7141, 1298 0x7142, 1299 0x7143, 1300 0x7144, 1301 0x7145, 1302 0x7146, 1303 0x7147, 1304 0x7149, 1305 0x714A, 1306 0x714B, 1307 0x714C, 1308 0x714D, 1309 0x714E, 1310 0x714F, 1311 0x7151, 1312 0x7152, 1313 0x7153, 1314 0x715E, 1315 0x715F, 1316 0x7180, 1317 0x7181, 1318 0x7183, 1319 0x7186, 1320 0x7187, 1321 0x7188, 1322 0x718A, 1323 0x718B, 1324 0x718C, 1325 0x718D, 1326 0x718F, 1327 0x7193, 1328 0x7196, 1329 0x719B, 1330 0x719F, 1331 0x71C0, 1332 0x71C1, 1333 0x71C2, 1334 0x71C3, 1335 0x71C4, 1336 0x71C5, 1337 0x71C6, 1338 0x71C7, 1339 0x71CD, 1340 0x71CE, 1341 0x71D2, 1342 0x71D4, 1343 0x71D5, 1344 0x71D6, 1345 0x71DA, 1346 0x71DE, 1347 0x7200, 1348 0x7210, 1349 0x7211, 1350 0x7240, 1351 0x7243, 1352 0x7244, 1353 0x7245, 1354 0x7246, 1355 0x7247, 1356 0x7248, 1357 0x7249, 1358 0x724A, 1359 0x724B, 1360 0x724C, 1361 0x724D, 1362 0x724E, 1363 0x724F, 1364 0x7280, 1365 0x7281, 1366 0x7283, 1367 0x7284, 1368 0x7287, 1369 0x7288, 1370 0x7289, 1371 0x728B, 1372 0x728C, 1373 0x7290, 1374 0x7291, 1375 0x7293, 1376 0x7297, 1377 0x7834, 1378 0x7835, 1379 0x791e, 1380 0x791f, 1381 0x793f, 1382 0x7941, 1383 0x7942, 1384 0x796c, 1385 0x796d, 1386 0x796e, 1387 0x796f, 1388 0x9400, 1389 0x9401, 1390 0x9402, 1391 0x9403, 1392 0x9405, 1393 0x940A, 1394 0x940B, 1395 0x940F, 1396 0x94A0, 1397 0x94A1, 1398 0x94A3, 1399 0x94B1, 1400 0x94B3, 1401 0x94B4, 1402 0x94B5, 1403 0x94B9, 1404 0x9440, 1405 0x9441, 1406 0x9442, 1407 0x9443, 1408 0x9444, 1409 0x9446, 1410 0x944A, 1411 0x944B, 1412 0x944C, 1413 0x944E, 1414 0x9450, 1415 0x9452, 1416 0x9456, 1417 0x945A, 1418 0x945B, 1419 0x945E, 1420 0x9460, 1421 0x9462, 1422 0x946A, 1423 0x946B, 1424 0x947A, 1425 0x947B, 1426 0x9480, 1427 0x9487, 1428 0x9488, 1429 0x9489, 1430 0x948A, 1431 0x948F, 1432 0x9490, 1433 0x9491, 1434 0x9495, 1435 0x9498, 1436 0x949C, 1437 0x949E, 1438 0x949F, 1439 0x94C0, 1440 0x94C1, 1441 0x94C3, 1442 0x94C4, 1443 0x94C5, 1444 0x94C6, 1445 0x94C7, 1446 0x94C8, 1447 0x94C9, 1448 0x94CB, 1449 0x94CC, 1450 0x94CD, 1451 0x9500, 1452 0x9501, 1453 0x9504, 1454 0x9505, 1455 0x9506, 1456 0x9507, 1457 0x9508, 1458 0x9509, 1459 0x950F, 1460 0x9511, 1461 0x9515, 1462 0x9517, 1463 0x9519, 1464 0x9540, 1465 0x9541, 1466 0x9542, 1467 0x954E, 1468 0x954F, 1469 0x9552, 1470 0x9553, 1471 0x9555, 1472 0x9557, 1473 0x955f, 1474 0x9580, 1475 0x9581, 1476 0x9583, 1477 0x9586, 1478 0x9587, 1479 0x9588, 1480 0x9589, 1481 0x958A, 1482 0x958B, 1483 0x958C, 1484 0x958D, 1485 0x958E, 1486 0x958F, 1487 0x9590, 1488 0x9591, 1489 0x9593, 1490 0x9595, 1491 0x9596, 1492 0x9597, 1493 0x9598, 1494 0x9599, 1495 0x959B, 1496 0x95C0, 1497 0x95C2, 1498 0x95C4, 1499 0x95C5, 1500 0x95C6, 1501 0x95C7, 1502 0x95C9, 1503 0x95CC, 1504 0x95CD, 1505 0x95CE, 1506 0x95CF, 1507 0x9610, 1508 0x9611, 1509 0x9612, 1510 0x9613, 1511 0x9614, 1512 0x9615, 1513 0x9616, 1514 0x9640, 1515 0x9641, 1516 0x9642, 1517 0x9643, 1518 0x9644, 1519 0x9645, 1520 0x9647, 1521 0x9648, 1522 0x9649, 1523 0x964a, 1524 0x964b, 1525 0x964c, 1526 0x964e, 1527 0x964f, 1528 0x9710, 1529 0x9711, 1530 0x9712, 1531 0x9713, 1532 0x9714, 1533 0x9715, 1534 0x9802, 1535 0x9803, 1536 0x9804, 1537 0x9805, 1538 0x9806, 1539 0x9807, 1540 0x9808, 1541 0x9809, 1542 0x980A, 1543 0x9900, 1544 0x9901, 1545 0x9903, 1546 0x9904, 1547 0x9905, 1548 0x9906, 1549 0x9907, 1550 0x9908, 1551 0x9909, 1552 0x990A, 1553 0x990B, 1554 0x990C, 1555 0x990D, 1556 0x990E, 1557 0x990F, 1558 0x9910, 1559 0x9913, 1560 0x9917, 1561 0x9918, 1562 0x9919, 1563 0x9990, 1564 0x9991, 1565 0x9992, 1566 0x9993, 1567 0x9994, 1568 0x9995, 1569 0x9996, 1570 0x9997, 1571 0x9998, 1572 0x9999, 1573 0x999A, 1574 0x999B, 1575 0x999C, 1576 0x999D, 1577 0x99A0, 1578 0x99A2, 1579 0x99A4, 1580 /* radeon secondary ids */ 1581 0x3171, 1582 0x3e70, 1583 0x4164, 1584 0x4165, 1585 0x4166, 1586 0x4168, 1587 0x4170, 1588 0x4171, 1589 0x4172, 1590 0x4173, 1591 0x496e, 1592 0x4a69, 1593 0x4a6a, 1594 0x4a6b, 1595 0x4a70, 1596 0x4a74, 1597 0x4b69, 1598 0x4b6b, 1599 0x4b6c, 1600 0x4c6e, 1601 0x4e64, 1602 0x4e65, 1603 0x4e66, 1604 0x4e67, 1605 0x4e68, 1606 0x4e69, 1607 0x4e6a, 1608 0x4e71, 1609 0x4f73, 1610 0x5569, 1611 0x556b, 1612 0x556d, 1613 0x556f, 1614 0x5571, 1615 0x5854, 1616 0x5874, 1617 0x5940, 1618 0x5941, 1619 0x5b70, 1620 0x5b72, 1621 0x5b73, 1622 0x5b74, 1623 0x5b75, 1624 0x5d44, 1625 0x5d45, 1626 0x5d6d, 1627 0x5d6f, 1628 0x5d72, 1629 0x5d77, 1630 0x5e6b, 1631 0x5e6d, 1632 0x7120, 1633 0x7124, 1634 0x7129, 1635 0x712e, 1636 0x712f, 1637 0x7162, 1638 0x7163, 1639 0x7166, 1640 0x7167, 1641 0x7172, 1642 0x7173, 1643 0x71a0, 1644 0x71a1, 1645 0x71a3, 1646 0x71a7, 1647 0x71bb, 1648 0x71e0, 1649 0x71e1, 1650 0x71e2, 1651 0x71e6, 1652 0x71e7, 1653 0x71f2, 1654 0x7269, 1655 0x726b, 1656 0x726e, 1657 0x72a0, 1658 0x72a8, 1659 0x72b1, 1660 0x72b3, 1661 0x793f, 1662 }; 1663 1664 static const struct pci_device_id pciidlist[] = { 1665 #ifdef CONFIG_DRM_AMDGPU_SI 1666 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1667 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1668 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1669 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1670 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1671 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1672 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1673 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1674 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1675 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1676 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1677 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1678 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 1679 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1680 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1681 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 1682 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1683 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1684 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1685 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1686 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1687 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1688 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1689 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1690 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 1691 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1692 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1693 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1694 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1695 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1696 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1697 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1698 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1699 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1700 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1701 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1702 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1703 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1704 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1705 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1706 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 1707 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 1708 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1709 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1710 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1711 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1712 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1713 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1714 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1715 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1716 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1717 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1718 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1719 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1720 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1721 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1722 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1723 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1724 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 1725 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1726 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1727 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1728 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1729 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1730 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1731 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 1732 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1733 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1734 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1735 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1736 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1737 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 1738 #endif 1739 #ifdef CONFIG_DRM_AMDGPU_CIK 1740 /* Kaveri */ 1741 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1742 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1743 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1744 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1745 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1746 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1747 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1748 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1749 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1750 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1751 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1752 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1753 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1754 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1755 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1756 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1757 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1758 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1759 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 1760 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1761 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1762 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 1763 /* Bonaire */ 1764 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1765 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1766 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1767 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 1768 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1769 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1770 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1771 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1772 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1773 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1774 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 1775 /* Hawaii */ 1776 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1777 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1778 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1779 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1780 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1781 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1782 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1783 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1784 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1785 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1786 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1787 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 1788 /* Kabini */ 1789 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1790 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1791 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1792 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1793 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1794 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1795 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1796 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1797 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1798 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1799 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1800 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 1801 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1802 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1803 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1804 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 1805 /* mullins */ 1806 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1807 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1808 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1809 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1810 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1811 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1812 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1813 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1814 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1815 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1816 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1817 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1818 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1819 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1820 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1821 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 1822 #endif 1823 /* topaz */ 1824 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1825 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1826 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1827 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1828 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 1829 /* tonga */ 1830 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1831 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1832 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1833 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1834 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1835 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1836 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1837 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1838 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 1839 /* fiji */ 1840 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1841 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 1842 /* carrizo */ 1843 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1844 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1845 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1846 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1847 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 1848 /* stoney */ 1849 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 1850 /* Polaris11 */ 1851 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1852 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1853 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1854 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1855 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1856 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1857 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1858 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1859 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 1860 /* Polaris10 */ 1861 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1862 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1863 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1864 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1865 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1866 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1867 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1868 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1869 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1870 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1871 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1872 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1873 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 1874 /* Polaris12 */ 1875 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1876 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1877 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1878 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1879 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1880 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1881 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1882 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 1883 /* VEGAM */ 1884 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1885 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1886 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 1887 /* Vega 10 */ 1888 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1889 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1890 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1891 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1892 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1893 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1894 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1895 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1896 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1897 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1898 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1899 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1900 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1901 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1902 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 1903 /* Vega 12 */ 1904 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1905 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1906 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1907 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1908 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 1909 /* Vega 20 */ 1910 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1911 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1912 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1913 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1914 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1915 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1916 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 1917 /* Raven */ 1918 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1919 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 1920 /* Arcturus */ 1921 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1922 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1923 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1924 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS}, 1925 /* Navi10 */ 1926 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1927 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1928 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1929 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1930 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1931 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1932 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1933 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1934 /* Navi14 */ 1935 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1936 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1937 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1938 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1939 1940 /* Renoir */ 1941 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1942 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1943 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1944 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1945 1946 /* Navi12 */ 1947 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1948 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12}, 1949 1950 /* Sienna_Cichlid */ 1951 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1952 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1953 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1954 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1955 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1956 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1957 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1958 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1959 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1960 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1961 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1962 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1963 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID}, 1964 1965 /* Van Gogh */ 1966 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU}, 1967 1968 /* Yellow Carp */ 1969 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1970 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, 1971 1972 /* Navy_Flounder */ 1973 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1974 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1975 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1976 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1977 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1978 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1979 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1980 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1981 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER}, 1982 1983 /* DIMGREY_CAVEFISH */ 1984 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1985 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1986 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1987 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1988 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1989 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1990 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1991 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1992 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1993 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1994 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1995 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH}, 1996 1997 /* Aldebaran */ 1998 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 1999 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2000 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2001 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN}, 2002 2003 /* CYAN_SKILLFISH */ 2004 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2005 {0x1002, 0x143F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, 2006 2007 /* BEIGE_GOBY */ 2008 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2009 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2010 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2011 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2012 {0x1002, 0x7424, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2013 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY}, 2014 2015 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2016 .class = PCI_CLASS_DISPLAY_VGA << 8, 2017 .class_mask = 0xffffff, 2018 .driver_data = CHIP_IP_DISCOVERY }, 2019 2020 { PCI_DEVICE(0x1002, PCI_ANY_ID), 2021 .class = PCI_CLASS_DISPLAY_OTHER << 8, 2022 .class_mask = 0xffffff, 2023 .driver_data = CHIP_IP_DISCOVERY }, 2024 2025 {0, 0, 0} 2026 }; 2027 2028 MODULE_DEVICE_TABLE(pci, pciidlist); 2029 2030 static const struct drm_driver amdgpu_kms_driver; 2031 2032 static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) 2033 { 2034 STUB(); 2035 #ifdef notyet 2036 struct pci_dev *p = NULL; 2037 int i; 2038 2039 /* 0 - GPU 2040 * 1 - audio 2041 * 2 - USB 2042 * 3 - UCSI 2043 */ 2044 for (i = 1; i < 4; i++) { 2045 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), 2046 adev->pdev->bus->number, i); 2047 if (p) { 2048 pm_runtime_get_sync(&p->dev); 2049 pm_runtime_mark_last_busy(&p->dev); 2050 pm_runtime_put_autosuspend(&p->dev); 2051 pci_dev_put(p); 2052 } 2053 } 2054 #endif 2055 } 2056 2057 #ifdef notyet 2058 static int amdgpu_pci_probe(struct pci_dev *pdev, 2059 const struct pci_device_id *ent) 2060 { 2061 struct drm_device *ddev; 2062 struct amdgpu_device *adev; 2063 unsigned long flags = ent->driver_data; 2064 int ret, retry = 0, i; 2065 bool supports_atomic = false; 2066 2067 /* skip devices which are owned by radeon */ 2068 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2069 if (amdgpu_unsupported_pciidlist[i] == pdev->device) 2070 return -ENODEV; 2071 } 2072 2073 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) 2074 amdgpu_aspm = 0; 2075 2076 if (amdgpu_virtual_display || 2077 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 2078 supports_atomic = true; 2079 2080 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 2081 DRM_INFO("This hardware requires experimental hardware support.\n" 2082 "See modparam exp_hw_support\n"); 2083 return -ENODEV; 2084 } 2085 /* differentiate between P10 and P11 asics with the same DID */ 2086 if (pdev->device == 0x67FF && 2087 (pdev->revision == 0xE3 || 2088 pdev->revision == 0xE7 || 2089 pdev->revision == 0xF3 || 2090 pdev->revision == 0xF7)) { 2091 flags &= ~AMD_ASIC_MASK; 2092 flags |= CHIP_POLARIS10; 2093 } 2094 2095 /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, 2096 * however, SME requires an indirect IOMMU mapping because the encryption 2097 * bit is beyond the DMA mask of the chip. 2098 */ 2099 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && 2100 ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { 2101 dev_info(&pdev->dev, 2102 "SME is not compatible with RAVEN\n"); 2103 return -ENOTSUPP; 2104 } 2105 2106 #ifdef CONFIG_DRM_AMDGPU_SI 2107 if (!amdgpu_si_support) { 2108 switch (flags & AMD_ASIC_MASK) { 2109 case CHIP_TAHITI: 2110 case CHIP_PITCAIRN: 2111 case CHIP_VERDE: 2112 case CHIP_OLAND: 2113 case CHIP_HAINAN: 2114 dev_info(&pdev->dev, 2115 "SI support provided by radeon.\n"); 2116 dev_info(&pdev->dev, 2117 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 2118 ); 2119 return -ENODEV; 2120 } 2121 } 2122 #endif 2123 #ifdef CONFIG_DRM_AMDGPU_CIK 2124 if (!amdgpu_cik_support) { 2125 switch (flags & AMD_ASIC_MASK) { 2126 case CHIP_KAVERI: 2127 case CHIP_BONAIRE: 2128 case CHIP_HAWAII: 2129 case CHIP_KABINI: 2130 case CHIP_MULLINS: 2131 dev_info(&pdev->dev, 2132 "CIK support provided by radeon.\n"); 2133 dev_info(&pdev->dev, 2134 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 2135 ); 2136 return -ENODEV; 2137 } 2138 } 2139 #endif 2140 2141 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev); 2142 if (IS_ERR(adev)) 2143 return PTR_ERR(adev); 2144 2145 adev->dev = &pdev->dev; 2146 adev->pdev = pdev; 2147 ddev = adev_to_drm(adev); 2148 2149 if (!supports_atomic) 2150 ddev->driver_features &= ~DRIVER_ATOMIC; 2151 2152 ret = pci_enable_device(pdev); 2153 if (ret) 2154 return ret; 2155 2156 pci_set_drvdata(pdev, ddev); 2157 2158 ret = amdgpu_driver_load_kms(adev, flags); 2159 if (ret) 2160 goto err_pci; 2161 2162 retry_init: 2163 ret = drm_dev_register(ddev, flags); 2164 if (ret == -EAGAIN && ++retry <= 3) { 2165 DRM_INFO("retry init %d\n", retry); 2166 /* Don't request EX mode too frequently which is attacking */ 2167 drm_msleep(5000); 2168 goto retry_init; 2169 } else if (ret) { 2170 goto err_pci; 2171 } 2172 2173 /* 2174 * 1. don't init fbdev on hw without DCE 2175 * 2. don't init fbdev if there are no connectors 2176 */ 2177 if (adev->mode_info.mode_config_initialized && 2178 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 2179 /* select 8 bpp console on low vram cards */ 2180 if (adev->gmc.real_vram_size <= (32*1024*1024)) 2181 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 2182 else 2183 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 2184 } 2185 2186 ret = amdgpu_debugfs_init(adev); 2187 if (ret) 2188 DRM_ERROR("Creating debugfs files failed (%d).\n", ret); 2189 2190 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2191 /* only need to skip on ATPX */ 2192 if (amdgpu_device_supports_px(ddev)) 2193 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 2194 /* we want direct complete for BOCO */ 2195 if (amdgpu_device_supports_boco(ddev)) 2196 dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | 2197 DPM_FLAG_SMART_SUSPEND | 2198 DPM_FLAG_MAY_SKIP_RESUME); 2199 pm_runtime_use_autosuspend(ddev->dev); 2200 pm_runtime_set_autosuspend_delay(ddev->dev, 5000); 2201 2202 pm_runtime_allow(ddev->dev); 2203 2204 pm_runtime_mark_last_busy(ddev->dev); 2205 pm_runtime_put_autosuspend(ddev->dev); 2206 2207 /* 2208 * For runpm implemented via BACO, PMFW will handle the 2209 * timing for BACO in and out: 2210 * - put ASIC into BACO state only when both video and 2211 * audio functions are in D3 state. 2212 * - pull ASIC out of BACO state when either video or 2213 * audio function is in D0 state. 2214 * Also, at startup, PMFW assumes both functions are in 2215 * D0 state. 2216 * 2217 * So if snd driver was loaded prior to amdgpu driver 2218 * and audio function was put into D3 state, there will 2219 * be no PMFW-aware D-state transition(D0->D3) on runpm 2220 * suspend. Thus the BACO will be not correctly kicked in. 2221 * 2222 * Via amdgpu_get_secondary_funcs(), the audio dev is put 2223 * into D0 state. Then there will be a PMFW-aware D-state 2224 * transition(D0->D3) on runpm suspend. 2225 */ 2226 if (amdgpu_device_supports_baco(ddev) && 2227 !(adev->flags & AMD_IS_APU) && 2228 (adev->asic_type >= CHIP_NAVI10)) 2229 amdgpu_get_secondary_funcs(adev); 2230 } 2231 2232 return 0; 2233 2234 err_pci: 2235 pci_disable_device(pdev); 2236 return ret; 2237 } 2238 2239 static void 2240 amdgpu_pci_remove(struct pci_dev *pdev) 2241 { 2242 struct drm_device *dev = pci_get_drvdata(pdev); 2243 struct amdgpu_device *adev = drm_to_adev(dev); 2244 2245 drm_dev_unplug(dev); 2246 2247 if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { 2248 pm_runtime_get_sync(dev->dev); 2249 pm_runtime_forbid(dev->dev); 2250 } 2251 2252 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && 2253 !amdgpu_sriov_vf(adev)) { 2254 bool need_to_reset_gpu = false; 2255 2256 if (adev->gmc.xgmi.num_physical_nodes > 1) { 2257 struct amdgpu_hive_info *hive; 2258 2259 hive = amdgpu_get_xgmi_hive(adev); 2260 if (hive->device_remove_count == 0) 2261 need_to_reset_gpu = true; 2262 hive->device_remove_count++; 2263 amdgpu_put_xgmi_hive(hive); 2264 } else { 2265 need_to_reset_gpu = true; 2266 } 2267 2268 /* Workaround for ASICs need to reset SMU. 2269 * Called only when the first device is removed. 2270 */ 2271 if (need_to_reset_gpu) { 2272 struct amdgpu_reset_context reset_context; 2273 2274 adev->shutdown = true; 2275 memset(&reset_context, 0, sizeof(reset_context)); 2276 reset_context.method = AMD_RESET_METHOD_NONE; 2277 reset_context.reset_req_dev = adev; 2278 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2279 set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); 2280 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 2281 } 2282 } 2283 2284 amdgpu_driver_unload_kms(dev); 2285 2286 /* 2287 * Flush any in flight DMA operations from device. 2288 * Clear the Bus Master Enable bit and then wait on the PCIe Device 2289 * StatusTransactions Pending bit. 2290 */ 2291 pci_disable_device(pdev); 2292 pci_wait_for_pending_transaction(pdev); 2293 } 2294 2295 static void 2296 amdgpu_pci_shutdown(struct pci_dev *pdev) 2297 { 2298 struct drm_device *dev = pci_get_drvdata(pdev); 2299 struct amdgpu_device *adev = drm_to_adev(dev); 2300 2301 if (amdgpu_ras_intr_triggered()) 2302 return; 2303 2304 /* if we are running in a VM, make sure the device 2305 * torn down properly on reboot/shutdown. 2306 * unfortunately we can't detect certain 2307 * hypervisors so just do this all the time. 2308 */ 2309 if (!amdgpu_passthrough(adev)) 2310 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2311 amdgpu_device_ip_suspend(adev); 2312 adev->mp1_state = PP_MP1_STATE_NONE; 2313 } 2314 #endif 2315 2316 /** 2317 * amdgpu_drv_delayed_reset_work_handler - work handler for reset 2318 * 2319 * @work: work_struct. 2320 */ 2321 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) 2322 { 2323 struct list_head device_list; 2324 struct amdgpu_device *adev; 2325 int i, r; 2326 struct amdgpu_reset_context reset_context; 2327 2328 memset(&reset_context, 0, sizeof(reset_context)); 2329 2330 mutex_lock(&mgpu_info.mutex); 2331 if (mgpu_info.pending_reset == true) { 2332 mutex_unlock(&mgpu_info.mutex); 2333 return; 2334 } 2335 mgpu_info.pending_reset = true; 2336 mutex_unlock(&mgpu_info.mutex); 2337 2338 /* Use a common context, just need to make sure full reset is done */ 2339 reset_context.method = AMD_RESET_METHOD_NONE; 2340 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 2341 2342 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2343 adev = mgpu_info.gpu_ins[i].adev; 2344 reset_context.reset_req_dev = adev; 2345 r = amdgpu_device_pre_asic_reset(adev, &reset_context); 2346 if (r) { 2347 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", 2348 r, adev_to_drm(adev)->unique); 2349 } 2350 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) 2351 r = -EALREADY; 2352 } 2353 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2354 adev = mgpu_info.gpu_ins[i].adev; 2355 flush_work(&adev->xgmi_reset_work); 2356 adev->gmc.xgmi.pending_reset = false; 2357 } 2358 2359 /* reset function will rebuild the xgmi hive info , clear it now */ 2360 for (i = 0; i < mgpu_info.num_dgpu; i++) 2361 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); 2362 2363 INIT_LIST_HEAD(&device_list); 2364 2365 for (i = 0; i < mgpu_info.num_dgpu; i++) 2366 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); 2367 2368 /* unregister the GPU first, reset function will add them back */ 2369 list_for_each_entry(adev, &device_list, reset_list) 2370 amdgpu_unregister_gpu_instance(adev); 2371 2372 /* Use a common context, just need to make sure full reset is done */ 2373 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); 2374 r = amdgpu_do_asic_reset(&device_list, &reset_context); 2375 2376 if (r) { 2377 DRM_ERROR("reinit gpus failure"); 2378 return; 2379 } 2380 for (i = 0; i < mgpu_info.num_dgpu; i++) { 2381 adev = mgpu_info.gpu_ins[i].adev; 2382 if (!adev->kfd.init_complete) 2383 amdgpu_amdkfd_device_init(adev); 2384 amdgpu_ttm_set_buffer_funcs_status(adev, true); 2385 } 2386 return; 2387 } 2388 2389 #ifdef notyet 2390 2391 static int amdgpu_pmops_prepare(struct device *dev) 2392 { 2393 struct drm_device *drm_dev = dev_get_drvdata(dev); 2394 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2395 2396 /* Return a positive number here so 2397 * DPM_FLAG_SMART_SUSPEND works properly 2398 */ 2399 if (amdgpu_device_supports_boco(drm_dev)) 2400 return pm_runtime_suspended(dev); 2401 2402 /* if we will not support s3 or s2i for the device 2403 * then skip suspend 2404 */ 2405 if (!amdgpu_acpi_is_s0ix_active(adev) && 2406 !amdgpu_acpi_is_s3_active(adev)) 2407 return 1; 2408 2409 return 0; 2410 } 2411 2412 static void amdgpu_pmops_complete(struct device *dev) 2413 { 2414 /* nothing to do */ 2415 } 2416 2417 static int amdgpu_pmops_suspend(struct device *dev) 2418 { 2419 struct drm_device *drm_dev = dev_get_drvdata(dev); 2420 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2421 2422 if (amdgpu_acpi_is_s0ix_active(adev)) 2423 adev->in_s0ix = true; 2424 else if (amdgpu_acpi_is_s3_active(adev)) 2425 adev->in_s3 = true; 2426 if (!adev->in_s0ix && !adev->in_s3) 2427 return 0; 2428 return amdgpu_device_suspend(drm_dev, true); 2429 } 2430 2431 static int amdgpu_pmops_suspend_noirq(struct device *dev) 2432 { 2433 struct drm_device *drm_dev = dev_get_drvdata(dev); 2434 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2435 2436 if (amdgpu_acpi_should_gpu_reset(adev)) 2437 return amdgpu_asic_reset(adev); 2438 2439 return 0; 2440 } 2441 2442 static int amdgpu_pmops_resume(struct device *dev) 2443 { 2444 struct drm_device *drm_dev = dev_get_drvdata(dev); 2445 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2446 int r; 2447 2448 if (!adev->in_s0ix && !adev->in_s3) 2449 return 0; 2450 2451 /* Avoids registers access if device is physically gone */ 2452 if (!pci_device_is_present(adev->pdev)) 2453 adev->no_hw_access = true; 2454 2455 r = amdgpu_device_resume(drm_dev, true); 2456 if (amdgpu_acpi_is_s0ix_active(adev)) 2457 adev->in_s0ix = false; 2458 else 2459 adev->in_s3 = false; 2460 return r; 2461 } 2462 2463 static int amdgpu_pmops_freeze(struct device *dev) 2464 { 2465 struct drm_device *drm_dev = dev_get_drvdata(dev); 2466 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2467 int r; 2468 2469 adev->in_s4 = true; 2470 r = amdgpu_device_suspend(drm_dev, true); 2471 adev->in_s4 = false; 2472 if (r) 2473 return r; 2474 2475 if (amdgpu_acpi_should_gpu_reset(adev)) 2476 return amdgpu_asic_reset(adev); 2477 return 0; 2478 } 2479 2480 static int amdgpu_pmops_thaw(struct device *dev) 2481 { 2482 struct drm_device *drm_dev = dev_get_drvdata(dev); 2483 2484 return amdgpu_device_resume(drm_dev, true); 2485 } 2486 2487 static int amdgpu_pmops_poweroff(struct device *dev) 2488 { 2489 struct drm_device *drm_dev = dev_get_drvdata(dev); 2490 2491 return amdgpu_device_suspend(drm_dev, true); 2492 } 2493 2494 static int amdgpu_pmops_restore(struct device *dev) 2495 { 2496 struct drm_device *drm_dev = dev_get_drvdata(dev); 2497 2498 return amdgpu_device_resume(drm_dev, true); 2499 } 2500 2501 static int amdgpu_runtime_idle_check_display(struct device *dev) 2502 { 2503 struct pci_dev *pdev = to_pci_dev(dev); 2504 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2505 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2506 2507 if (adev->mode_info.num_crtc) { 2508 struct drm_connector *list_connector; 2509 struct drm_connector_list_iter iter; 2510 int ret = 0; 2511 2512 /* XXX: Return busy if any displays are connected to avoid 2513 * possible display wakeups after runtime resume due to 2514 * hotplug events in case any displays were connected while 2515 * the GPU was in suspend. Remove this once that is fixed. 2516 */ 2517 mutex_lock(&drm_dev->mode_config.mutex); 2518 drm_connector_list_iter_begin(drm_dev, &iter); 2519 drm_for_each_connector_iter(list_connector, &iter) { 2520 if (list_connector->status == connector_status_connected) { 2521 ret = -EBUSY; 2522 break; 2523 } 2524 } 2525 drm_connector_list_iter_end(&iter); 2526 mutex_unlock(&drm_dev->mode_config.mutex); 2527 2528 if (ret) 2529 return ret; 2530 2531 if (amdgpu_device_has_dc_support(adev)) { 2532 struct drm_crtc *crtc; 2533 2534 drm_for_each_crtc(crtc, drm_dev) { 2535 drm_modeset_lock(&crtc->mutex, NULL); 2536 if (crtc->state->active) 2537 ret = -EBUSY; 2538 drm_modeset_unlock(&crtc->mutex); 2539 if (ret < 0) 2540 break; 2541 } 2542 } else { 2543 mutex_lock(&drm_dev->mode_config.mutex); 2544 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2545 2546 drm_connector_list_iter_begin(drm_dev, &iter); 2547 drm_for_each_connector_iter(list_connector, &iter) { 2548 if (list_connector->dpms == DRM_MODE_DPMS_ON) { 2549 ret = -EBUSY; 2550 break; 2551 } 2552 } 2553 2554 drm_connector_list_iter_end(&iter); 2555 2556 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2557 mutex_unlock(&drm_dev->mode_config.mutex); 2558 } 2559 if (ret) 2560 return ret; 2561 } 2562 2563 return 0; 2564 } 2565 2566 static int amdgpu_pmops_runtime_suspend(struct device *dev) 2567 { 2568 struct pci_dev *pdev = to_pci_dev(dev); 2569 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2570 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2571 int ret, i; 2572 2573 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2574 pm_runtime_forbid(dev); 2575 return -EBUSY; 2576 } 2577 2578 ret = amdgpu_runtime_idle_check_display(dev); 2579 if (ret) 2580 return ret; 2581 2582 /* wait for all rings to drain before suspending */ 2583 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 2584 struct amdgpu_ring *ring = adev->rings[i]; 2585 if (ring && ring->sched.ready) { 2586 ret = amdgpu_fence_wait_empty(ring); 2587 if (ret) 2588 return -EBUSY; 2589 } 2590 } 2591 2592 adev->in_runpm = true; 2593 if (amdgpu_device_supports_px(drm_dev)) 2594 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2595 2596 /* 2597 * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some 2598 * proper cleanups and put itself into a state ready for PNP. That 2599 * can address some random resuming failure observed on BOCO capable 2600 * platforms. 2601 * TODO: this may be also needed for PX capable platform. 2602 */ 2603 if (amdgpu_device_supports_boco(drm_dev)) 2604 adev->mp1_state = PP_MP1_STATE_UNLOAD; 2605 2606 ret = amdgpu_device_suspend(drm_dev, false); 2607 if (ret) { 2608 adev->in_runpm = false; 2609 if (amdgpu_device_supports_boco(drm_dev)) 2610 adev->mp1_state = PP_MP1_STATE_NONE; 2611 return ret; 2612 } 2613 2614 if (amdgpu_device_supports_boco(drm_dev)) 2615 adev->mp1_state = PP_MP1_STATE_NONE; 2616 2617 if (amdgpu_device_supports_px(drm_dev)) { 2618 /* Only need to handle PCI state in the driver for ATPX 2619 * PCI core handles it for _PR3. 2620 */ 2621 amdgpu_device_cache_pci_state(pdev); 2622 pci_disable_device(pdev); 2623 pci_ignore_hotplug(pdev); 2624 pci_set_power_state(pdev, PCI_D3cold); 2625 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 2626 } else if (amdgpu_device_supports_boco(drm_dev)) { 2627 /* nothing to do */ 2628 } else if (amdgpu_device_supports_baco(drm_dev)) { 2629 amdgpu_device_baco_enter(drm_dev); 2630 } 2631 2632 return 0; 2633 } 2634 2635 static int amdgpu_pmops_runtime_resume(struct device *dev) 2636 { 2637 struct pci_dev *pdev = to_pci_dev(dev); 2638 struct drm_device *drm_dev = pci_get_drvdata(pdev); 2639 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2640 int ret; 2641 2642 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) 2643 return -EINVAL; 2644 2645 /* Avoids registers access if device is physically gone */ 2646 if (!pci_device_is_present(adev->pdev)) 2647 adev->no_hw_access = true; 2648 2649 if (amdgpu_device_supports_px(drm_dev)) { 2650 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 2651 2652 /* Only need to handle PCI state in the driver for ATPX 2653 * PCI core handles it for _PR3. 2654 */ 2655 pci_set_power_state(pdev, PCI_D0); 2656 amdgpu_device_load_pci_state(pdev); 2657 ret = pci_enable_device(pdev); 2658 if (ret) 2659 return ret; 2660 pci_set_master(pdev); 2661 } else if (amdgpu_device_supports_boco(drm_dev)) { 2662 /* Only need to handle PCI state in the driver for ATPX 2663 * PCI core handles it for _PR3. 2664 */ 2665 pci_set_master(pdev); 2666 } else if (amdgpu_device_supports_baco(drm_dev)) { 2667 amdgpu_device_baco_exit(drm_dev); 2668 } 2669 ret = amdgpu_device_resume(drm_dev, false); 2670 if (ret) { 2671 if (amdgpu_device_supports_px(drm_dev)) 2672 pci_disable_device(pdev); 2673 return ret; 2674 } 2675 2676 if (amdgpu_device_supports_px(drm_dev)) 2677 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 2678 adev->in_runpm = false; 2679 return 0; 2680 } 2681 2682 static int amdgpu_pmops_runtime_idle(struct device *dev) 2683 { 2684 struct drm_device *drm_dev = dev_get_drvdata(dev); 2685 struct amdgpu_device *adev = drm_to_adev(drm_dev); 2686 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 2687 int ret = 1; 2688 2689 if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { 2690 pm_runtime_forbid(dev); 2691 return -EBUSY; 2692 } 2693 2694 ret = amdgpu_runtime_idle_check_display(dev); 2695 2696 pm_runtime_mark_last_busy(dev); 2697 pm_runtime_autosuspend(dev); 2698 return ret; 2699 } 2700 #endif /* notyet */ 2701 2702 #ifdef __linux__ 2703 long amdgpu_drm_ioctl(struct file *filp, 2704 unsigned int cmd, unsigned long arg) 2705 { 2706 struct drm_file *file_priv = filp->private_data; 2707 struct drm_device *dev; 2708 long ret; 2709 dev = file_priv->minor->dev; 2710 ret = pm_runtime_get_sync(dev->dev); 2711 if (ret < 0) 2712 goto out; 2713 2714 ret = drm_ioctl(filp, cmd, arg); 2715 2716 pm_runtime_mark_last_busy(dev->dev); 2717 out: 2718 pm_runtime_put_autosuspend(dev->dev); 2719 return ret; 2720 } 2721 2722 static const struct dev_pm_ops amdgpu_pm_ops = { 2723 .prepare = amdgpu_pmops_prepare, 2724 .complete = amdgpu_pmops_complete, 2725 .suspend = amdgpu_pmops_suspend, 2726 .suspend_noirq = amdgpu_pmops_suspend_noirq, 2727 .resume = amdgpu_pmops_resume, 2728 .freeze = amdgpu_pmops_freeze, 2729 .thaw = amdgpu_pmops_thaw, 2730 .poweroff = amdgpu_pmops_poweroff, 2731 .restore = amdgpu_pmops_restore, 2732 .runtime_suspend = amdgpu_pmops_runtime_suspend, 2733 .runtime_resume = amdgpu_pmops_runtime_resume, 2734 .runtime_idle = amdgpu_pmops_runtime_idle, 2735 }; 2736 2737 static int amdgpu_flush(struct file *f, fl_owner_t id) 2738 { 2739 struct drm_file *file_priv = f->private_data; 2740 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 2741 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 2742 2743 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 2744 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 2745 2746 return timeout >= 0 ? 0 : timeout; 2747 } 2748 2749 static const struct file_operations amdgpu_driver_kms_fops = { 2750 .owner = THIS_MODULE, 2751 .open = drm_open, 2752 .flush = amdgpu_flush, 2753 .release = drm_release, 2754 .unlocked_ioctl = amdgpu_drm_ioctl, 2755 .mmap = drm_gem_mmap, 2756 .poll = drm_poll, 2757 .read = drm_read, 2758 #ifdef CONFIG_COMPAT 2759 .compat_ioctl = amdgpu_kms_compat_ioctl, 2760 #endif 2761 #ifdef CONFIG_PROC_FS 2762 .show_fdinfo = amdgpu_show_fdinfo 2763 #endif 2764 }; 2765 2766 #endif /* __linux__ */ 2767 2768 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 2769 { 2770 STUB(); 2771 return -ENOSYS; 2772 #ifdef notyet 2773 struct drm_file *file; 2774 2775 if (!filp) 2776 return -EINVAL; 2777 2778 if (filp->f_op != &amdgpu_driver_kms_fops) { 2779 return -EINVAL; 2780 } 2781 2782 file = filp->private_data; 2783 *fpriv = file->driver_priv; 2784 return 0; 2785 #endif 2786 } 2787 2788 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 2789 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2790 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2791 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2792 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER), 2793 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2794 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2795 /* KMS */ 2796 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2797 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2798 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2799 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2800 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2801 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2802 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2803 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2804 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2805 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 2806 }; 2807 2808 static const struct drm_driver amdgpu_kms_driver = { 2809 .driver_features = 2810 DRIVER_ATOMIC | 2811 DRIVER_GEM | 2812 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 2813 DRIVER_SYNCOBJ_TIMELINE, 2814 .open = amdgpu_driver_open_kms, 2815 #ifdef __OpenBSD__ 2816 .mmap = drm_gem_mmap, 2817 #endif 2818 .postclose = amdgpu_driver_postclose_kms, 2819 .lastclose = amdgpu_driver_lastclose_kms, 2820 .ioctls = amdgpu_ioctls_kms, 2821 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), 2822 .dumb_create = amdgpu_mode_dumb_create, 2823 .dumb_map_offset = amdgpu_mode_dumb_mmap, 2824 #ifdef __linux__ 2825 .fops = &amdgpu_driver_kms_fops, 2826 #endif 2827 .release = &amdgpu_driver_release_kms, 2828 2829 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 2830 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 2831 .gem_prime_import = amdgpu_gem_prime_import, 2832 #ifdef notyet 2833 .gem_prime_mmap = drm_gem_prime_mmap, 2834 #endif 2835 2836 .name = DRIVER_NAME, 2837 .desc = DRIVER_DESC, 2838 .date = DRIVER_DATE, 2839 .major = KMS_DRIVER_MAJOR, 2840 .minor = KMS_DRIVER_MINOR, 2841 .patchlevel = KMS_DRIVER_PATCHLEVEL, 2842 }; 2843 2844 #ifdef __linux__ 2845 static struct pci_error_handlers amdgpu_pci_err_handler = { 2846 .error_detected = amdgpu_pci_error_detected, 2847 .mmio_enabled = amdgpu_pci_mmio_enabled, 2848 .slot_reset = amdgpu_pci_slot_reset, 2849 .resume = amdgpu_pci_resume, 2850 }; 2851 2852 extern const struct attribute_group amdgpu_vram_mgr_attr_group; 2853 extern const struct attribute_group amdgpu_gtt_mgr_attr_group; 2854 extern const struct attribute_group amdgpu_vbios_version_attr_group; 2855 2856 static const struct attribute_group *amdgpu_sysfs_groups[] = { 2857 &amdgpu_vram_mgr_attr_group, 2858 &amdgpu_gtt_mgr_attr_group, 2859 &amdgpu_vbios_version_attr_group, 2860 NULL, 2861 }; 2862 2863 2864 static struct pci_driver amdgpu_kms_pci_driver = { 2865 .name = DRIVER_NAME, 2866 .id_table = pciidlist, 2867 .probe = amdgpu_pci_probe, 2868 .remove = amdgpu_pci_remove, 2869 .shutdown = amdgpu_pci_shutdown, 2870 .driver.pm = &amdgpu_pm_ops, 2871 .err_handler = &amdgpu_pci_err_handler, 2872 .dev_groups = amdgpu_sysfs_groups, 2873 }; 2874 2875 static int __init amdgpu_init(void) 2876 { 2877 int r; 2878 2879 if (drm_firmware_drivers_only()) 2880 return -EINVAL; 2881 2882 r = amdgpu_sync_init(); 2883 if (r) 2884 goto error_sync; 2885 2886 r = amdgpu_fence_slab_init(); 2887 if (r) 2888 goto error_fence; 2889 2890 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 2891 amdgpu_register_atpx_handler(); 2892 amdgpu_acpi_detect(); 2893 2894 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 2895 amdgpu_amdkfd_init(); 2896 2897 /* let modprobe override vga console setting */ 2898 return pci_register_driver(&amdgpu_kms_pci_driver); 2899 2900 error_fence: 2901 amdgpu_sync_fini(); 2902 2903 error_sync: 2904 return r; 2905 } 2906 2907 static void __exit amdgpu_exit(void) 2908 { 2909 amdgpu_amdkfd_fini(); 2910 pci_unregister_driver(&amdgpu_kms_pci_driver); 2911 amdgpu_unregister_atpx_handler(); 2912 amdgpu_sync_fini(); 2913 amdgpu_fence_slab_fini(); 2914 mmu_notifier_synchronize(); 2915 } 2916 2917 module_init(amdgpu_init); 2918 module_exit(amdgpu_exit); 2919 2920 MODULE_AUTHOR(DRIVER_AUTHOR); 2921 MODULE_DESCRIPTION(DRIVER_DESC); 2922 MODULE_LICENSE("GPL and additional rights"); 2923 #endif /* __linux__ */ 2924 2925 #include <drm/drm_drv.h> 2926 #include <drm/drm_utils.h> 2927 2928 #include "vga.h" 2929 2930 #if NVGA > 0 2931 #include <dev/ic/mc6845reg.h> 2932 #include <dev/ic/pcdisplayvar.h> 2933 #include <dev/ic/vgareg.h> 2934 #include <dev/ic/vgavar.h> 2935 2936 extern int vga_console_attached; 2937 #endif 2938 2939 #ifdef __amd64__ 2940 #include "efifb.h" 2941 #include <machine/biosvar.h> 2942 #endif 2943 2944 #if NEFIFB > 0 2945 #include <machine/efifbvar.h> 2946 #endif 2947 2948 int amdgpu_probe(struct device *, void *, void *); 2949 void amdgpu_attach(struct device *, struct device *, void *); 2950 int amdgpu_detach(struct device *, int); 2951 int amdgpu_activate(struct device *, int); 2952 void amdgpu_attachhook(struct device *); 2953 int amdgpu_forcedetach(struct amdgpu_device *); 2954 2955 bool amdgpu_msi_ok(struct amdgpu_device *); 2956 2957 /* 2958 * set if the mountroot hook has a fatal error 2959 * such as not being able to find the firmware 2960 */ 2961 int amdgpu_fatal_error; 2962 2963 const struct cfattach amdgpu_ca = { 2964 sizeof (struct amdgpu_device), amdgpu_probe, amdgpu_attach, 2965 amdgpu_detach, amdgpu_activate 2966 }; 2967 2968 struct cfdriver amdgpu_cd = { 2969 NULL, "amdgpu", DV_DULL 2970 }; 2971 2972 int 2973 amdgpu_probe(struct device *parent, void *match, void *aux) 2974 { 2975 struct pci_attach_args *pa = aux; 2976 const struct pci_device_id *id_entry; 2977 unsigned long flags = 0; 2978 int i; 2979 2980 if (amdgpu_fatal_error) 2981 return 0; 2982 2983 id_entry = drm_find_description(PCI_VENDOR(pa->pa_id), 2984 PCI_PRODUCT(pa->pa_id), pciidlist); 2985 if (id_entry != NULL) { 2986 flags = id_entry->driver_data; 2987 2988 if (id_entry->device == PCI_ANY_ID) { 2989 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY) 2990 return 0; 2991 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA && 2992 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_MISC) 2993 return 0; 2994 } 2995 2996 /* skip devices which are owned by radeon */ 2997 for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist); i++) { 2998 if (amdgpu_unsupported_pciidlist[i] == 2999 PCI_PRODUCT(pa->pa_id)) 3000 return 0; 3001 } 3002 3003 if (flags & AMD_EXP_HW_SUPPORT) 3004 return 0; 3005 else 3006 return 20; 3007 } 3008 3009 return 0; 3010 } 3011 3012 /* 3013 * some functions are only called once on init regardless of how many times 3014 * amdgpu attaches in linux this is handled via module_init()/module_exit() 3015 */ 3016 int amdgpu_refcnt; 3017 3018 int __init drm_sched_fence_slab_init(void); 3019 void __exit drm_sched_fence_slab_fini(void); 3020 irqreturn_t amdgpu_irq_handler(void *); 3021 3022 void 3023 amdgpu_attach(struct device *parent, struct device *self, void *aux) 3024 { 3025 struct amdgpu_device *adev = (struct amdgpu_device *)self; 3026 struct drm_device *dev; 3027 struct pci_attach_args *pa = aux; 3028 const struct pci_device_id *id_entry; 3029 pcireg_t type; 3030 int i; 3031 uint8_t rmmio_bar; 3032 paddr_t fb_aper; 3033 pcireg_t addr, mask; 3034 int s; 3035 bool supports_atomic = false; 3036 3037 id_entry = drm_find_description(PCI_VENDOR(pa->pa_id), 3038 PCI_PRODUCT(pa->pa_id), pciidlist); 3039 adev->flags = id_entry->driver_data; 3040 adev->family = adev->flags & AMD_ASIC_MASK; 3041 adev->pc = pa->pa_pc; 3042 adev->pa_tag = pa->pa_tag; 3043 adev->iot = pa->pa_iot; 3044 adev->memt = pa->pa_memt; 3045 adev->dmat = pa->pa_dmat; 3046 3047 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && 3048 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA && 3049 (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) 3050 & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 3051 == (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) { 3052 adev->primary = 1; 3053 #if NVGA > 0 3054 adev->console = vga_is_console(pa->pa_iot, -1); 3055 vga_console_attached = 1; 3056 #endif 3057 } 3058 #if NEFIFB > 0 3059 if (efifb_is_primary(pa)) { 3060 adev->primary = 1; 3061 adev->console = efifb_is_console(pa); 3062 efifb_detach(); 3063 } 3064 #endif 3065 3066 #define AMDGPU_PCI_MEM 0x10 3067 3068 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM); 3069 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 3070 pci_mapreg_info(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM, 3071 type, &adev->fb_aper_offset, &adev->fb_aper_size, NULL)) { 3072 printf(": can't get frambuffer info\n"); 3073 return; 3074 } 3075 3076 if (adev->fb_aper_offset == 0) { 3077 bus_size_t start, end, pci_mem_end; 3078 bus_addr_t base; 3079 3080 KASSERT(pa->pa_memex != NULL); 3081 3082 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 3083 if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT) 3084 pci_mem_end = PCI_MEM64_END; 3085 else 3086 pci_mem_end = PCI_MEM_END; 3087 end = min(pci_mem_end, pa->pa_memex->ex_end); 3088 if (extent_alloc_subregion(pa->pa_memex, start, end, 3089 adev->fb_aper_size, adev->fb_aper_size, 0, 0, 0, &base)) { 3090 printf(": can't reserve framebuffer space\n"); 3091 return; 3092 } 3093 pci_conf_write(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM, base); 3094 if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT) 3095 pci_conf_write(pa->pa_pc, pa->pa_tag, 3096 AMDGPU_PCI_MEM + 4, (uint64_t)base >> 32); 3097 adev->fb_aper_offset = base; 3098 } 3099 3100 if (adev->family >= CHIP_BONAIRE) { 3101 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x18); 3102 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 3103 pci_mapreg_map(pa, 0x18, type, BUS_SPACE_MAP_LINEAR, 3104 &adev->doorbell.bst, &adev->doorbell.bsh, 3105 &adev->doorbell.base, &adev->doorbell.size, 0)) { 3106 printf(": can't map doorbell space\n"); 3107 return; 3108 } 3109 adev->doorbell.ptr = bus_space_vaddr(adev->doorbell.bst, 3110 adev->doorbell.bsh); 3111 } 3112 3113 if (adev->family >= CHIP_BONAIRE) 3114 rmmio_bar = 0x24; 3115 else 3116 rmmio_bar = 0x18; 3117 3118 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, rmmio_bar); 3119 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 3120 pci_mapreg_map(pa, rmmio_bar, type, BUS_SPACE_MAP_LINEAR, 3121 &adev->rmmio_bst, &adev->rmmio_bsh, &adev->rmmio_base, 3122 &adev->rmmio_size, 0)) { 3123 printf(": can't map rmmio space\n"); 3124 return; 3125 } 3126 adev->rmmio = bus_space_vaddr(adev->rmmio_bst, adev->rmmio_bsh); 3127 3128 /* 3129 * Make sure we have a base address for the ROM such that we 3130 * can map it later. 3131 */ 3132 s = splhigh(); 3133 addr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 3134 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 3135 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 3136 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, addr); 3137 splx(s); 3138 3139 if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) { 3140 bus_size_t size, start, end; 3141 bus_addr_t base; 3142 3143 size = PCI_ROM_SIZE(mask); 3144 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 3145 end = min(PCI_MEM_END, pa->pa_memex->ex_end); 3146 if (extent_alloc_subregion(pa->pa_memex, start, end, size, 3147 size, 0, 0, 0, &base) == 0) 3148 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, base); 3149 } 3150 3151 printf("\n"); 3152 3153 /* from amdgpu_pci_probe(), aspm test done later */ 3154 3155 if (!amdgpu_virtual_display && 3156 amdgpu_device_asic_has_dc_support(adev->family)) 3157 supports_atomic = true; 3158 3159 if ((adev->flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 3160 DRM_INFO("This hardware requires experimental hardware support.\n"); 3161 return; 3162 } 3163 3164 /* 3165 * Initialize amdkfd before starting radeon. 3166 */ 3167 amdgpu_amdkfd_init(); 3168 3169 dev = drm_attach_pci(&amdgpu_kms_driver, pa, 0, adev->primary, 3170 self, &adev->ddev); 3171 if (dev == NULL) { 3172 printf("%s: drm attach failed\n", adev->self.dv_xname); 3173 return; 3174 } 3175 adev->pdev = dev->pdev; 3176 3177 /* from amdgpu_pci_probe() */ 3178 if (amdgpu_aspm == -1 && !pcie_aspm_enabled(adev->pdev)) 3179 amdgpu_aspm = 0; 3180 3181 if (!supports_atomic) 3182 dev->driver_features &= ~DRIVER_ATOMIC; 3183 3184 if (!amdgpu_msi_ok(adev)) 3185 pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 3186 3187 /* from amdgpu_init() */ 3188 if (amdgpu_refcnt == 0) { 3189 drm_sched_fence_slab_init(); 3190 3191 if (amdgpu_sync_init()) { 3192 printf("%s: amdgpu_sync_init failed\n", 3193 adev->self.dv_xname); 3194 return; 3195 } 3196 3197 if (amdgpu_fence_slab_init()) { 3198 amdgpu_sync_fini(); 3199 printf("%s: amdgpu_fence_slab_init failed\n", 3200 adev->self.dv_xname); 3201 return; 3202 } 3203 3204 amdgpu_register_atpx_handler(); 3205 amdgpu_acpi_detect(); 3206 } 3207 amdgpu_refcnt++; 3208 3209 adev->irq.msi_enabled = false; 3210 if (pci_intr_map_msi(pa, &adev->intrh) == 0) 3211 adev->irq.msi_enabled = true; 3212 else if (pci_intr_map(pa, &adev->intrh) != 0) { 3213 printf("%s: couldn't map interrupt\n", adev->self.dv_xname); 3214 return; 3215 } 3216 printf("%s: %s\n", adev->self.dv_xname, 3217 pci_intr_string(pa->pa_pc, adev->intrh)); 3218 3219 adev->irqh = pci_intr_establish(pa->pa_pc, adev->intrh, IPL_TTY, 3220 amdgpu_irq_handler, &adev->ddev, adev->self.dv_xname); 3221 if (adev->irqh == NULL) { 3222 printf("%s: couldn't establish interrupt\n", 3223 adev->self.dv_xname); 3224 return; 3225 } 3226 adev->pdev->irq = 0; 3227 3228 fb_aper = bus_space_mmap(adev->memt, adev->fb_aper_offset, 0, 0, 0); 3229 if (fb_aper != -1) 3230 rasops_claim_framebuffer(fb_aper, adev->fb_aper_size, self); 3231 3232 3233 adev->shutdown = true; 3234 config_mountroot(self, amdgpu_attachhook); 3235 } 3236 3237 int 3238 amdgpu_forcedetach(struct amdgpu_device *adev) 3239 { 3240 struct pci_softc *sc = (struct pci_softc *)adev->self.dv_parent; 3241 pcitag_t tag = adev->pa_tag; 3242 3243 #if NVGA > 0 3244 if (adev->primary) 3245 vga_console_attached = 0; 3246 #endif 3247 3248 /* reprobe pci device for non efi systems */ 3249 #if NEFIFB > 0 3250 if (bios_efiinfo == NULL && !efifb_cb_found()) { 3251 #endif 3252 config_detach(&adev->self, 0); 3253 return pci_probe_device(sc, tag, NULL, NULL); 3254 #if NEFIFB > 0 3255 } else if (adev->primary) { 3256 efifb_reattach(); 3257 } 3258 #endif 3259 3260 return 0; 3261 } 3262 3263 void amdgpu_burner(void *, u_int, u_int); 3264 void amdgpu_burner_cb(void *); 3265 int amdgpu_wsioctl(void *, u_long, caddr_t, int, struct proc *); 3266 paddr_t amdgpu_wsmmap(void *, off_t, int); 3267 int amdgpu_alloc_screen(void *, const struct wsscreen_descr *, 3268 void **, int *, int *, uint32_t *); 3269 void amdgpu_free_screen(void *, void *); 3270 int amdgpu_show_screen(void *, void *, int, 3271 void (*)(void *, int, int), void *); 3272 void amdgpu_doswitch(void *); 3273 void amdgpu_enter_ddb(void *, void *); 3274 3275 struct wsscreen_descr amdgpu_stdscreen = { 3276 "std", 3277 0, 0, 3278 0, 3279 0, 0, 3280 WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 3281 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS 3282 }; 3283 3284 const struct wsscreen_descr *amdgpu_scrlist[] = { 3285 &amdgpu_stdscreen, 3286 }; 3287 3288 struct wsscreen_list amdgpu_screenlist = { 3289 nitems(amdgpu_scrlist), amdgpu_scrlist 3290 }; 3291 3292 struct wsdisplay_accessops amdgpu_accessops = { 3293 .ioctl = amdgpu_wsioctl, 3294 .mmap = amdgpu_wsmmap, 3295 .alloc_screen = amdgpu_alloc_screen, 3296 .free_screen = amdgpu_free_screen, 3297 .show_screen = amdgpu_show_screen, 3298 .enter_ddb = amdgpu_enter_ddb, 3299 .getchar = rasops_getchar, 3300 .load_font = rasops_load_font, 3301 .list_font = rasops_list_font, 3302 .scrollback = rasops_scrollback, 3303 .burn_screen = amdgpu_burner 3304 }; 3305 3306 int 3307 amdgpu_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 3308 { 3309 struct rasops_info *ri = v; 3310 struct amdgpu_device *adev = ri->ri_hw; 3311 struct backlight_device *bd = adev->dm.backlight_dev[0]; 3312 struct wsdisplay_param *dp = (struct wsdisplay_param *)data; 3313 struct wsdisplay_fbinfo *wdf; 3314 3315 switch (cmd) { 3316 case WSDISPLAYIO_GTYPE: 3317 *(u_int *)data = WSDISPLAY_TYPE_RADEONDRM; 3318 return 0; 3319 case WSDISPLAYIO_GINFO: 3320 wdf = (struct wsdisplay_fbinfo *)data; 3321 wdf->width = ri->ri_width; 3322 wdf->height = ri->ri_height; 3323 wdf->depth = ri->ri_depth; 3324 wdf->stride = ri->ri_stride; 3325 wdf->offset = 0; 3326 wdf->cmsize = 0; 3327 return 0; 3328 case WSDISPLAYIO_GETPARAM: 3329 if (bd == NULL) 3330 return -1; 3331 3332 switch (dp->param) { 3333 case WSDISPLAYIO_PARAM_BRIGHTNESS: 3334 dp->min = 0; 3335 dp->max = bd->props.max_brightness; 3336 dp->curval = bd->props.brightness; 3337 return (dp->max > dp->min) ? 0 : -1; 3338 } 3339 break; 3340 case WSDISPLAYIO_SETPARAM: 3341 if (bd == NULL || dp->curval > bd->props.max_brightness) 3342 return -1; 3343 3344 switch (dp->param) { 3345 case WSDISPLAYIO_PARAM_BRIGHTNESS: 3346 bd->props.brightness = dp->curval; 3347 backlight_update_status(bd); 3348 knote_locked(&adev->ddev.note, NOTE_CHANGE); 3349 return 0; 3350 } 3351 break; 3352 case WSDISPLAYIO_SVIDEO: 3353 case WSDISPLAYIO_GVIDEO: 3354 return 0; 3355 } 3356 3357 return (-1); 3358 } 3359 3360 paddr_t 3361 amdgpu_wsmmap(void *v, off_t off, int prot) 3362 { 3363 return (-1); 3364 } 3365 3366 int 3367 amdgpu_alloc_screen(void *v, const struct wsscreen_descr *type, 3368 void **cookiep, int *curxp, int *curyp, uint32_t *attrp) 3369 { 3370 return rasops_alloc_screen(v, cookiep, curxp, curyp, attrp); 3371 } 3372 3373 void 3374 amdgpu_free_screen(void *v, void *cookie) 3375 { 3376 return rasops_free_screen(v, cookie); 3377 } 3378 3379 int 3380 amdgpu_show_screen(void *v, void *cookie, int waitok, 3381 void (*cb)(void *, int, int), void *cbarg) 3382 { 3383 struct rasops_info *ri = v; 3384 struct amdgpu_device *adev = ri->ri_hw; 3385 3386 if (cookie == ri->ri_active) 3387 return (0); 3388 3389 adev->switchcb = cb; 3390 adev->switchcbarg = cbarg; 3391 adev->switchcookie = cookie; 3392 if (cb) { 3393 task_add(systq, &adev->switchtask); 3394 return (EAGAIN); 3395 } 3396 3397 amdgpu_doswitch(v); 3398 3399 return (0); 3400 } 3401 3402 void 3403 amdgpu_doswitch(void *v) 3404 { 3405 struct rasops_info *ri = v; 3406 struct amdgpu_device *adev = ri->ri_hw; 3407 struct amdgpu_crtc *amdgpu_crtc; 3408 int i, crtc; 3409 3410 rasops_show_screen(ri, adev->switchcookie, 0, NULL, NULL); 3411 drm_fb_helper_restore_fbdev_mode_unlocked(adev_to_drm(adev)->fb_helper); 3412 3413 if (adev->switchcb) 3414 (adev->switchcb)(adev->switchcbarg, 0, 0); 3415 } 3416 3417 void 3418 amdgpu_enter_ddb(void *v, void *cookie) 3419 { 3420 struct rasops_info *ri = v; 3421 struct amdgpu_device *adev = ri->ri_hw; 3422 struct drm_fb_helper *fb_helper = adev_to_drm(adev)->fb_helper; 3423 3424 if (cookie == ri->ri_active) 3425 return; 3426 3427 rasops_show_screen(ri, cookie, 0, NULL, NULL); 3428 drm_fb_helper_debug_enter(fb_helper->fbdev); 3429 } 3430 3431 void 3432 amdgpu_init_backlight(struct amdgpu_device *adev) 3433 { 3434 struct drm_device *dev = &adev->ddev; 3435 struct backlight_device *bd = adev->dm.backlight_dev[0]; 3436 struct drm_connector_list_iter conn_iter; 3437 struct drm_connector *connector; 3438 3439 if (bd == NULL) 3440 return; 3441 3442 drm_connector_list_iter_begin(dev, &conn_iter); 3443 drm_for_each_connector_iter(connector, &conn_iter) { 3444 if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS && 3445 connector->connector_type != DRM_MODE_CONNECTOR_eDP && 3446 connector->connector_type != DRM_MODE_CONNECTOR_DSI) 3447 continue; 3448 3449 connector->backlight_device = bd; 3450 connector->backlight_property = drm_property_create_range(dev, 3451 0, "Backlight", 0, bd->props.max_brightness); 3452 drm_object_attach_property(&connector->base, 3453 connector->backlight_property, bd->props.brightness); 3454 } 3455 drm_connector_list_iter_end(&conn_iter); 3456 } 3457 3458 void 3459 amdgpu_attachhook(struct device *self) 3460 { 3461 struct amdgpu_device *adev = (struct amdgpu_device *)self; 3462 struct drm_device *dev = &adev->ddev; 3463 int r, acpi_status; 3464 struct rasops_info *ri = &adev->ro; 3465 struct drm_fb_helper *fb_helper; 3466 struct drm_framebuffer *fb; 3467 struct drm_gem_object *obj; 3468 struct amdgpu_bo *rbo; 3469 3470 /* from amdgpu_driver_load_kms() */ 3471 3472 /* amdgpu_device_init should report only fatal error 3473 * like memory allocation failure or iomapping failure, 3474 * or memory manager initialization failure, it must 3475 * properly initialize the GPU MC controller and permit 3476 * VRAM allocation 3477 */ 3478 r = amdgpu_device_init(adev, adev->flags); 3479 if (r) { 3480 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 3481 goto out; 3482 } 3483 3484 adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; 3485 if (amdgpu_device_supports_px(dev) && 3486 (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ 3487 adev->pm.rpm_mode = AMDGPU_RUNPM_PX; 3488 dev_info(adev->dev, "Using ATPX for runtime pm\n"); 3489 } else if (amdgpu_device_supports_boco(dev) && 3490 (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ 3491 adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; 3492 dev_info(adev->dev, "Using BOCO for runtime pm\n"); 3493 } else if (amdgpu_device_supports_baco(dev) && 3494 (amdgpu_runtime_pm != 0)) { 3495 switch (adev->asic_type) { 3496 case CHIP_VEGA20: 3497 case CHIP_ARCTURUS: 3498 /* enable BACO as runpm mode if runpm=1 */ 3499 if (amdgpu_runtime_pm > 0) 3500 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 3501 break; 3502 case CHIP_VEGA10: 3503 /* enable BACO as runpm mode if noretry=0 */ 3504 if (!adev->gmc.noretry) 3505 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 3506 break; 3507 default: 3508 /* enable BACO as runpm mode on CI+ */ 3509 adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; 3510 break; 3511 } 3512 3513 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) 3514 dev_info(adev->dev, "Using BACO for runtime pm\n"); 3515 } 3516 3517 /* Call ACPI methods: require modeset init 3518 * but failure is not fatal 3519 */ 3520 3521 acpi_status = amdgpu_acpi_init(adev); 3522 if (acpi_status) 3523 dev_dbg(dev->dev, "Error during ACPI methods call\n"); 3524 3525 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) 3526 DRM_WARN("smart shift update failed\n"); 3527 3528 /* 3529 * 1. don't init fbdev on hw without DCE 3530 * 2. don't init fbdev if there are no connectors 3531 */ 3532 if (adev->mode_info.mode_config_initialized && 3533 !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { 3534 3535 /* OpenBSD specific backlight property on connector */ 3536 amdgpu_init_backlight(adev); 3537 3538 /* 3539 * in linux via amdgpu_pci_probe -> drm_dev_register 3540 * must be after (local) backlight property added not before 3541 * and before drm_fbdev_generic_setup() 3542 */ 3543 drm_dev_register(dev, adev->flags); 3544 3545 /* select 8 bpp console on low vram cards */ 3546 if (adev->gmc.real_vram_size <= (32*1024*1024)) 3547 drm_fbdev_generic_setup(adev_to_drm(adev), 8); 3548 else 3549 drm_fbdev_generic_setup(adev_to_drm(adev), 32); 3550 3551 fb_helper = adev_to_drm(adev)->fb_helper; 3552 if (fb_helper == NULL) { 3553 printf("fb_helper NULL\n"); 3554 return; 3555 } 3556 fb = fb_helper->fb; 3557 obj = fb->obj[0]; 3558 rbo = gem_to_amdgpu_bo(obj); 3559 amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM); 3560 amdgpu_bo_kmap(rbo, (void **)(&ri->ri_bits)); 3561 3562 ri->ri_depth = fb->format->cpp[0] * 8; 3563 ri->ri_stride = fb->pitches[0]; 3564 ri->ri_width = fb_helper->fbdev->var.xres; 3565 ri->ri_height = fb_helper->fbdev->var.yres; 3566 3567 switch (fb->format->format) { 3568 case DRM_FORMAT_XRGB8888: 3569 ri->ri_rnum = 8; 3570 ri->ri_rpos = 16; 3571 ri->ri_gnum = 8; 3572 ri->ri_gpos = 8; 3573 ri->ri_bnum = 8; 3574 ri->ri_bpos = 0; 3575 break; 3576 case DRM_FORMAT_RGB565: 3577 ri->ri_rnum = 5; 3578 ri->ri_rpos = 11; 3579 ri->ri_gnum = 6; 3580 ri->ri_gpos = 5; 3581 ri->ri_bnum = 5; 3582 ri->ri_bpos = 0; 3583 break; 3584 } 3585 } 3586 { 3587 struct wsemuldisplaydev_attach_args aa; 3588 int orientation_quirk; 3589 3590 task_set(&adev->switchtask, amdgpu_doswitch, ri); 3591 task_set(&adev->burner_task, amdgpu_burner_cb, adev); 3592 3593 if (ri->ri_bits == NULL) 3594 return; 3595 3596 ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY; 3597 3598 orientation_quirk = drm_get_panel_orientation_quirk(ri->ri_width, 3599 ri->ri_height); 3600 if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_LEFT_UP) 3601 ri->ri_flg |= RI_ROTATE_CCW; 3602 else if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_RIGHT_UP) 3603 ri->ri_flg |= RI_ROTATE_CW; 3604 3605 rasops_init(ri, 160, 160); 3606 3607 ri->ri_hw = adev; 3608 3609 amdgpu_stdscreen.capabilities = ri->ri_caps; 3610 amdgpu_stdscreen.nrows = ri->ri_rows; 3611 amdgpu_stdscreen.ncols = ri->ri_cols; 3612 amdgpu_stdscreen.textops = &ri->ri_ops; 3613 amdgpu_stdscreen.fontwidth = ri->ri_font->fontwidth; 3614 amdgpu_stdscreen.fontheight = ri->ri_font->fontheight; 3615 3616 aa.console = adev->console; 3617 aa.primary = adev->primary; 3618 aa.scrdata = &amdgpu_screenlist; 3619 aa.accessops = &amdgpu_accessops; 3620 aa.accesscookie = ri; 3621 aa.defaultscreens = 0; 3622 3623 if (adev->console) { 3624 uint32_t defattr; 3625 3626 ri->ri_ops.pack_attr(ri->ri_active, 0, 0, 0, &defattr); 3627 wsdisplay_cnattach(&amdgpu_stdscreen, ri->ri_active, 3628 ri->ri_ccol, ri->ri_crow, defattr); 3629 } 3630 3631 /* 3632 * Now that we've taken over the console, disable decoding of 3633 * VGA legacy addresses, and opt out of arbitration. 3634 */ 3635 amdgpu_asic_set_vga_state(adev, false); 3636 pci_disable_legacy_vga(&adev->self); 3637 3638 printf("%s: %dx%d, %dbpp\n", adev->self.dv_xname, 3639 ri->ri_width, ri->ri_height, ri->ri_depth); 3640 3641 config_found_sm(&adev->self, &aa, wsemuldisplaydevprint, 3642 wsemuldisplaydevsubmatch); 3643 } 3644 3645 out: 3646 if (r) { 3647 amdgpu_fatal_error = 1; 3648 amdgpu_forcedetach(adev); 3649 } 3650 } 3651 3652 /* from amdgpu_exit amdgpu_driver_unload_kms */ 3653 int 3654 amdgpu_detach(struct device *self, int flags) 3655 { 3656 struct amdgpu_device *adev = (struct amdgpu_device *)self; 3657 struct drm_device *dev = &adev->ddev; 3658 3659 if (adev == NULL) 3660 return 0; 3661 3662 amdgpu_refcnt--; 3663 3664 if (amdgpu_refcnt == 0) 3665 amdgpu_amdkfd_fini(); 3666 3667 pci_intr_disestablish(adev->pc, adev->irqh); 3668 3669 amdgpu_unregister_gpu_instance(adev); 3670 3671 amdgpu_acpi_fini(adev); 3672 amdgpu_device_fini_hw(adev); 3673 3674 if (amdgpu_refcnt == 0) { 3675 amdgpu_unregister_atpx_handler(); 3676 amdgpu_sync_fini(); 3677 amdgpu_fence_slab_fini(); 3678 3679 drm_sched_fence_slab_fini(); 3680 } 3681 3682 config_detach(adev->ddev.dev, flags); 3683 3684 return 0; 3685 } 3686 3687 int 3688 amdgpu_activate(struct device *self, int act) 3689 { 3690 struct amdgpu_device *adev = (struct amdgpu_device *)self; 3691 struct drm_device *dev = &adev->ddev; 3692 int rv = 0; 3693 3694 if (dev->dev == NULL || amdgpu_fatal_error) 3695 return (0); 3696 3697 switch (act) { 3698 case DVACT_QUIESCE: 3699 rv = config_activate_children(self, act); 3700 amdgpu_device_suspend(dev, true); 3701 break; 3702 case DVACT_SUSPEND: 3703 break; 3704 case DVACT_RESUME: 3705 break; 3706 case DVACT_WAKEUP: 3707 amdgpu_device_resume(dev, true); 3708 rv = config_activate_children(self, act); 3709 break; 3710 } 3711 3712 return (rv); 3713 } 3714 3715 void 3716 amdgpu_burner(void *v, u_int on, u_int flags) 3717 { 3718 struct rasops_info *ri = v; 3719 struct amdgpu_device *adev = ri->ri_hw; 3720 3721 task_del(systq, &adev->burner_task); 3722 3723 if (on) 3724 adev->burner_fblank = FB_BLANK_UNBLANK; 3725 else { 3726 if (flags & WSDISPLAY_BURN_VBLANK) 3727 adev->burner_fblank = FB_BLANK_VSYNC_SUSPEND; 3728 else 3729 adev->burner_fblank = FB_BLANK_NORMAL; 3730 } 3731 3732 /* 3733 * Setting the DPMS mode may sleep while waiting for vblank so 3734 * hand things off to a taskq. 3735 */ 3736 task_add(systq, &adev->burner_task); 3737 } 3738 3739 void 3740 amdgpu_burner_cb(void *arg1) 3741 { 3742 struct amdgpu_device *adev = arg1; 3743 struct drm_fb_helper *helper = adev_to_drm(adev)->fb_helper; 3744 3745 drm_fb_helper_blank(adev->burner_fblank, helper->fbdev); 3746 } 3747