1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 /* 25 * GPU doorbell structures, functions & helpers 26 */ 27 struct amdgpu_doorbell { 28 /* doorbell mmio */ 29 resource_size_t base; 30 resource_size_t size; 31 u32 __iomem *ptr; 32 bus_space_tag_t bst; 33 bus_space_handle_t bsh; 34 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 35 }; 36 37 /* Reserved doorbells for amdgpu (including multimedia). 38 * KFD can use all the rest in the 2M doorbell bar. 39 * For asic before vega10, doorbell is 32-bit, so the 40 * index/offset is in dword. For vega10 and after, doorbell 41 * can be 64-bit, so the index defined is in qword. 42 */ 43 struct amdgpu_doorbell_index { 44 uint32_t kiq; 45 uint32_t mec_ring0; 46 uint32_t mec_ring1; 47 uint32_t mec_ring2; 48 uint32_t mec_ring3; 49 uint32_t mec_ring4; 50 uint32_t mec_ring5; 51 uint32_t mec_ring6; 52 uint32_t mec_ring7; 53 uint32_t userqueue_start; 54 uint32_t userqueue_end; 55 uint32_t gfx_ring0; 56 uint32_t gfx_ring1; 57 uint32_t sdma_engine[8]; 58 uint32_t ih; 59 union { 60 struct { 61 uint32_t vcn_ring0_1; 62 uint32_t vcn_ring2_3; 63 uint32_t vcn_ring4_5; 64 uint32_t vcn_ring6_7; 65 } vcn; 66 struct { 67 uint32_t uvd_ring0_1; 68 uint32_t uvd_ring2_3; 69 uint32_t uvd_ring4_5; 70 uint32_t uvd_ring6_7; 71 uint32_t vce_ring0_1; 72 uint32_t vce_ring2_3; 73 uint32_t vce_ring4_5; 74 uint32_t vce_ring6_7; 75 } uvd_vce; 76 }; 77 uint32_t first_non_cp; 78 uint32_t last_non_cp; 79 uint32_t max_assignment; 80 /* Per engine SDMA doorbell size in dword */ 81 uint32_t sdma_doorbell_range; 82 }; 83 84 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 85 { 86 AMDGPU_DOORBELL_KIQ = 0x000, 87 AMDGPU_DOORBELL_HIQ = 0x001, 88 AMDGPU_DOORBELL_DIQ = 0x002, 89 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 90 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 91 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 92 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 93 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 94 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 95 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 96 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 97 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 98 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 99 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 100 AMDGPU_DOORBELL_IH = 0x1E8, 101 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 102 AMDGPU_DOORBELL_INVALID = 0xFFFF 103 } AMDGPU_DOORBELL_ASSIGNMENT; 104 105 typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT 106 { 107 /* Compute + GFX: 0~255 */ 108 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, 109 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, 110 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, 111 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, 112 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, 113 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, 114 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, 115 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, 116 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, 117 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, 118 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, 119 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, 120 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, 121 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, 122 /* SDMA:256~335*/ 123 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, 124 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, 125 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, 126 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, 127 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, 128 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, 129 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, 130 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, 131 /* IH: 376~391 */ 132 AMDGPU_VEGA20_DOORBELL_IH = 0x178, 133 /* MMSCH: 392~407 134 * overlap the doorbell assignment with VCN as they are mutually exclusive 135 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD 136 */ 137 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */ 138 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, 139 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, 140 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, 141 142 AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */ 143 AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D, 144 AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E, 145 AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F, 146 147 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, 148 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, 149 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, 150 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, 151 152 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, 153 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, 154 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, 155 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, 156 157 AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0, 158 AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7, 159 160 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F, 161 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF 162 } AMDGPU_VEGA20_DOORBELL_ASSIGNMENT; 163 164 typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT 165 { 166 /* Compute + GFX: 0~255 */ 167 AMDGPU_NAVI10_DOORBELL_KIQ = 0x000, 168 AMDGPU_NAVI10_DOORBELL_HIQ = 0x001, 169 AMDGPU_NAVI10_DOORBELL_DIQ = 0x002, 170 AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003, 171 AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004, 172 AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005, 173 AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006, 174 AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007, 175 AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008, 176 AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009, 177 AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A, 178 AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00B, 179 AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A, 180 AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B, 181 AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C, 182 /* SDMA:256~335*/ 183 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100, 184 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A, 185 /* IH: 376~391 */ 186 AMDGPU_NAVI10_DOORBELL_IH = 0x178, 187 /* MMSCH: 392~407 188 * overlap the doorbell assignment with VCN as they are mutually exclusive 189 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 190 */ 191 AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 192 AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189, 193 AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A, 194 AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B, 195 196 AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0, 197 AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCN6_7, 198 199 AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F, 200 AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF 201 } AMDGPU_NAVI10_DOORBELL_ASSIGNMENT; 202 203 /* 204 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 205 */ 206 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 207 { 208 /* 209 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 210 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 211 * Compute related doorbells are allocated from 0x00 to 0x8a 212 */ 213 214 215 /* kernel scheduling */ 216 AMDGPU_DOORBELL64_KIQ = 0x00, 217 218 /* HSA interface queue and debug queue */ 219 AMDGPU_DOORBELL64_HIQ = 0x01, 220 AMDGPU_DOORBELL64_DIQ = 0x02, 221 222 /* Compute engines */ 223 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 224 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 225 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 226 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 227 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 228 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 229 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 230 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 231 232 /* User queue doorbell range (128 doorbells) */ 233 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 234 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 235 236 /* Graphics engine */ 237 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 238 239 /* 240 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 241 * Graphics voltage island aperture 1 242 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 243 */ 244 245 /* For vega10 sriov, the sdma doorbell must be fixed as follow 246 * to keep the same setting with host driver, or it will 247 * happen conflicts 248 */ 249 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 250 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 251 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 252 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 253 254 /* Interrupt handler */ 255 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 256 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 257 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 258 259 /* VCN engine use 32 bits doorbell */ 260 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 261 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 262 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 263 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 264 265 /* overlap the doorbell assignment with VCN as they are mutually exclusive 266 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 267 */ 268 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 269 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 270 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 271 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 272 273 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 274 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 275 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 276 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 277 278 AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0, 279 AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7, 280 281 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 282 AMDGPU_DOORBELL64_INVALID = 0xFFFF 283 } AMDGPU_DOORBELL64_ASSIGNMENT; 284 285 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 286 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 287 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 288 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 289 290 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 291 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 292 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 293 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 294 295