1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 /* 25 * GPU doorbell structures, functions & helpers 26 */ 27 struct amdgpu_doorbell { 28 /* doorbell mmio */ 29 resource_size_t base; 30 resource_size_t size; 31 #ifdef __linux__ 32 u32 __iomem *ptr; 33 #else 34 bus_space_tag_t bst; 35 bus_space_handle_t bsh; 36 #endif 37 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 38 }; 39 40 /* Reserved doorbells for amdgpu (including multimedia). 41 * KFD can use all the rest in the 2M doorbell bar. 42 * For asic before vega10, doorbell is 32-bit, so the 43 * index/offset is in dword. For vega10 and after, doorbell 44 * can be 64-bit, so the index defined is in qword. 45 */ 46 struct amdgpu_doorbell_index { 47 uint32_t kiq; 48 uint32_t mec_ring0; 49 uint32_t mec_ring1; 50 uint32_t mec_ring2; 51 uint32_t mec_ring3; 52 uint32_t mec_ring4; 53 uint32_t mec_ring5; 54 uint32_t mec_ring6; 55 uint32_t mec_ring7; 56 uint32_t userqueue_start; 57 uint32_t userqueue_end; 58 uint32_t gfx_ring0; 59 uint32_t gfx_ring1; 60 uint32_t sdma_engine[8]; 61 uint32_t ih; 62 union { 63 struct { 64 uint32_t vcn_ring0_1; 65 uint32_t vcn_ring2_3; 66 uint32_t vcn_ring4_5; 67 uint32_t vcn_ring6_7; 68 } vcn; 69 struct { 70 uint32_t uvd_ring0_1; 71 uint32_t uvd_ring2_3; 72 uint32_t uvd_ring4_5; 73 uint32_t uvd_ring6_7; 74 uint32_t vce_ring0_1; 75 uint32_t vce_ring2_3; 76 uint32_t vce_ring4_5; 77 uint32_t vce_ring6_7; 78 } uvd_vce; 79 }; 80 uint32_t first_non_cp; 81 uint32_t last_non_cp; 82 uint32_t max_assignment; 83 /* Per engine SDMA doorbell size in dword */ 84 uint32_t sdma_doorbell_range; 85 }; 86 87 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 88 { 89 AMDGPU_DOORBELL_KIQ = 0x000, 90 AMDGPU_DOORBELL_HIQ = 0x001, 91 AMDGPU_DOORBELL_DIQ = 0x002, 92 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 93 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 94 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 95 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 96 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 97 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 98 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 99 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 100 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 101 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 102 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 103 AMDGPU_DOORBELL_IH = 0x1E8, 104 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 105 AMDGPU_DOORBELL_INVALID = 0xFFFF 106 } AMDGPU_DOORBELL_ASSIGNMENT; 107 108 typedef enum _AMDGPU_VEGA20_DOORBELL_ASSIGNMENT 109 { 110 /* Compute + GFX: 0~255 */ 111 AMDGPU_VEGA20_DOORBELL_KIQ = 0x000, 112 AMDGPU_VEGA20_DOORBELL_HIQ = 0x001, 113 AMDGPU_VEGA20_DOORBELL_DIQ = 0x002, 114 AMDGPU_VEGA20_DOORBELL_MEC_RING0 = 0x003, 115 AMDGPU_VEGA20_DOORBELL_MEC_RING1 = 0x004, 116 AMDGPU_VEGA20_DOORBELL_MEC_RING2 = 0x005, 117 AMDGPU_VEGA20_DOORBELL_MEC_RING3 = 0x006, 118 AMDGPU_VEGA20_DOORBELL_MEC_RING4 = 0x007, 119 AMDGPU_VEGA20_DOORBELL_MEC_RING5 = 0x008, 120 AMDGPU_VEGA20_DOORBELL_MEC_RING6 = 0x009, 121 AMDGPU_VEGA20_DOORBELL_MEC_RING7 = 0x00A, 122 AMDGPU_VEGA20_DOORBELL_USERQUEUE_START = 0x00B, 123 AMDGPU_VEGA20_DOORBELL_USERQUEUE_END = 0x08A, 124 AMDGPU_VEGA20_DOORBELL_GFX_RING0 = 0x08B, 125 /* SDMA:256~335*/ 126 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0 = 0x100, 127 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE1 = 0x10A, 128 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE2 = 0x114, 129 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE3 = 0x11E, 130 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE4 = 0x128, 131 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE5 = 0x132, 132 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE6 = 0x13C, 133 AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE7 = 0x146, 134 /* IH: 376~391 */ 135 AMDGPU_VEGA20_DOORBELL_IH = 0x178, 136 /* MMSCH: 392~407 137 * overlap the doorbell assignment with VCN as they are mutually exclusive 138 * VCN engine's doorbell is 32 bit and two VCN ring share one QWORD 139 */ 140 AMDGPU_VEGA20_DOORBELL64_VCN0_1 = 0x188, /* VNC0 */ 141 AMDGPU_VEGA20_DOORBELL64_VCN2_3 = 0x189, 142 AMDGPU_VEGA20_DOORBELL64_VCN4_5 = 0x18A, 143 AMDGPU_VEGA20_DOORBELL64_VCN6_7 = 0x18B, 144 145 AMDGPU_VEGA20_DOORBELL64_VCN8_9 = 0x18C, /* VNC1 */ 146 AMDGPU_VEGA20_DOORBELL64_VCNa_b = 0x18D, 147 AMDGPU_VEGA20_DOORBELL64_VCNc_d = 0x18E, 148 AMDGPU_VEGA20_DOORBELL64_VCNe_f = 0x18F, 149 150 AMDGPU_VEGA20_DOORBELL64_UVD_RING0_1 = 0x188, 151 AMDGPU_VEGA20_DOORBELL64_UVD_RING2_3 = 0x189, 152 AMDGPU_VEGA20_DOORBELL64_UVD_RING4_5 = 0x18A, 153 AMDGPU_VEGA20_DOORBELL64_UVD_RING6_7 = 0x18B, 154 155 AMDGPU_VEGA20_DOORBELL64_VCE_RING0_1 = 0x18C, 156 AMDGPU_VEGA20_DOORBELL64_VCE_RING2_3 = 0x18D, 157 AMDGPU_VEGA20_DOORBELL64_VCE_RING4_5 = 0x18E, 158 AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7 = 0x18F, 159 160 AMDGPU_VEGA20_DOORBELL64_FIRST_NON_CP = AMDGPU_VEGA20_DOORBELL_sDMA_ENGINE0, 161 AMDGPU_VEGA20_DOORBELL64_LAST_NON_CP = AMDGPU_VEGA20_DOORBELL64_VCE_RING6_7, 162 163 AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x18F, 164 AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF 165 } AMDGPU_VEGA20_DOORBELL_ASSIGNMENT; 166 167 typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT 168 { 169 /* Compute + GFX: 0~255 */ 170 AMDGPU_NAVI10_DOORBELL_KIQ = 0x000, 171 AMDGPU_NAVI10_DOORBELL_HIQ = 0x001, 172 AMDGPU_NAVI10_DOORBELL_DIQ = 0x002, 173 AMDGPU_NAVI10_DOORBELL_MEC_RING0 = 0x003, 174 AMDGPU_NAVI10_DOORBELL_MEC_RING1 = 0x004, 175 AMDGPU_NAVI10_DOORBELL_MEC_RING2 = 0x005, 176 AMDGPU_NAVI10_DOORBELL_MEC_RING3 = 0x006, 177 AMDGPU_NAVI10_DOORBELL_MEC_RING4 = 0x007, 178 AMDGPU_NAVI10_DOORBELL_MEC_RING5 = 0x008, 179 AMDGPU_NAVI10_DOORBELL_MEC_RING6 = 0x009, 180 AMDGPU_NAVI10_DOORBELL_MEC_RING7 = 0x00A, 181 AMDGPU_NAVI10_DOORBELL_USERQUEUE_START = 0x00B, 182 AMDGPU_NAVI10_DOORBELL_USERQUEUE_END = 0x08A, 183 AMDGPU_NAVI10_DOORBELL_GFX_RING0 = 0x08B, 184 AMDGPU_NAVI10_DOORBELL_GFX_RING1 = 0x08C, 185 /* SDMA:256~335*/ 186 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0 = 0x100, 187 AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1 = 0x10A, 188 /* IH: 376~391 */ 189 AMDGPU_NAVI10_DOORBELL_IH = 0x178, 190 /* MMSCH: 392~407 191 * overlap the doorbell assignment with VCN as they are mutually exclusive 192 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 193 */ 194 AMDGPU_NAVI10_DOORBELL64_VCN0_1 = 0x188, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 195 AMDGPU_NAVI10_DOORBELL64_VCN2_3 = 0x189, 196 AMDGPU_NAVI10_DOORBELL64_VCN4_5 = 0x18A, 197 AMDGPU_NAVI10_DOORBELL64_VCN6_7 = 0x18B, 198 199 AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0, 200 AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP = AMDGPU_NAVI10_DOORBELL64_VCN6_7, 201 202 AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT = 0x18F, 203 AMDGPU_NAVI10_DOORBELL_INVALID = 0xFFFF 204 } AMDGPU_NAVI10_DOORBELL_ASSIGNMENT; 205 206 /* 207 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 208 */ 209 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 210 { 211 /* 212 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 213 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 214 * Compute related doorbells are allocated from 0x00 to 0x8a 215 */ 216 217 218 /* kernel scheduling */ 219 AMDGPU_DOORBELL64_KIQ = 0x00, 220 221 /* HSA interface queue and debug queue */ 222 AMDGPU_DOORBELL64_HIQ = 0x01, 223 AMDGPU_DOORBELL64_DIQ = 0x02, 224 225 /* Compute engines */ 226 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 227 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 228 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 229 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 230 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 231 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 232 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 233 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 234 235 /* User queue doorbell range (128 doorbells) */ 236 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 237 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 238 239 /* Graphics engine */ 240 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 241 242 /* 243 * Other graphics doorbells can be allocated here: from 0x8c to 0xdf 244 * Graphics voltage island aperture 1 245 * default non-graphics QWORD index is 0xe0 - 0xFF inclusive 246 */ 247 248 /* For vega10 sriov, the sdma doorbell must be fixed as follow 249 * to keep the same setting with host driver, or it will 250 * happen conflicts 251 */ 252 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 253 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 254 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 255 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 256 257 /* Interrupt handler */ 258 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 259 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 260 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 261 262 /* VCN engine use 32 bits doorbell */ 263 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 264 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 265 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 266 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 267 268 /* overlap the doorbell assignment with VCN as they are mutually exclusive 269 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 270 */ 271 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 272 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 273 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 274 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 275 276 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 277 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 278 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 279 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 280 281 AMDGPU_DOORBELL64_FIRST_NON_CP = AMDGPU_DOORBELL64_sDMA_ENGINE0, 282 AMDGPU_DOORBELL64_LAST_NON_CP = AMDGPU_DOORBELL64_VCE_RING6_7, 283 284 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 285 AMDGPU_DOORBELL64_INVALID = 0xFFFF 286 } AMDGPU_DOORBELL64_ASSIGNMENT; 287 288 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 289 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 290 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 291 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 292 293 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 294 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 295 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 296 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 297 298