1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_i2c.h" 30 #include "atom.h" 31 #include "amdgpu_connectors.h" 32 #include "amdgpu_display.h" 33 #include "soc15_common.h" 34 #include "gc/gc_11_0_0_offset.h" 35 #include "gc/gc_11_0_0_sh_mask.h" 36 #include <asm/div64.h> 37 38 #include <linux/pci.h> 39 #include <linux/pm_runtime.h> 40 #include <drm/drm_crtc_helper.h> 41 #include <drm/drm_damage_helper.h> 42 #include <drm/drm_drv.h> 43 #include <drm/drm_edid.h> 44 #include <drm/drm_gem_framebuffer_helper.h> 45 #include <drm/drm_fb_helper.h> 46 #include <drm/drm_fourcc.h> 47 #include <drm/drm_vblank.h> 48 49 static int amdgpu_display_framebuffer_init(struct drm_device *dev, 50 struct amdgpu_framebuffer *rfb, 51 const struct drm_mode_fb_cmd2 *mode_cmd, 52 struct drm_gem_object *obj); 53 54 static void amdgpu_display_flip_callback(struct dma_fence *f, 55 struct dma_fence_cb *cb) 56 { 57 struct amdgpu_flip_work *work = 58 container_of(cb, struct amdgpu_flip_work, cb); 59 60 dma_fence_put(f); 61 schedule_work(&work->flip_work.work); 62 } 63 64 static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, 65 struct dma_fence **f) 66 { 67 struct dma_fence *fence= *f; 68 69 if (fence == NULL) 70 return false; 71 72 *f = NULL; 73 74 if (!dma_fence_add_callback(fence, &work->cb, 75 amdgpu_display_flip_callback)) 76 return true; 77 78 dma_fence_put(fence); 79 return false; 80 } 81 82 static void amdgpu_display_flip_work_func(struct work_struct *__work) 83 { 84 struct delayed_work *delayed_work = 85 container_of(__work, struct delayed_work, work); 86 struct amdgpu_flip_work *work = 87 container_of(delayed_work, struct amdgpu_flip_work, flip_work); 88 struct amdgpu_device *adev = work->adev; 89 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[work->crtc_id]; 90 91 struct drm_crtc *crtc = &amdgpu_crtc->base; 92 unsigned long flags; 93 unsigned i; 94 int vpos, hpos; 95 96 for (i = 0; i < work->shared_count; ++i) 97 if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) 98 return; 99 100 /* Wait until we're out of the vertical blank period before the one 101 * targeted by the flip 102 */ 103 if (amdgpu_crtc->enabled && 104 (amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, 0, 105 &vpos, &hpos, NULL, NULL, 106 &crtc->hwmode) 107 & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == 108 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && 109 (int)(work->target_vblank - 110 amdgpu_get_vblank_counter_kms(crtc)) > 0) { 111 schedule_delayed_work(&work->flip_work, usecs_to_jiffies(1000)); 112 return; 113 } 114 115 /* We borrow the event spin lock for protecting flip_status */ 116 spin_lock_irqsave(&crtc->dev->event_lock, flags); 117 118 /* Do the flip (mmio) */ 119 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); 120 121 /* Set the flip status */ 122 amdgpu_crtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 123 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 124 125 126 drm_dbg_vbl(adev_to_drm(adev), 127 "crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", 128 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 129 130 } 131 132 /* 133 * Handle unpin events outside the interrupt handler proper. 134 */ 135 static void amdgpu_display_unpin_work_func(struct work_struct *__work) 136 { 137 struct amdgpu_flip_work *work = 138 container_of(__work, struct amdgpu_flip_work, unpin_work); 139 int r; 140 141 /* unpin of the old buffer */ 142 r = amdgpu_bo_reserve(work->old_abo, true); 143 if (likely(r == 0)) { 144 amdgpu_bo_unpin(work->old_abo); 145 amdgpu_bo_unreserve(work->old_abo); 146 } else 147 DRM_ERROR("failed to reserve buffer after flip\n"); 148 149 amdgpu_bo_unref(&work->old_abo); 150 kfree(work->shared); 151 kfree(work); 152 } 153 154 int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, 155 struct drm_framebuffer *fb, 156 struct drm_pending_vblank_event *event, 157 uint32_t page_flip_flags, uint32_t target, 158 struct drm_modeset_acquire_ctx *ctx) 159 { 160 struct drm_device *dev = crtc->dev; 161 struct amdgpu_device *adev = drm_to_adev(dev); 162 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 163 struct drm_gem_object *obj; 164 struct amdgpu_flip_work *work; 165 struct amdgpu_bo *new_abo; 166 unsigned long flags; 167 u64 tiling_flags; 168 int i, r; 169 170 work = kzalloc(sizeof *work, GFP_KERNEL); 171 if (work == NULL) 172 return -ENOMEM; 173 174 INIT_DELAYED_WORK(&work->flip_work, amdgpu_display_flip_work_func); 175 INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); 176 177 work->event = event; 178 work->adev = adev; 179 work->crtc_id = amdgpu_crtc->crtc_id; 180 work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; 181 182 /* schedule unpin of the old buffer */ 183 obj = crtc->primary->fb->obj[0]; 184 185 /* take a reference to the old object */ 186 work->old_abo = gem_to_amdgpu_bo(obj); 187 amdgpu_bo_ref(work->old_abo); 188 189 obj = fb->obj[0]; 190 new_abo = gem_to_amdgpu_bo(obj); 191 192 /* pin the new buffer */ 193 r = amdgpu_bo_reserve(new_abo, false); 194 if (unlikely(r != 0)) { 195 DRM_ERROR("failed to reserve new abo buffer before flip\n"); 196 goto cleanup; 197 } 198 199 if (!adev->enable_virtual_display) { 200 r = amdgpu_bo_pin(new_abo, 201 amdgpu_display_supported_domains(adev, new_abo->flags)); 202 if (unlikely(r != 0)) { 203 DRM_ERROR("failed to pin new abo buffer before flip\n"); 204 goto unreserve; 205 } 206 } 207 208 r = amdgpu_ttm_alloc_gart(&new_abo->tbo); 209 if (unlikely(r != 0)) { 210 DRM_ERROR("%p bind failed\n", new_abo); 211 goto unpin; 212 } 213 214 r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE, 215 &work->shared_count, 216 &work->shared); 217 if (unlikely(r != 0)) { 218 DRM_ERROR("failed to get fences for buffer\n"); 219 goto unpin; 220 } 221 222 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 223 amdgpu_bo_unreserve(new_abo); 224 225 if (!adev->enable_virtual_display) 226 work->base = amdgpu_bo_gpu_offset(new_abo); 227 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 228 amdgpu_get_vblank_counter_kms(crtc); 229 230 /* we borrow the event spin lock for protecting flip_wrok */ 231 spin_lock_irqsave(&crtc->dev->event_lock, flags); 232 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 233 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 234 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 235 r = -EBUSY; 236 goto pflip_cleanup; 237 } 238 239 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 240 amdgpu_crtc->pflip_works = work; 241 242 243 DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", 244 amdgpu_crtc->crtc_id, amdgpu_crtc, work); 245 /* update crtc fb */ 246 crtc->primary->fb = fb; 247 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 248 amdgpu_display_flip_work_func(&work->flip_work.work); 249 return 0; 250 251 pflip_cleanup: 252 if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { 253 DRM_ERROR("failed to reserve new abo in error path\n"); 254 goto cleanup; 255 } 256 unpin: 257 if (!adev->enable_virtual_display) 258 amdgpu_bo_unpin(new_abo); 259 260 unreserve: 261 amdgpu_bo_unreserve(new_abo); 262 263 cleanup: 264 amdgpu_bo_unref(&work->old_abo); 265 for (i = 0; i < work->shared_count; ++i) 266 dma_fence_put(work->shared[i]); 267 kfree(work->shared); 268 kfree(work); 269 270 return r; 271 } 272 273 int amdgpu_display_crtc_set_config(struct drm_mode_set *set, 274 struct drm_modeset_acquire_ctx *ctx) 275 { 276 struct drm_device *dev; 277 struct amdgpu_device *adev; 278 struct drm_crtc *crtc; 279 bool active = false; 280 int ret; 281 282 if (!set || !set->crtc) 283 return -EINVAL; 284 285 dev = set->crtc->dev; 286 287 ret = pm_runtime_get_sync(dev->dev); 288 if (ret < 0) 289 goto out; 290 291 ret = drm_crtc_helper_set_config(set, ctx); 292 293 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 294 if (crtc->enabled) 295 active = true; 296 297 pm_runtime_mark_last_busy(dev->dev); 298 299 adev = drm_to_adev(dev); 300 /* if we have active crtcs and we don't have a power ref, 301 take the current one */ 302 if (active && !adev->have_disp_power_ref) { 303 adev->have_disp_power_ref = true; 304 return ret; 305 } 306 /* if we have no active crtcs, then drop the power ref 307 we got before */ 308 if (!active && adev->have_disp_power_ref) { 309 pm_runtime_put_autosuspend(dev->dev); 310 adev->have_disp_power_ref = false; 311 } 312 313 out: 314 /* drop the power reference we got coming in here */ 315 pm_runtime_put_autosuspend(dev->dev); 316 return ret; 317 } 318 319 static const char *encoder_names[41] = { 320 "NONE", 321 "INTERNAL_LVDS", 322 "INTERNAL_TMDS1", 323 "INTERNAL_TMDS2", 324 "INTERNAL_DAC1", 325 "INTERNAL_DAC2", 326 "INTERNAL_SDVOA", 327 "INTERNAL_SDVOB", 328 "SI170B", 329 "CH7303", 330 "CH7301", 331 "INTERNAL_DVO1", 332 "EXTERNAL_SDVOA", 333 "EXTERNAL_SDVOB", 334 "TITFP513", 335 "INTERNAL_LVTM1", 336 "VT1623", 337 "HDMI_SI1930", 338 "HDMI_INTERNAL", 339 "INTERNAL_KLDSCP_TMDS1", 340 "INTERNAL_KLDSCP_DVO1", 341 "INTERNAL_KLDSCP_DAC1", 342 "INTERNAL_KLDSCP_DAC2", 343 "SI178", 344 "MVPU_FPGA", 345 "INTERNAL_DDI", 346 "VT1625", 347 "HDMI_SI1932", 348 "DP_AN9801", 349 "DP_DP501", 350 "INTERNAL_UNIPHY", 351 "INTERNAL_KLDSCP_LVTMA", 352 "INTERNAL_UNIPHY1", 353 "INTERNAL_UNIPHY2", 354 "NUTMEG", 355 "TRAVIS", 356 "INTERNAL_VCE", 357 "INTERNAL_UNIPHY3", 358 "HDMI_ANX9805", 359 "INTERNAL_AMCLK", 360 "VIRTUAL", 361 }; 362 363 static const char *hpd_names[6] = { 364 "HPD1", 365 "HPD2", 366 "HPD3", 367 "HPD4", 368 "HPD5", 369 "HPD6", 370 }; 371 372 void amdgpu_display_print_display_setup(struct drm_device *dev) 373 { 374 struct drm_connector *connector; 375 struct amdgpu_connector *amdgpu_connector; 376 struct drm_encoder *encoder; 377 struct amdgpu_encoder *amdgpu_encoder; 378 struct drm_connector_list_iter iter; 379 uint32_t devices; 380 int i = 0; 381 382 drm_connector_list_iter_begin(dev, &iter); 383 DRM_INFO("AMDGPU Display Connectors\n"); 384 drm_for_each_connector_iter(connector, &iter) { 385 amdgpu_connector = to_amdgpu_connector(connector); 386 DRM_INFO("Connector %d:\n", i); 387 DRM_INFO(" %s\n", connector->name); 388 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 389 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 390 if (amdgpu_connector->ddc_bus) { 391 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 392 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 393 amdgpu_connector->ddc_bus->rec.mask_data_reg, 394 amdgpu_connector->ddc_bus->rec.a_clk_reg, 395 amdgpu_connector->ddc_bus->rec.a_data_reg, 396 amdgpu_connector->ddc_bus->rec.en_clk_reg, 397 amdgpu_connector->ddc_bus->rec.en_data_reg, 398 amdgpu_connector->ddc_bus->rec.y_clk_reg, 399 amdgpu_connector->ddc_bus->rec.y_data_reg); 400 if (amdgpu_connector->router.ddc_valid) 401 DRM_INFO(" DDC Router 0x%x/0x%x\n", 402 amdgpu_connector->router.ddc_mux_control_pin, 403 amdgpu_connector->router.ddc_mux_state); 404 if (amdgpu_connector->router.cd_valid) 405 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 406 amdgpu_connector->router.cd_mux_control_pin, 407 amdgpu_connector->router.cd_mux_state); 408 } else { 409 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 410 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 411 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 412 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 413 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 414 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 415 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n"); 416 } 417 DRM_INFO(" Encoders:\n"); 418 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 419 amdgpu_encoder = to_amdgpu_encoder(encoder); 420 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 421 if (devices) { 422 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 423 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 424 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 425 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 426 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 427 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 428 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 429 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 430 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 431 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 432 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 433 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 434 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 435 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 436 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 437 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 438 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 439 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 440 if (devices & ATOM_DEVICE_TV1_SUPPORT) 441 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 442 if (devices & ATOM_DEVICE_CV_SUPPORT) 443 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 444 } 445 } 446 i++; 447 } 448 drm_connector_list_iter_end(&iter); 449 } 450 451 bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, 452 bool use_aux) 453 { 454 u8 out = 0x0; 455 u8 buf[8]; 456 int ret; 457 struct i2c_msg msgs[] = { 458 { 459 .addr = DDC_ADDR, 460 .flags = 0, 461 .len = 1, 462 .buf = &out, 463 }, 464 { 465 .addr = DDC_ADDR, 466 .flags = I2C_M_RD, 467 .len = 8, 468 .buf = buf, 469 } 470 }; 471 472 /* on hw with routers, select right port */ 473 if (amdgpu_connector->router.ddc_valid) 474 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 475 476 if (use_aux) { 477 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 478 } else { 479 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 480 } 481 482 if (ret != 2) 483 /* Couldn't find an accessible DDC on this connector */ 484 return false; 485 /* Probe also for valid EDID header 486 * EDID header starts with: 487 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 488 * Only the first 6 bytes must be valid as 489 * drm_edid_block_valid() can fix the last 2 bytes */ 490 if (drm_edid_header_is_valid(buf) < 6) { 491 /* Couldn't find an accessible EDID on this 492 * connector */ 493 return false; 494 } 495 return true; 496 } 497 498 static int amdgpu_dirtyfb(struct drm_framebuffer *fb, struct drm_file *file, 499 unsigned int flags, unsigned int color, 500 struct drm_clip_rect *clips, unsigned int num_clips) 501 { 502 503 if (file) 504 return -ENOSYS; 505 506 return drm_atomic_helper_dirtyfb(fb, file, flags, color, clips, 507 num_clips); 508 } 509 510 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 511 .destroy = drm_gem_fb_destroy, 512 .create_handle = drm_gem_fb_create_handle, 513 }; 514 515 static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = { 516 .destroy = drm_gem_fb_destroy, 517 .create_handle = drm_gem_fb_create_handle, 518 .dirty = amdgpu_dirtyfb 519 }; 520 521 uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, 522 uint64_t bo_flags) 523 { 524 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 525 526 #if defined(CONFIG_DRM_AMD_DC) 527 /* 528 * if amdgpu_bo_support_uswc returns false it means that USWC mappings 529 * is not supported for this board. But this mapping is required 530 * to avoid hang caused by placement of scanout BO in GTT on certain 531 * APUs. So force the BO placement to VRAM in case this architecture 532 * will not allow USWC mappings. 533 * Also, don't allow GTT domain if the BO doesn't have USWC flag set. 534 */ 535 if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && 536 amdgpu_bo_support_uswc(bo_flags) && 537 amdgpu_device_asic_has_dc_support(adev->asic_type) && 538 adev->mode_info.gpu_vm_support) 539 domain |= AMDGPU_GEM_DOMAIN_GTT; 540 #endif 541 542 return domain; 543 } 544 545 static const struct drm_format_info dcc_formats[] = { 546 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 547 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 548 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 549 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 550 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 551 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 552 .has_alpha = true, }, 553 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 554 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 555 .has_alpha = true, }, 556 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 2, 557 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 558 .has_alpha = true, }, 559 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 560 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 561 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 562 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 563 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 564 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 565 .has_alpha = true, }, 566 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 567 .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 568 .has_alpha = true, }, 569 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 2, 570 .cpp = { 2, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 571 }; 572 573 static const struct drm_format_info dcc_retile_formats[] = { 574 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, 575 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 576 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, 577 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 578 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, 579 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 580 .has_alpha = true, }, 581 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, 582 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 583 .has_alpha = true, }, 584 { .format = DRM_FORMAT_BGRA8888, .depth = 32, .num_planes = 3, 585 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 586 .has_alpha = true, }, 587 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3, 588 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 589 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3, 590 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 591 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3, 592 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 593 .has_alpha = true, }, 594 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3, 595 .cpp = { 4, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, 596 .has_alpha = true, }, 597 { .format = DRM_FORMAT_RGB565, .depth = 16, .num_planes = 3, 598 .cpp = { 2, 0, 0 }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, 599 }; 600 601 static const struct drm_format_info * 602 lookup_format_info(const struct drm_format_info formats[], 603 int num_formats, u32 format) 604 { 605 int i; 606 607 for (i = 0; i < num_formats; i++) { 608 if (formats[i].format == format) 609 return &formats[i]; 610 } 611 612 return NULL; 613 } 614 615 const struct drm_format_info * 616 amdgpu_lookup_format_info(u32 format, uint64_t modifier) 617 { 618 if (!IS_AMD_FMT_MOD(modifier)) 619 return NULL; 620 621 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) 622 return lookup_format_info(dcc_retile_formats, 623 ARRAY_SIZE(dcc_retile_formats), 624 format); 625 626 if (AMD_FMT_MOD_GET(DCC, modifier)) 627 return lookup_format_info(dcc_formats, ARRAY_SIZE(dcc_formats), 628 format); 629 630 /* returning NULL will cause the default format structs to be used. */ 631 return NULL; 632 } 633 634 635 /* 636 * Tries to extract the renderable DCC offset from the opaque metadata attached 637 * to the buffer. 638 */ 639 static int 640 extract_render_dcc_offset(struct amdgpu_device *adev, 641 struct drm_gem_object *obj, 642 uint64_t *offset) 643 { 644 struct amdgpu_bo *rbo; 645 int r = 0; 646 uint32_t metadata[10]; /* Something that fits a descriptor + header. */ 647 uint32_t size; 648 649 rbo = gem_to_amdgpu_bo(obj); 650 r = amdgpu_bo_reserve(rbo, false); 651 652 if (unlikely(r)) { 653 /* Don't show error message when returning -ERESTARTSYS */ 654 if (r != -ERESTARTSYS) 655 DRM_ERROR("Unable to reserve buffer: %d\n", r); 656 return r; 657 } 658 659 r = amdgpu_bo_get_metadata(rbo, metadata, sizeof(metadata), &size, NULL); 660 amdgpu_bo_unreserve(rbo); 661 662 if (r) 663 return r; 664 665 /* 666 * The first word is the metadata version, and we need space for at least 667 * the version + pci vendor+device id + 8 words for a descriptor. 668 */ 669 if (size < 40 || metadata[0] != 1) 670 return -EINVAL; 671 672 if (adev->family >= AMDGPU_FAMILY_NV) { 673 /* resource word 6/7 META_DATA_ADDRESS{_LO} */ 674 *offset = ((u64)metadata[9] << 16u) | 675 ((metadata[8] & 0xFF000000u) >> 16); 676 } else { 677 /* resource word 5/7 META_DATA_ADDRESS */ 678 *offset = ((u64)metadata[9] << 8u) | 679 ((u64)(metadata[7] & 0x1FE0000u) << 23); 680 } 681 682 return 0; 683 } 684 685 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) 686 { 687 struct amdgpu_device *adev = drm_to_adev(afb->base.dev); 688 uint64_t modifier = 0; 689 int num_pipes = 0; 690 int num_pkrs = 0; 691 692 num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; 693 num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; 694 695 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { 696 modifier = DRM_FORMAT_MOD_LINEAR; 697 } else { 698 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); 699 bool has_xor = swizzle >= 16; 700 int block_size_bits; 701 int version; 702 int pipe_xor_bits = 0; 703 int bank_xor_bits = 0; 704 int packers = 0; 705 int rb = 0; 706 int pipes = ilog2(num_pipes); 707 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); 708 709 switch (swizzle >> 2) { 710 case 0: /* 256B */ 711 block_size_bits = 8; 712 break; 713 case 1: /* 4KiB */ 714 case 5: /* 4KiB _X */ 715 block_size_bits = 12; 716 break; 717 case 2: /* 64KiB */ 718 case 4: /* 64 KiB _T */ 719 case 6: /* 64 KiB _X */ 720 block_size_bits = 16; 721 break; 722 case 7: /* 256 KiB */ 723 block_size_bits = 18; 724 break; 725 default: 726 /* RESERVED or VAR */ 727 return -EINVAL; 728 } 729 730 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) 731 version = AMD_FMT_MOD_TILE_VER_GFX11; 732 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 733 version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; 734 else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) 735 version = AMD_FMT_MOD_TILE_VER_GFX10; 736 else 737 version = AMD_FMT_MOD_TILE_VER_GFX9; 738 739 switch (swizzle & 3) { 740 case 0: /* Z microtiling */ 741 return -EINVAL; 742 case 1: /* S microtiling */ 743 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { 744 if (!has_xor) 745 version = AMD_FMT_MOD_TILE_VER_GFX9; 746 } 747 break; 748 case 2: 749 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { 750 if (!has_xor && afb->base.format->cpp[0] != 4) 751 version = AMD_FMT_MOD_TILE_VER_GFX9; 752 } 753 break; 754 case 3: 755 break; 756 } 757 758 if (has_xor) { 759 if (num_pipes == num_pkrs && num_pkrs == 0) { 760 DRM_ERROR("invalid number of pipes and packers\n"); 761 return -EINVAL; 762 } 763 764 switch (version) { 765 case AMD_FMT_MOD_TILE_VER_GFX11: 766 pipe_xor_bits = min(block_size_bits - 8, pipes); 767 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); 768 break; 769 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: 770 pipe_xor_bits = min(block_size_bits - 8, pipes); 771 packers = min(block_size_bits - 8 - pipe_xor_bits, 772 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); 773 break; 774 case AMD_FMT_MOD_TILE_VER_GFX10: 775 pipe_xor_bits = min(block_size_bits - 8, pipes); 776 break; 777 case AMD_FMT_MOD_TILE_VER_GFX9: 778 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + 779 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); 780 pipe_xor_bits = min(block_size_bits - 8, pipes + 781 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); 782 bank_xor_bits = min(block_size_bits - 8 - pipe_xor_bits, 783 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); 784 break; 785 } 786 } 787 788 modifier = AMD_FMT_MOD | 789 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | 790 AMD_FMT_MOD_SET(TILE_VERSION, version) | 791 AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | 792 AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits) | 793 AMD_FMT_MOD_SET(PACKERS, packers); 794 795 if (dcc_offset != 0) { 796 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; 797 bool dcc_i128b = version >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; 798 const struct drm_format_info *format_info; 799 u64 render_dcc_offset; 800 801 /* Enable constant encode on RAVEN2 and later. */ 802 bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN || 803 (adev->asic_type == CHIP_RAVEN && 804 adev->external_rev_id >= 0x81)) && 805 adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0); 806 807 int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B : 808 dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B : 809 AMD_FMT_MOD_DCC_BLOCK_256B; 810 811 modifier |= AMD_FMT_MOD_SET(DCC, 1) | 812 AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, dcc_constant_encode) | 813 AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, dcc_i64b) | 814 AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, dcc_i128b) | 815 AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, max_cblock_size); 816 817 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0]; 818 afb->base.pitches[1] = 819 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; 820 821 /* 822 * If the userspace driver uses retiling the tiling flags do not contain 823 * info on the renderable DCC buffer. Luckily the opaque metadata contains 824 * the info so we can try to extract it. The kernel does not use this info 825 * but we should convert it to a modifier plane for getfb2, so the 826 * userspace driver that gets it doesn't have to juggle around another DCC 827 * plane internally. 828 */ 829 if (extract_render_dcc_offset(adev, afb->base.obj[0], 830 &render_dcc_offset) == 0 && 831 render_dcc_offset != 0 && 832 render_dcc_offset != afb->base.offsets[1] && 833 render_dcc_offset < UINT_MAX) { 834 uint32_t dcc_block_bits; /* of base surface data */ 835 836 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1); 837 afb->base.offsets[2] = render_dcc_offset; 838 839 if (adev->family >= AMDGPU_FAMILY_NV) { 840 int extra_pipe = 0; 841 842 if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) && 843 pipes == packers && pipes > 1) 844 extra_pipe = 1; 845 846 dcc_block_bits = max(20, 16 + pipes + extra_pipe); 847 } else { 848 modifier |= AMD_FMT_MOD_SET(RB, rb) | 849 AMD_FMT_MOD_SET(PIPE, pipes); 850 dcc_block_bits = max(20, 18 + rb); 851 } 852 853 dcc_block_bits -= ilog2(afb->base.format->cpp[0]); 854 afb->base.pitches[2] = roundup2(afb->base.width, 855 1u << ((dcc_block_bits + 1) / 2)); 856 } 857 format_info = amdgpu_lookup_format_info(afb->base.format->format, 858 modifier); 859 if (!format_info) 860 return -EINVAL; 861 862 afb->base.format = format_info; 863 } 864 } 865 866 afb->base.modifier = modifier; 867 afb->base.flags |= DRM_MODE_FB_MODIFIERS; 868 return 0; 869 } 870 871 /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */ 872 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) 873 { 874 u64 micro_tile_mode; 875 876 /* Zero swizzle mode means linear */ 877 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0) 878 return 0; 879 880 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE); 881 switch (micro_tile_mode) { 882 case 0: /* DISPLAY */ 883 case 3: /* RENDER */ 884 return 0; 885 default: 886 drm_dbg_kms(afb->base.dev, 887 "Micro tile mode %llu not supported for scanout\n", 888 micro_tile_mode); 889 return -EINVAL; 890 } 891 } 892 893 static void get_block_dimensions(unsigned int block_log2, unsigned int cpp, 894 unsigned int *width, unsigned int *height) 895 { 896 unsigned int cpp_log2 = ilog2(cpp); 897 unsigned int pixel_log2 = block_log2 - cpp_log2; 898 unsigned int width_log2 = (pixel_log2 + 1) / 2; 899 unsigned int height_log2 = pixel_log2 - width_log2; 900 901 *width = 1 << width_log2; 902 *height = 1 << height_log2; 903 } 904 905 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned, 906 bool pipe_aligned) 907 { 908 unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier); 909 910 switch (ver) { 911 case AMD_FMT_MOD_TILE_VER_GFX9: { 912 /* 913 * TODO: for pipe aligned we may need to check the alignment of the 914 * total size of the surface, which may need to be bigger than the 915 * natural alignment due to some HW workarounds 916 */ 917 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12); 918 } 919 case AMD_FMT_MOD_TILE_VER_GFX10: 920 case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: 921 case AMD_FMT_MOD_TILE_VER_GFX11: { 922 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); 923 924 if (ver >= AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS && pipes_log2 > 1 && 925 AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2) 926 ++pipes_log2; 927 928 return max(8 + (pipe_aligned ? pipes_log2 : 0), 12); 929 } 930 default: 931 return 0; 932 } 933 } 934 935 static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane, 936 const struct drm_format_info *format, 937 unsigned int block_width, unsigned int block_height, 938 unsigned int block_size_log2) 939 { 940 unsigned int width = rfb->base.width / 941 ((plane && plane < format->num_planes) ? format->hsub : 1); 942 unsigned int height = rfb->base.height / 943 ((plane && plane < format->num_planes) ? format->vsub : 1); 944 unsigned int cpp = plane < format->num_planes ? format->cpp[plane] : 1; 945 unsigned int block_pitch = block_width * cpp; 946 unsigned int min_pitch = roundup2(width * cpp, block_pitch); 947 unsigned int block_size = 1 << block_size_log2; 948 uint64_t size; 949 950 if (rfb->base.pitches[plane] % block_pitch) { 951 drm_dbg_kms(rfb->base.dev, 952 "pitch %d for plane %d is not a multiple of block pitch %d\n", 953 rfb->base.pitches[plane], plane, block_pitch); 954 return -EINVAL; 955 } 956 if (rfb->base.pitches[plane] < min_pitch) { 957 drm_dbg_kms(rfb->base.dev, 958 "pitch %d for plane %d is less than minimum pitch %d\n", 959 rfb->base.pitches[plane], plane, min_pitch); 960 return -EINVAL; 961 } 962 963 /* Force at least natural alignment. */ 964 if (rfb->base.offsets[plane] % block_size) { 965 drm_dbg_kms(rfb->base.dev, 966 "offset 0x%x for plane %d is not a multiple of block pitch 0x%x\n", 967 rfb->base.offsets[plane], plane, block_size); 968 return -EINVAL; 969 } 970 971 size = rfb->base.offsets[plane] + 972 (uint64_t)rfb->base.pitches[plane] / block_pitch * 973 block_size * DIV_ROUND_UP(height, block_height); 974 975 if (rfb->base.obj[0]->size < size) { 976 drm_dbg_kms(rfb->base.dev, 977 "BO size 0x%zx is less than 0x%llx required for plane %d\n", 978 rfb->base.obj[0]->size, size, plane); 979 return -EINVAL; 980 } 981 982 return 0; 983 } 984 985 986 static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) 987 { 988 const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format); 989 uint64_t modifier = rfb->base.modifier; 990 int ret; 991 unsigned int i, block_width, block_height, block_size_log2; 992 993 if (rfb->base.dev->mode_config.fb_modifiers_not_supported) 994 return 0; 995 996 for (i = 0; i < format_info->num_planes; ++i) { 997 if (modifier == DRM_FORMAT_MOD_LINEAR) { 998 block_width = 256 / format_info->cpp[i]; 999 block_height = 1; 1000 block_size_log2 = 8; 1001 } else { 1002 int swizzle = AMD_FMT_MOD_GET(TILE, modifier); 1003 1004 switch ((swizzle & ~3) + 1) { 1005 case DC_SW_256B_S: 1006 block_size_log2 = 8; 1007 break; 1008 case DC_SW_4KB_S: 1009 case DC_SW_4KB_S_X: 1010 block_size_log2 = 12; 1011 break; 1012 case DC_SW_64KB_S: 1013 case DC_SW_64KB_S_T: 1014 case DC_SW_64KB_S_X: 1015 block_size_log2 = 16; 1016 break; 1017 case DC_SW_VAR_S_X: 1018 block_size_log2 = 18; 1019 break; 1020 default: 1021 drm_dbg_kms(rfb->base.dev, 1022 "Swizzle mode with unknown block size: %d\n", swizzle); 1023 return -EINVAL; 1024 } 1025 1026 get_block_dimensions(block_size_log2, format_info->cpp[i], 1027 &block_width, &block_height); 1028 } 1029 1030 ret = amdgpu_display_verify_plane(rfb, i, format_info, 1031 block_width, block_height, block_size_log2); 1032 if (ret) 1033 return ret; 1034 } 1035 1036 if (AMD_FMT_MOD_GET(DCC, modifier)) { 1037 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) { 1038 block_size_log2 = get_dcc_block_size(modifier, false, false); 1039 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], 1040 &block_width, &block_height); 1041 ret = amdgpu_display_verify_plane(rfb, i, format_info, 1042 block_width, block_height, 1043 block_size_log2); 1044 if (ret) 1045 return ret; 1046 1047 ++i; 1048 block_size_log2 = get_dcc_block_size(modifier, true, true); 1049 } else { 1050 bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); 1051 1052 block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned); 1053 } 1054 get_block_dimensions(block_size_log2 + 8, format_info->cpp[0], 1055 &block_width, &block_height); 1056 ret = amdgpu_display_verify_plane(rfb, i, format_info, 1057 block_width, block_height, block_size_log2); 1058 if (ret) 1059 return ret; 1060 } 1061 1062 return 0; 1063 } 1064 1065 static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, 1066 uint64_t *tiling_flags, bool *tmz_surface) 1067 { 1068 struct amdgpu_bo *rbo; 1069 int r; 1070 1071 if (!amdgpu_fb) { 1072 *tiling_flags = 0; 1073 *tmz_surface = false; 1074 return 0; 1075 } 1076 1077 rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); 1078 r = amdgpu_bo_reserve(rbo, false); 1079 1080 if (unlikely(r)) { 1081 /* Don't show error message when returning -ERESTARTSYS */ 1082 if (r != -ERESTARTSYS) 1083 DRM_ERROR("Unable to reserve buffer: %d\n", r); 1084 return r; 1085 } 1086 1087 if (tiling_flags) 1088 amdgpu_bo_get_tiling_flags(rbo, tiling_flags); 1089 1090 if (tmz_surface) 1091 *tmz_surface = amdgpu_bo_encrypted(rbo); 1092 1093 amdgpu_bo_unreserve(rbo); 1094 1095 return r; 1096 } 1097 1098 static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, 1099 struct amdgpu_framebuffer *rfb, 1100 struct drm_file *file_priv, 1101 const struct drm_mode_fb_cmd2 *mode_cmd, 1102 struct drm_gem_object *obj) 1103 { 1104 int ret; 1105 1106 rfb->base.obj[0] = obj; 1107 drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); 1108 /* Verify that the modifier is supported. */ 1109 if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, 1110 mode_cmd->modifier[0])) { 1111 drm_dbg_kms(dev, 1112 "unsupported pixel format %p4cc / modifier 0x%llx\n", 1113 &mode_cmd->pixel_format, mode_cmd->modifier[0]); 1114 1115 ret = -EINVAL; 1116 goto err; 1117 } 1118 1119 ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); 1120 if (ret) 1121 goto err; 1122 1123 if (drm_drv_uses_atomic_modeset(dev)) 1124 ret = drm_framebuffer_init(dev, &rfb->base, 1125 &amdgpu_fb_funcs_atomic); 1126 else 1127 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 1128 1129 if (ret) 1130 goto err; 1131 1132 return 0; 1133 err: 1134 drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret); 1135 rfb->base.obj[0] = NULL; 1136 return ret; 1137 } 1138 1139 static int amdgpu_display_framebuffer_init(struct drm_device *dev, 1140 struct amdgpu_framebuffer *rfb, 1141 const struct drm_mode_fb_cmd2 *mode_cmd, 1142 struct drm_gem_object *obj) 1143 { 1144 struct amdgpu_device *adev = drm_to_adev(dev); 1145 int ret, i; 1146 1147 /* 1148 * This needs to happen before modifier conversion as that might change 1149 * the number of planes. 1150 */ 1151 for (i = 1; i < rfb->base.format->num_planes; ++i) { 1152 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { 1153 drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n", 1154 i, mode_cmd->handles[0], mode_cmd->handles[i]); 1155 ret = -EINVAL; 1156 return ret; 1157 } 1158 } 1159 1160 ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface); 1161 if (ret) 1162 return ret; 1163 1164 if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) { 1165 drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, 1166 "GFX9+ requires FB check based on format modifier\n"); 1167 ret = check_tiling_flags_gfx6(rfb); 1168 if (ret) 1169 return ret; 1170 } 1171 1172 if (!dev->mode_config.fb_modifiers_not_supported && 1173 !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { 1174 ret = convert_tiling_flags_to_modifier(rfb); 1175 if (ret) { 1176 drm_dbg_kms(dev, "Failed to convert tiling flags 0x%llX to a modifier", 1177 rfb->tiling_flags); 1178 return ret; 1179 } 1180 } 1181 1182 ret = amdgpu_display_verify_sizes(rfb); 1183 if (ret) 1184 return ret; 1185 1186 for (i = 0; i < rfb->base.format->num_planes; ++i) { 1187 drm_gem_object_get(rfb->base.obj[0]); 1188 rfb->base.obj[i] = rfb->base.obj[0]; 1189 } 1190 1191 return 0; 1192 } 1193 1194 struct drm_framebuffer * 1195 amdgpu_display_user_framebuffer_create(struct drm_device *dev, 1196 struct drm_file *file_priv, 1197 const struct drm_mode_fb_cmd2 *mode_cmd) 1198 { 1199 struct amdgpu_framebuffer *amdgpu_fb; 1200 struct drm_gem_object *obj; 1201 struct amdgpu_bo *bo; 1202 uint32_t domains; 1203 int ret; 1204 1205 obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]); 1206 if (obj == NULL) { 1207 drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, " 1208 "can't create framebuffer\n", mode_cmd->handles[0]); 1209 return ERR_PTR(-ENOENT); 1210 } 1211 1212 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 1213 bo = gem_to_amdgpu_bo(obj); 1214 domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); 1215 if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) { 1216 drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n"); 1217 drm_gem_object_put(obj); 1218 return ERR_PTR(-EINVAL); 1219 } 1220 1221 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 1222 if (amdgpu_fb == NULL) { 1223 drm_gem_object_put(obj); 1224 return ERR_PTR(-ENOMEM); 1225 } 1226 1227 ret = amdgpu_display_gem_fb_verify_and_init(dev, amdgpu_fb, file_priv, 1228 mode_cmd, obj); 1229 if (ret) { 1230 kfree(amdgpu_fb); 1231 drm_gem_object_put(obj); 1232 return ERR_PTR(ret); 1233 } 1234 1235 drm_gem_object_put(obj); 1236 return &amdgpu_fb->base; 1237 } 1238 1239 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 1240 .fb_create = amdgpu_display_user_framebuffer_create, 1241 }; 1242 1243 static const struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 1244 { { UNDERSCAN_OFF, "off" }, 1245 { UNDERSCAN_ON, "on" }, 1246 { UNDERSCAN_AUTO, "auto" }, 1247 }; 1248 1249 static const struct drm_prop_enum_list amdgpu_audio_enum_list[] = 1250 { { AMDGPU_AUDIO_DISABLE, "off" }, 1251 { AMDGPU_AUDIO_ENABLE, "on" }, 1252 { AMDGPU_AUDIO_AUTO, "auto" }, 1253 }; 1254 1255 /* XXX support different dither options? spatial, temporal, both, etc. */ 1256 static const struct drm_prop_enum_list amdgpu_dither_enum_list[] = 1257 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 1258 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 1259 }; 1260 1261 int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) 1262 { 1263 int sz; 1264 1265 adev->mode_info.coherent_mode_property = 1266 drm_property_create_range(adev_to_drm(adev), 0, "coherent", 0, 1); 1267 if (!adev->mode_info.coherent_mode_property) 1268 return -ENOMEM; 1269 1270 adev->mode_info.load_detect_property = 1271 drm_property_create_range(adev_to_drm(adev), 0, "load detection", 0, 1); 1272 if (!adev->mode_info.load_detect_property) 1273 return -ENOMEM; 1274 1275 drm_mode_create_scaling_mode_property(adev_to_drm(adev)); 1276 1277 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 1278 adev->mode_info.underscan_property = 1279 drm_property_create_enum(adev_to_drm(adev), 0, 1280 "underscan", 1281 amdgpu_underscan_enum_list, sz); 1282 1283 adev->mode_info.underscan_hborder_property = 1284 drm_property_create_range(adev_to_drm(adev), 0, 1285 "underscan hborder", 0, 128); 1286 if (!adev->mode_info.underscan_hborder_property) 1287 return -ENOMEM; 1288 1289 adev->mode_info.underscan_vborder_property = 1290 drm_property_create_range(adev_to_drm(adev), 0, 1291 "underscan vborder", 0, 128); 1292 if (!adev->mode_info.underscan_vborder_property) 1293 return -ENOMEM; 1294 1295 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 1296 adev->mode_info.audio_property = 1297 drm_property_create_enum(adev_to_drm(adev), 0, 1298 "audio", 1299 amdgpu_audio_enum_list, sz); 1300 1301 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 1302 adev->mode_info.dither_property = 1303 drm_property_create_enum(adev_to_drm(adev), 0, 1304 "dither", 1305 amdgpu_dither_enum_list, sz); 1306 1307 if (amdgpu_device_has_dc_support(adev)) { 1308 adev->mode_info.abm_level_property = 1309 drm_property_create_range(adev_to_drm(adev), 0, 1310 "abm level", 0, 4); 1311 if (!adev->mode_info.abm_level_property) 1312 return -ENOMEM; 1313 } 1314 1315 return 0; 1316 } 1317 1318 void amdgpu_display_update_priority(struct amdgpu_device *adev) 1319 { 1320 /* adjustment options for the display watermarks */ 1321 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 1322 adev->mode_info.disp_priority = 0; 1323 else 1324 adev->mode_info.disp_priority = amdgpu_disp_priority; 1325 1326 } 1327 1328 static bool amdgpu_display_is_hdtv_mode(const struct drm_display_mode *mode) 1329 { 1330 /* try and guess if this is a tv or a monitor */ 1331 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 1332 (mode->vdisplay == 576) || /* 576p */ 1333 (mode->vdisplay == 720) || /* 720p */ 1334 (mode->vdisplay == 1080)) /* 1080p */ 1335 return true; 1336 else 1337 return false; 1338 } 1339 1340 bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 1341 const struct drm_display_mode *mode, 1342 struct drm_display_mode *adjusted_mode) 1343 { 1344 struct drm_device *dev = crtc->dev; 1345 struct drm_encoder *encoder; 1346 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1347 struct amdgpu_encoder *amdgpu_encoder; 1348 struct drm_connector *connector; 1349 u32 src_v = 1, dst_v = 1; 1350 u32 src_h = 1, dst_h = 1; 1351 1352 amdgpu_crtc->h_border = 0; 1353 amdgpu_crtc->v_border = 0; 1354 1355 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1356 if (encoder->crtc != crtc) 1357 continue; 1358 amdgpu_encoder = to_amdgpu_encoder(encoder); 1359 connector = amdgpu_get_connector_for_encoder(encoder); 1360 1361 /* set scaling */ 1362 if (amdgpu_encoder->rmx_type == RMX_OFF) 1363 amdgpu_crtc->rmx_type = RMX_OFF; 1364 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 1365 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 1366 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 1367 else 1368 amdgpu_crtc->rmx_type = RMX_OFF; 1369 /* copy native mode */ 1370 memcpy(&amdgpu_crtc->native_mode, 1371 &amdgpu_encoder->native_mode, 1372 sizeof(struct drm_display_mode)); 1373 src_v = crtc->mode.vdisplay; 1374 dst_v = amdgpu_crtc->native_mode.vdisplay; 1375 src_h = crtc->mode.hdisplay; 1376 dst_h = amdgpu_crtc->native_mode.hdisplay; 1377 1378 /* fix up for overscan on hdmi */ 1379 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 1380 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 1381 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 1382 connector->display_info.is_hdmi && 1383 amdgpu_display_is_hdtv_mode(mode)))) { 1384 if (amdgpu_encoder->underscan_hborder != 0) 1385 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 1386 else 1387 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 1388 if (amdgpu_encoder->underscan_vborder != 0) 1389 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 1390 else 1391 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 1392 amdgpu_crtc->rmx_type = RMX_FULL; 1393 src_v = crtc->mode.vdisplay; 1394 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 1395 src_h = crtc->mode.hdisplay; 1396 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 1397 } 1398 } 1399 if (amdgpu_crtc->rmx_type != RMX_OFF) { 1400 fixed20_12 a, b; 1401 a.full = dfixed_const(src_v); 1402 b.full = dfixed_const(dst_v); 1403 amdgpu_crtc->vsc.full = dfixed_div(a, b); 1404 a.full = dfixed_const(src_h); 1405 b.full = dfixed_const(dst_h); 1406 amdgpu_crtc->hsc.full = dfixed_div(a, b); 1407 } else { 1408 amdgpu_crtc->vsc.full = dfixed_const(1); 1409 amdgpu_crtc->hsc.full = dfixed_const(1); 1410 } 1411 return true; 1412 } 1413 1414 /* 1415 * Retrieve current video scanout position of crtc on a given gpu, and 1416 * an optional accurate timestamp of when query happened. 1417 * 1418 * \param dev Device to query. 1419 * \param pipe Crtc to query. 1420 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 1421 * For driver internal use only also supports these flags: 1422 * 1423 * USE_REAL_VBLANKSTART to use the real start of vblank instead 1424 * of a fudged earlier start of vblank. 1425 * 1426 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 1427 * fudged earlier start of vblank in *vpos and the distance 1428 * to true start of vblank in *hpos. 1429 * 1430 * \param *vpos Location where vertical scanout position should be stored. 1431 * \param *hpos Location where horizontal scanout position should go. 1432 * \param *stime Target location for timestamp taken immediately before 1433 * scanout position query. Can be NULL to skip timestamp. 1434 * \param *etime Target location for timestamp taken immediately after 1435 * scanout position query. Can be NULL to skip timestamp. 1436 * 1437 * Returns vpos as a positive number while in active scanout area. 1438 * Returns vpos as a negative number inside vblank, counting the number 1439 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 1440 * until start of active scanout / end of vblank." 1441 * 1442 * \return Flags, or'ed together as follows: 1443 * 1444 * DRM_SCANOUTPOS_VALID = Query successful. 1445 * DRM_SCANOUTPOS_INVBL = Inside vblank. 1446 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 1447 * this flag means that returned position may be offset by a constant but 1448 * unknown small number of scanlines wrt. real scanout position. 1449 * 1450 */ 1451 int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, 1452 unsigned int pipe, unsigned int flags, int *vpos, 1453 int *hpos, ktime_t *stime, ktime_t *etime, 1454 const struct drm_display_mode *mode) 1455 { 1456 u32 vbl = 0, position = 0; 1457 int vbl_start, vbl_end, vtotal, ret = 0; 1458 bool in_vbl = true; 1459 1460 struct amdgpu_device *adev = drm_to_adev(dev); 1461 1462 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 1463 1464 /* Get optional system timestamp before query. */ 1465 if (stime) 1466 *stime = ktime_get(); 1467 1468 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 1469 ret |= DRM_SCANOUTPOS_VALID; 1470 1471 /* Get optional system timestamp after query. */ 1472 if (etime) 1473 *etime = ktime_get(); 1474 1475 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 1476 1477 /* Decode into vertical and horizontal scanout position. */ 1478 *vpos = position & 0x1fff; 1479 *hpos = (position >> 16) & 0x1fff; 1480 1481 /* Valid vblank area boundaries from gpu retrieved? */ 1482 if (vbl > 0) { 1483 /* Yes: Decode. */ 1484 ret |= DRM_SCANOUTPOS_ACCURATE; 1485 vbl_start = vbl & 0x1fff; 1486 vbl_end = (vbl >> 16) & 0x1fff; 1487 } 1488 else { 1489 /* No: Fake something reasonable which gives at least ok results. */ 1490 vbl_start = mode->crtc_vdisplay; 1491 vbl_end = 0; 1492 } 1493 1494 /* Called from driver internal vblank counter query code? */ 1495 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1496 /* Caller wants distance from real vbl_start in *hpos */ 1497 *hpos = *vpos - vbl_start; 1498 } 1499 1500 /* Fudge vblank to start a few scanlines earlier to handle the 1501 * problem that vblank irqs fire a few scanlines before start 1502 * of vblank. Some driver internal callers need the true vblank 1503 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 1504 * 1505 * The cause of the "early" vblank irq is that the irq is triggered 1506 * by the line buffer logic when the line buffer read position enters 1507 * the vblank, whereas our crtc scanout position naturally lags the 1508 * line buffer read position. 1509 */ 1510 if (!(flags & USE_REAL_VBLANKSTART)) 1511 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 1512 1513 /* Test scanout position against vblank region. */ 1514 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 1515 in_vbl = false; 1516 1517 /* In vblank? */ 1518 if (in_vbl) 1519 ret |= DRM_SCANOUTPOS_IN_VBLANK; 1520 1521 /* Called from driver internal vblank counter query code? */ 1522 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 1523 /* Caller wants distance from fudged earlier vbl_start */ 1524 *vpos -= vbl_start; 1525 return ret; 1526 } 1527 1528 /* Check if inside vblank area and apply corrective offsets: 1529 * vpos will then be >=0 in video scanout area, but negative 1530 * within vblank area, counting down the number of lines until 1531 * start of scanout. 1532 */ 1533 1534 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 1535 if (in_vbl && (*vpos >= vbl_start)) { 1536 vtotal = mode->crtc_vtotal; 1537 1538 /* With variable refresh rate displays the vpos can exceed 1539 * the vtotal value. Clamp to 0 to return -vbl_end instead 1540 * of guessing the remaining number of lines until scanout. 1541 */ 1542 *vpos = (*vpos < vtotal) ? (*vpos - vtotal) : 0; 1543 } 1544 1545 /* Correct for shifted end of vbl at vbl_end. */ 1546 *vpos = *vpos - vbl_end; 1547 1548 return ret; 1549 } 1550 1551 int amdgpu_display_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 1552 { 1553 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 1554 return AMDGPU_CRTC_IRQ_NONE; 1555 1556 switch (crtc) { 1557 case 0: 1558 return AMDGPU_CRTC_IRQ_VBLANK1; 1559 case 1: 1560 return AMDGPU_CRTC_IRQ_VBLANK2; 1561 case 2: 1562 return AMDGPU_CRTC_IRQ_VBLANK3; 1563 case 3: 1564 return AMDGPU_CRTC_IRQ_VBLANK4; 1565 case 4: 1566 return AMDGPU_CRTC_IRQ_VBLANK5; 1567 case 5: 1568 return AMDGPU_CRTC_IRQ_VBLANK6; 1569 default: 1570 return AMDGPU_CRTC_IRQ_NONE; 1571 } 1572 } 1573 1574 bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, 1575 bool in_vblank_irq, int *vpos, 1576 int *hpos, ktime_t *stime, ktime_t *etime, 1577 const struct drm_display_mode *mode) 1578 { 1579 struct drm_device *dev = crtc->dev; 1580 unsigned int pipe = crtc->index; 1581 1582 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1583 stime, etime, mode); 1584 } 1585 1586 static bool 1587 amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) 1588 { 1589 struct drm_device *dev = adev_to_drm(adev); 1590 struct drm_fb_helper *fb_helper = dev->fb_helper; 1591 1592 if (!fb_helper || !fb_helper->buffer) 1593 return false; 1594 1595 if (gem_to_amdgpu_bo(fb_helper->buffer->gem) != robj) 1596 return false; 1597 1598 return true; 1599 } 1600 1601 int amdgpu_display_suspend_helper(struct amdgpu_device *adev) 1602 { 1603 struct drm_device *dev = adev_to_drm(adev); 1604 struct drm_crtc *crtc; 1605 struct drm_connector *connector; 1606 struct drm_connector_list_iter iter; 1607 int r; 1608 1609 /* turn off display hw */ 1610 drm_modeset_lock_all(dev); 1611 drm_connector_list_iter_begin(dev, &iter); 1612 drm_for_each_connector_iter(connector, &iter) 1613 drm_helper_connector_dpms(connector, 1614 DRM_MODE_DPMS_OFF); 1615 drm_connector_list_iter_end(&iter); 1616 drm_modeset_unlock_all(dev); 1617 /* unpin the front buffers and cursors */ 1618 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1619 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1620 struct drm_framebuffer *fb = crtc->primary->fb; 1621 struct amdgpu_bo *robj; 1622 1623 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 1624 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1625 r = amdgpu_bo_reserve(aobj, true); 1626 if (r == 0) { 1627 amdgpu_bo_unpin(aobj); 1628 amdgpu_bo_unreserve(aobj); 1629 } 1630 } 1631 1632 if (fb == NULL || fb->obj[0] == NULL) { 1633 continue; 1634 } 1635 robj = gem_to_amdgpu_bo(fb->obj[0]); 1636 if (!amdgpu_display_robj_is_fb(adev, robj)) { 1637 r = amdgpu_bo_reserve(robj, true); 1638 if (r == 0) { 1639 amdgpu_bo_unpin(robj); 1640 amdgpu_bo_unreserve(robj); 1641 } 1642 } 1643 } 1644 return 0; 1645 } 1646 1647 int amdgpu_display_resume_helper(struct amdgpu_device *adev) 1648 { 1649 struct drm_device *dev = adev_to_drm(adev); 1650 struct drm_connector *connector; 1651 struct drm_connector_list_iter iter; 1652 struct drm_crtc *crtc; 1653 int r; 1654 1655 /* pin cursors */ 1656 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1657 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1658 1659 if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) { 1660 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1661 r = amdgpu_bo_reserve(aobj, true); 1662 if (r == 0) { 1663 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 1664 if (r != 0) 1665 dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); 1666 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 1667 amdgpu_bo_unreserve(aobj); 1668 } 1669 } 1670 } 1671 1672 drm_helper_resume_force_mode(dev); 1673 1674 /* turn on display hw */ 1675 drm_modeset_lock_all(dev); 1676 1677 drm_connector_list_iter_begin(dev, &iter); 1678 drm_for_each_connector_iter(connector, &iter) 1679 drm_helper_connector_dpms(connector, 1680 DRM_MODE_DPMS_ON); 1681 drm_connector_list_iter_end(&iter); 1682 1683 drm_modeset_unlock_all(dev); 1684 1685 return 0; 1686 } 1687 1688