1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: monk liu <monk.liu@amd.com> 23 */ 24 25 #include <drm/drm_auth.h> 26 #include "amdgpu.h" 27 #include "amdgpu_sched.h" 28 #include "amdgpu_ras.h" 29 30 #define to_amdgpu_ctx_entity(e) \ 31 container_of((e), struct amdgpu_ctx_entity, entity) 32 33 const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = { 34 [AMDGPU_HW_IP_GFX] = 1, 35 [AMDGPU_HW_IP_COMPUTE] = 4, 36 [AMDGPU_HW_IP_DMA] = 2, 37 [AMDGPU_HW_IP_UVD] = 1, 38 [AMDGPU_HW_IP_VCE] = 1, 39 [AMDGPU_HW_IP_UVD_ENC] = 1, 40 [AMDGPU_HW_IP_VCN_DEC] = 1, 41 [AMDGPU_HW_IP_VCN_ENC] = 1, 42 [AMDGPU_HW_IP_VCN_JPEG] = 1, 43 }; 44 45 static int amdgpu_ctx_priority_permit(struct drm_file *filp, 46 enum drm_sched_priority priority) 47 { 48 if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX) 49 return -EINVAL; 50 51 /* NORMAL and below are accessible by everyone */ 52 if (priority <= DRM_SCHED_PRIORITY_NORMAL) 53 return 0; 54 55 #ifdef notyet 56 if (capable(CAP_SYS_NICE)) 57 return 0; 58 #endif 59 60 if (drm_is_current_master(filp)) 61 return 0; 62 63 return -EACCES; 64 } 65 66 static enum gfx_pipe_priority amdgpu_ctx_sched_prio_to_compute_prio(enum drm_sched_priority prio) 67 { 68 switch (prio) { 69 case DRM_SCHED_PRIORITY_HIGH_HW: 70 case DRM_SCHED_PRIORITY_KERNEL: 71 return AMDGPU_GFX_PIPE_PRIO_HIGH; 72 default: 73 return AMDGPU_GFX_PIPE_PRIO_NORMAL; 74 } 75 } 76 77 static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, const u32 hw_ip, const u32 ring) 78 { 79 struct amdgpu_device *adev = ctx->adev; 80 struct amdgpu_ctx_entity *entity; 81 struct drm_gpu_scheduler **scheds = NULL, *sched = NULL; 82 unsigned num_scheds = 0; 83 enum gfx_pipe_priority hw_prio; 84 enum drm_sched_priority priority; 85 int r; 86 87 entity = kcalloc(1, offsetof(typeof(*entity), fences[amdgpu_sched_jobs]), 88 GFP_KERNEL); 89 if (!entity) 90 return -ENOMEM; 91 92 entity->sequence = 1; 93 priority = (ctx->override_priority == DRM_SCHED_PRIORITY_UNSET) ? 94 ctx->init_priority : ctx->override_priority; 95 switch (hw_ip) { 96 case AMDGPU_HW_IP_GFX: 97 sched = &adev->gfx.gfx_ring[0].sched; 98 scheds = &sched; 99 num_scheds = 1; 100 break; 101 case AMDGPU_HW_IP_COMPUTE: 102 hw_prio = amdgpu_ctx_sched_prio_to_compute_prio(priority); 103 scheds = adev->gfx.compute_prio_sched[hw_prio]; 104 num_scheds = adev->gfx.num_compute_sched[hw_prio]; 105 break; 106 case AMDGPU_HW_IP_DMA: 107 scheds = adev->sdma.sdma_sched; 108 num_scheds = adev->sdma.num_sdma_sched; 109 break; 110 case AMDGPU_HW_IP_UVD: 111 sched = &adev->uvd.inst[0].ring.sched; 112 scheds = &sched; 113 num_scheds = 1; 114 break; 115 case AMDGPU_HW_IP_VCE: 116 sched = &adev->vce.ring[0].sched; 117 scheds = &sched; 118 num_scheds = 1; 119 break; 120 case AMDGPU_HW_IP_UVD_ENC: 121 sched = &adev->uvd.inst[0].ring_enc[0].sched; 122 scheds = &sched; 123 num_scheds = 1; 124 break; 125 case AMDGPU_HW_IP_VCN_DEC: 126 sched = drm_sched_pick_best(adev->vcn.vcn_dec_sched, 127 adev->vcn.num_vcn_dec_sched); 128 scheds = &sched; 129 num_scheds = 1; 130 break; 131 case AMDGPU_HW_IP_VCN_ENC: 132 sched = drm_sched_pick_best(adev->vcn.vcn_enc_sched, 133 adev->vcn.num_vcn_enc_sched); 134 scheds = &sched; 135 num_scheds = 1; 136 break; 137 case AMDGPU_HW_IP_VCN_JPEG: 138 scheds = adev->jpeg.jpeg_sched; 139 num_scheds = adev->jpeg.num_jpeg_sched; 140 break; 141 } 142 143 r = drm_sched_entity_init(&entity->entity, priority, scheds, num_scheds, 144 &ctx->guilty); 145 if (r) 146 goto error_free_entity; 147 148 ctx->entities[hw_ip][ring] = entity; 149 return 0; 150 151 error_free_entity: 152 kfree(entity); 153 154 return r; 155 } 156 157 static int amdgpu_ctx_init(struct amdgpu_device *adev, 158 enum drm_sched_priority priority, 159 struct drm_file *filp, 160 struct amdgpu_ctx *ctx) 161 { 162 int r; 163 164 r = amdgpu_ctx_priority_permit(filp, priority); 165 if (r) 166 return r; 167 168 memset(ctx, 0, sizeof(*ctx)); 169 170 ctx->adev = adev; 171 172 kref_init(&ctx->refcount); 173 mtx_init(&ctx->ring_lock, IPL_TTY); 174 rw_init(&ctx->lock, "amctxlk"); 175 176 ctx->reset_counter = atomic_read(&adev->gpu_reset_counter); 177 ctx->reset_counter_query = ctx->reset_counter; 178 ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter); 179 ctx->init_priority = priority; 180 ctx->override_priority = DRM_SCHED_PRIORITY_UNSET; 181 182 return 0; 183 184 } 185 186 static void amdgpu_ctx_fini_entity(struct amdgpu_ctx_entity *entity) 187 { 188 189 int i; 190 191 if (!entity) 192 return; 193 194 for (i = 0; i < amdgpu_sched_jobs; ++i) 195 dma_fence_put(entity->fences[i]); 196 197 kfree(entity); 198 } 199 200 static void amdgpu_ctx_fini(struct kref *ref) 201 { 202 struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount); 203 struct amdgpu_device *adev = ctx->adev; 204 unsigned i, j; 205 206 if (!adev) 207 return; 208 209 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 210 for (j = 0; j < AMDGPU_MAX_ENTITY_NUM; ++j) { 211 amdgpu_ctx_fini_entity(ctx->entities[i][j]); 212 ctx->entities[i][j] = NULL; 213 } 214 } 215 216 mutex_destroy(&ctx->lock); 217 kfree(ctx); 218 } 219 220 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, 221 u32 ring, struct drm_sched_entity **entity) 222 { 223 int r; 224 225 if (hw_ip >= AMDGPU_HW_IP_NUM) { 226 DRM_ERROR("unknown HW IP type: %d\n", hw_ip); 227 return -EINVAL; 228 } 229 230 /* Right now all IPs have only one instance - multiple rings. */ 231 if (instance != 0) { 232 DRM_DEBUG("invalid ip instance: %d\n", instance); 233 return -EINVAL; 234 } 235 236 if (ring >= amdgpu_ctx_num_entities[hw_ip]) { 237 DRM_DEBUG("invalid ring: %d %d\n", hw_ip, ring); 238 return -EINVAL; 239 } 240 241 if (ctx->entities[hw_ip][ring] == NULL) { 242 r = amdgpu_ctx_init_entity(ctx, hw_ip, ring); 243 if (r) 244 return r; 245 } 246 247 *entity = &ctx->entities[hw_ip][ring]->entity; 248 return 0; 249 } 250 251 static int amdgpu_ctx_alloc(struct amdgpu_device *adev, 252 struct amdgpu_fpriv *fpriv, 253 struct drm_file *filp, 254 enum drm_sched_priority priority, 255 uint32_t *id) 256 { 257 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 258 struct amdgpu_ctx *ctx; 259 int r; 260 261 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 262 if (!ctx) 263 return -ENOMEM; 264 265 mutex_lock(&mgr->lock); 266 r = idr_alloc(&mgr->ctx_handles, ctx, 1, AMDGPU_VM_MAX_NUM_CTX, GFP_KERNEL); 267 if (r < 0) { 268 mutex_unlock(&mgr->lock); 269 kfree(ctx); 270 return r; 271 } 272 273 *id = (uint32_t)r; 274 r = amdgpu_ctx_init(adev, priority, filp, ctx); 275 if (r) { 276 idr_remove(&mgr->ctx_handles, *id); 277 *id = 0; 278 kfree(ctx); 279 } 280 mutex_unlock(&mgr->lock); 281 return r; 282 } 283 284 static void amdgpu_ctx_do_release(struct kref *ref) 285 { 286 struct amdgpu_ctx *ctx; 287 u32 i, j; 288 289 ctx = container_of(ref, struct amdgpu_ctx, refcount); 290 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 291 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 292 if (!ctx->entities[i][j]) 293 continue; 294 295 drm_sched_entity_destroy(&ctx->entities[i][j]->entity); 296 } 297 } 298 299 amdgpu_ctx_fini(ref); 300 } 301 302 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id) 303 { 304 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 305 struct amdgpu_ctx *ctx; 306 307 mutex_lock(&mgr->lock); 308 ctx = idr_remove(&mgr->ctx_handles, id); 309 if (ctx) 310 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 311 mutex_unlock(&mgr->lock); 312 return ctx ? 0 : -EINVAL; 313 } 314 315 static int amdgpu_ctx_query(struct amdgpu_device *adev, 316 struct amdgpu_fpriv *fpriv, uint32_t id, 317 union drm_amdgpu_ctx_out *out) 318 { 319 struct amdgpu_ctx *ctx; 320 struct amdgpu_ctx_mgr *mgr; 321 unsigned reset_counter; 322 323 if (!fpriv) 324 return -EINVAL; 325 326 mgr = &fpriv->ctx_mgr; 327 mutex_lock(&mgr->lock); 328 ctx = idr_find(&mgr->ctx_handles, id); 329 if (!ctx) { 330 mutex_unlock(&mgr->lock); 331 return -EINVAL; 332 } 333 334 /* TODO: these two are always zero */ 335 out->state.flags = 0x0; 336 out->state.hangs = 0x0; 337 338 /* determine if a GPU reset has occured since the last call */ 339 reset_counter = atomic_read(&adev->gpu_reset_counter); 340 /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ 341 if (ctx->reset_counter_query == reset_counter) 342 out->state.reset_status = AMDGPU_CTX_NO_RESET; 343 else 344 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; 345 ctx->reset_counter_query = reset_counter; 346 347 mutex_unlock(&mgr->lock); 348 return 0; 349 } 350 351 static int amdgpu_ctx_query2(struct amdgpu_device *adev, 352 struct amdgpu_fpriv *fpriv, uint32_t id, 353 union drm_amdgpu_ctx_out *out) 354 { 355 struct amdgpu_ctx *ctx; 356 struct amdgpu_ctx_mgr *mgr; 357 unsigned long ras_counter; 358 359 if (!fpriv) 360 return -EINVAL; 361 362 mgr = &fpriv->ctx_mgr; 363 mutex_lock(&mgr->lock); 364 ctx = idr_find(&mgr->ctx_handles, id); 365 if (!ctx) { 366 mutex_unlock(&mgr->lock); 367 return -EINVAL; 368 } 369 370 out->state.flags = 0x0; 371 out->state.hangs = 0x0; 372 373 if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter)) 374 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET; 375 376 if (ctx->vram_lost_counter != atomic_read(&adev->vram_lost_counter)) 377 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST; 378 379 if (atomic_read(&ctx->guilty)) 380 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; 381 382 /*query ue count*/ 383 ras_counter = amdgpu_ras_query_error_count(adev, false); 384 /*ras counter is monotonic increasing*/ 385 if (ras_counter != ctx->ras_counter_ue) { 386 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE; 387 ctx->ras_counter_ue = ras_counter; 388 } 389 390 /*query ce count*/ 391 ras_counter = amdgpu_ras_query_error_count(adev, true); 392 if (ras_counter != ctx->ras_counter_ce) { 393 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE; 394 ctx->ras_counter_ce = ras_counter; 395 } 396 397 mutex_unlock(&mgr->lock); 398 return 0; 399 } 400 401 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 402 struct drm_file *filp) 403 { 404 int r; 405 uint32_t id; 406 enum drm_sched_priority priority; 407 408 union drm_amdgpu_ctx *args = data; 409 struct amdgpu_device *adev = dev->dev_private; 410 struct amdgpu_fpriv *fpriv = filp->driver_priv; 411 412 r = 0; 413 id = args->in.ctx_id; 414 priority = amdgpu_to_sched_priority(args->in.priority); 415 416 /* For backwards compatibility reasons, we need to accept 417 * ioctls with garbage in the priority field */ 418 if (priority == DRM_SCHED_PRIORITY_INVALID) 419 priority = DRM_SCHED_PRIORITY_NORMAL; 420 421 switch (args->in.op) { 422 case AMDGPU_CTX_OP_ALLOC_CTX: 423 r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id); 424 args->out.alloc.ctx_id = id; 425 break; 426 case AMDGPU_CTX_OP_FREE_CTX: 427 r = amdgpu_ctx_free(fpriv, id); 428 break; 429 case AMDGPU_CTX_OP_QUERY_STATE: 430 r = amdgpu_ctx_query(adev, fpriv, id, &args->out); 431 break; 432 case AMDGPU_CTX_OP_QUERY_STATE2: 433 r = amdgpu_ctx_query2(adev, fpriv, id, &args->out); 434 break; 435 default: 436 return -EINVAL; 437 } 438 439 return r; 440 } 441 442 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) 443 { 444 struct amdgpu_ctx *ctx; 445 struct amdgpu_ctx_mgr *mgr; 446 447 if (!fpriv) 448 return NULL; 449 450 mgr = &fpriv->ctx_mgr; 451 452 mutex_lock(&mgr->lock); 453 ctx = idr_find(&mgr->ctx_handles, id); 454 if (ctx) 455 kref_get(&ctx->refcount); 456 mutex_unlock(&mgr->lock); 457 return ctx; 458 } 459 460 int amdgpu_ctx_put(struct amdgpu_ctx *ctx) 461 { 462 if (ctx == NULL) 463 return -EINVAL; 464 465 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 466 return 0; 467 } 468 469 void amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, 470 struct drm_sched_entity *entity, 471 struct dma_fence *fence, uint64_t* handle) 472 { 473 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 474 uint64_t seq = centity->sequence; 475 struct dma_fence *other = NULL; 476 unsigned idx = 0; 477 478 idx = seq & (amdgpu_sched_jobs - 1); 479 other = centity->fences[idx]; 480 if (other) 481 BUG_ON(!dma_fence_is_signaled(other)); 482 483 dma_fence_get(fence); 484 485 spin_lock(&ctx->ring_lock); 486 centity->fences[idx] = fence; 487 centity->sequence++; 488 spin_unlock(&ctx->ring_lock); 489 490 dma_fence_put(other); 491 if (handle) 492 *handle = seq; 493 } 494 495 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 496 struct drm_sched_entity *entity, 497 uint64_t seq) 498 { 499 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 500 struct dma_fence *fence; 501 502 spin_lock(&ctx->ring_lock); 503 504 if (seq == ~0ull) 505 seq = centity->sequence - 1; 506 507 if (seq >= centity->sequence) { 508 spin_unlock(&ctx->ring_lock); 509 return ERR_PTR(-EINVAL); 510 } 511 512 513 if (seq + amdgpu_sched_jobs < centity->sequence) { 514 spin_unlock(&ctx->ring_lock); 515 return NULL; 516 } 517 518 fence = dma_fence_get(centity->fences[seq & (amdgpu_sched_jobs - 1)]); 519 spin_unlock(&ctx->ring_lock); 520 521 return fence; 522 } 523 524 static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx, 525 struct amdgpu_ctx_entity *aentity, 526 int hw_ip, 527 enum drm_sched_priority priority) 528 { 529 struct amdgpu_device *adev = ctx->adev; 530 enum gfx_pipe_priority hw_prio; 531 struct drm_gpu_scheduler **scheds = NULL; 532 unsigned num_scheds; 533 534 /* set sw priority */ 535 drm_sched_entity_set_priority(&aentity->entity, priority); 536 537 /* set hw priority */ 538 if (hw_ip == AMDGPU_HW_IP_COMPUTE) { 539 hw_prio = amdgpu_ctx_sched_prio_to_compute_prio(priority); 540 scheds = adev->gfx.compute_prio_sched[hw_prio]; 541 num_scheds = adev->gfx.num_compute_sched[hw_prio]; 542 drm_sched_entity_modify_sched(&aentity->entity, scheds, 543 num_scheds); 544 } 545 } 546 547 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, 548 enum drm_sched_priority priority) 549 { 550 enum drm_sched_priority ctx_prio; 551 unsigned i, j; 552 553 ctx->override_priority = priority; 554 555 ctx_prio = (ctx->override_priority == DRM_SCHED_PRIORITY_UNSET) ? 556 ctx->init_priority : ctx->override_priority; 557 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 558 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 559 if (!ctx->entities[i][j]) 560 continue; 561 562 amdgpu_ctx_set_entity_priority(ctx, ctx->entities[i][j], 563 i, ctx_prio); 564 } 565 } 566 } 567 568 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, 569 struct drm_sched_entity *entity) 570 { 571 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 572 struct dma_fence *other; 573 unsigned idx; 574 long r; 575 576 spin_lock(&ctx->ring_lock); 577 idx = centity->sequence & (amdgpu_sched_jobs - 1); 578 other = dma_fence_get(centity->fences[idx]); 579 spin_unlock(&ctx->ring_lock); 580 581 if (!other) 582 return 0; 583 584 r = dma_fence_wait(other, true); 585 if (r < 0 && r != -ERESTARTSYS) 586 DRM_ERROR("Error (%ld) waiting for fence!\n", r); 587 588 dma_fence_put(other); 589 return r; 590 } 591 592 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr) 593 { 594 rw_init(&mgr->lock, "mgrlk"); 595 idr_init(&mgr->ctx_handles); 596 } 597 598 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout) 599 { 600 struct amdgpu_ctx *ctx; 601 struct idr *idp; 602 uint32_t id, i, j; 603 604 idp = &mgr->ctx_handles; 605 606 mutex_lock(&mgr->lock); 607 idr_for_each_entry(idp, ctx, id) { 608 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 609 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 610 struct drm_sched_entity *entity; 611 612 if (!ctx->entities[i][j]) 613 continue; 614 615 entity = &ctx->entities[i][j]->entity; 616 timeout = drm_sched_entity_flush(entity, timeout); 617 } 618 } 619 } 620 mutex_unlock(&mgr->lock); 621 return timeout; 622 } 623 624 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr) 625 { 626 struct amdgpu_ctx *ctx; 627 struct idr *idp; 628 uint32_t id, i, j; 629 630 idp = &mgr->ctx_handles; 631 632 idr_for_each_entry(idp, ctx, id) { 633 if (kref_read(&ctx->refcount) != 1) { 634 DRM_ERROR("ctx %p is still alive\n", ctx); 635 continue; 636 } 637 638 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 639 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 640 struct drm_sched_entity *entity; 641 642 if (!ctx->entities[i][j]) 643 continue; 644 645 entity = &ctx->entities[i][j]->entity; 646 drm_sched_entity_fini(entity); 647 } 648 } 649 } 650 } 651 652 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) 653 { 654 struct amdgpu_ctx *ctx; 655 struct idr *idp; 656 uint32_t id; 657 658 amdgpu_ctx_mgr_entity_fini(mgr); 659 660 idp = &mgr->ctx_handles; 661 662 idr_for_each_entry(idp, ctx, id) { 663 if (kref_put(&ctx->refcount, amdgpu_ctx_fini) != 1) 664 DRM_ERROR("ctx %p is still alive\n", ctx); 665 } 666 667 idr_destroy(&mgr->ctx_handles); 668 mutex_destroy(&mgr->lock); 669 } 670 671 672 static void amdgpu_ctx_init_compute_sched(struct amdgpu_device *adev) 673 { 674 int num_compute_sched_normal = 0; 675 int num_compute_sched_high = AMDGPU_MAX_COMPUTE_RINGS - 1; 676 int i; 677 678 /* use one drm sched array, gfx.compute_sched to store both high and 679 * normal priority drm compute schedulers */ 680 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 681 if (!adev->gfx.compute_ring[i].has_high_prio) 682 adev->gfx.compute_sched[num_compute_sched_normal++] = 683 &adev->gfx.compute_ring[i].sched; 684 else 685 adev->gfx.compute_sched[num_compute_sched_high--] = 686 &adev->gfx.compute_ring[i].sched; 687 } 688 689 /* compute ring only has two priority for now */ 690 i = AMDGPU_GFX_PIPE_PRIO_NORMAL; 691 adev->gfx.compute_prio_sched[i] = &adev->gfx.compute_sched[0]; 692 adev->gfx.num_compute_sched[i] = num_compute_sched_normal; 693 694 i = AMDGPU_GFX_PIPE_PRIO_HIGH; 695 if (num_compute_sched_high == (AMDGPU_MAX_COMPUTE_RINGS - 1)) { 696 /* When compute has no high priority rings then use */ 697 /* normal priority sched array */ 698 adev->gfx.compute_prio_sched[i] = &adev->gfx.compute_sched[0]; 699 adev->gfx.num_compute_sched[i] = num_compute_sched_normal; 700 } else { 701 adev->gfx.compute_prio_sched[i] = 702 &adev->gfx.compute_sched[num_compute_sched_high - 1]; 703 adev->gfx.num_compute_sched[i] = 704 adev->gfx.num_compute_rings - num_compute_sched_normal; 705 } 706 } 707 708 void amdgpu_ctx_init_sched(struct amdgpu_device *adev) 709 { 710 int i, j; 711 712 amdgpu_ctx_init_compute_sched(adev); 713 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 714 adev->gfx.gfx_sched[i] = &adev->gfx.gfx_ring[i].sched; 715 adev->gfx.num_gfx_sched++; 716 } 717 718 for (i = 0; i < adev->sdma.num_instances; i++) { 719 adev->sdma.sdma_sched[i] = &adev->sdma.instance[i].ring.sched; 720 adev->sdma.num_sdma_sched++; 721 } 722 723 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 724 if (adev->vcn.harvest_config & (1 << i)) 725 continue; 726 adev->vcn.vcn_dec_sched[adev->vcn.num_vcn_dec_sched++] = 727 &adev->vcn.inst[i].ring_dec.sched; 728 } 729 730 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { 731 if (adev->vcn.harvest_config & (1 << i)) 732 continue; 733 for (j = 0; j < adev->vcn.num_enc_rings; ++j) 734 adev->vcn.vcn_enc_sched[adev->vcn.num_vcn_enc_sched++] = 735 &adev->vcn.inst[i].ring_enc[j].sched; 736 } 737 738 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { 739 if (adev->jpeg.harvest_config & (1 << i)) 740 continue; 741 adev->jpeg.jpeg_sched[adev->jpeg.num_jpeg_sched++] = 742 &adev->jpeg.inst[i].ring_dec.sched; 743 } 744 } 745