1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: monk liu <monk.liu@amd.com> 23 */ 24 25 #include <drm/drm_auth.h> 26 #include <drm/drm_drv.h> 27 #include "amdgpu.h" 28 #include "amdgpu_sched.h" 29 #include "amdgpu_ras.h" 30 #include <linux/nospec.h> 31 32 #define to_amdgpu_ctx_entity(e) \ 33 container_of((e), struct amdgpu_ctx_entity, entity) 34 35 const unsigned int amdgpu_ctx_num_entities[AMDGPU_HW_IP_NUM] = { 36 [AMDGPU_HW_IP_GFX] = 1, 37 [AMDGPU_HW_IP_COMPUTE] = 4, 38 [AMDGPU_HW_IP_DMA] = 2, 39 [AMDGPU_HW_IP_UVD] = 1, 40 [AMDGPU_HW_IP_VCE] = 1, 41 [AMDGPU_HW_IP_UVD_ENC] = 1, 42 [AMDGPU_HW_IP_VCN_DEC] = 1, 43 [AMDGPU_HW_IP_VCN_ENC] = 1, 44 [AMDGPU_HW_IP_VCN_JPEG] = 1, 45 }; 46 47 bool amdgpu_ctx_priority_is_valid(int32_t ctx_prio) 48 { 49 switch (ctx_prio) { 50 case AMDGPU_CTX_PRIORITY_VERY_LOW: 51 case AMDGPU_CTX_PRIORITY_LOW: 52 case AMDGPU_CTX_PRIORITY_NORMAL: 53 case AMDGPU_CTX_PRIORITY_HIGH: 54 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 55 return true; 56 default: 57 case AMDGPU_CTX_PRIORITY_UNSET: 58 return false; 59 } 60 } 61 62 static enum drm_sched_priority 63 amdgpu_ctx_to_drm_sched_prio(int32_t ctx_prio) 64 { 65 switch (ctx_prio) { 66 case AMDGPU_CTX_PRIORITY_UNSET: 67 pr_warn_once("AMD-->DRM context priority value UNSET-->NORMAL"); 68 return DRM_SCHED_PRIORITY_NORMAL; 69 70 case AMDGPU_CTX_PRIORITY_VERY_LOW: 71 return DRM_SCHED_PRIORITY_MIN; 72 73 case AMDGPU_CTX_PRIORITY_LOW: 74 return DRM_SCHED_PRIORITY_MIN; 75 76 case AMDGPU_CTX_PRIORITY_NORMAL: 77 return DRM_SCHED_PRIORITY_NORMAL; 78 79 case AMDGPU_CTX_PRIORITY_HIGH: 80 return DRM_SCHED_PRIORITY_HIGH; 81 82 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 83 return DRM_SCHED_PRIORITY_HIGH; 84 85 /* This should not happen as we sanitized userspace provided priority 86 * already, WARN if this happens. 87 */ 88 default: 89 WARN(1, "Invalid context priority %d\n", ctx_prio); 90 return DRM_SCHED_PRIORITY_NORMAL; 91 } 92 93 } 94 95 static int amdgpu_ctx_priority_permit(struct drm_file *filp, 96 int32_t priority) 97 { 98 if (!amdgpu_ctx_priority_is_valid(priority)) 99 return -EINVAL; 100 101 /* NORMAL and below are accessible by everyone */ 102 if (priority <= AMDGPU_CTX_PRIORITY_NORMAL) 103 return 0; 104 105 if (capable(CAP_SYS_NICE)) 106 return 0; 107 108 if (drm_is_current_master(filp)) 109 return 0; 110 111 return -EACCES; 112 } 113 114 static enum amdgpu_gfx_pipe_priority amdgpu_ctx_prio_to_gfx_pipe_prio(int32_t prio) 115 { 116 switch (prio) { 117 case AMDGPU_CTX_PRIORITY_HIGH: 118 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 119 return AMDGPU_GFX_PIPE_PRIO_HIGH; 120 default: 121 return AMDGPU_GFX_PIPE_PRIO_NORMAL; 122 } 123 } 124 125 static enum amdgpu_ring_priority_level amdgpu_ctx_sched_prio_to_ring_prio(int32_t prio) 126 { 127 switch (prio) { 128 case AMDGPU_CTX_PRIORITY_HIGH: 129 return AMDGPU_RING_PRIO_1; 130 case AMDGPU_CTX_PRIORITY_VERY_HIGH: 131 return AMDGPU_RING_PRIO_2; 132 default: 133 return AMDGPU_RING_PRIO_0; 134 } 135 } 136 137 static unsigned int amdgpu_ctx_get_hw_prio(struct amdgpu_ctx *ctx, u32 hw_ip) 138 { 139 struct amdgpu_device *adev = ctx->mgr->adev; 140 unsigned int hw_prio; 141 int32_t ctx_prio; 142 143 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 144 ctx->init_priority : ctx->override_priority; 145 146 switch (hw_ip) { 147 case AMDGPU_HW_IP_GFX: 148 case AMDGPU_HW_IP_COMPUTE: 149 hw_prio = amdgpu_ctx_prio_to_gfx_pipe_prio(ctx_prio); 150 break; 151 case AMDGPU_HW_IP_VCE: 152 case AMDGPU_HW_IP_VCN_ENC: 153 hw_prio = amdgpu_ctx_sched_prio_to_ring_prio(ctx_prio); 154 break; 155 default: 156 hw_prio = AMDGPU_RING_PRIO_DEFAULT; 157 break; 158 } 159 160 hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM); 161 if (adev->gpu_sched[hw_ip][hw_prio].num_scheds == 0) 162 hw_prio = AMDGPU_RING_PRIO_DEFAULT; 163 164 return hw_prio; 165 } 166 167 /* Calculate the time spend on the hw */ 168 static ktime_t amdgpu_ctx_fence_time(struct dma_fence *fence) 169 { 170 struct drm_sched_fence *s_fence; 171 172 if (!fence) 173 return ns_to_ktime(0); 174 175 /* When the fence is not even scheduled it can't have spend time */ 176 s_fence = to_drm_sched_fence(fence); 177 if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->scheduled.flags)) 178 return ns_to_ktime(0); 179 180 /* When it is still running account how much already spend */ 181 if (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &s_fence->finished.flags)) 182 return ktime_sub(ktime_get(), s_fence->scheduled.timestamp); 183 184 return ktime_sub(s_fence->finished.timestamp, 185 s_fence->scheduled.timestamp); 186 } 187 188 static ktime_t amdgpu_ctx_entity_time(struct amdgpu_ctx *ctx, 189 struct amdgpu_ctx_entity *centity) 190 { 191 ktime_t res = ns_to_ktime(0); 192 uint32_t i; 193 194 spin_lock(&ctx->ring_lock); 195 for (i = 0; i < amdgpu_sched_jobs; i++) { 196 res = ktime_add(res, amdgpu_ctx_fence_time(centity->fences[i])); 197 } 198 spin_unlock(&ctx->ring_lock); 199 return res; 200 } 201 202 static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, 203 const u32 ring) 204 { 205 struct drm_gpu_scheduler **scheds = NULL, *sched = NULL; 206 struct amdgpu_device *adev = ctx->mgr->adev; 207 struct amdgpu_ctx_entity *entity; 208 enum drm_sched_priority drm_prio; 209 unsigned int hw_prio, num_scheds; 210 int32_t ctx_prio; 211 int r; 212 213 entity = kzalloc(struct_size(entity, fences, amdgpu_sched_jobs), 214 GFP_KERNEL); 215 if (!entity) 216 return -ENOMEM; 217 218 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 219 ctx->init_priority : ctx->override_priority; 220 entity->hw_ip = hw_ip; 221 entity->sequence = 1; 222 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 223 drm_prio = amdgpu_ctx_to_drm_sched_prio(ctx_prio); 224 225 hw_ip = array_index_nospec(hw_ip, AMDGPU_HW_IP_NUM); 226 scheds = adev->gpu_sched[hw_ip][hw_prio].sched; 227 num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 228 229 /* disable load balance if the hw engine retains context among dependent jobs */ 230 if (hw_ip == AMDGPU_HW_IP_VCN_ENC || 231 hw_ip == AMDGPU_HW_IP_VCN_DEC || 232 hw_ip == AMDGPU_HW_IP_UVD_ENC || 233 hw_ip == AMDGPU_HW_IP_UVD) { 234 sched = drm_sched_pick_best(scheds, num_scheds); 235 scheds = &sched; 236 num_scheds = 1; 237 } 238 239 r = drm_sched_entity_init(&entity->entity, drm_prio, scheds, num_scheds, 240 &ctx->guilty); 241 if (r) 242 goto error_free_entity; 243 244 /* It's not an error if we fail to install the new entity */ 245 if (cmpxchg(&ctx->entities[hw_ip][ring], NULL, entity)) 246 goto cleanup_entity; 247 248 return 0; 249 250 cleanup_entity: 251 drm_sched_entity_fini(&entity->entity); 252 253 error_free_entity: 254 kfree(entity); 255 256 return r; 257 } 258 259 static ktime_t amdgpu_ctx_fini_entity(struct amdgpu_ctx_entity *entity) 260 { 261 ktime_t res = ns_to_ktime(0); 262 int i; 263 264 if (!entity) 265 return res; 266 267 for (i = 0; i < amdgpu_sched_jobs; ++i) { 268 res = ktime_add(res, amdgpu_ctx_fence_time(entity->fences[i])); 269 dma_fence_put(entity->fences[i]); 270 } 271 272 kfree(entity); 273 return res; 274 } 275 276 static int amdgpu_ctx_get_stable_pstate(struct amdgpu_ctx *ctx, 277 u32 *stable_pstate) 278 { 279 struct amdgpu_device *adev = ctx->mgr->adev; 280 enum amd_dpm_forced_level current_level; 281 282 current_level = amdgpu_dpm_get_performance_level(adev); 283 284 switch (current_level) { 285 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 286 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_STANDARD; 287 break; 288 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 289 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK; 290 break; 291 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 292 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK; 293 break; 294 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 295 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_PEAK; 296 break; 297 default: 298 *stable_pstate = AMDGPU_CTX_STABLE_PSTATE_NONE; 299 break; 300 } 301 return 0; 302 } 303 304 static int amdgpu_ctx_init(struct amdgpu_ctx_mgr *mgr, int32_t priority, 305 struct drm_file *filp, struct amdgpu_ctx *ctx) 306 { 307 u32 current_stable_pstate; 308 int r; 309 310 r = amdgpu_ctx_priority_permit(filp, priority); 311 if (r) 312 return r; 313 314 memset(ctx, 0, sizeof(*ctx)); 315 316 kref_init(&ctx->refcount); 317 ctx->mgr = mgr; 318 mtx_init(&ctx->ring_lock, IPL_TTY); 319 320 ctx->reset_counter = atomic_read(&mgr->adev->gpu_reset_counter); 321 ctx->reset_counter_query = ctx->reset_counter; 322 ctx->vram_lost_counter = atomic_read(&mgr->adev->vram_lost_counter); 323 ctx->init_priority = priority; 324 ctx->override_priority = AMDGPU_CTX_PRIORITY_UNSET; 325 326 r = amdgpu_ctx_get_stable_pstate(ctx, ¤t_stable_pstate); 327 if (r) 328 return r; 329 330 if (mgr->adev->pm.stable_pstate_ctx) 331 ctx->stable_pstate = mgr->adev->pm.stable_pstate_ctx->stable_pstate; 332 else 333 ctx->stable_pstate = current_stable_pstate; 334 335 return 0; 336 } 337 338 static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx, 339 u32 stable_pstate) 340 { 341 struct amdgpu_device *adev = ctx->mgr->adev; 342 enum amd_dpm_forced_level level; 343 u32 current_stable_pstate; 344 int r; 345 346 mutex_lock(&adev->pm.stable_pstate_ctx_lock); 347 if (adev->pm.stable_pstate_ctx && adev->pm.stable_pstate_ctx != ctx) { 348 r = -EBUSY; 349 goto done; 350 } 351 352 r = amdgpu_ctx_get_stable_pstate(ctx, ¤t_stable_pstate); 353 if (r || (stable_pstate == current_stable_pstate)) 354 goto done; 355 356 switch (stable_pstate) { 357 case AMDGPU_CTX_STABLE_PSTATE_NONE: 358 level = AMD_DPM_FORCED_LEVEL_AUTO; 359 break; 360 case AMDGPU_CTX_STABLE_PSTATE_STANDARD: 361 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 362 break; 363 case AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK: 364 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 365 break; 366 case AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK: 367 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 368 break; 369 case AMDGPU_CTX_STABLE_PSTATE_PEAK: 370 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 371 break; 372 default: 373 r = -EINVAL; 374 goto done; 375 } 376 377 r = amdgpu_dpm_force_performance_level(adev, level); 378 379 if (level == AMD_DPM_FORCED_LEVEL_AUTO) 380 adev->pm.stable_pstate_ctx = NULL; 381 else 382 adev->pm.stable_pstate_ctx = ctx; 383 done: 384 mutex_unlock(&adev->pm.stable_pstate_ctx_lock); 385 386 return r; 387 } 388 389 static void amdgpu_ctx_fini(struct kref *ref) 390 { 391 struct amdgpu_ctx *ctx = container_of(ref, struct amdgpu_ctx, refcount); 392 struct amdgpu_ctx_mgr *mgr = ctx->mgr; 393 struct amdgpu_device *adev = mgr->adev; 394 unsigned i, j, idx; 395 396 if (!adev) 397 return; 398 399 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 400 for (j = 0; j < AMDGPU_MAX_ENTITY_NUM; ++j) { 401 ktime_t spend; 402 403 spend = amdgpu_ctx_fini_entity(ctx->entities[i][j]); 404 atomic64_add(ktime_to_ns(spend), &mgr->time_spend[i]); 405 } 406 } 407 408 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 409 amdgpu_ctx_set_stable_pstate(ctx, ctx->stable_pstate); 410 drm_dev_exit(idx); 411 } 412 413 kfree(ctx); 414 } 415 416 int amdgpu_ctx_get_entity(struct amdgpu_ctx *ctx, u32 hw_ip, u32 instance, 417 u32 ring, struct drm_sched_entity **entity) 418 { 419 int r; 420 421 if (hw_ip >= AMDGPU_HW_IP_NUM) { 422 DRM_ERROR("unknown HW IP type: %d\n", hw_ip); 423 return -EINVAL; 424 } 425 426 /* Right now all IPs have only one instance - multiple rings. */ 427 if (instance != 0) { 428 DRM_DEBUG("invalid ip instance: %d\n", instance); 429 return -EINVAL; 430 } 431 432 if (ring >= amdgpu_ctx_num_entities[hw_ip]) { 433 DRM_DEBUG("invalid ring: %d %d\n", hw_ip, ring); 434 return -EINVAL; 435 } 436 437 if (ctx->entities[hw_ip][ring] == NULL) { 438 r = amdgpu_ctx_init_entity(ctx, hw_ip, ring); 439 if (r) 440 return r; 441 } 442 443 *entity = &ctx->entities[hw_ip][ring]->entity; 444 return 0; 445 } 446 447 static int amdgpu_ctx_alloc(struct amdgpu_device *adev, 448 struct amdgpu_fpriv *fpriv, 449 struct drm_file *filp, 450 int32_t priority, 451 uint32_t *id) 452 { 453 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 454 struct amdgpu_ctx *ctx; 455 int r; 456 457 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 458 if (!ctx) 459 return -ENOMEM; 460 461 mutex_lock(&mgr->lock); 462 r = idr_alloc(&mgr->ctx_handles, ctx, 1, AMDGPU_VM_MAX_NUM_CTX, GFP_KERNEL); 463 if (r < 0) { 464 mutex_unlock(&mgr->lock); 465 kfree(ctx); 466 return r; 467 } 468 469 *id = (uint32_t)r; 470 r = amdgpu_ctx_init(mgr, priority, filp, ctx); 471 if (r) { 472 idr_remove(&mgr->ctx_handles, *id); 473 *id = 0; 474 kfree(ctx); 475 } 476 mutex_unlock(&mgr->lock); 477 return r; 478 } 479 480 static void amdgpu_ctx_do_release(struct kref *ref) 481 { 482 struct amdgpu_ctx *ctx; 483 u32 i, j; 484 485 ctx = container_of(ref, struct amdgpu_ctx, refcount); 486 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 487 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 488 if (!ctx->entities[i][j]) 489 continue; 490 491 drm_sched_entity_destroy(&ctx->entities[i][j]->entity); 492 } 493 } 494 495 amdgpu_ctx_fini(ref); 496 } 497 498 static int amdgpu_ctx_free(struct amdgpu_fpriv *fpriv, uint32_t id) 499 { 500 struct amdgpu_ctx_mgr *mgr = &fpriv->ctx_mgr; 501 struct amdgpu_ctx *ctx; 502 503 mutex_lock(&mgr->lock); 504 ctx = idr_remove(&mgr->ctx_handles, id); 505 if (ctx) 506 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 507 mutex_unlock(&mgr->lock); 508 return ctx ? 0 : -EINVAL; 509 } 510 511 static int amdgpu_ctx_query(struct amdgpu_device *adev, 512 struct amdgpu_fpriv *fpriv, uint32_t id, 513 union drm_amdgpu_ctx_out *out) 514 { 515 struct amdgpu_ctx *ctx; 516 struct amdgpu_ctx_mgr *mgr; 517 unsigned reset_counter; 518 519 if (!fpriv) 520 return -EINVAL; 521 522 mgr = &fpriv->ctx_mgr; 523 mutex_lock(&mgr->lock); 524 ctx = idr_find(&mgr->ctx_handles, id); 525 if (!ctx) { 526 mutex_unlock(&mgr->lock); 527 return -EINVAL; 528 } 529 530 /* TODO: these two are always zero */ 531 out->state.flags = 0x0; 532 out->state.hangs = 0x0; 533 534 /* determine if a GPU reset has occured since the last call */ 535 reset_counter = atomic_read(&adev->gpu_reset_counter); 536 /* TODO: this should ideally return NO, GUILTY, or INNOCENT. */ 537 if (ctx->reset_counter_query == reset_counter) 538 out->state.reset_status = AMDGPU_CTX_NO_RESET; 539 else 540 out->state.reset_status = AMDGPU_CTX_UNKNOWN_RESET; 541 ctx->reset_counter_query = reset_counter; 542 543 mutex_unlock(&mgr->lock); 544 return 0; 545 } 546 547 #define AMDGPU_RAS_COUNTE_DELAY_MS 3000 548 549 static int amdgpu_ctx_query2(struct amdgpu_device *adev, 550 struct amdgpu_fpriv *fpriv, uint32_t id, 551 union drm_amdgpu_ctx_out *out) 552 { 553 struct amdgpu_ras *con = amdgpu_ras_get_context(adev); 554 struct amdgpu_ctx *ctx; 555 struct amdgpu_ctx_mgr *mgr; 556 557 if (!fpriv) 558 return -EINVAL; 559 560 mgr = &fpriv->ctx_mgr; 561 mutex_lock(&mgr->lock); 562 ctx = idr_find(&mgr->ctx_handles, id); 563 if (!ctx) { 564 mutex_unlock(&mgr->lock); 565 return -EINVAL; 566 } 567 568 out->state.flags = 0x0; 569 out->state.hangs = 0x0; 570 571 if (ctx->reset_counter != atomic_read(&adev->gpu_reset_counter)) 572 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RESET; 573 574 if (ctx->vram_lost_counter != atomic_read(&adev->vram_lost_counter)) 575 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST; 576 577 if (atomic_read(&ctx->guilty)) 578 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_GUILTY; 579 580 if (adev->ras_enabled && con) { 581 /* Return the cached values in O(1), 582 * and schedule delayed work to cache 583 * new vaues. 584 */ 585 int ce_count, ue_count; 586 587 ce_count = atomic_read(&con->ras_ce_count); 588 ue_count = atomic_read(&con->ras_ue_count); 589 590 if (ce_count != ctx->ras_counter_ce) { 591 ctx->ras_counter_ce = ce_count; 592 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE; 593 } 594 595 if (ue_count != ctx->ras_counter_ue) { 596 ctx->ras_counter_ue = ue_count; 597 out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE; 598 } 599 600 schedule_delayed_work(&con->ras_counte_delay_work, 601 msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS)); 602 } 603 604 mutex_unlock(&mgr->lock); 605 return 0; 606 } 607 608 609 610 static int amdgpu_ctx_stable_pstate(struct amdgpu_device *adev, 611 struct amdgpu_fpriv *fpriv, uint32_t id, 612 bool set, u32 *stable_pstate) 613 { 614 struct amdgpu_ctx *ctx; 615 struct amdgpu_ctx_mgr *mgr; 616 int r; 617 618 if (!fpriv) 619 return -EINVAL; 620 621 mgr = &fpriv->ctx_mgr; 622 mutex_lock(&mgr->lock); 623 ctx = idr_find(&mgr->ctx_handles, id); 624 if (!ctx) { 625 mutex_unlock(&mgr->lock); 626 return -EINVAL; 627 } 628 629 if (set) 630 r = amdgpu_ctx_set_stable_pstate(ctx, *stable_pstate); 631 else 632 r = amdgpu_ctx_get_stable_pstate(ctx, stable_pstate); 633 634 mutex_unlock(&mgr->lock); 635 return r; 636 } 637 638 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 639 struct drm_file *filp) 640 { 641 int r; 642 uint32_t id, stable_pstate; 643 int32_t priority; 644 645 union drm_amdgpu_ctx *args = data; 646 struct amdgpu_device *adev = drm_to_adev(dev); 647 struct amdgpu_fpriv *fpriv = filp->driver_priv; 648 649 id = args->in.ctx_id; 650 priority = args->in.priority; 651 652 /* For backwards compatibility reasons, we need to accept 653 * ioctls with garbage in the priority field */ 654 if (!amdgpu_ctx_priority_is_valid(priority)) 655 priority = AMDGPU_CTX_PRIORITY_NORMAL; 656 657 switch (args->in.op) { 658 case AMDGPU_CTX_OP_ALLOC_CTX: 659 r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id); 660 args->out.alloc.ctx_id = id; 661 break; 662 case AMDGPU_CTX_OP_FREE_CTX: 663 r = amdgpu_ctx_free(fpriv, id); 664 break; 665 case AMDGPU_CTX_OP_QUERY_STATE: 666 r = amdgpu_ctx_query(adev, fpriv, id, &args->out); 667 break; 668 case AMDGPU_CTX_OP_QUERY_STATE2: 669 r = amdgpu_ctx_query2(adev, fpriv, id, &args->out); 670 break; 671 case AMDGPU_CTX_OP_GET_STABLE_PSTATE: 672 if (args->in.flags) 673 return -EINVAL; 674 r = amdgpu_ctx_stable_pstate(adev, fpriv, id, false, &stable_pstate); 675 if (!r) 676 args->out.pstate.flags = stable_pstate; 677 break; 678 case AMDGPU_CTX_OP_SET_STABLE_PSTATE: 679 if (args->in.flags & ~AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK) 680 return -EINVAL; 681 stable_pstate = args->in.flags & AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK; 682 if (stable_pstate > AMDGPU_CTX_STABLE_PSTATE_PEAK) 683 return -EINVAL; 684 r = amdgpu_ctx_stable_pstate(adev, fpriv, id, true, &stable_pstate); 685 break; 686 default: 687 return -EINVAL; 688 } 689 690 return r; 691 } 692 693 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id) 694 { 695 struct amdgpu_ctx *ctx; 696 struct amdgpu_ctx_mgr *mgr; 697 698 if (!fpriv) 699 return NULL; 700 701 mgr = &fpriv->ctx_mgr; 702 703 mutex_lock(&mgr->lock); 704 ctx = idr_find(&mgr->ctx_handles, id); 705 if (ctx) 706 kref_get(&ctx->refcount); 707 mutex_unlock(&mgr->lock); 708 return ctx; 709 } 710 711 int amdgpu_ctx_put(struct amdgpu_ctx *ctx) 712 { 713 if (ctx == NULL) 714 return -EINVAL; 715 716 kref_put(&ctx->refcount, amdgpu_ctx_do_release); 717 return 0; 718 } 719 720 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, 721 struct drm_sched_entity *entity, 722 struct dma_fence *fence) 723 { 724 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 725 uint64_t seq = centity->sequence; 726 struct dma_fence *other = NULL; 727 unsigned idx = 0; 728 729 idx = seq & (amdgpu_sched_jobs - 1); 730 other = centity->fences[idx]; 731 WARN_ON(other && !dma_fence_is_signaled(other)); 732 733 dma_fence_get(fence); 734 735 spin_lock(&ctx->ring_lock); 736 centity->fences[idx] = fence; 737 centity->sequence++; 738 spin_unlock(&ctx->ring_lock); 739 740 atomic64_add(ktime_to_ns(amdgpu_ctx_fence_time(other)), 741 &ctx->mgr->time_spend[centity->hw_ip]); 742 743 dma_fence_put(other); 744 return seq; 745 } 746 747 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 748 struct drm_sched_entity *entity, 749 uint64_t seq) 750 { 751 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 752 struct dma_fence *fence; 753 754 spin_lock(&ctx->ring_lock); 755 756 if (seq == ~0ull) 757 seq = centity->sequence - 1; 758 759 if (seq >= centity->sequence) { 760 spin_unlock(&ctx->ring_lock); 761 return ERR_PTR(-EINVAL); 762 } 763 764 765 if (seq + amdgpu_sched_jobs < centity->sequence) { 766 spin_unlock(&ctx->ring_lock); 767 return NULL; 768 } 769 770 fence = dma_fence_get(centity->fences[seq & (amdgpu_sched_jobs - 1)]); 771 spin_unlock(&ctx->ring_lock); 772 773 return fence; 774 } 775 776 static void amdgpu_ctx_set_entity_priority(struct amdgpu_ctx *ctx, 777 struct amdgpu_ctx_entity *aentity, 778 int hw_ip, 779 int32_t priority) 780 { 781 struct amdgpu_device *adev = ctx->mgr->adev; 782 unsigned int hw_prio; 783 struct drm_gpu_scheduler **scheds = NULL; 784 unsigned num_scheds; 785 786 /* set sw priority */ 787 drm_sched_entity_set_priority(&aentity->entity, 788 amdgpu_ctx_to_drm_sched_prio(priority)); 789 790 /* set hw priority */ 791 if (hw_ip == AMDGPU_HW_IP_COMPUTE || hw_ip == AMDGPU_HW_IP_GFX) { 792 hw_prio = amdgpu_ctx_get_hw_prio(ctx, hw_ip); 793 hw_prio = array_index_nospec(hw_prio, AMDGPU_RING_PRIO_MAX); 794 scheds = adev->gpu_sched[hw_ip][hw_prio].sched; 795 num_scheds = adev->gpu_sched[hw_ip][hw_prio].num_scheds; 796 drm_sched_entity_modify_sched(&aentity->entity, scheds, 797 num_scheds); 798 } 799 } 800 801 void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx, 802 int32_t priority) 803 { 804 int32_t ctx_prio; 805 unsigned i, j; 806 807 ctx->override_priority = priority; 808 809 ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? 810 ctx->init_priority : ctx->override_priority; 811 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 812 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 813 if (!ctx->entities[i][j]) 814 continue; 815 816 amdgpu_ctx_set_entity_priority(ctx, ctx->entities[i][j], 817 i, ctx_prio); 818 } 819 } 820 } 821 822 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, 823 struct drm_sched_entity *entity) 824 { 825 struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); 826 struct dma_fence *other; 827 unsigned idx; 828 long r; 829 830 spin_lock(&ctx->ring_lock); 831 idx = centity->sequence & (amdgpu_sched_jobs - 1); 832 other = dma_fence_get(centity->fences[idx]); 833 spin_unlock(&ctx->ring_lock); 834 835 if (!other) 836 return 0; 837 838 r = dma_fence_wait(other, true); 839 if (r < 0 && r != -ERESTARTSYS) 840 DRM_ERROR("Error (%ld) waiting for fence!\n", r); 841 842 dma_fence_put(other); 843 return r; 844 } 845 846 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr, 847 struct amdgpu_device *adev) 848 { 849 unsigned int i; 850 851 mgr->adev = adev; 852 rw_init(&mgr->lock, "mgrlk"); 853 idr_init_base(&mgr->ctx_handles, 1); 854 855 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) 856 atomic64_set(&mgr->time_spend[i], 0); 857 } 858 859 long amdgpu_ctx_mgr_entity_flush(struct amdgpu_ctx_mgr *mgr, long timeout) 860 { 861 struct amdgpu_ctx *ctx; 862 struct idr *idp; 863 uint32_t id, i, j; 864 865 idp = &mgr->ctx_handles; 866 867 mutex_lock(&mgr->lock); 868 idr_for_each_entry(idp, ctx, id) { 869 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 870 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 871 struct drm_sched_entity *entity; 872 873 if (!ctx->entities[i][j]) 874 continue; 875 876 entity = &ctx->entities[i][j]->entity; 877 timeout = drm_sched_entity_flush(entity, timeout); 878 } 879 } 880 } 881 mutex_unlock(&mgr->lock); 882 return timeout; 883 } 884 885 void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr) 886 { 887 struct amdgpu_ctx *ctx; 888 struct idr *idp; 889 uint32_t id, i, j; 890 891 idp = &mgr->ctx_handles; 892 893 idr_for_each_entry(idp, ctx, id) { 894 if (kref_read(&ctx->refcount) != 1) { 895 DRM_ERROR("ctx %p is still alive\n", ctx); 896 continue; 897 } 898 899 for (i = 0; i < AMDGPU_HW_IP_NUM; ++i) { 900 for (j = 0; j < amdgpu_ctx_num_entities[i]; ++j) { 901 struct drm_sched_entity *entity; 902 903 if (!ctx->entities[i][j]) 904 continue; 905 906 entity = &ctx->entities[i][j]->entity; 907 drm_sched_entity_fini(entity); 908 } 909 } 910 } 911 } 912 913 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr) 914 { 915 struct amdgpu_ctx *ctx; 916 struct idr *idp; 917 uint32_t id; 918 919 amdgpu_ctx_mgr_entity_fini(mgr); 920 921 idp = &mgr->ctx_handles; 922 923 idr_for_each_entry(idp, ctx, id) { 924 if (kref_put(&ctx->refcount, amdgpu_ctx_fini) != 1) 925 DRM_ERROR("ctx %p is still alive\n", ctx); 926 } 927 928 idr_destroy(&mgr->ctx_handles); 929 mutex_destroy(&mgr->lock); 930 } 931 932 void amdgpu_ctx_mgr_usage(struct amdgpu_ctx_mgr *mgr, 933 ktime_t usage[AMDGPU_HW_IP_NUM]) 934 { 935 struct amdgpu_ctx *ctx; 936 unsigned int hw_ip, i; 937 uint32_t id; 938 939 /* 940 * This is a little bit racy because it can be that a ctx or a fence are 941 * destroyed just in the moment we try to account them. But that is ok 942 * since exactly that case is explicitely allowed by the interface. 943 */ 944 mutex_lock(&mgr->lock); 945 for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 946 uint64_t ns = atomic64_read(&mgr->time_spend[hw_ip]); 947 948 usage[hw_ip] = ns_to_ktime(ns); 949 } 950 951 idr_for_each_entry(&mgr->ctx_handles, ctx, id) { 952 for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { 953 for (i = 0; i < amdgpu_ctx_num_entities[hw_ip]; ++i) { 954 struct amdgpu_ctx_entity *centity; 955 ktime_t spend; 956 957 centity = ctx->entities[hw_ip][i]; 958 if (!centity) 959 continue; 960 spend = amdgpu_ctx_entity_time(ctx, centity); 961 usage[hw_ip] = ktime_add(usage[hw_ip], spend); 962 } 963 } 964 } 965 mutex_unlock(&mgr->lock); 966 } 967