1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_fb_helper.h> 30 #include <drm/amdgpu_drm.h> 31 #include "amdgpu.h" 32 #include "atom.h" 33 #include "atombios_encoders.h" 34 #include "atombios_dp.h" 35 #include "amdgpu_connectors.h" 36 #include "amdgpu_i2c.h" 37 38 #include <linux/pm_runtime.h> 39 40 void amdgpu_connector_hotplug(struct drm_connector *connector) 41 { 42 struct drm_device *dev = connector->dev; 43 struct amdgpu_device *adev = dev->dev_private; 44 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 45 46 /* bail if the connector does not have hpd pin, e.g., 47 * VGA, TV, etc. 48 */ 49 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) 50 return; 51 52 amdgpu_display_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 53 54 /* if the connector is already off, don't turn it back on */ 55 if (connector->dpms != DRM_MODE_DPMS_ON) 56 return; 57 58 /* just deal with DP (not eDP) here. */ 59 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 60 struct amdgpu_connector_atom_dig *dig_connector = 61 amdgpu_connector->con_priv; 62 63 /* if existing sink type was not DP no need to retrain */ 64 if (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) 65 return; 66 67 /* first get sink type as it may be reset after (un)plug */ 68 dig_connector->dp_sink_type = amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 69 /* don't do anything if sink is not display port, i.e., 70 * passive dp->(dvi|hdmi) adaptor 71 */ 72 if (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT && 73 amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd) && 74 amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { 75 /* Don't start link training before we have the DPCD */ 76 if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 77 return; 78 79 /* Turn the connector off and back on immediately, which 80 * will trigger link training 81 */ 82 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 83 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 84 } 85 } 86 } 87 88 static void amdgpu_connector_property_change_mode(struct drm_encoder *encoder) 89 { 90 struct drm_crtc *crtc = encoder->crtc; 91 92 if (crtc && crtc->enabled) { 93 drm_crtc_helper_set_mode(crtc, &crtc->mode, 94 crtc->x, crtc->y, crtc->primary->fb); 95 } 96 } 97 98 int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 99 { 100 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 101 struct amdgpu_connector_atom_dig *dig_connector; 102 int bpc = 8; 103 unsigned mode_clock, max_tmds_clock; 104 105 switch (connector->connector_type) { 106 case DRM_MODE_CONNECTOR_DVII: 107 case DRM_MODE_CONNECTOR_HDMIB: 108 if (amdgpu_connector->use_digital) { 109 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 110 if (connector->display_info.bpc) 111 bpc = connector->display_info.bpc; 112 } 113 } 114 break; 115 case DRM_MODE_CONNECTOR_DVID: 116 case DRM_MODE_CONNECTOR_HDMIA: 117 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 118 if (connector->display_info.bpc) 119 bpc = connector->display_info.bpc; 120 } 121 break; 122 case DRM_MODE_CONNECTOR_DisplayPort: 123 dig_connector = amdgpu_connector->con_priv; 124 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 125 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || 126 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 127 if (connector->display_info.bpc) 128 bpc = connector->display_info.bpc; 129 } 130 break; 131 case DRM_MODE_CONNECTOR_eDP: 132 case DRM_MODE_CONNECTOR_LVDS: 133 if (connector->display_info.bpc) 134 bpc = connector->display_info.bpc; 135 else { 136 const struct drm_connector_helper_funcs *connector_funcs = 137 connector->helper_private; 138 struct drm_encoder *encoder = connector_funcs->best_encoder(connector); 139 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 140 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 141 142 if (dig->lcd_misc & ATOM_PANEL_MISC_V13_6BIT_PER_COLOR) 143 bpc = 6; 144 else if (dig->lcd_misc & ATOM_PANEL_MISC_V13_8BIT_PER_COLOR) 145 bpc = 8; 146 } 147 break; 148 } 149 150 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 151 /* 152 * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make 153 * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at 154 * 12 bpc is always supported on hdmi deep color sinks, as this is 155 * required by the HDMI-1.3 spec. Clamp to a safe 12 bpc maximum. 156 */ 157 if (bpc > 12) { 158 DRM_DEBUG("%s: HDMI deep color %d bpc unsupported. Using 12 bpc.\n", 159 connector->name, bpc); 160 bpc = 12; 161 } 162 163 /* Any defined maximum tmds clock limit we must not exceed? */ 164 if (connector->display_info.max_tmds_clock > 0) { 165 /* mode_clock is clock in kHz for mode to be modeset on this connector */ 166 mode_clock = amdgpu_connector->pixelclock_for_modeset; 167 168 /* Maximum allowable input clock in kHz */ 169 max_tmds_clock = connector->display_info.max_tmds_clock; 170 171 DRM_DEBUG("%s: hdmi mode dotclock %d kHz, max tmds input clock %d kHz.\n", 172 connector->name, mode_clock, max_tmds_clock); 173 174 /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ 175 if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { 176 if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && 177 (mode_clock * 5/4 <= max_tmds_clock)) 178 bpc = 10; 179 else 180 bpc = 8; 181 182 DRM_DEBUG("%s: HDMI deep color 12 bpc exceeds max tmds clock. Using %d bpc.\n", 183 connector->name, bpc); 184 } 185 186 if ((bpc == 10) && (mode_clock * 5/4 > max_tmds_clock)) { 187 bpc = 8; 188 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n", 189 connector->name, bpc); 190 } 191 } else if (bpc > 8) { 192 /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */ 193 DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n", 194 connector->name); 195 bpc = 8; 196 } 197 } 198 199 if ((amdgpu_deep_color == 0) && (bpc > 8)) { 200 DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n", 201 connector->name); 202 bpc = 8; 203 } 204 205 DRM_DEBUG("%s: Display bpc=%d, returned bpc=%d\n", 206 connector->name, connector->display_info.bpc, bpc); 207 208 return bpc; 209 } 210 211 static void 212 amdgpu_connector_update_scratch_regs(struct drm_connector *connector, 213 enum drm_connector_status status) 214 { 215 struct drm_encoder *best_encoder; 216 struct drm_encoder *encoder; 217 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 218 bool connected; 219 int i; 220 221 best_encoder = connector_funcs->best_encoder(connector); 222 223 drm_connector_for_each_possible_encoder(connector, encoder, i) { 224 if ((encoder == best_encoder) && (status == connector_status_connected)) 225 connected = true; 226 else 227 connected = false; 228 229 amdgpu_atombios_encoder_set_bios_scratch_regs(connector, encoder, connected); 230 } 231 } 232 233 static struct drm_encoder * 234 amdgpu_connector_find_encoder(struct drm_connector *connector, 235 int encoder_type) 236 { 237 struct drm_encoder *encoder; 238 int i; 239 240 drm_connector_for_each_possible_encoder(connector, encoder, i) { 241 if (encoder->encoder_type == encoder_type) 242 return encoder; 243 } 244 245 return NULL; 246 } 247 248 struct edid *amdgpu_connector_edid(struct drm_connector *connector) 249 { 250 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 251 struct drm_property_blob *edid_blob = connector->edid_blob_ptr; 252 253 if (amdgpu_connector->edid) { 254 return amdgpu_connector->edid; 255 } else if (edid_blob) { 256 struct edid *edid = kmemdup(edid_blob->data, edid_blob->length, GFP_KERNEL); 257 if (edid) 258 amdgpu_connector->edid = edid; 259 } 260 return amdgpu_connector->edid; 261 } 262 263 static struct edid * 264 amdgpu_connector_get_hardcoded_edid(struct amdgpu_device *adev) 265 { 266 struct edid *edid; 267 268 if (adev->mode_info.bios_hardcoded_edid) { 269 edid = kmalloc(adev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 270 if (edid) { 271 memcpy((unsigned char *)edid, 272 (unsigned char *)adev->mode_info.bios_hardcoded_edid, 273 adev->mode_info.bios_hardcoded_edid_size); 274 return edid; 275 } 276 } 277 return NULL; 278 } 279 280 static void amdgpu_connector_get_edid(struct drm_connector *connector) 281 { 282 struct drm_device *dev = connector->dev; 283 struct amdgpu_device *adev = dev->dev_private; 284 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 285 286 if (amdgpu_connector->edid) 287 return; 288 289 /* on hw with routers, select right port */ 290 if (amdgpu_connector->router.ddc_valid) 291 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 292 293 if ((amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 294 ENCODER_OBJECT_ID_NONE) && 295 amdgpu_connector->ddc_bus->has_aux) { 296 amdgpu_connector->edid = drm_get_edid(connector, 297 &amdgpu_connector->ddc_bus->aux.ddc); 298 } else if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) || 299 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) { 300 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 301 302 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT || 303 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && 304 amdgpu_connector->ddc_bus->has_aux) 305 amdgpu_connector->edid = drm_get_edid(connector, 306 &amdgpu_connector->ddc_bus->aux.ddc); 307 else if (amdgpu_connector->ddc_bus) 308 amdgpu_connector->edid = drm_get_edid(connector, 309 &amdgpu_connector->ddc_bus->adapter); 310 } else if (amdgpu_connector->ddc_bus) { 311 amdgpu_connector->edid = drm_get_edid(connector, 312 &amdgpu_connector->ddc_bus->adapter); 313 } 314 315 if (!amdgpu_connector->edid) { 316 /* some laptops provide a hardcoded edid in rom for LCDs */ 317 if (((connector->connector_type == DRM_MODE_CONNECTOR_LVDS) || 318 (connector->connector_type == DRM_MODE_CONNECTOR_eDP))) 319 amdgpu_connector->edid = amdgpu_connector_get_hardcoded_edid(adev); 320 } 321 } 322 323 static void amdgpu_connector_free_edid(struct drm_connector *connector) 324 { 325 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 326 327 kfree(amdgpu_connector->edid); 328 amdgpu_connector->edid = NULL; 329 } 330 331 static int amdgpu_connector_ddc_get_modes(struct drm_connector *connector) 332 { 333 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 334 int ret; 335 336 if (amdgpu_connector->edid) { 337 drm_connector_update_edid_property(connector, amdgpu_connector->edid); 338 ret = drm_add_edid_modes(connector, amdgpu_connector->edid); 339 return ret; 340 } 341 drm_connector_update_edid_property(connector, NULL); 342 return 0; 343 } 344 345 static struct drm_encoder * 346 amdgpu_connector_best_single_encoder(struct drm_connector *connector) 347 { 348 struct drm_encoder *encoder; 349 int i; 350 351 /* pick the first one */ 352 drm_connector_for_each_possible_encoder(connector, encoder, i) 353 return encoder; 354 355 return NULL; 356 } 357 358 static void amdgpu_get_native_mode(struct drm_connector *connector) 359 { 360 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 361 struct amdgpu_encoder *amdgpu_encoder; 362 363 if (encoder == NULL) 364 return; 365 366 amdgpu_encoder = to_amdgpu_encoder(encoder); 367 368 if (!list_empty(&connector->probed_modes)) { 369 struct drm_display_mode *preferred_mode = 370 list_first_entry(&connector->probed_modes, 371 struct drm_display_mode, head); 372 373 amdgpu_encoder->native_mode = *preferred_mode; 374 } else { 375 amdgpu_encoder->native_mode.clock = 0; 376 } 377 } 378 379 static struct drm_display_mode * 380 amdgpu_connector_lcd_native_mode(struct drm_encoder *encoder) 381 { 382 struct drm_device *dev = encoder->dev; 383 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 384 struct drm_display_mode *mode = NULL; 385 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 386 387 if (native_mode->hdisplay != 0 && 388 native_mode->vdisplay != 0 && 389 native_mode->clock != 0) { 390 mode = drm_mode_duplicate(dev, native_mode); 391 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 392 drm_mode_set_name(mode); 393 394 DRM_DEBUG_KMS("Adding native panel mode %s\n", mode->name); 395 } else if (native_mode->hdisplay != 0 && 396 native_mode->vdisplay != 0) { 397 /* mac laptops without an edid */ 398 /* Note that this is not necessarily the exact panel mode, 399 * but an approximation based on the cvt formula. For these 400 * systems we should ideally read the mode info out of the 401 * registers or add a mode table, but this works and is much 402 * simpler. 403 */ 404 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); 405 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 406 DRM_DEBUG_KMS("Adding cvt approximation of native panel mode %s\n", mode->name); 407 } 408 return mode; 409 } 410 411 static void amdgpu_connector_add_common_modes(struct drm_encoder *encoder, 412 struct drm_connector *connector) 413 { 414 struct drm_device *dev = encoder->dev; 415 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 416 struct drm_display_mode *mode = NULL; 417 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 418 int i; 419 static const struct mode_size { 420 int w; 421 int h; 422 } common_modes[17] = { 423 { 640, 480}, 424 { 720, 480}, 425 { 800, 600}, 426 { 848, 480}, 427 {1024, 768}, 428 {1152, 768}, 429 {1280, 720}, 430 {1280, 800}, 431 {1280, 854}, 432 {1280, 960}, 433 {1280, 1024}, 434 {1440, 900}, 435 {1400, 1050}, 436 {1680, 1050}, 437 {1600, 1200}, 438 {1920, 1080}, 439 {1920, 1200} 440 }; 441 442 for (i = 0; i < 17; i++) { 443 if (amdgpu_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 444 if (common_modes[i].w > 1024 || 445 common_modes[i].h > 768) 446 continue; 447 } 448 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 449 if (common_modes[i].w > native_mode->hdisplay || 450 common_modes[i].h > native_mode->vdisplay || 451 (common_modes[i].w == native_mode->hdisplay && 452 common_modes[i].h == native_mode->vdisplay)) 453 continue; 454 } 455 if (common_modes[i].w < 320 || common_modes[i].h < 200) 456 continue; 457 458 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false); 459 drm_mode_probed_add(connector, mode); 460 } 461 } 462 463 static int amdgpu_connector_set_property(struct drm_connector *connector, 464 struct drm_property *property, 465 uint64_t val) 466 { 467 struct drm_device *dev = connector->dev; 468 struct amdgpu_device *adev = dev->dev_private; 469 struct drm_encoder *encoder; 470 struct amdgpu_encoder *amdgpu_encoder; 471 472 if (property == adev->mode_info.coherent_mode_property) { 473 struct amdgpu_encoder_atom_dig *dig; 474 bool new_coherent_mode; 475 476 /* need to find digital encoder on connector */ 477 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 478 if (!encoder) 479 return 0; 480 481 amdgpu_encoder = to_amdgpu_encoder(encoder); 482 483 if (!amdgpu_encoder->enc_priv) 484 return 0; 485 486 dig = amdgpu_encoder->enc_priv; 487 new_coherent_mode = val ? true : false; 488 if (dig->coherent_mode != new_coherent_mode) { 489 dig->coherent_mode = new_coherent_mode; 490 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 491 } 492 } 493 494 if (property == adev->mode_info.audio_property) { 495 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 496 /* need to find digital encoder on connector */ 497 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 498 if (!encoder) 499 return 0; 500 501 amdgpu_encoder = to_amdgpu_encoder(encoder); 502 503 if (amdgpu_connector->audio != val) { 504 amdgpu_connector->audio = val; 505 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 506 } 507 } 508 509 if (property == adev->mode_info.dither_property) { 510 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 511 /* need to find digital encoder on connector */ 512 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 513 if (!encoder) 514 return 0; 515 516 amdgpu_encoder = to_amdgpu_encoder(encoder); 517 518 if (amdgpu_connector->dither != val) { 519 amdgpu_connector->dither = val; 520 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 521 } 522 } 523 524 if (property == adev->mode_info.underscan_property) { 525 /* need to find digital encoder on connector */ 526 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 527 if (!encoder) 528 return 0; 529 530 amdgpu_encoder = to_amdgpu_encoder(encoder); 531 532 if (amdgpu_encoder->underscan_type != val) { 533 amdgpu_encoder->underscan_type = val; 534 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 535 } 536 } 537 538 if (property == adev->mode_info.underscan_hborder_property) { 539 /* need to find digital encoder on connector */ 540 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 541 if (!encoder) 542 return 0; 543 544 amdgpu_encoder = to_amdgpu_encoder(encoder); 545 546 if (amdgpu_encoder->underscan_hborder != val) { 547 amdgpu_encoder->underscan_hborder = val; 548 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 549 } 550 } 551 552 if (property == adev->mode_info.underscan_vborder_property) { 553 /* need to find digital encoder on connector */ 554 encoder = amdgpu_connector_find_encoder(connector, DRM_MODE_ENCODER_TMDS); 555 if (!encoder) 556 return 0; 557 558 amdgpu_encoder = to_amdgpu_encoder(encoder); 559 560 if (amdgpu_encoder->underscan_vborder != val) { 561 amdgpu_encoder->underscan_vborder = val; 562 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 563 } 564 } 565 566 if (property == adev->mode_info.load_detect_property) { 567 struct amdgpu_connector *amdgpu_connector = 568 to_amdgpu_connector(connector); 569 570 if (val == 0) 571 amdgpu_connector->dac_load_detect = false; 572 else 573 amdgpu_connector->dac_load_detect = true; 574 } 575 576 if (property == dev->mode_config.scaling_mode_property) { 577 enum amdgpu_rmx_type rmx_type; 578 579 if (connector->encoder) { 580 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 581 } else { 582 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 583 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 584 } 585 586 switch (val) { 587 default: 588 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 589 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 590 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 591 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 592 } 593 if (amdgpu_encoder->rmx_type == rmx_type) 594 return 0; 595 596 if ((rmx_type != DRM_MODE_SCALE_NONE) && 597 (amdgpu_encoder->native_mode.clock == 0)) 598 return 0; 599 600 amdgpu_encoder->rmx_type = rmx_type; 601 602 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 603 } 604 605 return 0; 606 } 607 608 static void 609 amdgpu_connector_fixup_lcd_native_mode(struct drm_encoder *encoder, 610 struct drm_connector *connector) 611 { 612 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 613 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 614 struct drm_display_mode *t, *mode; 615 616 /* If the EDID preferred mode doesn't match the native mode, use it */ 617 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 618 if (mode->type & DRM_MODE_TYPE_PREFERRED) { 619 if (mode->hdisplay != native_mode->hdisplay || 620 mode->vdisplay != native_mode->vdisplay) 621 memcpy(native_mode, mode, sizeof(*mode)); 622 } 623 } 624 625 /* Try to get native mode details from EDID if necessary */ 626 if (!native_mode->clock) { 627 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 628 if (mode->hdisplay == native_mode->hdisplay && 629 mode->vdisplay == native_mode->vdisplay) { 630 *native_mode = *mode; 631 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V); 632 DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n"); 633 break; 634 } 635 } 636 } 637 638 if (!native_mode->clock) { 639 DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n"); 640 amdgpu_encoder->rmx_type = RMX_OFF; 641 } 642 } 643 644 static int amdgpu_connector_lvds_get_modes(struct drm_connector *connector) 645 { 646 struct drm_encoder *encoder; 647 int ret = 0; 648 struct drm_display_mode *mode; 649 650 amdgpu_connector_get_edid(connector); 651 ret = amdgpu_connector_ddc_get_modes(connector); 652 if (ret > 0) { 653 encoder = amdgpu_connector_best_single_encoder(connector); 654 if (encoder) { 655 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 656 /* add scaled modes */ 657 amdgpu_connector_add_common_modes(encoder, connector); 658 } 659 return ret; 660 } 661 662 encoder = amdgpu_connector_best_single_encoder(connector); 663 if (!encoder) 664 return 0; 665 666 /* we have no EDID modes */ 667 mode = amdgpu_connector_lcd_native_mode(encoder); 668 if (mode) { 669 ret = 1; 670 drm_mode_probed_add(connector, mode); 671 /* add the width/height from vbios tables if available */ 672 connector->display_info.width_mm = mode->width_mm; 673 connector->display_info.height_mm = mode->height_mm; 674 /* add scaled modes */ 675 amdgpu_connector_add_common_modes(encoder, connector); 676 } 677 678 return ret; 679 } 680 681 static enum drm_mode_status amdgpu_connector_lvds_mode_valid(struct drm_connector *connector, 682 struct drm_display_mode *mode) 683 { 684 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 685 686 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 687 return MODE_PANEL; 688 689 if (encoder) { 690 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 691 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 692 693 /* AVIVO hardware supports downscaling modes larger than the panel 694 * to the panel size, but I'm not sure this is desirable. 695 */ 696 if ((mode->hdisplay > native_mode->hdisplay) || 697 (mode->vdisplay > native_mode->vdisplay)) 698 return MODE_PANEL; 699 700 /* if scaling is disabled, block non-native modes */ 701 if (amdgpu_encoder->rmx_type == RMX_OFF) { 702 if ((mode->hdisplay != native_mode->hdisplay) || 703 (mode->vdisplay != native_mode->vdisplay)) 704 return MODE_PANEL; 705 } 706 } 707 708 return MODE_OK; 709 } 710 711 static enum drm_connector_status 712 amdgpu_connector_lvds_detect(struct drm_connector *connector, bool force) 713 { 714 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 715 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 716 enum drm_connector_status ret = connector_status_disconnected; 717 int r; 718 719 r = pm_runtime_get_sync(connector->dev->dev); 720 if (r < 0) 721 return connector_status_disconnected; 722 723 if (encoder) { 724 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 725 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 726 727 /* check if panel is valid */ 728 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 729 ret = connector_status_connected; 730 731 } 732 733 /* check for edid as well */ 734 amdgpu_connector_get_edid(connector); 735 if (amdgpu_connector->edid) 736 ret = connector_status_connected; 737 /* check acpi lid status ??? */ 738 739 amdgpu_connector_update_scratch_regs(connector, ret); 740 741 pm_runtime_mark_last_busy(connector->dev->dev); 742 pm_runtime_put_autosuspend(connector->dev->dev); 743 744 return ret; 745 } 746 747 static void amdgpu_connector_unregister(struct drm_connector *connector) 748 { 749 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 750 751 if (amdgpu_connector->ddc_bus && amdgpu_connector->ddc_bus->has_aux) { 752 drm_dp_aux_unregister(&amdgpu_connector->ddc_bus->aux); 753 amdgpu_connector->ddc_bus->has_aux = false; 754 } 755 } 756 757 static void amdgpu_connector_destroy(struct drm_connector *connector) 758 { 759 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 760 761 amdgpu_connector_free_edid(connector); 762 kfree(amdgpu_connector->con_priv); 763 drm_connector_unregister(connector); 764 drm_connector_cleanup(connector); 765 kfree(connector); 766 } 767 768 static int amdgpu_connector_set_lcd_property(struct drm_connector *connector, 769 struct drm_property *property, 770 uint64_t value) 771 { 772 struct drm_device *dev = connector->dev; 773 struct amdgpu_encoder *amdgpu_encoder; 774 enum amdgpu_rmx_type rmx_type; 775 776 DRM_DEBUG_KMS("\n"); 777 if (property != dev->mode_config.scaling_mode_property) 778 return 0; 779 780 if (connector->encoder) 781 amdgpu_encoder = to_amdgpu_encoder(connector->encoder); 782 else { 783 const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; 784 amdgpu_encoder = to_amdgpu_encoder(connector_funcs->best_encoder(connector)); 785 } 786 787 switch (value) { 788 case DRM_MODE_SCALE_NONE: rmx_type = RMX_OFF; break; 789 case DRM_MODE_SCALE_CENTER: rmx_type = RMX_CENTER; break; 790 case DRM_MODE_SCALE_ASPECT: rmx_type = RMX_ASPECT; break; 791 default: 792 case DRM_MODE_SCALE_FULLSCREEN: rmx_type = RMX_FULL; break; 793 } 794 if (amdgpu_encoder->rmx_type == rmx_type) 795 return 0; 796 797 amdgpu_encoder->rmx_type = rmx_type; 798 799 amdgpu_connector_property_change_mode(&amdgpu_encoder->base); 800 return 0; 801 } 802 803 804 static const struct drm_connector_helper_funcs amdgpu_connector_lvds_helper_funcs = { 805 .get_modes = amdgpu_connector_lvds_get_modes, 806 .mode_valid = amdgpu_connector_lvds_mode_valid, 807 .best_encoder = amdgpu_connector_best_single_encoder, 808 }; 809 810 static const struct drm_connector_funcs amdgpu_connector_lvds_funcs = { 811 .dpms = drm_helper_connector_dpms, 812 .detect = amdgpu_connector_lvds_detect, 813 .fill_modes = drm_helper_probe_single_connector_modes, 814 .early_unregister = amdgpu_connector_unregister, 815 .destroy = amdgpu_connector_destroy, 816 .set_property = amdgpu_connector_set_lcd_property, 817 }; 818 819 static int amdgpu_connector_vga_get_modes(struct drm_connector *connector) 820 { 821 int ret; 822 823 amdgpu_connector_get_edid(connector); 824 ret = amdgpu_connector_ddc_get_modes(connector); 825 826 return ret; 827 } 828 829 static enum drm_mode_status amdgpu_connector_vga_mode_valid(struct drm_connector *connector, 830 struct drm_display_mode *mode) 831 { 832 struct drm_device *dev = connector->dev; 833 struct amdgpu_device *adev = dev->dev_private; 834 835 /* XXX check mode bandwidth */ 836 837 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 838 return MODE_CLOCK_HIGH; 839 840 return MODE_OK; 841 } 842 843 static enum drm_connector_status 844 amdgpu_connector_vga_detect(struct drm_connector *connector, bool force) 845 { 846 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 847 struct drm_encoder *encoder; 848 const struct drm_encoder_helper_funcs *encoder_funcs; 849 bool dret = false; 850 enum drm_connector_status ret = connector_status_disconnected; 851 int r; 852 853 r = pm_runtime_get_sync(connector->dev->dev); 854 if (r < 0) 855 return connector_status_disconnected; 856 857 encoder = amdgpu_connector_best_single_encoder(connector); 858 if (!encoder) 859 ret = connector_status_disconnected; 860 861 if (amdgpu_connector->ddc_bus) 862 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 863 if (dret) { 864 amdgpu_connector->detected_by_load = false; 865 amdgpu_connector_free_edid(connector); 866 amdgpu_connector_get_edid(connector); 867 868 if (!amdgpu_connector->edid) { 869 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 870 connector->name); 871 ret = connector_status_connected; 872 } else { 873 amdgpu_connector->use_digital = 874 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 875 876 /* some oems have boards with separate digital and analog connectors 877 * with a shared ddc line (often vga + hdmi) 878 */ 879 if (amdgpu_connector->use_digital && amdgpu_connector->shared_ddc) { 880 amdgpu_connector_free_edid(connector); 881 ret = connector_status_disconnected; 882 } else { 883 ret = connector_status_connected; 884 } 885 } 886 } else { 887 888 /* if we aren't forcing don't do destructive polling */ 889 if (!force) { 890 /* only return the previous status if we last 891 * detected a monitor via load. 892 */ 893 if (amdgpu_connector->detected_by_load) 894 ret = connector->status; 895 goto out; 896 } 897 898 if (amdgpu_connector->dac_load_detect && encoder) { 899 encoder_funcs = encoder->helper_private; 900 ret = encoder_funcs->detect(encoder, connector); 901 if (ret != connector_status_disconnected) 902 amdgpu_connector->detected_by_load = true; 903 } 904 } 905 906 amdgpu_connector_update_scratch_regs(connector, ret); 907 908 out: 909 pm_runtime_mark_last_busy(connector->dev->dev); 910 pm_runtime_put_autosuspend(connector->dev->dev); 911 912 return ret; 913 } 914 915 static const struct drm_connector_helper_funcs amdgpu_connector_vga_helper_funcs = { 916 .get_modes = amdgpu_connector_vga_get_modes, 917 .mode_valid = amdgpu_connector_vga_mode_valid, 918 .best_encoder = amdgpu_connector_best_single_encoder, 919 }; 920 921 static const struct drm_connector_funcs amdgpu_connector_vga_funcs = { 922 .dpms = drm_helper_connector_dpms, 923 .detect = amdgpu_connector_vga_detect, 924 .fill_modes = drm_helper_probe_single_connector_modes, 925 .early_unregister = amdgpu_connector_unregister, 926 .destroy = amdgpu_connector_destroy, 927 .set_property = amdgpu_connector_set_property, 928 }; 929 930 static bool 931 amdgpu_connector_check_hpd_status_unchanged(struct drm_connector *connector) 932 { 933 struct drm_device *dev = connector->dev; 934 struct amdgpu_device *adev = dev->dev_private; 935 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 936 enum drm_connector_status status; 937 938 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) { 939 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) 940 status = connector_status_connected; 941 else 942 status = connector_status_disconnected; 943 if (connector->status == status) 944 return true; 945 } 946 947 return false; 948 } 949 950 /* 951 * DVI is complicated 952 * Do a DDC probe, if DDC probe passes, get the full EDID so 953 * we can do analog/digital monitor detection at this point. 954 * If the monitor is an analog monitor or we got no DDC, 955 * we need to find the DAC encoder object for this connector. 956 * If we got no DDC, we do load detection on the DAC encoder object. 957 * If we got analog DDC or load detection passes on the DAC encoder 958 * we have to check if this analog encoder is shared with anyone else (TV) 959 * if its shared we have to set the other connector to disconnected. 960 */ 961 static enum drm_connector_status 962 amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) 963 { 964 struct drm_device *dev = connector->dev; 965 struct amdgpu_device *adev = dev->dev_private; 966 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 967 const struct drm_encoder_helper_funcs *encoder_funcs; 968 int r; 969 enum drm_connector_status ret = connector_status_disconnected; 970 bool dret = false, broken_edid = false; 971 972 r = pm_runtime_get_sync(connector->dev->dev); 973 if (r < 0) 974 return connector_status_disconnected; 975 976 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 977 ret = connector->status; 978 goto exit; 979 } 980 981 if (amdgpu_connector->ddc_bus) 982 dret = amdgpu_display_ddc_probe(amdgpu_connector, false); 983 if (dret) { 984 amdgpu_connector->detected_by_load = false; 985 amdgpu_connector_free_edid(connector); 986 amdgpu_connector_get_edid(connector); 987 988 if (!amdgpu_connector->edid) { 989 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n", 990 connector->name); 991 ret = connector_status_connected; 992 broken_edid = true; /* defer use_digital to later */ 993 } else { 994 amdgpu_connector->use_digital = 995 !!(amdgpu_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 996 997 /* some oems have boards with separate digital and analog connectors 998 * with a shared ddc line (often vga + hdmi) 999 */ 1000 if ((!amdgpu_connector->use_digital) && amdgpu_connector->shared_ddc) { 1001 amdgpu_connector_free_edid(connector); 1002 ret = connector_status_disconnected; 1003 } else { 1004 ret = connector_status_connected; 1005 } 1006 1007 /* This gets complicated. We have boards with VGA + HDMI with a 1008 * shared DDC line and we have boards with DVI-D + HDMI with a shared 1009 * DDC line. The latter is more complex because with DVI<->HDMI adapters 1010 * you don't really know what's connected to which port as both are digital. 1011 */ 1012 if (amdgpu_connector->shared_ddc && (ret == connector_status_connected)) { 1013 struct drm_connector *list_connector; 1014 struct amdgpu_connector *list_amdgpu_connector; 1015 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) { 1016 if (connector == list_connector) 1017 continue; 1018 list_amdgpu_connector = to_amdgpu_connector(list_connector); 1019 if (list_amdgpu_connector->shared_ddc && 1020 (list_amdgpu_connector->ddc_bus->rec.i2c_id == 1021 amdgpu_connector->ddc_bus->rec.i2c_id)) { 1022 /* cases where both connectors are digital */ 1023 if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) { 1024 /* hpd is our only option in this case */ 1025 if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1026 amdgpu_connector_free_edid(connector); 1027 ret = connector_status_disconnected; 1028 } 1029 } 1030 } 1031 } 1032 } 1033 } 1034 } 1035 1036 if ((ret == connector_status_connected) && (amdgpu_connector->use_digital == true)) 1037 goto out; 1038 1039 /* DVI-D and HDMI-A are digital only */ 1040 if ((connector->connector_type == DRM_MODE_CONNECTOR_DVID) || 1041 (connector->connector_type == DRM_MODE_CONNECTOR_HDMIA)) 1042 goto out; 1043 1044 /* if we aren't forcing don't do destructive polling */ 1045 if (!force) { 1046 /* only return the previous status if we last 1047 * detected a monitor via load. 1048 */ 1049 if (amdgpu_connector->detected_by_load) 1050 ret = connector->status; 1051 goto out; 1052 } 1053 1054 /* find analog encoder */ 1055 if (amdgpu_connector->dac_load_detect) { 1056 struct drm_encoder *encoder; 1057 int i; 1058 1059 drm_connector_for_each_possible_encoder(connector, encoder, i) { 1060 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && 1061 encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) 1062 continue; 1063 1064 encoder_funcs = encoder->helper_private; 1065 if (encoder_funcs->detect) { 1066 if (!broken_edid) { 1067 if (ret != connector_status_connected) { 1068 /* deal with analog monitors without DDC */ 1069 ret = encoder_funcs->detect(encoder, connector); 1070 if (ret == connector_status_connected) { 1071 amdgpu_connector->use_digital = false; 1072 } 1073 if (ret != connector_status_disconnected) 1074 amdgpu_connector->detected_by_load = true; 1075 } 1076 } else { 1077 enum drm_connector_status lret; 1078 /* assume digital unless load detected otherwise */ 1079 amdgpu_connector->use_digital = true; 1080 lret = encoder_funcs->detect(encoder, connector); 1081 DRM_DEBUG_KMS("load_detect %x returned: %x\n",encoder->encoder_type,lret); 1082 if (lret == connector_status_connected) 1083 amdgpu_connector->use_digital = false; 1084 } 1085 break; 1086 } 1087 } 1088 } 1089 1090 out: 1091 /* updated in get modes as well since we need to know if it's analog or digital */ 1092 amdgpu_connector_update_scratch_regs(connector, ret); 1093 1094 exit: 1095 pm_runtime_mark_last_busy(connector->dev->dev); 1096 pm_runtime_put_autosuspend(connector->dev->dev); 1097 1098 return ret; 1099 } 1100 1101 /* okay need to be smart in here about which encoder to pick */ 1102 static struct drm_encoder * 1103 amdgpu_connector_dvi_encoder(struct drm_connector *connector) 1104 { 1105 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1106 struct drm_encoder *encoder; 1107 int i; 1108 1109 drm_connector_for_each_possible_encoder(connector, encoder, i) { 1110 if (amdgpu_connector->use_digital == true) { 1111 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1112 return encoder; 1113 } else { 1114 if (encoder->encoder_type == DRM_MODE_ENCODER_DAC || 1115 encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1116 return encoder; 1117 } 1118 } 1119 1120 /* see if we have a default encoder TODO */ 1121 1122 /* then check use digitial */ 1123 /* pick the first one */ 1124 drm_connector_for_each_possible_encoder(connector, encoder, i) 1125 return encoder; 1126 1127 return NULL; 1128 } 1129 1130 static void amdgpu_connector_dvi_force(struct drm_connector *connector) 1131 { 1132 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1133 if (connector->force == DRM_FORCE_ON) 1134 amdgpu_connector->use_digital = false; 1135 if (connector->force == DRM_FORCE_ON_DIGITAL) 1136 amdgpu_connector->use_digital = true; 1137 } 1138 1139 static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector *connector, 1140 struct drm_display_mode *mode) 1141 { 1142 struct drm_device *dev = connector->dev; 1143 struct amdgpu_device *adev = dev->dev_private; 1144 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1145 1146 /* XXX check mode bandwidth */ 1147 1148 if (amdgpu_connector->use_digital && (mode->clock > 165000)) { 1149 if ((amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 1150 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 1151 (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { 1152 return MODE_OK; 1153 } else if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1154 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1155 if (mode->clock > 340000) 1156 return MODE_CLOCK_HIGH; 1157 else 1158 return MODE_OK; 1159 } else { 1160 return MODE_CLOCK_HIGH; 1161 } 1162 } 1163 1164 /* check against the max pixel clock */ 1165 if ((mode->clock / 10) > adev->clock.max_pixel_clock) 1166 return MODE_CLOCK_HIGH; 1167 1168 return MODE_OK; 1169 } 1170 1171 static const struct drm_connector_helper_funcs amdgpu_connector_dvi_helper_funcs = { 1172 .get_modes = amdgpu_connector_vga_get_modes, 1173 .mode_valid = amdgpu_connector_dvi_mode_valid, 1174 .best_encoder = amdgpu_connector_dvi_encoder, 1175 }; 1176 1177 static const struct drm_connector_funcs amdgpu_connector_dvi_funcs = { 1178 .dpms = drm_helper_connector_dpms, 1179 .detect = amdgpu_connector_dvi_detect, 1180 .fill_modes = drm_helper_probe_single_connector_modes, 1181 .set_property = amdgpu_connector_set_property, 1182 .early_unregister = amdgpu_connector_unregister, 1183 .destroy = amdgpu_connector_destroy, 1184 .force = amdgpu_connector_dvi_force, 1185 }; 1186 1187 static int amdgpu_connector_dp_get_modes(struct drm_connector *connector) 1188 { 1189 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1190 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1191 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1192 int ret; 1193 1194 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1195 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1196 struct drm_display_mode *mode; 1197 1198 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1199 if (!amdgpu_dig_connector->edp_on) 1200 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1201 ATOM_TRANSMITTER_ACTION_POWER_ON); 1202 amdgpu_connector_get_edid(connector); 1203 ret = amdgpu_connector_ddc_get_modes(connector); 1204 if (!amdgpu_dig_connector->edp_on) 1205 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1206 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1207 } else { 1208 /* need to setup ddc on the bridge */ 1209 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1210 ENCODER_OBJECT_ID_NONE) { 1211 if (encoder) 1212 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1213 } 1214 amdgpu_connector_get_edid(connector); 1215 ret = amdgpu_connector_ddc_get_modes(connector); 1216 } 1217 1218 if (ret > 0) { 1219 if (encoder) { 1220 amdgpu_connector_fixup_lcd_native_mode(encoder, connector); 1221 /* add scaled modes */ 1222 amdgpu_connector_add_common_modes(encoder, connector); 1223 } 1224 return ret; 1225 } 1226 1227 if (!encoder) 1228 return 0; 1229 1230 /* we have no EDID modes */ 1231 mode = amdgpu_connector_lcd_native_mode(encoder); 1232 if (mode) { 1233 ret = 1; 1234 drm_mode_probed_add(connector, mode); 1235 /* add the width/height from vbios tables if available */ 1236 connector->display_info.width_mm = mode->width_mm; 1237 connector->display_info.height_mm = mode->height_mm; 1238 /* add scaled modes */ 1239 amdgpu_connector_add_common_modes(encoder, connector); 1240 } 1241 } else { 1242 /* need to setup ddc on the bridge */ 1243 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1244 ENCODER_OBJECT_ID_NONE) { 1245 if (encoder) 1246 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1247 } 1248 amdgpu_connector_get_edid(connector); 1249 ret = amdgpu_connector_ddc_get_modes(connector); 1250 1251 amdgpu_get_native_mode(connector); 1252 } 1253 1254 return ret; 1255 } 1256 1257 u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector) 1258 { 1259 struct drm_encoder *encoder; 1260 struct amdgpu_encoder *amdgpu_encoder; 1261 int i; 1262 1263 drm_connector_for_each_possible_encoder(connector, encoder, i) { 1264 amdgpu_encoder = to_amdgpu_encoder(encoder); 1265 1266 switch (amdgpu_encoder->encoder_id) { 1267 case ENCODER_OBJECT_ID_TRAVIS: 1268 case ENCODER_OBJECT_ID_NUTMEG: 1269 return amdgpu_encoder->encoder_id; 1270 default: 1271 break; 1272 } 1273 } 1274 1275 return ENCODER_OBJECT_ID_NONE; 1276 } 1277 1278 static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) 1279 { 1280 struct drm_encoder *encoder; 1281 struct amdgpu_encoder *amdgpu_encoder; 1282 int i; 1283 bool found = false; 1284 1285 drm_connector_for_each_possible_encoder(connector, encoder, i) { 1286 amdgpu_encoder = to_amdgpu_encoder(encoder); 1287 if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) 1288 found = true; 1289 } 1290 1291 return found; 1292 } 1293 1294 bool amdgpu_connector_is_dp12_capable(struct drm_connector *connector) 1295 { 1296 struct drm_device *dev = connector->dev; 1297 struct amdgpu_device *adev = dev->dev_private; 1298 1299 if ((adev->clock.default_dispclk >= 53900) && 1300 amdgpu_connector_encoder_is_hbr2(connector)) { 1301 return true; 1302 } 1303 1304 return false; 1305 } 1306 1307 static enum drm_connector_status 1308 amdgpu_connector_dp_detect(struct drm_connector *connector, bool force) 1309 { 1310 struct drm_device *dev = connector->dev; 1311 struct amdgpu_device *adev = dev->dev_private; 1312 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1313 enum drm_connector_status ret = connector_status_disconnected; 1314 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1315 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1316 int r; 1317 1318 r = pm_runtime_get_sync(connector->dev->dev); 1319 if (r < 0) 1320 return connector_status_disconnected; 1321 1322 if (!force && amdgpu_connector_check_hpd_status_unchanged(connector)) { 1323 ret = connector->status; 1324 goto out; 1325 } 1326 1327 amdgpu_connector_free_edid(connector); 1328 1329 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1330 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1331 if (encoder) { 1332 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1333 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1334 1335 /* check if panel is valid */ 1336 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240) 1337 ret = connector_status_connected; 1338 } 1339 /* eDP is always DP */ 1340 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1341 if (!amdgpu_dig_connector->edp_on) 1342 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1343 ATOM_TRANSMITTER_ACTION_POWER_ON); 1344 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1345 ret = connector_status_connected; 1346 if (!amdgpu_dig_connector->edp_on) 1347 amdgpu_atombios_encoder_set_edp_panel_power(connector, 1348 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1349 } else if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) != 1350 ENCODER_OBJECT_ID_NONE) { 1351 /* DP bridges are always DP */ 1352 amdgpu_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT; 1353 /* get the DPCD from the bridge */ 1354 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1355 1356 if (encoder) { 1357 /* setup ddc on the bridge */ 1358 amdgpu_atombios_encoder_setup_ext_encoder_ddc(encoder); 1359 /* bridge chips are always aux */ 1360 /* try DDC */ 1361 if (amdgpu_display_ddc_probe(amdgpu_connector, true)) 1362 ret = connector_status_connected; 1363 else if (amdgpu_connector->dac_load_detect) { /* try load detection */ 1364 const struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; 1365 ret = encoder_funcs->detect(encoder, connector); 1366 } 1367 } 1368 } else { 1369 amdgpu_dig_connector->dp_sink_type = 1370 amdgpu_atombios_dp_get_sinktype(amdgpu_connector); 1371 if (amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { 1372 ret = connector_status_connected; 1373 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1374 amdgpu_atombios_dp_get_dpcd(amdgpu_connector); 1375 } else { 1376 if (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 1377 if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) 1378 ret = connector_status_connected; 1379 } else { 1380 /* try non-aux ddc (DP to DVI/HDMI/etc. adapter) */ 1381 if (amdgpu_display_ddc_probe(amdgpu_connector, 1382 false)) 1383 ret = connector_status_connected; 1384 } 1385 } 1386 } 1387 1388 amdgpu_connector_update_scratch_regs(connector, ret); 1389 out: 1390 pm_runtime_mark_last_busy(connector->dev->dev); 1391 pm_runtime_put_autosuspend(connector->dev->dev); 1392 1393 return ret; 1394 } 1395 1396 static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector *connector, 1397 struct drm_display_mode *mode) 1398 { 1399 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 1400 struct amdgpu_connector_atom_dig *amdgpu_dig_connector = amdgpu_connector->con_priv; 1401 1402 /* XXX check mode bandwidth */ 1403 1404 if ((connector->connector_type == DRM_MODE_CONNECTOR_eDP) || 1405 (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { 1406 struct drm_encoder *encoder = amdgpu_connector_best_single_encoder(connector); 1407 1408 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) 1409 return MODE_PANEL; 1410 1411 if (encoder) { 1412 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1413 struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; 1414 1415 /* AVIVO hardware supports downscaling modes larger than the panel 1416 * to the panel size, but I'm not sure this is desirable. 1417 */ 1418 if ((mode->hdisplay > native_mode->hdisplay) || 1419 (mode->vdisplay > native_mode->vdisplay)) 1420 return MODE_PANEL; 1421 1422 /* if scaling is disabled, block non-native modes */ 1423 if (amdgpu_encoder->rmx_type == RMX_OFF) { 1424 if ((mode->hdisplay != native_mode->hdisplay) || 1425 (mode->vdisplay != native_mode->vdisplay)) 1426 return MODE_PANEL; 1427 } 1428 } 1429 return MODE_OK; 1430 } else { 1431 if ((amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 1432 (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 1433 return amdgpu_atombios_dp_mode_valid_helper(connector, mode); 1434 } else { 1435 if (drm_detect_hdmi_monitor(amdgpu_connector_edid(connector))) { 1436 /* HDMI 1.3+ supports max clock of 340 Mhz */ 1437 if (mode->clock > 340000) 1438 return MODE_CLOCK_HIGH; 1439 } else { 1440 if (mode->clock > 165000) 1441 return MODE_CLOCK_HIGH; 1442 } 1443 } 1444 } 1445 1446 return MODE_OK; 1447 } 1448 1449 static const struct drm_connector_helper_funcs amdgpu_connector_dp_helper_funcs = { 1450 .get_modes = amdgpu_connector_dp_get_modes, 1451 .mode_valid = amdgpu_connector_dp_mode_valid, 1452 .best_encoder = amdgpu_connector_dvi_encoder, 1453 }; 1454 1455 static const struct drm_connector_funcs amdgpu_connector_dp_funcs = { 1456 .dpms = drm_helper_connector_dpms, 1457 .detect = amdgpu_connector_dp_detect, 1458 .fill_modes = drm_helper_probe_single_connector_modes, 1459 .set_property = amdgpu_connector_set_property, 1460 .early_unregister = amdgpu_connector_unregister, 1461 .destroy = amdgpu_connector_destroy, 1462 .force = amdgpu_connector_dvi_force, 1463 }; 1464 1465 static const struct drm_connector_funcs amdgpu_connector_edp_funcs = { 1466 .dpms = drm_helper_connector_dpms, 1467 .detect = amdgpu_connector_dp_detect, 1468 .fill_modes = drm_helper_probe_single_connector_modes, 1469 .set_property = amdgpu_connector_set_lcd_property, 1470 .early_unregister = amdgpu_connector_unregister, 1471 .destroy = amdgpu_connector_destroy, 1472 .force = amdgpu_connector_dvi_force, 1473 }; 1474 1475 void 1476 amdgpu_connector_add(struct amdgpu_device *adev, 1477 uint32_t connector_id, 1478 uint32_t supported_device, 1479 int connector_type, 1480 struct amdgpu_i2c_bus_rec *i2c_bus, 1481 uint16_t connector_object_id, 1482 struct amdgpu_hpd *hpd, 1483 struct amdgpu_router *router) 1484 { 1485 struct drm_device *dev = adev->ddev; 1486 struct drm_connector *connector; 1487 struct amdgpu_connector *amdgpu_connector; 1488 struct amdgpu_connector_atom_dig *amdgpu_dig_connector; 1489 struct drm_encoder *encoder; 1490 struct amdgpu_encoder *amdgpu_encoder; 1491 uint32_t subpixel_order = SubPixelNone; 1492 bool shared_ddc = false; 1493 bool is_dp_bridge = false; 1494 bool has_aux = false; 1495 1496 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 1497 return; 1498 1499 /* see if we already added it */ 1500 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1501 amdgpu_connector = to_amdgpu_connector(connector); 1502 if (amdgpu_connector->connector_id == connector_id) { 1503 amdgpu_connector->devices |= supported_device; 1504 return; 1505 } 1506 if (amdgpu_connector->ddc_bus && i2c_bus->valid) { 1507 if (amdgpu_connector->ddc_bus->rec.i2c_id == i2c_bus->i2c_id) { 1508 amdgpu_connector->shared_ddc = true; 1509 shared_ddc = true; 1510 } 1511 if (amdgpu_connector->router_bus && router->ddc_valid && 1512 (amdgpu_connector->router.router_id == router->router_id)) { 1513 amdgpu_connector->shared_ddc = false; 1514 shared_ddc = false; 1515 } 1516 } 1517 } 1518 1519 /* check if it's a dp bridge */ 1520 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1521 amdgpu_encoder = to_amdgpu_encoder(encoder); 1522 if (amdgpu_encoder->devices & supported_device) { 1523 switch (amdgpu_encoder->encoder_id) { 1524 case ENCODER_OBJECT_ID_TRAVIS: 1525 case ENCODER_OBJECT_ID_NUTMEG: 1526 is_dp_bridge = true; 1527 break; 1528 default: 1529 break; 1530 } 1531 } 1532 } 1533 1534 amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL); 1535 if (!amdgpu_connector) 1536 return; 1537 1538 connector = &amdgpu_connector->base; 1539 1540 amdgpu_connector->connector_id = connector_id; 1541 amdgpu_connector->devices = supported_device; 1542 amdgpu_connector->shared_ddc = shared_ddc; 1543 amdgpu_connector->connector_object_id = connector_object_id; 1544 amdgpu_connector->hpd = *hpd; 1545 1546 amdgpu_connector->router = *router; 1547 if (router->ddc_valid || router->cd_valid) { 1548 amdgpu_connector->router_bus = amdgpu_i2c_lookup(adev, &router->i2c_info); 1549 if (!amdgpu_connector->router_bus) 1550 DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n"); 1551 } 1552 1553 if (is_dp_bridge) { 1554 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1555 if (!amdgpu_dig_connector) 1556 goto failed; 1557 amdgpu_connector->con_priv = amdgpu_dig_connector; 1558 if (i2c_bus->valid) { 1559 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1560 if (amdgpu_connector->ddc_bus) 1561 has_aux = true; 1562 else 1563 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1564 } 1565 switch (connector_type) { 1566 case DRM_MODE_CONNECTOR_VGA: 1567 case DRM_MODE_CONNECTOR_DVIA: 1568 default: 1569 drm_connector_init(dev, &amdgpu_connector->base, 1570 &amdgpu_connector_dp_funcs, connector_type); 1571 drm_connector_helper_add(&amdgpu_connector->base, 1572 &amdgpu_connector_dp_helper_funcs); 1573 connector->interlace_allowed = true; 1574 connector->doublescan_allowed = true; 1575 amdgpu_connector->dac_load_detect = true; 1576 drm_object_attach_property(&amdgpu_connector->base.base, 1577 adev->mode_info.load_detect_property, 1578 1); 1579 drm_object_attach_property(&amdgpu_connector->base.base, 1580 dev->mode_config.scaling_mode_property, 1581 DRM_MODE_SCALE_NONE); 1582 break; 1583 case DRM_MODE_CONNECTOR_DVII: 1584 case DRM_MODE_CONNECTOR_DVID: 1585 case DRM_MODE_CONNECTOR_HDMIA: 1586 case DRM_MODE_CONNECTOR_HDMIB: 1587 case DRM_MODE_CONNECTOR_DisplayPort: 1588 drm_connector_init(dev, &amdgpu_connector->base, 1589 &amdgpu_connector_dp_funcs, connector_type); 1590 drm_connector_helper_add(&amdgpu_connector->base, 1591 &amdgpu_connector_dp_helper_funcs); 1592 drm_object_attach_property(&amdgpu_connector->base.base, 1593 adev->mode_info.underscan_property, 1594 UNDERSCAN_OFF); 1595 drm_object_attach_property(&amdgpu_connector->base.base, 1596 adev->mode_info.underscan_hborder_property, 1597 0); 1598 drm_object_attach_property(&amdgpu_connector->base.base, 1599 adev->mode_info.underscan_vborder_property, 1600 0); 1601 1602 drm_object_attach_property(&amdgpu_connector->base.base, 1603 dev->mode_config.scaling_mode_property, 1604 DRM_MODE_SCALE_NONE); 1605 1606 drm_object_attach_property(&amdgpu_connector->base.base, 1607 adev->mode_info.dither_property, 1608 AMDGPU_FMT_DITHER_DISABLE); 1609 1610 if (amdgpu_audio != 0) 1611 drm_object_attach_property(&amdgpu_connector->base.base, 1612 adev->mode_info.audio_property, 1613 AMDGPU_AUDIO_AUTO); 1614 1615 subpixel_order = SubPixelHorizontalRGB; 1616 connector->interlace_allowed = true; 1617 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1618 connector->doublescan_allowed = true; 1619 else 1620 connector->doublescan_allowed = false; 1621 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1622 amdgpu_connector->dac_load_detect = true; 1623 drm_object_attach_property(&amdgpu_connector->base.base, 1624 adev->mode_info.load_detect_property, 1625 1); 1626 } 1627 break; 1628 case DRM_MODE_CONNECTOR_LVDS: 1629 case DRM_MODE_CONNECTOR_eDP: 1630 drm_connector_init(dev, &amdgpu_connector->base, 1631 &amdgpu_connector_edp_funcs, connector_type); 1632 drm_connector_helper_add(&amdgpu_connector->base, 1633 &amdgpu_connector_dp_helper_funcs); 1634 drm_object_attach_property(&amdgpu_connector->base.base, 1635 dev->mode_config.scaling_mode_property, 1636 DRM_MODE_SCALE_FULLSCREEN); 1637 subpixel_order = SubPixelHorizontalRGB; 1638 connector->interlace_allowed = false; 1639 connector->doublescan_allowed = false; 1640 break; 1641 } 1642 } else { 1643 switch (connector_type) { 1644 case DRM_MODE_CONNECTOR_VGA: 1645 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1646 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1647 if (i2c_bus->valid) { 1648 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1649 if (!amdgpu_connector->ddc_bus) 1650 DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1651 } 1652 amdgpu_connector->dac_load_detect = true; 1653 drm_object_attach_property(&amdgpu_connector->base.base, 1654 adev->mode_info.load_detect_property, 1655 1); 1656 drm_object_attach_property(&amdgpu_connector->base.base, 1657 dev->mode_config.scaling_mode_property, 1658 DRM_MODE_SCALE_NONE); 1659 /* no HPD on analog connectors */ 1660 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1661 connector->interlace_allowed = true; 1662 connector->doublescan_allowed = true; 1663 break; 1664 case DRM_MODE_CONNECTOR_DVIA: 1665 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_vga_funcs, connector_type); 1666 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_vga_helper_funcs); 1667 if (i2c_bus->valid) { 1668 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1669 if (!amdgpu_connector->ddc_bus) 1670 DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1671 } 1672 amdgpu_connector->dac_load_detect = true; 1673 drm_object_attach_property(&amdgpu_connector->base.base, 1674 adev->mode_info.load_detect_property, 1675 1); 1676 drm_object_attach_property(&amdgpu_connector->base.base, 1677 dev->mode_config.scaling_mode_property, 1678 DRM_MODE_SCALE_NONE); 1679 /* no HPD on analog connectors */ 1680 amdgpu_connector->hpd.hpd = AMDGPU_HPD_NONE; 1681 connector->interlace_allowed = true; 1682 connector->doublescan_allowed = true; 1683 break; 1684 case DRM_MODE_CONNECTOR_DVII: 1685 case DRM_MODE_CONNECTOR_DVID: 1686 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1687 if (!amdgpu_dig_connector) 1688 goto failed; 1689 amdgpu_connector->con_priv = amdgpu_dig_connector; 1690 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1691 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1692 if (i2c_bus->valid) { 1693 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1694 if (!amdgpu_connector->ddc_bus) 1695 DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1696 } 1697 subpixel_order = SubPixelHorizontalRGB; 1698 drm_object_attach_property(&amdgpu_connector->base.base, 1699 adev->mode_info.coherent_mode_property, 1700 1); 1701 drm_object_attach_property(&amdgpu_connector->base.base, 1702 adev->mode_info.underscan_property, 1703 UNDERSCAN_OFF); 1704 drm_object_attach_property(&amdgpu_connector->base.base, 1705 adev->mode_info.underscan_hborder_property, 1706 0); 1707 drm_object_attach_property(&amdgpu_connector->base.base, 1708 adev->mode_info.underscan_vborder_property, 1709 0); 1710 drm_object_attach_property(&amdgpu_connector->base.base, 1711 dev->mode_config.scaling_mode_property, 1712 DRM_MODE_SCALE_NONE); 1713 1714 if (amdgpu_audio != 0) { 1715 drm_object_attach_property(&amdgpu_connector->base.base, 1716 adev->mode_info.audio_property, 1717 AMDGPU_AUDIO_AUTO); 1718 } 1719 drm_object_attach_property(&amdgpu_connector->base.base, 1720 adev->mode_info.dither_property, 1721 AMDGPU_FMT_DITHER_DISABLE); 1722 if (connector_type == DRM_MODE_CONNECTOR_DVII) { 1723 amdgpu_connector->dac_load_detect = true; 1724 drm_object_attach_property(&amdgpu_connector->base.base, 1725 adev->mode_info.load_detect_property, 1726 1); 1727 } 1728 connector->interlace_allowed = true; 1729 if (connector_type == DRM_MODE_CONNECTOR_DVII) 1730 connector->doublescan_allowed = true; 1731 else 1732 connector->doublescan_allowed = false; 1733 break; 1734 case DRM_MODE_CONNECTOR_HDMIA: 1735 case DRM_MODE_CONNECTOR_HDMIB: 1736 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1737 if (!amdgpu_dig_connector) 1738 goto failed; 1739 amdgpu_connector->con_priv = amdgpu_dig_connector; 1740 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dvi_funcs, connector_type); 1741 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dvi_helper_funcs); 1742 if (i2c_bus->valid) { 1743 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1744 if (!amdgpu_connector->ddc_bus) 1745 DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1746 } 1747 drm_object_attach_property(&amdgpu_connector->base.base, 1748 adev->mode_info.coherent_mode_property, 1749 1); 1750 drm_object_attach_property(&amdgpu_connector->base.base, 1751 adev->mode_info.underscan_property, 1752 UNDERSCAN_OFF); 1753 drm_object_attach_property(&amdgpu_connector->base.base, 1754 adev->mode_info.underscan_hborder_property, 1755 0); 1756 drm_object_attach_property(&amdgpu_connector->base.base, 1757 adev->mode_info.underscan_vborder_property, 1758 0); 1759 drm_object_attach_property(&amdgpu_connector->base.base, 1760 dev->mode_config.scaling_mode_property, 1761 DRM_MODE_SCALE_NONE); 1762 if (amdgpu_audio != 0) { 1763 drm_object_attach_property(&amdgpu_connector->base.base, 1764 adev->mode_info.audio_property, 1765 AMDGPU_AUDIO_AUTO); 1766 } 1767 drm_object_attach_property(&amdgpu_connector->base.base, 1768 adev->mode_info.dither_property, 1769 AMDGPU_FMT_DITHER_DISABLE); 1770 subpixel_order = SubPixelHorizontalRGB; 1771 connector->interlace_allowed = true; 1772 if (connector_type == DRM_MODE_CONNECTOR_HDMIB) 1773 connector->doublescan_allowed = true; 1774 else 1775 connector->doublescan_allowed = false; 1776 break; 1777 case DRM_MODE_CONNECTOR_DisplayPort: 1778 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1779 if (!amdgpu_dig_connector) 1780 goto failed; 1781 amdgpu_connector->con_priv = amdgpu_dig_connector; 1782 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_dp_funcs, connector_type); 1783 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1784 if (i2c_bus->valid) { 1785 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1786 if (amdgpu_connector->ddc_bus) 1787 has_aux = true; 1788 else 1789 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1790 } 1791 subpixel_order = SubPixelHorizontalRGB; 1792 drm_object_attach_property(&amdgpu_connector->base.base, 1793 adev->mode_info.coherent_mode_property, 1794 1); 1795 drm_object_attach_property(&amdgpu_connector->base.base, 1796 adev->mode_info.underscan_property, 1797 UNDERSCAN_OFF); 1798 drm_object_attach_property(&amdgpu_connector->base.base, 1799 adev->mode_info.underscan_hborder_property, 1800 0); 1801 drm_object_attach_property(&amdgpu_connector->base.base, 1802 adev->mode_info.underscan_vborder_property, 1803 0); 1804 drm_object_attach_property(&amdgpu_connector->base.base, 1805 dev->mode_config.scaling_mode_property, 1806 DRM_MODE_SCALE_NONE); 1807 if (amdgpu_audio != 0) { 1808 drm_object_attach_property(&amdgpu_connector->base.base, 1809 adev->mode_info.audio_property, 1810 AMDGPU_AUDIO_AUTO); 1811 } 1812 drm_object_attach_property(&amdgpu_connector->base.base, 1813 adev->mode_info.dither_property, 1814 AMDGPU_FMT_DITHER_DISABLE); 1815 connector->interlace_allowed = true; 1816 /* in theory with a DP to VGA converter... */ 1817 connector->doublescan_allowed = false; 1818 break; 1819 case DRM_MODE_CONNECTOR_eDP: 1820 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1821 if (!amdgpu_dig_connector) 1822 goto failed; 1823 amdgpu_connector->con_priv = amdgpu_dig_connector; 1824 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_edp_funcs, connector_type); 1825 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_dp_helper_funcs); 1826 if (i2c_bus->valid) { 1827 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1828 if (amdgpu_connector->ddc_bus) 1829 has_aux = true; 1830 else 1831 DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1832 } 1833 drm_object_attach_property(&amdgpu_connector->base.base, 1834 dev->mode_config.scaling_mode_property, 1835 DRM_MODE_SCALE_FULLSCREEN); 1836 subpixel_order = SubPixelHorizontalRGB; 1837 connector->interlace_allowed = false; 1838 connector->doublescan_allowed = false; 1839 break; 1840 case DRM_MODE_CONNECTOR_LVDS: 1841 amdgpu_dig_connector = kzalloc(sizeof(struct amdgpu_connector_atom_dig), GFP_KERNEL); 1842 if (!amdgpu_dig_connector) 1843 goto failed; 1844 amdgpu_connector->con_priv = amdgpu_dig_connector; 1845 drm_connector_init(dev, &amdgpu_connector->base, &amdgpu_connector_lvds_funcs, connector_type); 1846 drm_connector_helper_add(&amdgpu_connector->base, &amdgpu_connector_lvds_helper_funcs); 1847 if (i2c_bus->valid) { 1848 amdgpu_connector->ddc_bus = amdgpu_i2c_lookup(adev, i2c_bus); 1849 if (!amdgpu_connector->ddc_bus) 1850 DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n"); 1851 } 1852 drm_object_attach_property(&amdgpu_connector->base.base, 1853 dev->mode_config.scaling_mode_property, 1854 DRM_MODE_SCALE_FULLSCREEN); 1855 subpixel_order = SubPixelHorizontalRGB; 1856 connector->interlace_allowed = false; 1857 connector->doublescan_allowed = false; 1858 break; 1859 } 1860 } 1861 1862 if (amdgpu_connector->hpd.hpd == AMDGPU_HPD_NONE) { 1863 if (i2c_bus->valid) { 1864 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1865 DRM_CONNECTOR_POLL_DISCONNECT; 1866 } 1867 } else 1868 connector->polled = DRM_CONNECTOR_POLL_HPD; 1869 1870 connector->display_info.subpixel_order = subpixel_order; 1871 drm_connector_register(connector); 1872 1873 if (has_aux) 1874 amdgpu_atombios_dp_aux_init(amdgpu_connector); 1875 1876 return; 1877 1878 failed: 1879 drm_connector_cleanup(connector); 1880 kfree(connector); 1881 } 1882