1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Stanislaw Skowronek 23 */ 24 25 #include <linux/module.h> 26 #include <linux/sched.h> 27 #include <linux/slab.h> 28 #include <asm/unaligned.h> 29 30 #include <drm/drm_util.h> 31 32 #define ATOM_DEBUG 33 34 #include "atomfirmware.h" 35 #include "atom.h" 36 #include "atom-names.h" 37 #include "atom-bits.h" 38 #include "amdgpu.h" 39 40 #define ATOM_COND_ABOVE 0 41 #define ATOM_COND_ABOVEOREQUAL 1 42 #define ATOM_COND_ALWAYS 2 43 #define ATOM_COND_BELOW 3 44 #define ATOM_COND_BELOWOREQUAL 4 45 #define ATOM_COND_EQUAL 5 46 #define ATOM_COND_NOTEQUAL 6 47 48 #define ATOM_PORT_ATI 0 49 #define ATOM_PORT_PCI 1 50 #define ATOM_PORT_SYSIO 2 51 52 #define ATOM_UNIT_MICROSEC 0 53 #define ATOM_UNIT_MILLISEC 1 54 55 #define PLL_INDEX 2 56 #define PLL_DATA 3 57 58 #define ATOM_CMD_TIMEOUT_SEC 20 59 60 typedef struct { 61 struct atom_context *ctx; 62 uint32_t *ps, *ws; 63 int ps_shift; 64 uint16_t start; 65 unsigned last_jump; 66 unsigned long last_jump_jiffies; 67 bool abort; 68 } atom_exec_context; 69 70 int amdgpu_atom_debug; 71 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params); 72 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params); 73 74 static uint32_t atom_arg_mask[8] = 75 { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, 76 0xFF000000 }; 77 static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; 78 79 static int atom_dst_to_src[8][4] = { 80 /* translate destination alignment field to the source alignment encoding */ 81 {0, 0, 0, 0}, 82 {1, 2, 3, 0}, 83 {1, 2, 3, 0}, 84 {1, 2, 3, 0}, 85 {4, 5, 6, 7}, 86 {4, 5, 6, 7}, 87 {4, 5, 6, 7}, 88 {4, 5, 6, 7}, 89 }; 90 static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 }; 91 92 static int debug_depth; 93 #ifdef ATOM_DEBUG 94 static void debug_print_spaces(int n) 95 { 96 while (n--) 97 printk(" "); 98 } 99 100 #ifdef DEBUG 101 #undef DEBUG 102 #endif 103 104 #define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0) 105 #define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0) 106 #else 107 #define DEBUG(...) do { } while (0) 108 #define SDEBUG(...) do { } while (0) 109 #endif 110 111 static uint32_t atom_iio_execute(struct atom_context *ctx, int base, 112 uint32_t index, uint32_t data) 113 { 114 uint32_t temp = 0xCDCDCDCD; 115 116 while (1) 117 switch (CU8(base)) { 118 case ATOM_IIO_NOP: 119 base++; 120 break; 121 case ATOM_IIO_READ: 122 temp = ctx->card->reg_read(ctx->card, CU16(base + 1)); 123 base += 3; 124 break; 125 case ATOM_IIO_WRITE: 126 ctx->card->reg_write(ctx->card, CU16(base + 1), temp); 127 base += 3; 128 break; 129 case ATOM_IIO_CLEAR: 130 temp &= 131 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 132 CU8(base + 2)); 133 base += 3; 134 break; 135 case ATOM_IIO_SET: 136 temp |= 137 (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 138 2); 139 base += 3; 140 break; 141 case ATOM_IIO_MOVE_INDEX: 142 temp &= 143 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 144 CU8(base + 3)); 145 temp |= 146 ((index >> CU8(base + 2)) & 147 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 148 3); 149 base += 4; 150 break; 151 case ATOM_IIO_MOVE_DATA: 152 temp &= 153 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 154 CU8(base + 3)); 155 temp |= 156 ((data >> CU8(base + 2)) & 157 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 158 3); 159 base += 4; 160 break; 161 case ATOM_IIO_MOVE_ATTR: 162 temp &= 163 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 164 CU8(base + 3)); 165 temp |= 166 ((ctx-> 167 io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - 168 CU8 169 (base 170 + 171 1)))) 172 << CU8(base + 3); 173 base += 4; 174 break; 175 case ATOM_IIO_END: 176 return temp; 177 default: 178 pr_info("Unknown IIO opcode\n"); 179 return 0; 180 } 181 } 182 183 static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, 184 int *ptr, uint32_t *saved, int print) 185 { 186 uint32_t idx, val = 0xCDCDCDCD, align, arg; 187 struct atom_context *gctx = ctx->ctx; 188 arg = attr & 7; 189 align = (attr >> 3) & 7; 190 switch (arg) { 191 case ATOM_ARG_REG: 192 idx = U16(*ptr); 193 (*ptr) += 2; 194 if (print) 195 DEBUG("REG[0x%04X]", idx); 196 idx += gctx->reg_block; 197 switch (gctx->io_mode) { 198 case ATOM_IO_MM: 199 val = gctx->card->reg_read(gctx->card, idx); 200 break; 201 case ATOM_IO_PCI: 202 pr_info("PCI registers are not implemented\n"); 203 return 0; 204 case ATOM_IO_SYSIO: 205 pr_info("SYSIO registers are not implemented\n"); 206 return 0; 207 default: 208 if (!(gctx->io_mode & 0x80)) { 209 pr_info("Bad IO mode\n"); 210 return 0; 211 } 212 if (!gctx->iio[gctx->io_mode & 0x7F]) { 213 pr_info("Undefined indirect IO read method %d\n", 214 gctx->io_mode & 0x7F); 215 return 0; 216 } 217 val = 218 atom_iio_execute(gctx, 219 gctx->iio[gctx->io_mode & 0x7F], 220 idx, 0); 221 } 222 break; 223 case ATOM_ARG_PS: 224 idx = U8(*ptr); 225 (*ptr)++; 226 /* get_unaligned_le32 avoids unaligned accesses from atombios 227 * tables, noticed on a DEC Alpha. */ 228 val = get_unaligned_le32((u32 *)&ctx->ps[idx]); 229 if (print) 230 DEBUG("PS[0x%02X,0x%04X]", idx, val); 231 break; 232 case ATOM_ARG_WS: 233 idx = U8(*ptr); 234 (*ptr)++; 235 if (print) 236 DEBUG("WS[0x%02X]", idx); 237 switch (idx) { 238 case ATOM_WS_QUOTIENT: 239 val = gctx->divmul[0]; 240 break; 241 case ATOM_WS_REMAINDER: 242 val = gctx->divmul[1]; 243 break; 244 case ATOM_WS_DATAPTR: 245 val = gctx->data_block; 246 break; 247 case ATOM_WS_SHIFT: 248 val = gctx->shift; 249 break; 250 case ATOM_WS_OR_MASK: 251 val = 1 << gctx->shift; 252 break; 253 case ATOM_WS_AND_MASK: 254 val = ~(1 << gctx->shift); 255 break; 256 case ATOM_WS_FB_WINDOW: 257 val = gctx->fb_base; 258 break; 259 case ATOM_WS_ATTRIBUTES: 260 val = gctx->io_attr; 261 break; 262 case ATOM_WS_REGPTR: 263 val = gctx->reg_block; 264 break; 265 default: 266 val = ctx->ws[idx]; 267 } 268 break; 269 case ATOM_ARG_ID: 270 idx = U16(*ptr); 271 (*ptr) += 2; 272 if (print) { 273 if (gctx->data_block) 274 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block); 275 else 276 DEBUG("ID[0x%04X]", idx); 277 } 278 val = U32(idx + gctx->data_block); 279 break; 280 case ATOM_ARG_FB: 281 idx = U8(*ptr); 282 (*ptr)++; 283 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 284 DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n", 285 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 286 val = 0; 287 } else 288 val = gctx->scratch[(gctx->fb_base / 4) + idx]; 289 if (print) 290 DEBUG("FB[0x%02X]", idx); 291 break; 292 case ATOM_ARG_IMM: 293 switch (align) { 294 case ATOM_SRC_DWORD: 295 val = U32(*ptr); 296 (*ptr) += 4; 297 if (print) 298 DEBUG("IMM 0x%08X\n", val); 299 return val; 300 case ATOM_SRC_WORD0: 301 case ATOM_SRC_WORD8: 302 case ATOM_SRC_WORD16: 303 val = U16(*ptr); 304 (*ptr) += 2; 305 if (print) 306 DEBUG("IMM 0x%04X\n", val); 307 return val; 308 case ATOM_SRC_BYTE0: 309 case ATOM_SRC_BYTE8: 310 case ATOM_SRC_BYTE16: 311 case ATOM_SRC_BYTE24: 312 val = U8(*ptr); 313 (*ptr)++; 314 if (print) 315 DEBUG("IMM 0x%02X\n", val); 316 return val; 317 } 318 return 0; 319 case ATOM_ARG_PLL: 320 idx = U8(*ptr); 321 (*ptr)++; 322 if (print) 323 DEBUG("PLL[0x%02X]", idx); 324 val = gctx->card->pll_read(gctx->card, idx); 325 break; 326 case ATOM_ARG_MC: 327 idx = U8(*ptr); 328 (*ptr)++; 329 if (print) 330 DEBUG("MC[0x%02X]", idx); 331 val = gctx->card->mc_read(gctx->card, idx); 332 break; 333 } 334 if (saved) 335 *saved = val; 336 val &= atom_arg_mask[align]; 337 val >>= atom_arg_shift[align]; 338 if (print) 339 switch (align) { 340 case ATOM_SRC_DWORD: 341 DEBUG(".[31:0] -> 0x%08X\n", val); 342 break; 343 case ATOM_SRC_WORD0: 344 DEBUG(".[15:0] -> 0x%04X\n", val); 345 break; 346 case ATOM_SRC_WORD8: 347 DEBUG(".[23:8] -> 0x%04X\n", val); 348 break; 349 case ATOM_SRC_WORD16: 350 DEBUG(".[31:16] -> 0x%04X\n", val); 351 break; 352 case ATOM_SRC_BYTE0: 353 DEBUG(".[7:0] -> 0x%02X\n", val); 354 break; 355 case ATOM_SRC_BYTE8: 356 DEBUG(".[15:8] -> 0x%02X\n", val); 357 break; 358 case ATOM_SRC_BYTE16: 359 DEBUG(".[23:16] -> 0x%02X\n", val); 360 break; 361 case ATOM_SRC_BYTE24: 362 DEBUG(".[31:24] -> 0x%02X\n", val); 363 break; 364 } 365 return val; 366 } 367 368 static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr) 369 { 370 uint32_t align = (attr >> 3) & 7, arg = attr & 7; 371 switch (arg) { 372 case ATOM_ARG_REG: 373 case ATOM_ARG_ID: 374 (*ptr) += 2; 375 break; 376 case ATOM_ARG_PLL: 377 case ATOM_ARG_MC: 378 case ATOM_ARG_PS: 379 case ATOM_ARG_WS: 380 case ATOM_ARG_FB: 381 (*ptr)++; 382 break; 383 case ATOM_ARG_IMM: 384 switch (align) { 385 case ATOM_SRC_DWORD: 386 (*ptr) += 4; 387 return; 388 case ATOM_SRC_WORD0: 389 case ATOM_SRC_WORD8: 390 case ATOM_SRC_WORD16: 391 (*ptr) += 2; 392 return; 393 case ATOM_SRC_BYTE0: 394 case ATOM_SRC_BYTE8: 395 case ATOM_SRC_BYTE16: 396 case ATOM_SRC_BYTE24: 397 (*ptr)++; 398 return; 399 } 400 return; 401 } 402 } 403 404 static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr) 405 { 406 return atom_get_src_int(ctx, attr, ptr, NULL, 1); 407 } 408 409 static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr) 410 { 411 uint32_t val = 0xCDCDCDCD; 412 413 switch (align) { 414 case ATOM_SRC_DWORD: 415 val = U32(*ptr); 416 (*ptr) += 4; 417 break; 418 case ATOM_SRC_WORD0: 419 case ATOM_SRC_WORD8: 420 case ATOM_SRC_WORD16: 421 val = U16(*ptr); 422 (*ptr) += 2; 423 break; 424 case ATOM_SRC_BYTE0: 425 case ATOM_SRC_BYTE8: 426 case ATOM_SRC_BYTE16: 427 case ATOM_SRC_BYTE24: 428 val = U8(*ptr); 429 (*ptr)++; 430 break; 431 } 432 return val; 433 } 434 435 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, 436 int *ptr, uint32_t *saved, int print) 437 { 438 return atom_get_src_int(ctx, 439 arg | atom_dst_to_src[(attr >> 3) & 440 7][(attr >> 6) & 3] << 3, 441 ptr, saved, print); 442 } 443 444 static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr) 445 { 446 atom_skip_src_int(ctx, 447 arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 448 3] << 3, ptr); 449 } 450 451 static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, 452 int *ptr, uint32_t val, uint32_t saved) 453 { 454 uint32_t align = 455 atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val = 456 val, idx; 457 struct atom_context *gctx = ctx->ctx; 458 old_val &= atom_arg_mask[align] >> atom_arg_shift[align]; 459 val <<= atom_arg_shift[align]; 460 val &= atom_arg_mask[align]; 461 saved &= ~atom_arg_mask[align]; 462 val |= saved; 463 switch (arg) { 464 case ATOM_ARG_REG: 465 idx = U16(*ptr); 466 (*ptr) += 2; 467 DEBUG("REG[0x%04X]", idx); 468 idx += gctx->reg_block; 469 switch (gctx->io_mode) { 470 case ATOM_IO_MM: 471 if (idx == 0) 472 gctx->card->reg_write(gctx->card, idx, 473 val << 2); 474 else 475 gctx->card->reg_write(gctx->card, idx, val); 476 break; 477 case ATOM_IO_PCI: 478 pr_info("PCI registers are not implemented\n"); 479 return; 480 case ATOM_IO_SYSIO: 481 pr_info("SYSIO registers are not implemented\n"); 482 return; 483 default: 484 if (!(gctx->io_mode & 0x80)) { 485 pr_info("Bad IO mode\n"); 486 return; 487 } 488 if (!gctx->iio[gctx->io_mode & 0xFF]) { 489 pr_info("Undefined indirect IO write method %d\n", 490 gctx->io_mode & 0x7F); 491 return; 492 } 493 atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], 494 idx, val); 495 } 496 break; 497 case ATOM_ARG_PS: 498 idx = U8(*ptr); 499 (*ptr)++; 500 DEBUG("PS[0x%02X]", idx); 501 ctx->ps[idx] = cpu_to_le32(val); 502 break; 503 case ATOM_ARG_WS: 504 idx = U8(*ptr); 505 (*ptr)++; 506 DEBUG("WS[0x%02X]", idx); 507 switch (idx) { 508 case ATOM_WS_QUOTIENT: 509 gctx->divmul[0] = val; 510 break; 511 case ATOM_WS_REMAINDER: 512 gctx->divmul[1] = val; 513 break; 514 case ATOM_WS_DATAPTR: 515 gctx->data_block = val; 516 break; 517 case ATOM_WS_SHIFT: 518 gctx->shift = val; 519 break; 520 case ATOM_WS_OR_MASK: 521 case ATOM_WS_AND_MASK: 522 break; 523 case ATOM_WS_FB_WINDOW: 524 gctx->fb_base = val; 525 break; 526 case ATOM_WS_ATTRIBUTES: 527 gctx->io_attr = val; 528 break; 529 case ATOM_WS_REGPTR: 530 gctx->reg_block = val; 531 break; 532 default: 533 ctx->ws[idx] = val; 534 } 535 break; 536 case ATOM_ARG_FB: 537 idx = U8(*ptr); 538 (*ptr)++; 539 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 540 DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n", 541 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 542 } else 543 gctx->scratch[(gctx->fb_base / 4) + idx] = val; 544 DEBUG("FB[0x%02X]", idx); 545 break; 546 case ATOM_ARG_PLL: 547 idx = U8(*ptr); 548 (*ptr)++; 549 DEBUG("PLL[0x%02X]", idx); 550 gctx->card->pll_write(gctx->card, idx, val); 551 break; 552 case ATOM_ARG_MC: 553 idx = U8(*ptr); 554 (*ptr)++; 555 DEBUG("MC[0x%02X]", idx); 556 gctx->card->mc_write(gctx->card, idx, val); 557 return; 558 } 559 switch (align) { 560 case ATOM_SRC_DWORD: 561 DEBUG(".[31:0] <- 0x%08X\n", old_val); 562 break; 563 case ATOM_SRC_WORD0: 564 DEBUG(".[15:0] <- 0x%04X\n", old_val); 565 break; 566 case ATOM_SRC_WORD8: 567 DEBUG(".[23:8] <- 0x%04X\n", old_val); 568 break; 569 case ATOM_SRC_WORD16: 570 DEBUG(".[31:16] <- 0x%04X\n", old_val); 571 break; 572 case ATOM_SRC_BYTE0: 573 DEBUG(".[7:0] <- 0x%02X\n", old_val); 574 break; 575 case ATOM_SRC_BYTE8: 576 DEBUG(".[15:8] <- 0x%02X\n", old_val); 577 break; 578 case ATOM_SRC_BYTE16: 579 DEBUG(".[23:16] <- 0x%02X\n", old_val); 580 break; 581 case ATOM_SRC_BYTE24: 582 DEBUG(".[31:24] <- 0x%02X\n", old_val); 583 break; 584 } 585 } 586 587 static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg) 588 { 589 uint8_t attr = U8((*ptr)++); 590 uint32_t dst, src, saved; 591 int dptr = *ptr; 592 SDEBUG(" dst: "); 593 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 594 SDEBUG(" src: "); 595 src = atom_get_src(ctx, attr, ptr); 596 dst += src; 597 SDEBUG(" dst: "); 598 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 599 } 600 601 static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg) 602 { 603 uint8_t attr = U8((*ptr)++); 604 uint32_t dst, src, saved; 605 int dptr = *ptr; 606 SDEBUG(" dst: "); 607 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 608 SDEBUG(" src: "); 609 src = atom_get_src(ctx, attr, ptr); 610 dst &= src; 611 SDEBUG(" dst: "); 612 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 613 } 614 615 static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg) 616 { 617 printk("ATOM BIOS beeped!\n"); 618 } 619 620 static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg) 621 { 622 int idx = U8((*ptr)++); 623 int r = 0; 624 625 if (idx < ATOM_TABLE_NAMES_CNT) 626 SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]); 627 else 628 SDEBUG(" table: %d\n", idx); 629 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) 630 r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); 631 if (r) { 632 ctx->abort = true; 633 } 634 } 635 636 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) 637 { 638 uint8_t attr = U8((*ptr)++); 639 uint32_t saved; 640 int dptr = *ptr; 641 attr &= 0x38; 642 attr |= atom_def_dst[attr >> 3] << 6; 643 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 644 SDEBUG(" dst: "); 645 atom_put_dst(ctx, arg, attr, &dptr, 0, saved); 646 } 647 648 static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg) 649 { 650 uint8_t attr = U8((*ptr)++); 651 uint32_t dst, src; 652 SDEBUG(" src1: "); 653 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 654 SDEBUG(" src2: "); 655 src = atom_get_src(ctx, attr, ptr); 656 ctx->ctx->cs_equal = (dst == src); 657 ctx->ctx->cs_above = (dst > src); 658 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE", 659 ctx->ctx->cs_above ? "GT" : "LE"); 660 } 661 662 static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) 663 { 664 unsigned count = U8((*ptr)++); 665 SDEBUG(" count: %d\n", count); 666 if (arg == ATOM_UNIT_MICROSEC) 667 udelay(count); 668 else if (!drm_can_sleep()) 669 mdelay(count); 670 else 671 drm_msleep(count); 672 } 673 674 static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg) 675 { 676 uint8_t attr = U8((*ptr)++); 677 uint32_t dst, src; 678 SDEBUG(" src1: "); 679 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 680 SDEBUG(" src2: "); 681 src = atom_get_src(ctx, attr, ptr); 682 if (src != 0) { 683 ctx->ctx->divmul[0] = dst / src; 684 ctx->ctx->divmul[1] = dst % src; 685 } else { 686 ctx->ctx->divmul[0] = 0; 687 ctx->ctx->divmul[1] = 0; 688 } 689 } 690 691 static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg) 692 { 693 uint64_t val64; 694 uint8_t attr = U8((*ptr)++); 695 uint32_t dst, src; 696 SDEBUG(" src1: "); 697 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 698 SDEBUG(" src2: "); 699 src = atom_get_src(ctx, attr, ptr); 700 if (src != 0) { 701 val64 = dst; 702 val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32; 703 do_div(val64, src); 704 ctx->ctx->divmul[0] = lower_32_bits(val64); 705 ctx->ctx->divmul[1] = upper_32_bits(val64); 706 } else { 707 ctx->ctx->divmul[0] = 0; 708 ctx->ctx->divmul[1] = 0; 709 } 710 } 711 712 static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg) 713 { 714 /* functionally, a nop */ 715 } 716 717 static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) 718 { 719 int execute = 0, target = U16(*ptr); 720 unsigned long cjiffies; 721 722 (*ptr) += 2; 723 switch (arg) { 724 case ATOM_COND_ABOVE: 725 execute = ctx->ctx->cs_above; 726 break; 727 case ATOM_COND_ABOVEOREQUAL: 728 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal; 729 break; 730 case ATOM_COND_ALWAYS: 731 execute = 1; 732 break; 733 case ATOM_COND_BELOW: 734 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal); 735 break; 736 case ATOM_COND_BELOWOREQUAL: 737 execute = !ctx->ctx->cs_above; 738 break; 739 case ATOM_COND_EQUAL: 740 execute = ctx->ctx->cs_equal; 741 break; 742 case ATOM_COND_NOTEQUAL: 743 execute = !ctx->ctx->cs_equal; 744 break; 745 } 746 if (arg != ATOM_COND_ALWAYS) 747 SDEBUG(" taken: %s\n", execute ? "yes" : "no"); 748 SDEBUG(" target: 0x%04X\n", target); 749 if (execute) { 750 if (ctx->last_jump == (ctx->start + target)) { 751 cjiffies = jiffies; 752 if (time_after(cjiffies, ctx->last_jump_jiffies)) { 753 cjiffies -= ctx->last_jump_jiffies; 754 if ((jiffies_to_msecs(cjiffies) > ATOM_CMD_TIMEOUT_SEC*1000)) { 755 DRM_ERROR("atombios stuck in loop for more than %dsecs aborting\n", 756 ATOM_CMD_TIMEOUT_SEC); 757 ctx->abort = true; 758 } 759 } else { 760 /* jiffies wrap around we will just wait a little longer */ 761 ctx->last_jump_jiffies = jiffies; 762 } 763 } else { 764 ctx->last_jump = ctx->start + target; 765 ctx->last_jump_jiffies = jiffies; 766 } 767 *ptr = ctx->start + target; 768 } 769 } 770 771 static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg) 772 { 773 uint8_t attr = U8((*ptr)++); 774 uint32_t dst, mask, src, saved; 775 int dptr = *ptr; 776 SDEBUG(" dst: "); 777 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 778 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr); 779 SDEBUG(" mask: 0x%08x", mask); 780 SDEBUG(" src: "); 781 src = atom_get_src(ctx, attr, ptr); 782 dst &= mask; 783 dst |= src; 784 SDEBUG(" dst: "); 785 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 786 } 787 788 static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg) 789 { 790 uint8_t attr = U8((*ptr)++); 791 uint32_t src, saved; 792 int dptr = *ptr; 793 if (((attr >> 3) & 7) != ATOM_SRC_DWORD) 794 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 795 else { 796 atom_skip_dst(ctx, arg, attr, ptr); 797 saved = 0xCDCDCDCD; 798 } 799 SDEBUG(" src: "); 800 src = atom_get_src(ctx, attr, ptr); 801 SDEBUG(" dst: "); 802 atom_put_dst(ctx, arg, attr, &dptr, src, saved); 803 } 804 805 static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg) 806 { 807 uint8_t attr = U8((*ptr)++); 808 uint32_t dst, src; 809 SDEBUG(" src1: "); 810 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 811 SDEBUG(" src2: "); 812 src = atom_get_src(ctx, attr, ptr); 813 ctx->ctx->divmul[0] = dst * src; 814 } 815 816 static void atom_op_mul32(atom_exec_context *ctx, int *ptr, int arg) 817 { 818 uint64_t val64; 819 uint8_t attr = U8((*ptr)++); 820 uint32_t dst, src; 821 SDEBUG(" src1: "); 822 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 823 SDEBUG(" src2: "); 824 src = atom_get_src(ctx, attr, ptr); 825 val64 = (uint64_t)dst * (uint64_t)src; 826 ctx->ctx->divmul[0] = lower_32_bits(val64); 827 ctx->ctx->divmul[1] = upper_32_bits(val64); 828 } 829 830 static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg) 831 { 832 /* nothing */ 833 } 834 835 static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg) 836 { 837 uint8_t attr = U8((*ptr)++); 838 uint32_t dst, src, saved; 839 int dptr = *ptr; 840 SDEBUG(" dst: "); 841 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 842 SDEBUG(" src: "); 843 src = atom_get_src(ctx, attr, ptr); 844 dst |= src; 845 SDEBUG(" dst: "); 846 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 847 } 848 849 static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg) 850 { 851 uint8_t val = U8((*ptr)++); 852 SDEBUG("POST card output: 0x%02X\n", val); 853 } 854 855 static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg) 856 { 857 pr_info("unimplemented!\n"); 858 } 859 860 static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg) 861 { 862 pr_info("unimplemented!\n"); 863 } 864 865 static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg) 866 { 867 pr_info("unimplemented!\n"); 868 } 869 870 static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg) 871 { 872 int idx = U8(*ptr); 873 (*ptr)++; 874 SDEBUG(" block: %d\n", idx); 875 if (!idx) 876 ctx->ctx->data_block = 0; 877 else if (idx == 255) 878 ctx->ctx->data_block = ctx->start; 879 else 880 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx); 881 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block); 882 } 883 884 static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg) 885 { 886 uint8_t attr = U8((*ptr)++); 887 SDEBUG(" fb_base: "); 888 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr); 889 } 890 891 static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg) 892 { 893 int port; 894 switch (arg) { 895 case ATOM_PORT_ATI: 896 port = U16(*ptr); 897 if (port < ATOM_IO_NAMES_CNT) 898 SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]); 899 else 900 SDEBUG(" port: %d\n", port); 901 if (!port) 902 ctx->ctx->io_mode = ATOM_IO_MM; 903 else 904 ctx->ctx->io_mode = ATOM_IO_IIO | port; 905 (*ptr) += 2; 906 break; 907 case ATOM_PORT_PCI: 908 ctx->ctx->io_mode = ATOM_IO_PCI; 909 (*ptr)++; 910 break; 911 case ATOM_PORT_SYSIO: 912 ctx->ctx->io_mode = ATOM_IO_SYSIO; 913 (*ptr)++; 914 break; 915 } 916 } 917 918 static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg) 919 { 920 ctx->ctx->reg_block = U16(*ptr); 921 (*ptr) += 2; 922 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); 923 } 924 925 static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg) 926 { 927 uint8_t attr = U8((*ptr)++), shift; 928 uint32_t saved, dst; 929 int dptr = *ptr; 930 attr &= 0x38; 931 attr |= atom_def_dst[attr >> 3] << 6; 932 SDEBUG(" dst: "); 933 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 934 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 935 SDEBUG(" shift: %d\n", shift); 936 dst <<= shift; 937 SDEBUG(" dst: "); 938 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 939 } 940 941 static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg) 942 { 943 uint8_t attr = U8((*ptr)++), shift; 944 uint32_t saved, dst; 945 int dptr = *ptr; 946 attr &= 0x38; 947 attr |= atom_def_dst[attr >> 3] << 6; 948 SDEBUG(" dst: "); 949 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 950 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 951 SDEBUG(" shift: %d\n", shift); 952 dst >>= shift; 953 SDEBUG(" dst: "); 954 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 955 } 956 957 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) 958 { 959 uint8_t attr = U8((*ptr)++), shift; 960 uint32_t saved, dst; 961 int dptr = *ptr; 962 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 963 SDEBUG(" dst: "); 964 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 965 /* op needs to full dst value */ 966 dst = saved; 967 shift = atom_get_src(ctx, attr, ptr); 968 SDEBUG(" shift: %d\n", shift); 969 dst <<= shift; 970 dst &= atom_arg_mask[dst_align]; 971 dst >>= atom_arg_shift[dst_align]; 972 SDEBUG(" dst: "); 973 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 974 } 975 976 static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg) 977 { 978 uint8_t attr = U8((*ptr)++), shift; 979 uint32_t saved, dst; 980 int dptr = *ptr; 981 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 982 SDEBUG(" dst: "); 983 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 984 /* op needs to full dst value */ 985 dst = saved; 986 shift = atom_get_src(ctx, attr, ptr); 987 SDEBUG(" shift: %d\n", shift); 988 dst >>= shift; 989 dst &= atom_arg_mask[dst_align]; 990 dst >>= atom_arg_shift[dst_align]; 991 SDEBUG(" dst: "); 992 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 993 } 994 995 static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg) 996 { 997 uint8_t attr = U8((*ptr)++); 998 uint32_t dst, src, saved; 999 int dptr = *ptr; 1000 SDEBUG(" dst: "); 1001 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 1002 SDEBUG(" src: "); 1003 src = atom_get_src(ctx, attr, ptr); 1004 dst -= src; 1005 SDEBUG(" dst: "); 1006 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 1007 } 1008 1009 static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg) 1010 { 1011 uint8_t attr = U8((*ptr)++); 1012 uint32_t src, val, target; 1013 SDEBUG(" switch: "); 1014 src = atom_get_src(ctx, attr, ptr); 1015 while (U16(*ptr) != ATOM_CASE_END) 1016 if (U8(*ptr) == ATOM_CASE_MAGIC) { 1017 (*ptr)++; 1018 SDEBUG(" case: "); 1019 val = 1020 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM, 1021 ptr); 1022 target = U16(*ptr); 1023 if (val == src) { 1024 SDEBUG(" target: %04X\n", target); 1025 *ptr = ctx->start + target; 1026 return; 1027 } 1028 (*ptr) += 2; 1029 } else { 1030 pr_info("Bad case\n"); 1031 return; 1032 } 1033 (*ptr) += 2; 1034 } 1035 1036 static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg) 1037 { 1038 uint8_t attr = U8((*ptr)++); 1039 uint32_t dst, src; 1040 SDEBUG(" src1: "); 1041 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 1042 SDEBUG(" src2: "); 1043 src = atom_get_src(ctx, attr, ptr); 1044 ctx->ctx->cs_equal = ((dst & src) == 0); 1045 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE"); 1046 } 1047 1048 static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg) 1049 { 1050 uint8_t attr = U8((*ptr)++); 1051 uint32_t dst, src, saved; 1052 int dptr = *ptr; 1053 SDEBUG(" dst: "); 1054 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 1055 SDEBUG(" src: "); 1056 src = atom_get_src(ctx, attr, ptr); 1057 dst ^= src; 1058 SDEBUG(" dst: "); 1059 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 1060 } 1061 1062 static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg) 1063 { 1064 uint8_t val = U8((*ptr)++); 1065 SDEBUG("DEBUG output: 0x%02X\n", val); 1066 } 1067 1068 static void atom_op_processds(atom_exec_context *ctx, int *ptr, int arg) 1069 { 1070 uint16_t val = U16(*ptr); 1071 (*ptr) += val + 2; 1072 SDEBUG("PROCESSDS output: 0x%02X\n", val); 1073 } 1074 1075 static struct { 1076 void (*func) (atom_exec_context *, int *, int); 1077 int arg; 1078 } opcode_table[ATOM_OP_CNT] = { 1079 { 1080 NULL, 0}, { 1081 atom_op_move, ATOM_ARG_REG}, { 1082 atom_op_move, ATOM_ARG_PS}, { 1083 atom_op_move, ATOM_ARG_WS}, { 1084 atom_op_move, ATOM_ARG_FB}, { 1085 atom_op_move, ATOM_ARG_PLL}, { 1086 atom_op_move, ATOM_ARG_MC}, { 1087 atom_op_and, ATOM_ARG_REG}, { 1088 atom_op_and, ATOM_ARG_PS}, { 1089 atom_op_and, ATOM_ARG_WS}, { 1090 atom_op_and, ATOM_ARG_FB}, { 1091 atom_op_and, ATOM_ARG_PLL}, { 1092 atom_op_and, ATOM_ARG_MC}, { 1093 atom_op_or, ATOM_ARG_REG}, { 1094 atom_op_or, ATOM_ARG_PS}, { 1095 atom_op_or, ATOM_ARG_WS}, { 1096 atom_op_or, ATOM_ARG_FB}, { 1097 atom_op_or, ATOM_ARG_PLL}, { 1098 atom_op_or, ATOM_ARG_MC}, { 1099 atom_op_shift_left, ATOM_ARG_REG}, { 1100 atom_op_shift_left, ATOM_ARG_PS}, { 1101 atom_op_shift_left, ATOM_ARG_WS}, { 1102 atom_op_shift_left, ATOM_ARG_FB}, { 1103 atom_op_shift_left, ATOM_ARG_PLL}, { 1104 atom_op_shift_left, ATOM_ARG_MC}, { 1105 atom_op_shift_right, ATOM_ARG_REG}, { 1106 atom_op_shift_right, ATOM_ARG_PS}, { 1107 atom_op_shift_right, ATOM_ARG_WS}, { 1108 atom_op_shift_right, ATOM_ARG_FB}, { 1109 atom_op_shift_right, ATOM_ARG_PLL}, { 1110 atom_op_shift_right, ATOM_ARG_MC}, { 1111 atom_op_mul, ATOM_ARG_REG}, { 1112 atom_op_mul, ATOM_ARG_PS}, { 1113 atom_op_mul, ATOM_ARG_WS}, { 1114 atom_op_mul, ATOM_ARG_FB}, { 1115 atom_op_mul, ATOM_ARG_PLL}, { 1116 atom_op_mul, ATOM_ARG_MC}, { 1117 atom_op_div, ATOM_ARG_REG}, { 1118 atom_op_div, ATOM_ARG_PS}, { 1119 atom_op_div, ATOM_ARG_WS}, { 1120 atom_op_div, ATOM_ARG_FB}, { 1121 atom_op_div, ATOM_ARG_PLL}, { 1122 atom_op_div, ATOM_ARG_MC}, { 1123 atom_op_add, ATOM_ARG_REG}, { 1124 atom_op_add, ATOM_ARG_PS}, { 1125 atom_op_add, ATOM_ARG_WS}, { 1126 atom_op_add, ATOM_ARG_FB}, { 1127 atom_op_add, ATOM_ARG_PLL}, { 1128 atom_op_add, ATOM_ARG_MC}, { 1129 atom_op_sub, ATOM_ARG_REG}, { 1130 atom_op_sub, ATOM_ARG_PS}, { 1131 atom_op_sub, ATOM_ARG_WS}, { 1132 atom_op_sub, ATOM_ARG_FB}, { 1133 atom_op_sub, ATOM_ARG_PLL}, { 1134 atom_op_sub, ATOM_ARG_MC}, { 1135 atom_op_setport, ATOM_PORT_ATI}, { 1136 atom_op_setport, ATOM_PORT_PCI}, { 1137 atom_op_setport, ATOM_PORT_SYSIO}, { 1138 atom_op_setregblock, 0}, { 1139 atom_op_setfbbase, 0}, { 1140 atom_op_compare, ATOM_ARG_REG}, { 1141 atom_op_compare, ATOM_ARG_PS}, { 1142 atom_op_compare, ATOM_ARG_WS}, { 1143 atom_op_compare, ATOM_ARG_FB}, { 1144 atom_op_compare, ATOM_ARG_PLL}, { 1145 atom_op_compare, ATOM_ARG_MC}, { 1146 atom_op_switch, 0}, { 1147 atom_op_jump, ATOM_COND_ALWAYS}, { 1148 atom_op_jump, ATOM_COND_EQUAL}, { 1149 atom_op_jump, ATOM_COND_BELOW}, { 1150 atom_op_jump, ATOM_COND_ABOVE}, { 1151 atom_op_jump, ATOM_COND_BELOWOREQUAL}, { 1152 atom_op_jump, ATOM_COND_ABOVEOREQUAL}, { 1153 atom_op_jump, ATOM_COND_NOTEQUAL}, { 1154 atom_op_test, ATOM_ARG_REG}, { 1155 atom_op_test, ATOM_ARG_PS}, { 1156 atom_op_test, ATOM_ARG_WS}, { 1157 atom_op_test, ATOM_ARG_FB}, { 1158 atom_op_test, ATOM_ARG_PLL}, { 1159 atom_op_test, ATOM_ARG_MC}, { 1160 atom_op_delay, ATOM_UNIT_MILLISEC}, { 1161 atom_op_delay, ATOM_UNIT_MICROSEC}, { 1162 atom_op_calltable, 0}, { 1163 atom_op_repeat, 0}, { 1164 atom_op_clear, ATOM_ARG_REG}, { 1165 atom_op_clear, ATOM_ARG_PS}, { 1166 atom_op_clear, ATOM_ARG_WS}, { 1167 atom_op_clear, ATOM_ARG_FB}, { 1168 atom_op_clear, ATOM_ARG_PLL}, { 1169 atom_op_clear, ATOM_ARG_MC}, { 1170 atom_op_nop, 0}, { 1171 atom_op_eot, 0}, { 1172 atom_op_mask, ATOM_ARG_REG}, { 1173 atom_op_mask, ATOM_ARG_PS}, { 1174 atom_op_mask, ATOM_ARG_WS}, { 1175 atom_op_mask, ATOM_ARG_FB}, { 1176 atom_op_mask, ATOM_ARG_PLL}, { 1177 atom_op_mask, ATOM_ARG_MC}, { 1178 atom_op_postcard, 0}, { 1179 atom_op_beep, 0}, { 1180 atom_op_savereg, 0}, { 1181 atom_op_restorereg, 0}, { 1182 atom_op_setdatablock, 0}, { 1183 atom_op_xor, ATOM_ARG_REG}, { 1184 atom_op_xor, ATOM_ARG_PS}, { 1185 atom_op_xor, ATOM_ARG_WS}, { 1186 atom_op_xor, ATOM_ARG_FB}, { 1187 atom_op_xor, ATOM_ARG_PLL}, { 1188 atom_op_xor, ATOM_ARG_MC}, { 1189 atom_op_shl, ATOM_ARG_REG}, { 1190 atom_op_shl, ATOM_ARG_PS}, { 1191 atom_op_shl, ATOM_ARG_WS}, { 1192 atom_op_shl, ATOM_ARG_FB}, { 1193 atom_op_shl, ATOM_ARG_PLL}, { 1194 atom_op_shl, ATOM_ARG_MC}, { 1195 atom_op_shr, ATOM_ARG_REG}, { 1196 atom_op_shr, ATOM_ARG_PS}, { 1197 atom_op_shr, ATOM_ARG_WS}, { 1198 atom_op_shr, ATOM_ARG_FB}, { 1199 atom_op_shr, ATOM_ARG_PLL}, { 1200 atom_op_shr, ATOM_ARG_MC}, { 1201 atom_op_debug, 0}, { 1202 atom_op_processds, 0}, { 1203 atom_op_mul32, ATOM_ARG_PS}, { 1204 atom_op_mul32, ATOM_ARG_WS}, { 1205 atom_op_div32, ATOM_ARG_PS}, { 1206 atom_op_div32, ATOM_ARG_WS}, 1207 }; 1208 1209 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params) 1210 { 1211 int base = CU16(ctx->cmd_table + 4 + 2 * index); 1212 int len, ws, ps, ptr; 1213 unsigned char op; 1214 atom_exec_context ectx; 1215 int ret = 0; 1216 1217 if (!base) 1218 return -EINVAL; 1219 1220 len = CU16(base + ATOM_CT_SIZE_PTR); 1221 ws = CU8(base + ATOM_CT_WS_PTR); 1222 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; 1223 ptr = base + ATOM_CT_CODE_PTR; 1224 1225 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); 1226 1227 ectx.ctx = ctx; 1228 ectx.ps_shift = ps / 4; 1229 ectx.start = base; 1230 ectx.ps = params; 1231 ectx.abort = false; 1232 ectx.last_jump = 0; 1233 if (ws) 1234 ectx.ws = kcalloc(4, ws, GFP_KERNEL); 1235 else 1236 ectx.ws = NULL; 1237 1238 debug_depth++; 1239 while (1) { 1240 op = CU8(ptr++); 1241 if (op < ATOM_OP_NAMES_CNT) 1242 SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1); 1243 else 1244 SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1); 1245 if (ectx.abort) { 1246 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n", 1247 base, len, ws, ps, ptr - 1); 1248 ret = -EINVAL; 1249 goto free; 1250 } 1251 1252 if (op < ATOM_OP_CNT && op > 0) 1253 opcode_table[op].func(&ectx, &ptr, 1254 opcode_table[op].arg); 1255 else 1256 break; 1257 1258 if (op == ATOM_OP_EOT) 1259 break; 1260 } 1261 debug_depth--; 1262 SDEBUG("<<\n"); 1263 1264 free: 1265 if (ws) 1266 kfree(ectx.ws); 1267 return ret; 1268 } 1269 1270 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params) 1271 { 1272 int r; 1273 1274 mutex_lock(&ctx->mutex); 1275 /* reset data block */ 1276 ctx->data_block = 0; 1277 /* reset reg block */ 1278 ctx->reg_block = 0; 1279 /* reset fb window */ 1280 ctx->fb_base = 0; 1281 /* reset io mode */ 1282 ctx->io_mode = ATOM_IO_MM; 1283 /* reset divmul */ 1284 ctx->divmul[0] = 0; 1285 ctx->divmul[1] = 0; 1286 r = amdgpu_atom_execute_table_locked(ctx, index, params); 1287 mutex_unlock(&ctx->mutex); 1288 return r; 1289 } 1290 1291 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 }; 1292 1293 static void atom_index_iio(struct atom_context *ctx, int base) 1294 { 1295 ctx->iio = kzalloc(2 * 256, GFP_KERNEL); 1296 if (!ctx->iio) 1297 return; 1298 while (CU8(base) == ATOM_IIO_START) { 1299 ctx->iio[CU8(base + 1)] = base + 2; 1300 base += 2; 1301 while (CU8(base) != ATOM_IIO_END) 1302 base += atom_iio_len[CU8(base)]; 1303 base += 3; 1304 } 1305 } 1306 1307 static void atom_get_vbios_name(struct atom_context *ctx) 1308 { 1309 unsigned char *p_rom; 1310 unsigned char str_num; 1311 unsigned short off_to_vbios_str; 1312 unsigned char *c_ptr; 1313 int name_size; 1314 int i; 1315 1316 const char *na = "--N/A--"; 1317 char *back; 1318 1319 p_rom = ctx->bios; 1320 1321 str_num = *(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS); 1322 if (str_num != 0) { 1323 off_to_vbios_str = 1324 *(unsigned short *)(p_rom + OFFSET_TO_GET_ATOMBIOS_STRING_START); 1325 1326 c_ptr = (unsigned char *)(p_rom + off_to_vbios_str); 1327 } else { 1328 /* do not know where to find name */ 1329 memcpy(ctx->name, na, 7); 1330 ctx->name[7] = 0; 1331 return; 1332 } 1333 1334 /* 1335 * skip the atombios strings, usually 4 1336 * 1st is P/N, 2nd is ASIC, 3rd is PCI type, 4th is Memory type 1337 */ 1338 for (i = 0; i < str_num; i++) { 1339 while (*c_ptr != 0) 1340 c_ptr++; 1341 c_ptr++; 1342 } 1343 1344 /* skip the following 2 chars: 0x0D 0x0A */ 1345 c_ptr += 2; 1346 1347 name_size = strnlen(c_ptr, STRLEN_LONG - 1); 1348 memcpy(ctx->name, c_ptr, name_size); 1349 back = ctx->name + name_size; 1350 while ((*--back) == ' ') 1351 ; 1352 *(back + 1) = '\0'; 1353 } 1354 1355 static void atom_get_vbios_date(struct atom_context *ctx) 1356 { 1357 unsigned char *p_rom; 1358 unsigned char *date_in_rom; 1359 1360 p_rom = ctx->bios; 1361 1362 date_in_rom = p_rom + OFFSET_TO_VBIOS_DATE; 1363 1364 ctx->date[0] = '2'; 1365 ctx->date[1] = '0'; 1366 ctx->date[2] = date_in_rom[6]; 1367 ctx->date[3] = date_in_rom[7]; 1368 ctx->date[4] = '/'; 1369 ctx->date[5] = date_in_rom[0]; 1370 ctx->date[6] = date_in_rom[1]; 1371 ctx->date[7] = '/'; 1372 ctx->date[8] = date_in_rom[3]; 1373 ctx->date[9] = date_in_rom[4]; 1374 ctx->date[10] = ' '; 1375 ctx->date[11] = date_in_rom[9]; 1376 ctx->date[12] = date_in_rom[10]; 1377 ctx->date[13] = date_in_rom[11]; 1378 ctx->date[14] = date_in_rom[12]; 1379 ctx->date[15] = date_in_rom[13]; 1380 ctx->date[16] = '\0'; 1381 } 1382 1383 static unsigned char *atom_find_str_in_rom(struct atom_context *ctx, char *str, int start, 1384 int end, int maxlen) 1385 { 1386 unsigned long str_off; 1387 unsigned char *p_rom; 1388 unsigned short str_len; 1389 1390 str_off = 0; 1391 str_len = strnlen(str, maxlen); 1392 p_rom = ctx->bios; 1393 1394 for (; start <= end; ++start) { 1395 for (str_off = 0; str_off < str_len; ++str_off) { 1396 if (str[str_off] != *(p_rom + start + str_off)) 1397 break; 1398 } 1399 1400 if (str_off == str_len || str[str_off] == 0) 1401 return p_rom + start; 1402 } 1403 return NULL; 1404 } 1405 1406 static void atom_get_vbios_pn(struct atom_context *ctx) 1407 { 1408 unsigned char *p_rom; 1409 unsigned short off_to_vbios_str; 1410 unsigned char *vbios_str; 1411 int count; 1412 1413 off_to_vbios_str = 0; 1414 p_rom = ctx->bios; 1415 1416 if (*(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS) != 0) { 1417 off_to_vbios_str = 1418 *(unsigned short *)(p_rom + OFFSET_TO_GET_ATOMBIOS_STRING_START); 1419 1420 vbios_str = (unsigned char *)(p_rom + off_to_vbios_str); 1421 } else { 1422 vbios_str = p_rom + OFFSET_TO_VBIOS_PART_NUMBER; 1423 } 1424 1425 if (*vbios_str == 0) { 1426 vbios_str = atom_find_str_in_rom(ctx, BIOS_ATOM_PREFIX, 3, 1024, 64); 1427 if (vbios_str == NULL) 1428 vbios_str += sizeof(BIOS_ATOM_PREFIX) - 1; 1429 } 1430 if (vbios_str != NULL && *vbios_str == 0) 1431 vbios_str++; 1432 1433 if (vbios_str != NULL) { 1434 count = 0; 1435 while ((count < BIOS_STRING_LENGTH) && vbios_str[count] >= ' ' && 1436 vbios_str[count] <= 'z') { 1437 ctx->vbios_pn[count] = vbios_str[count]; 1438 count++; 1439 } 1440 1441 ctx->vbios_pn[count] = 0; 1442 } 1443 } 1444 1445 static void atom_get_vbios_version(struct atom_context *ctx) 1446 { 1447 unsigned char *vbios_ver; 1448 1449 /* find anchor ATOMBIOSBK-AMD */ 1450 vbios_ver = atom_find_str_in_rom(ctx, BIOS_VERSION_PREFIX, 3, 1024, 64); 1451 if (vbios_ver != NULL) { 1452 /* skip ATOMBIOSBK-AMD VER */ 1453 vbios_ver += 18; 1454 memcpy(ctx->vbios_ver_str, vbios_ver, STRLEN_NORMAL); 1455 } else { 1456 ctx->vbios_ver_str[0] = '\0'; 1457 } 1458 } 1459 1460 struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) 1461 { 1462 int base; 1463 struct atom_context *ctx = 1464 kzalloc(sizeof(struct atom_context), GFP_KERNEL); 1465 char *str; 1466 struct _ATOM_ROM_HEADER *atom_rom_header; 1467 struct _ATOM_MASTER_DATA_TABLE *master_table; 1468 struct _ATOM_FIRMWARE_INFO *atom_fw_info; 1469 u16 idx; 1470 1471 if (!ctx) 1472 return NULL; 1473 1474 ctx->card = card; 1475 ctx->bios = bios; 1476 1477 if (CU16(0) != ATOM_BIOS_MAGIC) { 1478 pr_info("Invalid BIOS magic\n"); 1479 kfree(ctx); 1480 return NULL; 1481 } 1482 if (strncmp 1483 (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC, 1484 strlen(ATOM_ATI_MAGIC))) { 1485 pr_info("Invalid ATI magic\n"); 1486 kfree(ctx); 1487 return NULL; 1488 } 1489 1490 base = CU16(ATOM_ROM_TABLE_PTR); 1491 if (strncmp 1492 (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, 1493 strlen(ATOM_ROM_MAGIC))) { 1494 pr_info("Invalid ATOM magic\n"); 1495 kfree(ctx); 1496 return NULL; 1497 } 1498 1499 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR); 1500 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR); 1501 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4); 1502 if (!ctx->iio) { 1503 amdgpu_atom_destroy(ctx); 1504 return NULL; 1505 } 1506 1507 idx = CU16(ATOM_ROM_PART_NUMBER_PTR); 1508 if (idx == 0) 1509 idx = 0x80; 1510 1511 str = CSTR(idx); 1512 if (*str != '\0') { 1513 pr_info("ATOM BIOS: %s\n", str); 1514 strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version)); 1515 } 1516 1517 atom_rom_header = (struct _ATOM_ROM_HEADER *)CSTR(base); 1518 if (atom_rom_header->usMasterDataTableOffset != 0) { 1519 master_table = (struct _ATOM_MASTER_DATA_TABLE *) 1520 CSTR(atom_rom_header->usMasterDataTableOffset); 1521 if (master_table->ListOfDataTables.FirmwareInfo != 0) { 1522 atom_fw_info = (struct _ATOM_FIRMWARE_INFO *) 1523 CSTR(master_table->ListOfDataTables.FirmwareInfo); 1524 ctx->version = atom_fw_info->ulFirmwareRevision; 1525 } 1526 } 1527 1528 atom_get_vbios_name(ctx); 1529 atom_get_vbios_pn(ctx); 1530 atom_get_vbios_date(ctx); 1531 atom_get_vbios_version(ctx); 1532 1533 return ctx; 1534 } 1535 1536 int amdgpu_atom_asic_init(struct atom_context *ctx) 1537 { 1538 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR); 1539 uint32_t ps[16]; 1540 int ret; 1541 1542 memset(ps, 0, 64); 1543 1544 ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR)); 1545 ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR)); 1546 if (!ps[0] || !ps[1]) 1547 return 1; 1548 1549 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT)) 1550 return 1; 1551 ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps); 1552 if (ret) 1553 return ret; 1554 1555 memset(ps, 0, 64); 1556 1557 return ret; 1558 } 1559 1560 void amdgpu_atom_destroy(struct atom_context *ctx) 1561 { 1562 kfree(ctx->iio); 1563 kfree(ctx); 1564 } 1565 1566 bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index, 1567 uint16_t *size, uint8_t *frev, uint8_t *crev, 1568 uint16_t *data_start) 1569 { 1570 int offset = index * 2 + 4; 1571 int idx = CU16(ctx->data_table + offset); 1572 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4); 1573 1574 if (!mdt[index]) 1575 return false; 1576 1577 if (size) 1578 *size = CU16(idx); 1579 if (frev) 1580 *frev = CU8(idx + 2); 1581 if (crev) 1582 *crev = CU8(idx + 3); 1583 *data_start = idx; 1584 return true; 1585 } 1586 1587 bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev, 1588 uint8_t *crev) 1589 { 1590 int offset = index * 2 + 4; 1591 int idx = CU16(ctx->cmd_table + offset); 1592 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4); 1593 1594 if (!mct[index]) 1595 return false; 1596 1597 if (frev) 1598 *frev = CU8(idx + 2); 1599 if (crev) 1600 *crev = CU8(idx + 3); 1601 return true; 1602 } 1603 1604